Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method of forming the same. The method of forming the same provides a semiconductor substrate having a plurality of trenches formed therein, the trenches being separated by active regions, and isolation structures formed in the trenches. A portion of the active regions is removed by etching back to form recesses between adjacent isolation structures. A semiconductor channel layer is formed in the recesses, the semiconductor channel layer having a top surface that is flush with a top surface of the isolation structures, the semiconductor channel layer being configured to increase carrier mobility of a transistor. A portion of the semiconductor channel layer is oxidized to form a first gate oxide layer on a surface of the semiconductor channel layer. The method prevents the edge region of the transistor from turning on before the middle region.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor, and in particular, to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] Metal-oxide-semiconductor (MOS) transistor is the most basic device in semiconductor manufacturing, which is widely used in various integrated circuits, and is divided into NMOS transistor and PMOS transistor according to the main carrier and the doping type during manufacturing.

[0003] In the process of manufacturing PMOS transistor, in order to improve the mobility of carriers (holes), a silicon germanium layer is usually formed on the surface of the active region as a channel layer, and then a gate dielectric layer and a gate electrode are formed on the silicon germanium layer. However, the existing PMOS transistor has the problem that the edge region is turned on before the middle region, which affects the performance of the device. SUMMARY

[0004] Some embodiments of the present disclosure provide a forming method of a semiconductor structure, comprising:

[0005] A semiconductor substrate is provided, a plurality of trenches are formed in the semiconductor substrate, the active region is between the trenches, and an isolation structure is formed in the trench.

[0006] The etching-back removes part of the thickness of the active region, and forms a groove between the adjacent isolation structures.

[0007] A semiconductor channel layer is formed in the groove, the top surface of the semiconductor channel layer is flush with the top surface of the isolation structure, and the semiconductor channel layer is used to improve the carrier mobility of the transistor.

[0008] Part of the semiconductor channel layer is oxidized to form a first gate oxide layer on the surface of the semiconductor channel layer.

[0009] In some embodiments, the material of the semiconductor substrate is silicon, and the material of the semiconductor channel layer is silicon germanium.

[0010] In some embodiments, the semiconductor substrate includes a first transistor region and a second transistor region; the etching-back removes part of the thickness of the active region of the first transistor region to form the groove; after the semiconductor channel layer is formed, a protective layer is formed on the surface of the semiconductor channel layer and the isolation structure of the first transistor region; after the protective layer is formed, a second gate oxide layer is formed on the surface of the active region of the second transistor region; the protective layer is removed, and a first gate oxide layer is formed on the surface of the semiconductor channel layer, and the thickness of the first gate oxide layer is less than the thickness of the second gate oxide layer.

[0011] In some embodiments, the first gate oxide layer and the second gate oxide layer are formed by an in-situ steam oxidation process, and the active region of the second transistor region is continuously oxidized to increase the thickness of the second gate oxide layer while the first gate oxide layer is formed.

[0012] In some embodiments, the depth of the recess is 5-10 nm, and the thickness of the semiconductor channel layer is 5-10 nm.

[0013] In some embodiments, the etching gas used for etching away part of the thickness of the active region is HCl, the flow rate of the etching gas is 20-100 sccm, and the temperature of the chamber is 680-800 degrees Celsius.

[0014] In some embodiments, the semiconductor channel layer is formed by a selective epitaxy process.

[0015] In some embodiments, the selective epitaxy process uses SiH4 as the silicon source gas, the flow rate of the silicon source gas is 40-80 sccm, GeH4 as the germanium source gas, the flow rate of the germanium source gas is 20-50 sccm, the temperature of the chamber is 550-700 degrees Celsius, and HCl as the selective gas, the flow rate of the selective gas is 30-70 sccm.

[0016] In some embodiments, the material of the protective layer is silicon oxide, the protective layer is formed by an atomic layer deposition process, and the protective layer is removed by an isotropic wet etching process.

[0017] Some embodiments of the present disclosure also provide a semiconductor structure, comprising:

[0018] a semiconductor substrate having a plurality of trenches therein, the trenches being separated by active regions, and an isolation structure in the trenches;

[0019] the top surface of the active region is lower than the top surface of the isolation structure, so that a recess is formed between adjacent isolation structures;

[0020] a semiconductor channel layer on the top surface of the active region and in the recess, the top surface of the semiconductor channel layer being flush with the top surface of the isolation structure, the semiconductor channel layer being used to improve the carrier mobility of the transistor;

[0021] a first gate oxide layer on the surface of the semiconductor channel layer.

[0022] In some embodiments of the semiconductor structure and the method of forming the same, the method comprises: providing a semiconductor substrate, the semiconductor substrate having a plurality of trenches formed therein, the trenches being separated by active regions, and isolation structures formed in the trenches; etching back to remove a portion of the thickness of the active regions, forming recesses between adjacent isolation structures; forming a semiconductor channel layer in the recesses, the top surface of the semiconductor channel layer being flush with the top surface of the isolation structures, the semiconductor channel layer being used to increase the carrier mobility of the transistor; oxidizing a portion of the semiconductor channel layer, forming a first gate oxide layer on the surface of the semiconductor channel layer. By etching back to remove a portion of the thickness of the active regions in the first transistor region, recesses are formed between adjacent isolation structures in the first transistor region, i.e., the bottom surface of the recesses (or the surface of the active region after etching back) is lower than the top surface of the isolation structures, and subsequently, a semiconductor channel layer is formed in the recesses, the top surface of the semiconductor channel layer being flush with the top surface of the isolation structures. When it is subsequently required to form gate dielectric layers of different thicknesses in different regions, a protective layer is first formed on the surface of the semiconductor channel layer formed in the first transistor region and on the surface of the isolation structures, and after the corresponding gate dielectric layer is formed, the protective layer is removed. Since the top surface of the semiconductor channel layer and the isolation structures is flush when the protective layer is formed, the surface of the protective layer formed is flat and does not have a top corner region, and when the protective layer is removed, the etching rate is uniform at different positions of the protective layer and does not have the difference in etching rate caused by the stress of the top corner region, so that over-etching is not caused to the semiconductor channel layer near the junction between the semiconductor channel layer and the isolation structures, the thickness of the semiconductor channel layer in the edge region and the middle region can be kept uniform, and a recess defect is not formed in the isolation structures, so that when the gate dielectric layer is subsequently formed on the top surface of the semiconductor channel layer and the gate electrode is formed on the gate dielectric layer, the semiconductor channel layer as the channel region of the transistor does not have the problem of the edge region being turned on earlier than the middle region, and the performance of the transistor is improved. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figures 1-2 Partial structure schematic diagram of the forming process of the semiconductor structure of some embodiments of the present disclosure;

[0024] Figures 3-12 Structure schematic diagram of the forming process of the semiconductor structure of some embodiments of the present disclosure. DETAILED DESCRIPTION

[0025] As described in the background, the existing PMOS transistor has the problem of the edge region being turned on earlier than the middle region, which affects the performance of the device.

[0026] It is found that in the actual fabrication process of PMOS transistors, not only the silicon germanium layer is formed to improve the mobility of the carriers (holes), but also the threshold voltage or the turn-on voltage of the PMOS transistors formed in different regions is required to be different, i.e. the thickness of the gate dielectric layer of the PMOS transistors formed in different regions is required to be different. Specifically, referring to Figure 1 , a semiconductor substrate 100 is provided, which includes a first region 21 and a second region (not shown in the figure), and the PMOS transistors with different thicknesses of the gate dielectric layer are subsequently fabricated on the semiconductor substrate in the first region 21 and the second region. The semiconductor substrate 100 in the first region 21 is provided with isolation structures 102, and the active regions 101 are between the isolation structures 102. The isolation structure 102 includes a first silicon oxide layer 103 located on the side wall and the bottom of the trench in the semiconductor substrate 100, a silicon nitride layer 104 located on the surface of the first silicon oxide layer 103, and a second silicon oxide layer 105 located on the surface of the silicon nitride layer 104 and filling the trench. The surface of the isolation structure 102 is flush with the surface of the active region 101. A silicon germanium layer 103 protruding from the surface of the active region 101 is further formed on the surface of the active region 101. The silicon germanium layer 103 is subsequently used as the channel layer of the PMOS transistor formed in the first region 21 to improve the mobility of the carriers (holes) of the PMOS transistor. After the formation of the silicon germanium layer 103, a protective layer 106 (the material of the protective layer 106 is generally silicon oxide) is formed on the surface of the isolation structure 102 and the silicon germanium layer 103. The protective layer 106 forms a top corner region 22 at the junction of the isolation structure 102 and the silicon germanium layer 103 (or the active region). The purpose of forming the protective layer 106 is to protect the silicon germanium layer 103 and the isolation structure 102 from damage when the active region surface of the semiconductor substrate 100 in other regions (such as the second region) is formed with a gate dielectric layer of a different thickness (different from the thickness of the gate dielectric layer subsequently formed on the silicon germanium layer 103 in the first region 21). Referring to Figure 2 , after the formation of the gate dielectric layer of the first thickness in the other regions (such as the second region) of the semiconductor substrate 100 (not shown in the figure), the protective layer 106 in the first region 21 is removed by wet etching (refer to Figure 1 ). Then, the gate dielectric layer of the second thickness is formed on the silicon germanium layer 103 (not shown in the figure). It is further found that the stress at the top corner region 22 (refer to Figure 1 ) formed by the protective layer 106 at the junction of the isolation structure 102 and the silicon germanium layer 103 (or the active region) is large. When the protective layer 106 is removed by wet etching, the etching rate of the protective layer at the top corner region 22 is greater than the etching rate of the protective layer on the top surface of the silicon germanium layer 103, so that the side surface of the silicon germanium layer 103 is exposed and over-etched, forming a silicon germanium layer 103 edge region 23 (refer toFigure 2 ) will be thinner, i.e. the thickness of the edge region 23 of the silicon germanium layer 103 will be thinner than the thickness of the middle region, and after subsequently forming a gate dielectric layer covering the side surface and the top surface of the silicon germanium layer 103 and a gate electrode on the gate dielectric layer (not shown in the figure), the edge region of the silicon germanium layer 103 will be turned on earlier than the middle region when the silicon germanium layer 103 is used as a channel region of a PMOS transistor, which will affect the performance of the PMOS transistor. In addition, when etching the protective layer 106, a recess 24 (see Figure 2 ) is also likely to be formed in the isolation structure 102 at the junction of the isolation structure 102 and the silicon germanium layer 103 (or the active region), which will also affect the performance of the PMOS transistor.

[0027] Therefore, the present disclosure provides a semiconductor structure and a forming method thereof, which prevents the problem of the edge region of the channel region of the formed transistor being turned on earlier than the middle region, and improves the performance of the transistor.

[0028] The specific embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. In the detailed description of the embodiments of the present disclosure, the schematic diagrams will be partially enlarged without the general proportion for the convenience of description, and the schematic diagrams are only examples, which should not limit the protection scope of the present disclosure herein. In addition, the three-dimensional spatial dimensions including length, width and depth should be included in the actual manufacture.

[0029] Some embodiments of the present disclosure first provide a forming method of a semiconductor structure, which will be described in detail below with reference to the accompanying drawings.

[0030] Referring to Figure 3 , a semiconductor substrate 200 is provided, in which a plurality of trenches are formed, the trenches are active regions, and an isolation structure is formed in the trenches.

[0031] The semiconductor substrate 200 is a platform for subsequent processes, and the material of the semiconductor substrate 200 can be silicon (Si), germanium (Ge); can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or can also be other materials, such as group III-V compound of gallium arsenide, etc. In the present embodiment, the material of the semiconductor substrate 200 is silicon. The semiconductor substrate 200 is doped with a certain impurity ion as needed, which can be an N-type impurity ion or a P-type impurity ion, the P-type impurity ion can be one or more of boron, gallium, indium, and the N-type impurity ion can be one or more of phosphorus, arsenic, and antimony.

[0032] In some embodiments, the semiconductor substrate 200 can include a first transistor region 11 and a second transistor region 12, the first transistor region 11 is to form a first transistor, and the second transistor region 12 is to form a second transistor. In specific embodiments, the first transistor is a PMOS transistor, and the second transistor is a PMOS transistor or an NMOS transistor.

[0033] The number of the first transistor region 11 and the second transistor region 12 can be one or more, and the first transistor region 11 and the second transistor region 12 can be adjacent or not adjacent.

[0034] The semiconductor substrate 200 of the first transistor region 11 has a plurality of trenches, and the active regions 201 are between the trenches. The isolation structures 206 are formed in the trenches, and the isolation structures 206 of the first transistor region 11 are used for electrical isolation between adjacent active regions 201. The semiconductor substrate 200 of the second transistor region 12 also has a plurality of trenches, and the active regions 202 are between the trenches. The isolation structures 216 are formed in the trenches, and the isolation structures 216 of the second transistor region 12 are used for electrical isolation between adjacent active regions 202.

[0035] In some embodiments, the trench depths in the first transistor region 11 and the second transistor region 12 are the same, the formation of the trenches in the semiconductor substrate 200 of the first transistor region 11 and the second transistor region 12 is performed synchronously, and the steps of forming the isolation structures (206, 216) in the trenches are performed synchronously. In other embodiments, the trench depths in the first transistor region 11 and the second transistor region 12 can be different.

[0036] The isolation structures (206, 216) formed in the trenches in the first transistor region 11 and the second transistor region 12 have the same structure, and the top surfaces of the isolation structures (206, 216) are flush with the top surfaces of the active regions (201, 202). In some embodiments, the isolation structure 206 and the isolation structure 216 each include a first silicon oxide layer 203 on the sidewalls and the bottom surface of the trench, a silicon nitride layer 204 on the surface of the first silicon oxide layer 203, and a second silicon oxide layer 205 on the surface of the silicon nitride layer 204.

[0037] In one embodiment, the isolation structure 206 and the isolation structure 216 are formed by the following steps: forming a plurality of trenches in the semiconductor substrate 200 of the first transistor region 11 and the second transistor region 12; forming a first silicon oxide film on the sidewall and bottom wall surfaces of the trenches and the surface of the semiconductor substrate 200; forming a silicon nitride film on the surface of the first silicon oxide film; forming a second silicon oxide film on the surface of the silicon nitride film, the second silicon oxide film filling the trenches; removing the first silicon oxide film, the silicon nitride film and the second silicon oxide film on the surface of the semiconductor substrate 200 by a chemical mechanical polishing process to form a first silicon oxide layer 203, a silicon nitride layer 204 on the surface of the first silicon oxide layer 203, and a second silicon oxide layer 205 on the surface of the silicon nitride layer 204 in the trenches.

[0038] Referring to Figure 4 and Figure 5 , the active region 201 of the first transistor region 11 is etched back to form a groove 209 between the adjacent isolation structures 206 of the first transistor region 11.

[0039] In some embodiments, before the active region 201 of the first transistor region 11 is etched back, a first mask layer 207 is formed on the surface of the active region 202 of the second transistor region 12 and the isolation structure 216 and the surface of the isolation structure 206 of the first transistor region 11, the first mask layer 207 having an opening 208 exposing the surface of the active region 201 of the first transistor region 11, the material of the first mask layer 207 can be photoresist, the opening 208 is formed in the first mask layer 207 by an exposure and development process; the first mask layer 207 is used as a mask to etch back the active region 201 of the first transistor region 11 to form a groove 209 between the adjacent isolation structures 206 of the first transistor region 11.

[0040] The active region 201 of the first transistor region 11 is etched back to form a groove 209 between the adjacent isolation structures 206 of the first transistor region 11, i.e. the bottom surface of the groove 209 (or the surface of the active region 201 after etching back) is lower than the top surface of the isolation structure 206, and a semiconductor channel layer 210 is subsequently formed in the groove 209 (see Figure 8 ), the top surface of the semiconductor channel layer 210 is flush with the top surface of the isolation structure 206, and a protective layer 211 is subsequently formed on the surface of the semiconductor channel layer 210 formed in the first transistor region 11 and the surface of the isolation structure 206 when it is required to form a gate medium layer of different thickness in different regions (see Figure 8), after forming the corresponding gate dielectric layer, the protective layer will be removed. Since the top surface of the semiconductor channel layer 210 and the top surface of the isolation structure 206 are flush when the protective layer 211 is formed, the surface of the protective layer 211 formed is flat and there is no top corner area. When the protective layer 211 is removed, the etching rate of each position of the protective layer 211 is uniform and there is no difference in etching rate caused by stress in the top corner area. Therefore, over-etching of the semiconductor channel layer 210 and the isolation structure 206 near the junction between the semiconductor channel layer 210 and the isolation structure 206 is avoided, the thickness of the edge region and the middle region of the semiconductor channel layer 210 can be kept uniform, and no recess defect is formed in the isolation structure 206. Therefore, after forming the gate dielectric layer on the top surface of the semiconductor channel layer 210 and the gate electrode on the gate dielectric layer, when the semiconductor channel layer 210 is used as the channel region of the transistor, there is no problem of the edge region being turned on earlier than the middle region, and the performance of the transistor is improved.

[0041] In some embodiments, the depth of the groove 209 is 5-10 nm.

[0042] In some embodiments, the etching gas used when etching to remove part of the thickness of the active region 201 is HCl, the flow rate of the etching gas is 20-100 sccm, and the temperature of the chamber is 680-800 degrees Celsius. In some embodiments, when etching, the etching gas is HCl which can be ionized to form plasma to etch the active region 201.

[0043] Reference Figure 6 The semiconductor channel layer 210 is formed in the groove 209, and the top surface of the semiconductor channel layer 210 is flush with the top surface of the isolation structure 206.

[0044] The semiconductor channel layer 210 is used as the channel region of the transistor formed subsequently, and the semiconductor channel layer 210 is used to improve the mobility of the carriers of the transistor formed subsequently.

[0045] The first transistor region 11 is used to form a PMOS transistor subsequently, the material of the semiconductor channel layer 210 can be silicon germanium, and the semiconductor channel layer 210 is used to improve the mobility of the hole carriers of the PMOS transistor formed subsequently.

[0046] The semiconductor channel layer 210 is formed by using a selective epitaxy process.

[0047] In some embodiments, the selective epitaxy process uses SiH4as the silicon source gas, the flow rate of the silicon source gas is 40-80sccm, GeH4as the germanium source gas, the flow rate of the germanium source gas is 20-50sccm, the temperature of the chamber is 550-700 degrees Celsius, and further includes a selective gas HCl, the flow rate of the selective gas is 30-70sccm.

[0048] In some embodiments, the thickness of the semiconductor channel layer 210 is 5-10nm.

[0049] Since HCl gas is used in both the step of removing part of the thickness of the active region 201 by etching back and the step of forming the semiconductor channel layer 210, in some embodiments, the step of removing part of the thickness of the active region 201 by etching back and the step of forming the semiconductor channel layer 210 can be performed in the same chamber, such as in a selective epitaxy deposition chamber. After the step of removing part of the thickness of the active region 201 by etching back is performed in the selective epitaxy deposition chamber, the step of forming the semiconductor channel layer 210 is performed in the same selective epitaxy deposition chamber, so as to save the time of the process, improve the efficiency of the process, and prevent the sidewall and the bottom of the recess 208 from being contaminated or oxidized after the recess 209 is formed when the sidewall and the bottom of the recess 208 leave the chamber, and improve the quality of the semiconductor channel layer 210 formed.

[0050] In other embodiments, the step of removing part of the thickness of the active region 201 by etching back and the step of forming the semiconductor channel layer 210 are performed in different process chambers.

[0051] In some embodiments, referring to Figure 7 , the first mask layer 207 is removed (referring to Figure 6 ).

[0052] The first mask layer 207 can be removed by an etching process or an ashing process.

[0053] In some embodiments, referring to Figure 8 , the method further includes: after the semiconductor channel layer 210 is formed, a protective layer 211 is formed on the surface of the semiconductor channel layer 210 and the isolation structure 206 in the first transistor region 11.

[0054] The protective layer 211 covers the surface of the semiconductor channel layer 210 and the isolation structure 206 in the first transistor region 11 to form a protective layer 211, and exposes the surface of the active region 202 (and the isolation structure 216) in the second transistor region 12. When subsequent corresponding processes (such as forming a gate dielectric layer (or a second gate oxide layer)) are performed on the second transistor region 12, the protective layer 211 protects the semiconductor channel layer 210 and the isolation structure 206 in the first transistor region 11 from being damaged.

[0055] The protective layer 211 can be a single layer or a multi-layer stack structure, and the material of the protective layer 211 can be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride.

[0056] The protective layer 211 is formed by a deposition process, and is removed by an etching process to form the protective layer of the second transistor region 12. The deposition process includes atomic layer deposition, atmospheric pressure chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), thermal chemical vapor deposition (Thermal CVD), and high-density plasma chemical vapor deposition (HDPCVD).

[0057] In some embodiments, referring to Figure 9 Further comprising: forming a gate dielectric layer (second gate oxide layer 212) on the surface of the active region 202 of the second transistor region 12 after forming the protective layer 211.

[0058] The material of the second gate oxide layer 212 can be silicon oxide. In an embodiment, the second gate oxide layer 212 is formed by an in-situ water vapor oxidation process. The second gate oxide layer 212 serves as the gate dielectric layer of the transistor formed in the second transistor region 12. The transistor formed in the second transistor region 12 can be a PMOS transistor or an NMOS transistor.

[0059] In some embodiments, referring to Figure 10 Further comprising: forming a second mask layer 213 covering the second gate oxide layer 212 and the isolation structure 216 of the second transistor region 12, and the second mask layer 213 exposes the protective layer 211 of the first transistor region 11.

[0060] The second mask layer 213 is used to protect the second gate oxide layer 212 and the isolation structure 216 of the second transistor region 12 when the protective layer 211 is removed.

[0061] The material of the second mask layer 213 is different from the material of the protective layer 211. In an embodiment, the material of the second mask layer 213 is photoresist.

[0062] In some embodiments, referring to Figure 11 Further comprising: removing the protective layer 211 (refer to Figure 10 ).

[0063] The protective layer 211 can be removed by an isotropic wet etching process or an isotropic dry etching process.

[0064] In the present disclosure, since the top surface of the semiconductor channel layer 210 formed in the groove 209 is flush with the top surface of the isolation structure 206, when a gate dielectric layer (second gate oxide layer 212) with different thickness needs to be formed in the second transistor region 12, a protective layer 211 is first formed on the surface of the semiconductor channel layer 210 and the surface of the isolation structure 206 formed in the first transistor region 11, and after the corresponding gate dielectric layer (second gate oxide layer 212) is formed, the protective layer 211 is removed. Since the top surface of the semiconductor channel layer 210 and the isolation structure 206 is flush when the protective layer 211 is formed, the surface of the protective layer 211 formed is flat and there is no top corner area. When the protective layer 211 is removed, the etching rate of the protective layer 211 at different positions is uniform and there is no difference in etching rate caused by stress in the top corner area, so that over-etching of the semiconductor channel layer 210 and the isolation structure 206 near the junction between the semiconductor channel layer 210 and the isolation structure 206 in the first transistor region 11 is avoided, the thickness of the semiconductor channel layer 210 in the edge region and the middle region can be kept uniform, and no recess defect is formed in the isolation structure 206. Therefore, when the semiconductor channel layer 210 is used as the channel region of the transistor after the gate dielectric layer and the gate electrode on the gate dielectric layer are formed on the top surface of the semiconductor channel layer 210, there is no problem of the edge region being turned on earlier than the middle region, and the performance of the transistor formed in the first transistor region 11 is improved.

[0065] Reference Figure 12 The second mask layer 213 is removed (see reference Figure 11 ), and part of the semiconductor channel layer 210 is oxidized to form a first gate oxide layer 215 on the surface of the semiconductor channel layer 210.

[0066] The second mask layer 213 can be removed by a wet etching process or a dry etching process.

[0067] Part of the semiconductor channel layer 210 is oxidized by an in-situ steam oxidation process, and at the same time (or when the first gate oxide layer is formed), the active region 202 of the second transistor region 12 is continuously oxidized to increase the thickness of the second gate oxide layer 212, that is, the thickness of the second gate oxide layer 212 formed is greater than the thickness of the first gate oxide layer 215 (or the thickness of the first gate oxide layer 215 is less than the thickness of the second gate oxide layer 212), so as to meet the requirements of the performance (such as different threshold voltages or turn-on voltages) of the transistors formed in different regions.

[0068] In some embodiments, a first gate electrode (not shown in the figure) is formed on the surface of the first gate oxide layer 215, and a second gate electrode (not shown in the figure) is formed on the surface of the second gate oxide layer 212.

[0069] The material of the first gate electrode and the first gate electrode is one or more of W, Al, Cu, Ti, Ag, Au, Pt, Ni.

[0070] In some embodiments, before forming the first gate electrode and the first gate electrode, a first work function layer can also be formed on the surface of the first gate oxide layer 215; and a second work function layer can also be formed on the surface of the second gate oxide layer 212.

[0071] The first work function layer is used to adjust the work function of the transistor formed by the first transistor region 11. The second work function layer is used to adjust the work function of the transistor formed by the second transistor region 12.

[0072] The material of the first work function layer and the second work function layer can be the same or different.

[0073] In some embodiments, the material of the first work function layer or the second work function layer includes titanium, tantalum, titanium nitride, tantalum nitride, cobalt, titanium aluminum nitride, titanium aluminum cobalt, ruthenium, copper manganese, titanium aluminum nitride, titanium aluminum, or lanthanum.

[0074] Some embodiments of the present disclosure also provide a semiconductor structure, referring to Figure 12 , comprising:

[0075] A semiconductor substrate 200 having a plurality of trenches therein, an active region 201 between the trenches, and an isolation structure 206 in the trenches;

[0076] The top surface of the active region 201 is lower than the top surface of the isolation structure 206, so that there is a groove 209 between adjacent isolation structures 206;

[0077] A semiconductor channel layer 210 on the top surface of the active region 201 and in the groove 209, the top surface of the semiconductor channel layer 210 being flush with the top surface of the isolation structure 206, the semiconductor channel layer 210 being used to improve the carrier mobility of the transistor;

[0078] A first gate oxide layer 215 on the surface of the semiconductor channel layer 210.

[0079] In some embodiments, the semiconductor substrate 200 includes a first transistor region 11 and a second transistor region 12; the top surface of the active region 201 of the first transistor region 11 is lower than the top surface of the active region 202 of the second transistor region 12; the top surface of the active region 202 of the second transistor region 12 has a second gate oxide layer 212, and the thickness of the first gate oxide layer 215 is less than the thickness of the second gate oxide layer 212.

[0080] In some embodiments, the material of the semiconductor substrate 200 is silicon, and the material of the semiconductor channel layer 210 is silicon germanium.

[0081] In some embodiments, the depth of the groove 209 is 5-10 nm, and the thickness of the semiconductor channel layer 210 is 5-10 nm.

[0082] In some embodiments, further comprising: a first gate electrode (not shown in the figure) on the surface of the first gate oxide layer 215; and a second gate electrode (not shown in the figure) on the surface of the second gate oxide layer 212.

[0083] The material of the first gate electrode and the second gate electrode is one or more of W, Al, Cu, Ti, Ag, Au, Pt, and Ni.

[0084] In some embodiments, further comprising: a first work function layer between the first gate oxide layer 215 and the first gate electrode; and a second work function layer between the second gate oxide layer 212 and the second gate electrode.

[0085] The first work function layer is used to adjust the work function of the transistor formed by the first transistor region 11. The second work function layer is used to adjust the work function of the transistor formed by the second transistor region 12.

[0086] The material of the first work function layer and the second work function layer can be the same or different.

[0087] In some embodiments, the material of the first work function layer or the second work function layer includes titanium, tantalum, titanium nitride, tantalum nitride, cobalt, titanium aluminum nitride, titanium aluminum cobalt, ruthenium, copper manganese, titanium aluminum nitride, titanium aluminum, or lanthanum.

[0088] It should be noted that the terms “include” and “have” and their variants as used in the present disclosure are intended to cover the non-exclusive inclusion. The terms “first”, “second”, and the like are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence, unless the context clearly indicates otherwise, and it should be understood that the data thus used can be interchanged under appropriate circumstances. In addition, the embodiments and features in the present disclosure can be combined with each other, without conflict, unless otherwise specified. Furthermore, in the above description, the description of well-known components and technologies has been omitted to avoid unnecessary confusion of the concepts of the present disclosure. In each of the above embodiments, each embodiment focuses on the difference from other embodiments, and the same / similar parts between the embodiments can be referred to each other (or referenced).

[0089] Although the present disclosure has been disclosed in the above preferred embodiments, it is not intended to limit the present disclosure, and any person skilled in the art can make possible changes and modifications to the technical solutions of the present disclosure without departing from the spirit and scope of the present disclosure by using the methods and technical contents disclosed above. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present disclosure without departing from the technical solutions of the present disclosure shall fall within the protection scope of the present disclosure.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A semiconductor substrate is provided, wherein a plurality of trenches are formed therein, the trenches are active regions, and isolation structures are formed therein; the semiconductor substrate includes a first transistor region and a second transistor region. The active region, which has a portion of the thickness of the first transistor region, is etched back to form a groove between adjacent isolation structures; A semiconductor channel layer is formed in the groove, the top surface of the semiconductor channel layer is flush with the top surface of the isolation structure, the semiconductor channel layer is used to improve the carrier mobility of the transistor, and the material of the semiconductor channel layer is silicon germanium; A protective layer is formed on the surface of the semiconductor channel layer and the isolation structure in the first transistor region; after forming the protective layer, a second gate oxide layer is formed on the surface of the active region in the second transistor region; the protective layer is etched away, with the etching rate being consistent at all locations of the protective layer; a portion of the semiconductor channel layer is oxidized to form a first gate oxide layer on the surface of the semiconductor channel layer; while oxidizing a portion of the semiconductor channel layer, the active region in the second transistor region continues to be oxidized to increase the thickness of the second gate oxide layer; the thickness of the first gate oxide layer is less than the thickness of the second gate oxide layer.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The semiconductor substrate is made of silicon.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The depth of the groove is 5-10 nm, and the thickness of the semiconductor channel layer is 5-10 nm.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, When etching back to remove part of the thickness of the active region of the first transistor region, the etching gas used is HCl, the flow rate of the etching gas is 20-100 sccm, and the temperature of the chamber is 680-800 degrees Celsius.

5. The method for forming a semiconductor structure as described in claim 4, characterized in that, The semiconductor channel layer is formed using a selective epitaxial growth process.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that, The selective epitaxial process uses SiH4 as the silicon source gas with a flow rate of 40-80 sccm, GeH4 as the germanium source gas with a flow rate of 20-50 sccm, and the chamber temperature is 550-700 degrees Celsius. It also includes the selective gas HCl with a flow rate of 30-70 sccm.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The protective layer is made of silicon oxide; the protective layer is formed by atomic layer deposition; and the protective layer is removed by isotropic wet etching.

8. A semiconductor structure formed by the method according to any one of claims 1-7, characterized in that, include: A semiconductor substrate having multiple trenches, with active regions between the trenches and isolation structures within the trenches; The top surface of the active region is lower than the top surface of the isolation structure, so that there is a groove between adjacent isolation structures; A semiconductor channel layer located on the top surface of the active region and in the groove, the top surface of the semiconductor channel layer being flush with the top surface of the isolation structure, the semiconductor channel layer being used to improve the carrier mobility of the transistor; The first gate oxide layer located on the surface of the semiconductor channel layer.

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