Built-in ballast resistor of IGBT device and forming method thereof and IGBT device

Abstract

The present invention relates to the technical field of power semiconductor devices, and in particular to a built-in ballast resistor of an IGBT device, a method for forming the same, and an IGBT device. The layout unit of the IGBT device includes a plurality of groove regions and an N+ type source region, a polysilicon region, and a contact hole region, wherein the plurality of N+ type source regions and the polysilicon region are alternately arranged along the length direction of the groove region, and the contact hole region is located inside the N+ type source region; the built-in ballast resistor includes an N-substrate, and a deep groove is formed by etching the corresponding groove region on the N-substrate; the N-substrate on opposite sides of the deep groove is provided with a first doping region and a second doping region alternately arranged, wherein the position of the first doping region corresponds to the N+ type source region, and the position of the second doping region corresponds to the polysilicon region; the top of the first doping region has an N+ well region, and the top of the second doping region has a second N-well region. The IGBT device with a built-in ballast resistor of the present invention can obtain a larger positive temperature coefficient, and the on-state voltage drop V of the IGBT device at room temperature is reduced. CESAT The impact is not significant.

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductor devices, and in particular to a built-in ballast resistor of an IGBT device and a forming method thereof, and an IGBT device. Background Art

[0002] As the fastest-growing power semiconductor device, the insulated gate bipolar transistor (IGBT) has been widely used in rail transit, smart grid and other fields due to its easy gate drive and high current density. It is known as the "CPU" of power converters. Load short circuit is an occasional electrical fault of IGBT in application. In order to avoid damage to the device caused by short circuit fault, IGBT is required to withstand the short circuit stress impact within the response time of the protection circuit. The short circuit capability of the device has become an important indicator for measuring the reliability of IGBT application. Due to the application environment, high-voltage IGBT has stricter requirements on short circuit withstand. In order to leave response time for the external protection circuit, the IGBT device is turned off in the case of short circuit. Generally, the short circuit withstand time of the device itself is required to be no less than 10us. In the case of short circuit, the two ends of the IGBT bear a large voltage so that the output current reaches saturation. The current at this time is called short-circuit saturation current. The larger the saturation current, the shorter the short circuit time.

[0003] In order to pursue a lower saturation voltage drop, the current trench gate IGBT technology has made the trench size smaller and smaller, and the channel density larger and larger, which will increase the saturation current of the device, thereby greatly reducing the short-circuit resistance of the device. In order to improve the short-circuit resistance of the device, the existing technology periodically injects N-type impurities between the trenches of the conventional carrier storage trench gate IGBT to form an N+ region, which increases the channel length and the channel resistance R CH This method can improve the short-circuit resistance of the device, but it will also cause the on-state voltage drop V CESAT The lightly doped N-type ballast resistor of the prior art solution is mainly proposed for the planar gate IGBT device, and does not provide the layout unit of the N-type ballast resistor, the corresponding vertical device structure diagram and the manufacturing process. Summary of the invention

[0004] In view of this, the purpose of the present invention is to provide a built-in ballast resistor of an IGBT device and a method for forming the same, and an IGBT device, so as to at least solve the problems of the existing trench IGBT device in that the short-circuit resistance is weak and the on-state voltage drop V CESAT Significantly increasing problem.

[0005] The present invention solves the above technical problems by the following technical means:

[0006] In a first aspect, an embodiment of the present invention provides a built-in ballast resistor of an IGBT device, wherein a layout unit of the IGBT device includes a plurality of trench regions, and an N+ type source region, a polysilicon region, and a contact hole region arranged between each two adjacent trench regions, wherein at least two of the N+ type source regions, the polysilicon region, and the contact hole region are provided, and the plurality of N+ type source regions and the polysilicon region are alternately arranged along a first direction, and the contact hole region is located inside the N+ type source region, and the first direction is a direction along the length of the trench region;

[0007] Along the second direction, the built-in ballast resistor includes an N-substrate, and a first doped region and a second doped region arranged on the N-substrate, and a deep groove is formed by etching the corresponding groove area on the N-substrate. The second direction is along the thickness of the IGBT device; the first doped region and the second doped region are alternately arranged on the N-substrate on opposite sides of the deep groove, and the position of the first doped region corresponds to the N+ type source region, and the position of the second doped region corresponds to the polysilicon region; the top of the first doped region has an N+ well region, and the top of the second doped region has a second N-well region.

[0008] In combination with the first aspect, in some embodiments, the first doped region includes a P-well region, a first N-well region and an N+ well region formed in sequence on an N-substrate, a P+ well region is arranged inside the first doped region, an upper end of the P+ well region is located inside the N+ well region, and a lower end is located inside the P-well region, and a position of the P+ well region corresponds to a contact hole region.

[0009] In combination with the first aspect, in some embodiments, the concentration of arsenic ions injected into the N+ well region is 10 19 ~10 20 cm -3 .

[0010] In combination with the first aspect, in some embodiments, the second doped region includes a P-well region, a first N-well region, and a second N-well region formed sequentially on an N-substrate, the first N-well region and the second N-well region have the same composition and formation conditions, and the first N-well region and the second N-well region are formed by push junction at the same time.

[0011] In combination with the first aspect, in some embodiments, the first N-well regions in the first doping region and the second doping region are completely identical, and the phosphorus ion concentrations injected into the first N-well region and the second N-well region are 10 17 ~10 18 cm -3 .

[0012] In combination with the first aspect, in some embodiments, the depth of the deep groove is 4 to 6 microns.

[0013] In combination with the first aspect, in some embodiments, polysilicon material is deposited inside the deep trench to form gate polysilicon, polysilicon material is also deposited on the second doped region to form a polysilicon layer, the polysilicon layer covers the deep trench and the second doped region, and the polysilicon layer is connected to the gate polysilicon;

[0014] In combination with the first aspect, in some embodiments, a gate oxide layer is formed between the groove wall and the groove bottom of the deep groove and the gate polysilicon, and a gate oxide layer is also formed between the polysilicon layer and the second doping region, and the thickness of the gate oxide layer is 800Å~1200Å.

[0015] In a second aspect, an embodiment of the present invention provides a method for preparing a built-in ballast resistor of an IGBT device, comprising the following steps:

[0016] Providing an N-substrate, performing photolithography on the N-substrate using a mask plate to form a patterned first mask layer, wherein the first mask layer is photolithographically formed with a groove region, and etching the N-substrate corresponding to the groove region to form at least two deep grooves on the N-substrate, wherein the depth of the deep grooves is 4 to 6 microns;

[0017] Thermally growing a gate oxide layer on the groove wall and the groove bottom of the deep groove and the top surface of the N-substrate, wherein the thickness of the gate oxide layer is 800Å to 1200Å;

[0018] Performing boron ion implantation on the N-substrate at opposite sides of the deep trench and high-temperature junction pushing to form a P-well region, wherein the junction depth of the P-well region on the N-substrate is 2.5 to 3.5 microns;

[0019] Depositing polysilicon material on the gate oxide layer, forming gate polysilicon in the deep trench, and forming a polysilicon layer outside the deep trench, using a mask plate to perform photolithography on the polysilicon layer to form a patterned second mask layer, along a first direction, the second mask layer is photolithographically formed with a plurality of N+ type source regions and polysilicon regions that are alternately distributed, etching the polysilicon layer corresponding to the N+ type source region to the gate oxide layer, and the first direction is the direction along the length of the deep trench;

[0020] Phosphorus ion implantation is performed on the P-well region at a concentration of 10 17 ~10 18 cm -3 , and push the junction at 900-1000℃ for 50-70min to form an N-well region with a junction depth of 0.35-0.45 microns;

[0021] Arsenic is implanted into the N-well region corresponding to the N+ source region at a concentration of 10 19 ~10 20 cm -3, and annealed at 900-1000℃ for 20-40min to form an N+ well region with a junction depth of 0.2~0.25um.

[0022] In a third aspect, an embodiment of the present invention provides an IGBT device, comprising the built-in ballast resistor described in the first aspect above, and also comprising a collector metal layer, a P+ substrate, an emitter metal layer and an ILD dielectric layer, wherein one side of the P+ substrate is connected to the N- substrate, and the other side opposite thereto is connected to the collector metal layer; one side of the ILD dielectric layer faces the emitter metal layer, and the other side opposite thereto faces the first doping region and the second doping region.

[0023] The IGBT device containing the built-in ballast resistor of the present invention forms an alternating distribution area of ​​N+ well region and second N-well region along the length direction of the deep trench, and the second N-well region is lightly doped. The lower the doping concentration, the higher the ballast resistor R N- The greater the rate of change with temperature, the more positive the temperature coefficient is, which can play a ballast role at high temperatures and improve the short-circuit resistance of the IGBT device. Since the N-substrate is located below the polysilicon gate, when the IGBT device is forward-conducting, the polysilicon gate is at a high potential, and electrons accumulate on the surface of the N-substrate area, reducing the on-resistance. Therefore, compared with the structure of traditional IGBT devices, the on-voltage drop V CESAT It won't add much.

[0024] The IGBT device containing the built-in ballast resistor of the present invention can obtain a larger positive temperature coefficient, and the on-state voltage drop V of the IGBT device at room temperature is CESAT Compared with the traditional IGBT device process or structure, it has the advantages of simple process, low cost, strong short-circuit resistance, long service life, etc., and is suitable for mass industrial production. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a layout unit of the IGBT device of the present invention;

[0026] Figure 2 yes Figure 1 The corresponding transverse cross-sectional structure diagram of the A-A' unit connection line;

[0027] Figure 3 yes Figure 1 The corresponding transverse cross-sectional structure diagram of the B-B' unit connection line;

[0028] Figure 4 Is when V GE >V TH hour, Figure 1 The circuit diagram of the current Ic flow path at the A-A' position and the B-B' position, Figure 4In the figure, Vbi represents the voltage generated by the built-in electric field of the PN junction, R SUB Represents the substrate resistance, R CH Represents the channel resistance, R N- Represents the N-well resistance, R N+ Represents the resistance of the N+ well region;

[0029] Figure 5 is a schematic diagram of a structure formed by executing step S1;

[0030] Figure 6 is a schematic diagram of a structure formed by executing step S2;

[0031] Figure 7 is a schematic diagram of a structure formed by executing step S3;

[0032] Figure 8 is a schematic diagram of a structure formed by executing step S4;

[0033] Fig. 9 is a schematic diagram of a structure formed by executing step S5;

[0034] Fig.10 It is a comparison diagram of the short-circuit current density simulation waveforms of the IGBT device of the present invention and the conventional trench gate IGBT device;

[0035] Among them, trench area 1, N+ type source area 2, polysilicon area 3, contact hole area 4, N-substrate 100, deep trench 110, N+ well area 210, first N-well area 220, P+ well area 230, second N-well area 310, P-well area 400, gate polysilicon 500, polysilicon layer 600, gate oxide layer 700, collector metal layer 810, P+ substrate 820, emitter metal layer 830, and ILD dielectric layer 840. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0037] The terms "first" and "second" in the specification and claims herein are used to distinguish different objects rather than to describe a specific order of objects. In the description of the embodiments of the present application, unless otherwise specified, the meaning of "multiple" refers to two or more, for example, multiple processing units refer to two or more processing units, etc., multiple elements refer to two or more elements, etc.

[0038] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0039] The built-in ballast resistor of the IGBT device of the present application is formed by photolithography and etching of the polysilicon layer, retaining the polysilicon strip connected to the polysilicon gate, realizing self-aligned injection of N-type impurities, and then forming an alternating distribution area of ​​N+ well region and N- well region through phosphorus P injection, high temperature junction pushing, arsenic As injection, and high temperature activation. In the present application, the N- region is required to be lightly doped. The lower the doping concentration, the greater the ballast resistor R N- The greater the rate of change with temperature, the more positive the temperature coefficient. It can play a ballast role at high temperatures and improve the short-circuit resistance of IGBT devices. Since the N-substrate is located below the polysilicon gate, when the IGBT device is forward-conducting, the polysilicon gate is at a high potential, and electrons accumulate on the surface of the N-substrate area, reducing the on-resistance. Therefore, compared with the structure of traditional IGBT devices, the on-voltage drop V CESAT It won't add much.

[0040] In order to better understand the above technical solution, the above technical solution will be described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0041] Please refer to Figure 1-10 :

[0042] Figure 1 For the layout unit diagram of the IGBT device, please refer to Figure 1 The layout unit of the IGBT device includes a plurality of trench regions 1, and an N+ source region 2, a polysilicon region 3, and a contact hole region 4 arranged between each two adjacent trench regions 1. At least two N+ source regions 2, polysilicon regions 3, and contact hole regions 4 are provided. The plurality of N+ source regions 2 and polysilicon regions 3 are alternately arranged along a first direction, for example, arranged according to the rule of N+ source region 2, polysilicon region 3, N+ source region 2, polysilicon region 3, etc. The contact hole region 4 is located inside the N+ source region 2, and the first direction is the direction along the length of the trench region 1.

[0043] Along the second direction, the built-in ballast resistor includes an N-substrate 100, and a first doping region and a second doping region disposed on the N-substrate 100. A deep groove 110 is formed by etching the N-substrate 100 corresponding to the groove region 1. Generally, the depth of the deep groove 110 is 4 to 6 microns. The second direction is along the thickness of the IGBT device.

[0044] The first doping region and the second doping region are alternately arranged on the N-substrate 100 on opposite sides of the deep groove 110. The position of the first doping region corresponds to the N+ type source region 2, and the position of the second doping region corresponds to the polysilicon region 3; the top of the first doping region has an N+ well region 210, and the top of the second doping region has a second N-well region 310.

[0045] Please refer to Figure 2 The first doped region includes a P-well region 400, a first N-well region 220 and an N+ well region 210 formed in sequence on an N-substrate 100. A P+ well region 230 is disposed inside the first doped region. The upper end of the P+ well region 230 is located inside the N+ well region 210, and the lower end is located inside the P-well region 400. The position of the P+ well region 230 corresponds to the contact hole region 4. The N+ well region 210 is formed by injecting arsenic ions into the first N-well region 220 and pushing the junction at a high temperature. The concentration of the arsenic ions injected into the N+ well region 210 is 10 19 ~10 20 cm -3 The junction depth of the N+ well region 210 on the first N-well region 220 is 0.2-0.25 microns.

[0046] Please refer to Figure 3 The second doping region includes a P-well region 400, a first N-well region 220 and a second N-well region 310 formed sequentially on an N-substrate 100. The first N-well region 220 and the second N-well region 310 have the same composition and formation conditions. The first N-well region 220 in the first doping region and the second doping region are completely identical. The phosphorus ion concentrations injected into the first N-well region 220 and the second N-well region 310 are both 10 17 ~10 18 cm -3 .

[0047] Polysilicon material is deposited inside the deep trench 110 to form gate polysilicon 500 , and polysilicon material is also deposited on the second doped region to form a polysilicon layer 600 . The polysilicon layer 600 covers the deep trench 110 and the second doped region, and the polysilicon layer 600 is connected to the gate polysilicon 500 .

[0048] A gate oxide layer 700 is formed between the trench wall and the bottom of the deep trench 110 and the gate polysilicon 500 , and a gate oxide layer 700 is also formed between the polysilicon layer 600 and the second doped region. The thickness of the gate oxide layer 700 is 800Å-1200Å.

[0049] In another embodiment of the present application, a method for preparing the built-in ballast resistor of the above-mentioned IGBT device is disclosed, comprising the following steps:

[0050] Step S1, providing an N-substrate 100, using a mask plate to perform photolithography on the N-substrate 100 to form a patterned first mask layer, the first mask layer is photolithographically formed with a groove area 1, and the N-substrate 100 is etched corresponding to the groove area 1 to form at least two deep grooves 110 on the N-substrate 100, and the depth of the deep groove 110 is 4 to 6 microns, see Figure 5 .

[0051] Step S2, forming a silicon dioxide gate oxide layer 700 on the groove wall and groove bottom of the deep groove 110 and the top surface of the N-substrate 100 by thermal growth, the thickness of the gate oxide layer 700 is 800Å~1200Å, see Figure 6 The gate oxide layer 700 in this embodiment is formed by a conventional thermal growth method, and this embodiment does not specifically limit it as long as the gate oxide layer can be formed at a corresponding position.

[0052] Step S3, boron ion implantation is performed on the N-substrate 100 at two opposite sides of the deep trench 110, and the implantation concentration of the boron ions is 10 13 ~10 14 cm -2 , and push the junction at 900-1000 degrees Celsius for 50-60 minutes, preferably at 950 degrees Celsius for 55 minutes, to form a P-well region 400 on the N-substrate 100 on opposite sides of the deep trench 110. The junction depth of the P-well region 400 on the N-substrate 100 is 2.5-3.5 microns, see Figure 7 .

[0053] Step S4, depositing polysilicon material on the gate oxide layer 700, forming gate polysilicon 500 in the deep trench 110, and forming a polysilicon layer 600 outside the deep trench. Using a mask plate to perform photolithography on the polysilicon layer to form a patterned second mask layer, along the first direction, the second mask layer is photolithographically formed with a plurality of N+ type source regions 2 and polysilicon regions 3 that are alternately distributed, and etching the polysilicon layer corresponding to the N+ type source region to the gate oxide layer. After etching, the gate polysilicon 500 and the polysilicon layer 600 are still connected. See Figure 8 The polysilicon layer 600 can block the subsequent N+ (arsenic) injection. The polysilicon in the deep trench 110 acts as a gate electrode. The polysilicon layer 600 is connected to the polysilicon in the deep trench 100 to achieve equipotential. In this way, when the gate is pressurized, the other side of the gate oxide layer 700 will be inverted or the electrons will be gathered into N. When the device is turned on at room temperature, the internal resistance will not increase too much. At high temperature, R N- The ballast resistor has a positive temperature coefficient to achieve the ballast effect. In addition, the width of the polysilicon region can be adjusted to adjust R N- The size of the ballast resistor.

[0054] Step S5, phosphorus ion implantation is performed on the P-well region 400, with an implantation concentration of 1017 ~10 18 cm -3 , and push the junction at 900-1000℃ for 50-70min, preferably at 950℃ for 60min, to form an N-well region on the P-well region 400, with a junction depth of 0.35-0.45 microns. The N-well region corresponding to the polysilicon region at this time is the first N-well region 220 and the second N-well region 230 of the second doping region. Then, arsenic is implanted on the N-well region corresponding to the N+ type source region 2, with an implant concentration of 10 19 ~10 20 cm -3 , and anneal at 900-1000℃ for 20-40min, preferably at 950℃ for 30min, to form an N+ well region 210 on the N-well region corresponding to the N+ source region, with a junction depth of 0.2-0.25um. At this time, the N-well region in the N+ source region is the first N-well region of the first doping region. Please refer to Fig. 9 .

[0055] In the IGBT device of the present application, along the first direction, the top of the first N-well region between each two adjacent deep trenches 110 is provided with an N+ well region 210 and a second N-well region 310 that are alternately distributed at intervals, and the N+ well region 210 and the second N-well region 310 that are alternately distributed at intervals correspond to the N+ type source region 2 and the polysilicon region 3, respectively. The polysilicon layer connected to the polysilicon gate blocks the injection of N+ (arsenic), and through the difference in diffusion coefficients of phosphorus and arsenic, only an N-ballast resistor region is formed under the polysilicon layer, and the length of the N-region is indirectly increased in the polysilicon region, thereby realizing the ballast resistor R N- The polysilicon layer is connected to the polysilicon gate in the deep trench to achieve equipotential. When the gate is pressurized, the other side of the gate oxide layer will be inverted or the electrons will be gathered into N. When the IGBT device is turned on at room temperature, the internal resistance will not increase too much. At high temperatures, the ballast resistor R N- The positive temperature coefficient can achieve ballast effect.

[0056] The purpose of selecting the ballast resistor as N-type lightly doped in this application is that at room temperature, the impurities in the single crystal silicon are completely ionized. When the temperature rises, due to the lattice vibration scattering, especially the dominant phonon scattering, the mobility decreases with the increase of temperature, so that the resistivity increases with the increase of temperature, and the temperature coefficient is positive at this time. If the ballast resistor is heavily doped with N-type, the temperature coefficient may be negative, or the positive temperature coefficient is small, and the ballast effect is poor.

[0057] In another embodiment of the present application, an IGBT device is disclosed, which includes the built-in ballast resistor described above, and also includes a collector metal layer 810, a P+ substrate 820, an emitter metal layer 830 and an ILD dielectric layer 840, one side of the P+ substrate 820 is connected to the N- substrate 100, and the other side opposite to the collector metal layer 810. One side of the ILD dielectric layer 840 faces the emitter metal layer 830, and the other side opposite to the first doping region and the second doping region.

[0058] The IGBT device sequentially deposits an ILD dielectric layer on the first doping region, the second doping region and the groove region of the built-in ballast resistor to form an ILD dielectric layer, etches contact holes (Si groove depth 0.5um), injects contact holes into the P+ well region, deposits metal, etches metal to form an emitter metal layer, and then thins the back surface on the other side of the N- substrate, injects phosphorus and boron into the back surface to form a P+ substrate, and metalizes to form a collector metal. The above steps of ILD dielectric layer deposition, contact hole etching, injection of contact hole P+ well region, metal deposition, metal etching, back surface thinning, back surface phosphorus and boron injection are the same as the corresponding steps of the existing trench gate IGBT device, and will not be repeated in this application.

[0059] Using the IGBT device of this application, when V GE >V TH When the current I C See the circuit diagram of the flow path for Figure 4 , Figure 4 In the figure, Vbi represents the voltage generated by the built-in electric field of the PN junction, R SUB Represents the substrate resistance, R CH Represents the channel resistance, R N- Represents the N-well resistance, R N+ Represents the N+ well region resistance.

[0060] Depend on Figure 4 Knowable Figure 1 The current Ic at the A-A' position and the B-B' position flows through the ballast resistor R N- . Ballast resistor R N- The value of is calculated as follows:

[0061]

[0062] in, μ n represents the electron mobility, q represents the elementary charge, t s Represents thickness, N D represents the doping concentration, p sRepresents resistivity, in Ω·cm.

[0063] In order to detect the relevant performance of the IGBT device of the present application, the IGBT device of the present application and the conventional trench gate IGBT device are used as the detection objects, and the MEDICI software is used to simulate and compare the R N- Ballast resistor (IGBT device in this application) and no R N- The 1200V trench gate IGBT short-circuit current density waveform of the ballast resistor (conventional trench gate IGBT device) is shown in the simulation comparison chart. Fig.10 .Depend on Fig.10 It can be seen that at the beginning of the short circuit, there is R N- Ballast resistor and no R N- The saturation current of the ballast resistor is not much different. As the short circuit time increases, the temperature of the device gradually increases, and the ballast resistor R N- As the temperature increases, the saturation current is forced to decrease, and finally R N- The short-circuit withstand time of a 1200V trench-gate IGBT with ballast resistor is longer than that without R N- The length of the ballast resistor.

[0064] The above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the present invention. Although the present invention is described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the purpose and scope of the technical solutions of the present invention, which should be included in the scope of the claims of the present invention. The techniques, shapes, and structural parts not described in detail in the present invention are all known technologies.

Claims

1. The built-in ballast resistor of the IGBT device is characterized by: The layout unit of the IGBT device includes a plurality of trench regions, and an N+ type source region, a polysilicon region and a contact hole region arranged between each two adjacent trench regions, at least two of the N+ type source regions, the polysilicon region and the contact hole region are provided, and the plurality of N+ type source regions and the polysilicon region are alternately arranged along a first direction, and the contact hole region is located inside the N+ type source region, and the first direction is a direction along the length of the trench region; Along the second direction, the built-in ballast resistor includes an N-substrate, and a first doped region and a second doped region arranged on the N-substrate, and a deep groove is formed by etching the corresponding groove area on the N-substrate. The second direction is along the thickness of the IGBT device; the first doped region and the second doped region are alternately arranged on the N-substrate on opposite sides of the deep groove, and the position of the first doped region corresponds to the N+ type source region, and the position of the second doped region corresponds to the polysilicon region; the top of the first doped region has an N+ well region, and the top of the second doped region has a second N-well region.

2. The built-in ballast resistor of the IGBT device according to claim 1, characterized in that: The first doped region includes a P-well region, a first N-well region and an N+ well region formed in sequence on an N-substrate, a P+ well region is arranged inside the first doped region, an upper end of the P+ well region is located inside the N+ well region, and a lower end is located inside the P-well region, and a position of the P+ well region corresponds to a contact hole region.

3. The built-in ballast resistor of the IGBT device according to claim 2, characterized in that: The concentration of arsenic ions injected into the N+ well region is 10 19 ~10 20 cm -3 .

4. The built-in ballast resistor of the IGBT device according to claim 3, characterized in that: The second doped region includes a P-well region, a first N-well region and a second N-well region sequentially formed on an N-substrate, and the first N-well region and the second N-well region have the same composition and formation conditions.

5. The built-in ballast resistor of the IGBT device according to claim 4, characterized in that: The first N-well regions in the first doping region and the second doping region are completely identical, and the phosphorus ion concentrations injected into the first N-well region and the second N-well region are 10 17 ~10 18 cm -3 .

6. The built-in ballast resistor of the IGBT device according to claim 1, characterized in that: The depth of the deep groove is 4 to 6 microns.

7. The built-in ballast resistor of the IGBT device according to claim 6, characterized in that: Polysilicon material is deposited inside the deep trench to form gate polysilicon, and polysilicon material is also deposited on the second doped region to form a polysilicon layer. The polysilicon layer covers the deep trench and the second doped region, and the polysilicon layer is connected to the gate polysilicon.

8. The built-in ballast resistor of the IGBT device according to claim 7, characterized in that: A gate oxide layer is formed between the groove wall and the groove bottom of the deep groove and the gate polysilicon, and a gate oxide layer is also formed between the polysilicon layer and the second doping area. The thickness of the gate oxide layer is 800Å~1200Å.

9. A method for preparing a built-in ballast resistor of an IGBT device, characterized in that: The following steps are involved: Providing an N-substrate, performing photolithography on the N-substrate using a mask plate to form a patterned first mask layer, wherein the first mask layer is photolithographically formed with a groove region, and etching the N-substrate corresponding to the groove region to form at least two deep grooves on the N-substrate, wherein the depth of the deep grooves is 4 to 6 microns; Thermally growing a gate oxide layer on the groove wall and the groove bottom of the deep groove and the top surface of the N-substrate, wherein the thickness of the gate oxide layer is 800Å to 1200Å; Performing boron ion implantation on the N-substrate at opposite sides of the deep trench and high-temperature junction pushing to form a P-well region, wherein the junction depth of the P-well region on the N-substrate is 2.5 to 3.5 microns; Depositing polysilicon material on the gate oxide layer, forming gate polysilicon in the deep trench, and forming a polysilicon layer outside the deep trench, using a mask plate to perform photolithography on the polysilicon layer to form a patterned second mask layer, along a first direction, the second mask layer is photolithographically formed with a plurality of N+ type source regions and polysilicon regions that are alternately distributed, etching the polysilicon layer corresponding to the N+ type source region to the gate oxide layer, and the first direction is the direction along the length of the deep trench; Phosphorus ion implantation is performed on the P-well region at a concentration of 10 17 ~10 18 cm -3 , and push the junction at 900-1000℃ for 50-70min to form an N-well region with a junction depth of 0.35-0.45 microns; Arsenic is implanted into the N-well region corresponding to the N+ source region at a concentration of 10 19 ~10 20 cm -3 , and annealed at 900-1000℃ for 20-40min to form an N+ well region with a junction depth of 0.2~0.25um.

10. An IGBT device, characterized in that: The IGBT device comprises the built-in ballast resistor according to any one of claims 1 to 8, and further comprises a collector metal layer, a P+ substrate, an emitter metal layer and an ILD dielectric layer, wherein one side of the P+ substrate is connected to the N- substrate, and the other side opposite thereto is connected to the collector metal layer; One side of the ILD dielectric layer faces the emitter metal layer, and the other side opposite thereto faces the first doping region and the second doping region.

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