Nanometer device structure and preparation method
By adopting the step-shaped top source and drain structure and interlayer dielectric layer design in CFET devices, the problem of large area of a single device in existing CFET devices is solved, and the device area is reduced without affecting the current intensity. Effect.
Patent Information
- Application Number
- CN202411540639.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-31
- Publication Date
- 2025-02-11
AI Technical Summary
The area of a single device of existing CFET devices is large, making it difficult to reduce the area of the device without affecting the current intensity.
Adopt a nanodevice structure, including a substrate, shallow trough isolation region, nanosheet channel, metal gate and source and drain, by forming a step-shaped top source and drain structure on the substrate, and on the shallow trough isolation region Part of the top source and drain electrodes are removed to form interlayer dielectric layers and conductive channels to reduce the unit area of the device.
The area of a single nano device is effectively reduced while maintaining the current intensity, avoiding the impact on the channel region.
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Figure CN119421489A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of nano devices, and in particular to a nano device structure and a preparation method thereof. Background Art
[0002] Complementary field effect transistor (CFET) is considered to be a device architecture with great potential after the 1nm CMOS technology node, in which n- and p-MOS nanosheet devices are stacked on top of each other to achieve further unit area reduction. The current mainstream manufacturing process is monolithic CFET, whose metal interconnection is carried out outside the source and drain regions, which invisibly increases the area of a single device.
[0003] Therefore, it is necessary to develop a method for preparing nanodevice structures that can effectively reduce the area of a single device.
[0004] In view of this, the present invention is proposed. Summary of the invention
[0005] The object of the present invention is to provide a nano device structure and a preparation method thereof, wherein the nano device structure can reduce the area of a single nano device without affecting the current intensity.
[0006] The first aspect of the present invention provides a nanodevice structure, comprising: a substrate, a shallow trench isolation region, a nanosheet channel, a metal gate, and a source and drain; the nanosheet channel is located above the substrate, and the metal gate surrounds the nanosheet channel; the shallow trench isolation region is located on both sides of the substrate; the source and drain are connected to the nanosheet channel; a sidewall structure is provided between the source and drain and the metal gate; the source and drain include: a bottom source and drain and a top source and drain, an isolation layer is provided between the bottom source and drain and the top source and drain, and a step-like structure is formed between the layer where the top source and drain is located and the isolation layer.
[0007] Preferably, the bottom source and drain are connected to the lower portion of the nanosheet channel; and the top source and drain are connected to the upper portion of the nanosheet channel.
[0008] Preferably, it further comprises: an interlayer dielectric layer; the interlayer dielectric layer is located above the step-shaped structure between the layer where the top source and drain are located and the isolation layer.
[0009] Preferably, the side wall structure comprises: a side wall and an inner side wall; the side wall is flush with the inner side wall.
[0010] Preferably, it further comprises: a plurality of conductive channels; the conductive channels are located inside the interlayer dielectric layer, and the conductive channels are respectively connected to the source and drain and the metal gate.
[0011] The second aspect of the present invention provides a method for preparing a nanodevice structure, comprising the following steps: after forming a top source and drain, removing a portion of the top source and drain on the single-sided shallow trench isolation region to form a step-like structure between the layer where the top source and drain are located and the isolation layer.
[0012] Preferably, the method comprises the following steps:
[0013] S1. Provide a substrate, grow a stacked layer for forming a fin structure on the substrate, form the fin structure using a graphic process, and deposit an insulating material on both sides of the fin structure to form a shallow trench isolation region.
[0014] Preferably, step S1 comprises the following steps:
[0015] S11, providing a substrate, and sequentially growing a bottom channel region, a middle isolation region, and a top channel region on the substrate by epitaxy, that is, forming a stack of fin structures;
[0016] S12, after patterning, the epitaxially grown stack is formed into a fin structure through an etching process;
[0017] S13, continue to etch the substrate downward, and deposit insulating material (preferably SiO2) on both sides of the fin structure to form a shallow trench isolation (STI).
[0018] Preferably, the bottom channel region and the top channel region are alternately grown Si layers and Si 1-x Ge x Layer, where x is 0.1-0.4.
[0019] Preferably, the intermediate isolation region is an alternately grown Ge layer and Si layer. 1-x Ge x Alternatively, the Ge layer can also be replaced by a Ge-rich SiGe layer, that is, an alternately grown Si 1-y Ge y Layer and Si 1-x Ge x Layer; where x is 0.1-0.4 and y is 0.5-1.
[0020] Preferably, the number of layers of the bottom channel region, the middle isolation region and the top channel region is not limited and can be set according to actual needs. For example, the bottom channel region and the top channel region can be 1-9 layers of Si layers and Si layers grown alternately. 1-x Ge x The middle isolation region can be 1-10 layers of Ge and Si grown alternately. 1-x Ge x layer.
[0021] Preferably, the Si layer, Si1-x Ge x layer, Ge layer, Si 1-y Ge y The single layer thickness of the layer is 10nm-100nm.
[0022] Preferably, the depth of the shallow trench isolation region is greater than 10 nm.
[0023] S2, forming a false gate across the fin structure;
[0024] Preferably, step S2 comprises the following steps:
[0025] S21, first grow an amorphous silicon (α-Si) layer, and then grow an ONO (SIO2-SiN-SiO2) layer; preferably, the total height of the dummy gate (the sum of the thickness of α-Si + ONO) is greater than 50nm;
[0026] S22, forming a dummy gate across the fin structure through photolithography and etching patterning processes.
[0027] S3, forming sidewalls on both sides of the dummy gate; etching the fin structure to form source and drain regions on both sides of the sidewalls for preparing source and drain electrodes.
[0028] Preferably, step S3 comprises the following steps:
[0029] S31, selectively etching to remove the Ge layer in the middle isolation region;
[0030] S32, filling SiN to form an intermediate dielectric isolation (MDI), and forming sidewalls on both sides of the dummy gate by anisotropic etching; preferably, the sidewall thickness is less than 50 nm;
[0031] S33, vertically etching the fin structure to remove the fin structure not protected by the sidewalls and the dummy gate, and forming source and drain regions for preparing source and drain electrodes on both sides of the sidewalls.
[0032] S4, etching part of the edge of the fin structure from the source and drain regions toward the center, so that an embedded groove is formed at the edge of the fin structure, and inner sidewalls are formed on both sides of the fin structure, and the inner sidewalls are flush with the sidewalls.
[0033] Preferably, step S4 comprises the following steps:
[0034] S41, dry selectively etch the Si of the fin structure from the source and drain regions to the center 1-x Ge x The edge of the layer makes Si 1-x Ge x The two ends of the layer form inset grooves;
[0035] S42, depositing an inner sidewall dielectric so that the inner sidewall dielectric fills the groove and covers the fin structure; the inner sidewall dielectric material is preferably silicon nitride (SiN);
[0036] S43, etching back the inner sidewall dielectric until the edge of the inner sidewall dielectric is flush with the sidewall.
[0037] S5. Epitaxial growth is performed at the bottom of the source and drain regions, and the bottom of the source and drain regions is doped to form bottom source and drain electrodes; an isolation layer is deposited on the bottom source and drain electrodes; epitaxial growth is performed at the top of the source and drain regions, and the top of the source and drain regions is doped to form top source and drain electrodes.
[0038] Preferably, one of the top source and drain and the bottom source and drain is a PMOS source and drain, and the other is an NMOS source and drain.
[0039] In a specific implementation, step S5 includes the following steps:
[0040] S51, epitaxially growing at the bottom of the source and drain regions, and doping the bottom of the source and drain regions to form PMOS source and drain;
[0041] S52, depositing an isolation layer (SiN) on the PMOS source and drain by using an atomic layer deposition (ALD) process;
[0042] S53 , epitaxially growing on the top of the source and drain regions, and doping the top of the source and drain regions to form top NMOS source and drain.
[0043] S6. Remove the dummy gate and perform channel release to form a nanosheet channel.
[0044] Preferably, step S6 comprises the following steps:
[0045] S61, removing the ONO layer in the dummy gate by dry etching, and removing the α-Si layer in the dummy gate by TMAH wet etching;
[0046] S62, selective etching to remove the Si of the fin structure 1-X Ge x layer, and perform channel release to form a nanosheet channel.
[0047] S7. Deposit a metal gate surrounding the nanosheet channel.
[0048] Preferably, step S7 comprises the following steps: depositing a high-K dielectric layer and a metal gate in sequence by an atomic layer deposition (ALD) process to form a metal gate surrounding the nanosheet channel.
[0049] Preferably, the high-K dielectric layer material includes but is not limited to HfO2, HfAlO, HfZrO and the like.
[0050] Preferably, the metal gate material includes but is not limited to W, Ta, Mo, TiN, TaN, Au, Pt, etc.
[0051] S8. Use a graphical process to remove the top source and drain electrodes on the single-sided shallow trench isolation area to form a step-like structure between the layer where the top source and drain electrodes are located and the isolation layer; fill SiO2 above the step-like structure and perform chemical mechanical polishing (CMP) to form an interlayer dielectric layer (ILD), form contact holes in the interlayer dielectric layer that are in contact with the source and drain electrodes and the metal gate, and form a conductive channel in the contact holes.
[0052] Beneficial effects:
[0053] The present invention prepares a step-type complementary field effect nanodevice structure, which can interconnect the source and drain upward, effectively reducing the unit area of the device. Moreover, since the part removed to form the step is located above the shallow trench isolation area and does not involve the channel area, it will not affect the current intensity. BRIEF DESCRIPTION OF THE DRAWINGS
[0054] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0055] Figure 1 It is a schematic diagram of the three-dimensional structure after the stacked layers are grown on the substrate of the present invention;
[0056] Figure 2 It is a schematic diagram of the three-dimensional structure after the stack is made into a fin structure in the present invention;
[0057] Figure 3 It is a schematic diagram of the three-dimensional structure after the shallow trench isolation region is formed in the present invention;
[0058] Figure 4 It is a schematic diagram of the three-dimensional structure after an amorphous silicon layer and an ONO layer are grown on the surface of the fin structure of the present invention;
[0059] Figure 5 It is a schematic diagram of the three-dimensional structure after the false gate is graphically formed in the present invention;
[0060] Figure 6 It is a schematic diagram of the three-dimensional structure after the Ge layer in the middle isolation region is selectively etched away in the present invention;
[0061] Figure 7 It is a schematic diagram of the three-dimensional structure after the side wall is formed in the present invention;
[0062] Figure 8 It is a schematic diagram of the three-dimensional structure after the source and drain regions are formed in the present invention;
[0063] Fig. 9 A process diagram of forming the inner wall of the present invention;
[0064] Fig.10 This is a schematic diagram of the three-dimensional structure after the inner wall is formed in the present invention;
[0065] Fig.11 It is a schematic diagram of the three-dimensional structure after the bottom source and drain are formed in the present invention;
[0066] Fig.12 It is a schematic diagram of the three-dimensional structure after the isolation layer is deposited in the present invention;
[0067] Fig.13 It is a schematic diagram of the three-dimensional structure after forming the top source and drain of the present invention;
[0068] Fig.14 It is a schematic diagram of the three-dimensional structure after removing the false grid etching of the present invention;
[0069] Fig.15 This is a schematic diagram of the three-dimensional structure after the nanosheet channel is formed in the present invention;
[0070] Figure 16-19 They are schematic diagrams of the three-dimensional structure after conformally growing a high-K dielectric layer, filling metal W, SiN, and metal W according to the present invention;
[0071] Fig. 20 It is a schematic diagram of the three-dimensional structure after the step-shaped structure is formed in the present invention;
[0072] Fig.21 It is a schematic diagram of the three-dimensional structure after the interlayer dielectric layer is formed in the present invention;
[0073] Fig. 22 It is a schematic diagram of the three-dimensional structure after the conductive channel is formed in the present invention;
[0074] Fig.23 A perspective view of a nanodevice structure prepared by the present invention.
[0075] Explanation of the reference numerals: 1. substrate; 2. bottom channel region; 3. middle isolation region; 4. top channel region; 5. shallow trench isolation region; 6. dummy gate; 7-1. side wall; 7-2. inner side wall; 8. bottom source and drain; 9. isolation layer; 10. top source and drain; 11. nanosheet channel; 12. high-K dielectric layer; 13. metal W; 14. SiN; 15. interlayer dielectric layer; 16. conductive channel. DETAILED DESCRIPTION
[0076] It should be noted that the following detailed descriptions are illustrative and are intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present application belongs.
[0077] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form also includes the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.
[0078] The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0079] Example
[0080] The present embodiment provides a nanodevice structure, characterized in that it includes: a substrate 1, a shallow trench isolation region 5, a nanosheet channel 11, a metal gate, and a source and drain; the nanosheet channel 11 is located above the substrate 1, and the metal gate surrounds the nanosheet channel 11; the shallow trench isolation region 5 is located on both sides of the substrate 1; the source and drain are connected to the nanosheet channel 11; a side wall 7-1 structure is arranged between the source and drain and the metal gate; the source and drain include: a bottom source and drain 8 and a top source and drain 10, an isolation layer 9 is provided between the bottom source and drain 8 and the top source and drain 10, and a step-like structure is formed between the layer where the top source and drain 10 is located and the isolation layer 9.
[0081] In this embodiment, the bottom source and drain electrode 8 is connected to the lower part of the nanosheet channel 11 ; and the top source and drain electrode 10 is connected to the upper part of the nanosheet channel 11 .
[0082] In this embodiment, it also includes: an interlayer dielectric layer 15 ; the interlayer dielectric layer 15 is located above the step-shaped structure between the layer where the top source and drain electrodes 10 are located and the isolation layer 9 .
[0083] In this embodiment, it also includes: a plurality of conductive channels 16; the conductive channels 16 are located inside the interlayer dielectric layer 15, and the conductive channels 16 are respectively connected to the source, drain and metal gate.
[0084] This embodiment also provides a method for preparing a nanodevice structure, comprising the following steps:
[0085] S1, providing a substrate 1, growing a stacked layer for forming a fin structure on the substrate 1, forming the fin structure by a patterning process, and depositing an insulating material on both sides of the fin structure to form a shallow trench isolation region 5;
[0086] S2, forming a dummy gate 6 across the fin structure;
[0087] S3, forming sidewalls 7-1 on both sides of the dummy gate 6; etching the fin structure to form source and drain regions for preparing source and drain electrodes on both sides of the sidewalls 7-1;
[0088] S4, etching part of the edge of the fin structure from the source and drain regions toward the center, so that an embedded groove is formed at the edge of the fin structure, and inner sidewalls 7-2 are formed on both sides of the fin structure, and the inner sidewalls 7-2 are flush with the sidewalls 7-1;
[0089] S5, epitaxially growing at the bottom of the source and drain region, and doping the bottom of the source and drain region to form a bottom source and drain electrode 8; depositing an isolation layer 9 on the bottom source and drain electrode 8; epitaxially growing at the top of the source and drain region, and doping the top of the source and drain region to form a top source and drain electrode 10;
[0090] S6, removing the dummy gate 6, and performing channel release to form a nanosheet channel 11;
[0091] S7, depositing a metal gate surrounding the nanosheet channel 11;
[0092] S8. Use a graphical process to remove part of the top source and drain 10 on the single-sided shallow trench isolation area 5, so that a step-like structure is formed between the layer where the top source and drain 10 is located and the isolation layer 9; deposit an interlayer dielectric layer 15 above the step-like structure, form contact holes in the interlayer dielectric layer 15 that are in contact with the source and drain and the metal gate respectively, and form a conductive channel 16 in the contact hole.
[0093] The preparation method of this embodiment is described in more detail below:
[0094] For step S1, Figure 1 As shown, a bottom channel region 2, a middle isolation region 3 and a top channel region 4 are sequentially grown on a silicon substrate 1 by epitaxy, that is, a stacked layer for forming a fin structure; the bottom channel region 2 and the top channel region 4 are both alternately grown Si layers (1 layer) and Si 1-x Ge x Layer (1 layer), in this embodiment, x is 0.3; the middle isolation region 3 is an alternately grown Ge layer (2 layers) and Si 1-x Ge x Layer (2 layers), in this embodiment, x is 0.3. Figure 2 As shown, after patterning, the epitaxially grown stack is made into a fin structure through an etching process. Figure 3As shown, the substrate 1 is further etched downwards, and SiO2 is deposited on both sides of the fin structure to form a shallow trench isolation region 5 (STI), with a depth of more than 10 nm.
[0095] For step S2, Figure 4 As shown, the amorphous silicon (α-Si) layer is first grown, and then the ONO (SIO2-SiN-SiO2) layer is grown. The sum of the thickness of the α-Si+ONO layers is above 50nm. Figure 5 As shown, a dummy gate 6 across the fin structure is formed by photolithography and etching patterning processes.
[0096] For step S3, Figure 6 As shown, the Ge layer in the middle isolation region 3 is removed by selective etching. Figure 7 As shown, SiN is filled to form an intermediate dielectric isolation (MDI), and a sidewall 7-1 is formed on both sides of the dummy gate 6 by anisotropic etching. The thickness of the sidewall 7-1 is less than 50nm. Figure 8 As shown, the fin structure is vertically etched to remove the fin structure not protected by the sidewall 7 - 1 and the dummy gate 6 , and source and drain regions for preparing source and drain electrodes are formed on both sides of the sidewall 7 - 1 .
[0097] For step S4, Fig. 9 As shown, the Si of the fin structure is selectively etched laterally from the source and drain regions toward the center by dry etching. 1- x Ge x The edge of the layer makes Si 1-x Ge x The two ends of the layer form an embedded groove; deposit the inner side wall 7-17-2 dielectric SiN, so that the SiN fills the groove and covers the fin structure; the inner side wall 7-2 dielectric is etched back until the edge of the inner side wall 7-2 dielectric is flush with the side wall 7-1 (such as Fig.10 shown).
[0098] For step S5, Fig.11 As shown, epitaxial growth is performed at the bottom of the source and drain regions, and at the same time, the bottom of the source and drain regions are doped to form p + Area, do PMOS source and drain. Fig.12 As shown, an isolation layer 9 (SiN) is deposited on the PMOS source and drain using an atomic layer deposition process (ALD). Fig.13 As shown, epitaxial growth is performed on the top of the source and drain regions, and at the same time, the top of the source and drain regions are doped to form n + Area, used as NMOS source and drain.
[0099] For step S6, Fig.14 As shown, the ONO layer in the dummy gate 6 is removed by dry etching, and the α-Si layer in the dummy gate 6 is removed by TMAH wet etching. Fig.15 As shown, selective etching is used to remove the Si of the fin structure. 1-X Ge x layer, and performing channel release to form a nanosheet channel 11.
[0100] For step S7, Figure 16-19 As shown, a high-K dielectric layer 12 is conformally grown by an atomic layer deposition (ALD) process, and then metal W13, SiN14, and metal W13 are filled in sequence to form a metal gate surrounding the nanosheet channel 11.
[0101] For step S8, Fig. 20 As shown, a graphic process is used to remove a portion of the top source and drain electrode 10 on the single-sided shallow trench isolation region 5, so that a step-like structure is formed between the layer where the top source and drain electrode 10 is located and the isolation layer 9. Fig.21 As shown, SiO2 is filled on the stepped structure and chemical mechanical polishing (CMP) is performed to planarize the structure to form an interlayer dielectric layer 15 (ILD). Figure 22-23 As shown, contact holes are formed in the interlayer dielectric layer 15 to contact the source, drain and metal gate respectively, and a conductive channel 16 is formed in the contact hole, and the conductive channel 16 is connected to the source, drain and metal gate respectively.
[0102] This embodiment constructs a step-type complementary field effect transistor CFET. The source and drain electrodes can be interconnected upward, effectively reducing the unit area of the device. Because the portion removed to form the step is located above the shallow trench isolation region and does not involve the channel region, it will not affect the current intensity.
[0103] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.
[0104] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A nanodevice structure, characterized in that: include: A substrate, a shallow trench isolation region, a nanosheet channel, a metal gate, and a source and drain; the nanosheet channel is located above the substrate, and the metal gate surrounds the nanosheet channel; The shallow trench isolation region is located on both sides of the substrate; The source and drain are connected to the nanosheet channel; a sidewall structure is arranged between the source and drain and the metal gate; the source and drain include: a bottom source and drain and a top source and drain, an isolation layer is arranged between the bottom source and drain and the top source and drain, and a step-like structure is formed between the layer where the top source and drain is located and the isolation layer.
2. The nanodevice structure according to claim 1, characterized in that: The bottom source and drain are connected to the lower part of the nanosheet channel; and the top source and drain are connected to the upper part of the nanosheet channel.
3. The nanodevice structure according to claim 1, characterized in that: Also includes: Interlayer dielectric layer; the interlayer dielectric layer is located above the step-shaped structure between the layer where the top source and drain are located and the isolation layer.
4. The nanodevice structure according to claim 3, characterized in that: Also includes: Multiple conductive channels; The conductive channel is located inside the interlayer dielectric layer, and the conductive channel is connected to the source and drain and the metal gate respectively.
5. The method for preparing a nanodevice structure according to any one of claims 1 to 4, characterized in that: The method comprises the following steps: after forming the top source and drain, removing the upper part of the top source and drain in the single-side shallow trench isolation region, so as to form a step-shaped structure between the layer where the top source and drain are located and the isolation layer.
6. The method for preparing a nanodevice structure according to claim 5, characterized in that: The steps include: S1. providing a substrate, growing a stack for forming a fin structure on the substrate, forming the fin structure by a patterning process, and depositing an insulating material on both sides of the fin structure to form a shallow trench isolation region; S2, forming a false gate across the fin structure; S3, forming sidewalls on both sides of the dummy gate; etching the fin structure to form source and drain regions on both sides of the sidewalls for preparing source and drain electrodes; S4, etching the edge of a portion of the fin structure from the source and drain regions toward the center, so that an embedded groove is formed at the edge of the fin structure, and inner sidewalls are formed on both sides of the fin structure, and the inner sidewalls are flush with the sidewalls; S5, epitaxially growing at the bottom of the source and drain regions, and doping the bottom of the source and drain regions to form bottom source and drain electrodes; depositing an isolation layer on the bottom source and drain electrodes; epitaxially growing at the top of the source and drain regions, and doping the top of the source and drain regions to form top source and drain electrodes; S6, removing the dummy gate and performing channel release to form a nanosheet channel; S7, depositing a metal gate surrounding the nanosheet channel; S8. Use a graphical process to remove the top source and drain electrodes on the single-sided shallow trench isolation area, so that a step-like structure is formed between the layer where the top source and drain electrodes are located and the isolation layer; deposit an interlayer dielectric layer above the step-like structure, form contact holes in the interlayer dielectric layer that are in contact with the source and drain electrodes and the metal gate, and form a conductive channel in the contact holes.
7. The method for preparing a nanodevice structure according to claim 6, characterized in that: The stack includes: a bottom channel region, a middle isolation region and a top channel region which are grown in sequence.
8. The method for preparing a nanodevice structure according to claim 7, characterized in that: The intermediate isolation region is composed of Ge layers and Si layers grown alternately. 1-x Ge x layers, or, alternately grown Si 1-y Ge y Layer and Si 1-x Ge x Layer; where x is 0.1-0.4 and y is 0.5-1.
9. The method for preparing a nanodevice structure according to claim 7, characterized in that: The bottom channel region and the top channel region are alternately grown Si layers and Si 1-x Ge x Layer, where x is 0.1-0.
4.
10. The method for preparing a nanodevice structure according to claim 6, characterized in that: One of the top source and drain and the bottom source and drain is a PMOS source and drain, and the other is an NMOS source and drain.