Solar cell, manufacturing method thereof and photovoltaic module

Abstract

The invention discloses a solar cell and a manufacturing method thereof, and a photovoltaic module, and the solar cell comprises a semiconductor substrate which is provided with a first surface and a second surface which are opposite to each other; the first semiconductor layer is arranged on the first face, the first semiconductor layer comprises a first part and a second part adjacent to the first part in the second direction, the crystallization degree of the first part is larger than that of the second part, and the first semiconductor layer comprises at least one of amorphous silicon, nanocrystalline silicon and microcrystalline silicon. According to the solar cell, the reasonable crystallization area and the non-crystallization area are arranged on the first semiconductor layer, the overall cell efficiency of the solar cell is optimized and improved by means of the high crystallization degree of the first part, and meanwhile the passivation effect of the second part is guaranteed and electric leakage is prevented by means of the low crystallization degree of the second part.

Description

[0001] This application claims the priority of the Chinese patent filed with the China Patent Office on July 26, 2024, with application number 202411017051.5 and application name “A solar cell and its manufacturing method, photovoltaic module”, all contents of which are incorporated by reference in this application. Technical Field

[0002] The present invention relates to the field of photovoltaic technology, and in particular to a solar cell and a manufacturing method thereof, and a photovoltaic module. Background Art

[0003] In the solar cell structure, the semiconductor layer on the velvet surface is treated with laser. Some semiconductor layer materials contain hydrogen. The semiconductor layer containing hydrogen heats up after absorbing light, and the H in the semiconductor layer escapes, increasing the effective doping. After the laser action, the contact resistance of the solar cell can be reduced, thereby reducing the energy loss in the current collection process and improving the battery efficiency. However, if the laser treatment area is unreasonable, it will lead to a greater risk of leakage in some areas of the solar cell, affecting the battery efficiency. Summary of the invention

[0004] The object of the present invention is to provide a solar cell and a method for manufacturing the same, and a photovoltaic module, so as to reduce contact resistance, reduce leakage risk, and improve battery efficiency.

[0005] In order to achieve the above objectives, this application provides the following technical solutions:

[0006] A solar cell comprising:

[0007] A semiconductor substrate having a first surface and a second surface opposite to each other;

[0008] The first semiconductor layer is arranged on the first surface, and the first semiconductor layer includes a first part and a second part adjacent to the first part along a second direction. The degree of crystallization of the first part is greater than that of the second part. The first semiconductor layer includes at least one of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon.

[0009] In the case of adopting the above technical solution, a crystallized structure is formed in the first part of the first semiconductor layer, so that the first part has a crystallized part and another part that is not crystallized. The first part is not entirely a crystallized structure, but mostly an amorphous structure, and only a part forms a crystallized structure, such as nanocrystal, while the second part of the first semiconductor layer adjacent to the first part along the second direction is not crystallized, retaining the original amorphous structure (it should be noted that when the first semiconductor layer includes nanocrystalline silicon and microcrystalline silicon, the crystallization degree or crystallinity of the nanocrystalline silicon and microcrystalline silicon of the second part remains unchanged), so that the overall crystallization degree of the first part of the first semiconductor layer is greater than the overall crystallization degree of the second part. It can be understood that, under the same other factors, when the crystallization degree of the semiconductor layer is smaller, the grains in the semiconductor layer are smaller, and even present the disorder of amorphous silicon material. The smaller the grains in the semiconductor layer, the more interfaces between the grains in the semiconductor layer, so the resistance of the grain interface will be larger. Therefore, the crystallization structure in the first part of the first semiconductor layer reduces the contact resistance, reduces the contact resistance between the first part and the conductive material (transparent conductive layer or electrode), and thus helps to reduce the transmission loss of the carriers collected in the first semiconductor layer to the conductive material. At the same time, the degree of crystallization of the second part of the first semiconductor layer is less than that of the first part, which ensures the passivation effect of the second part adjacent to the first part along the second direction, and reduces the recombination of the edge of the first semiconductor layer, that is, for the back contact solar cell, the second part of the first semiconductor layer is close to the second semiconductor, and the degree of crystallization of the second part is small to ensure the passivation effect of the second part, and prevent leakage between the second part and the second semiconductor layer. It can be seen from the above that by setting a reasonable crystallization area and amorphization area on the first semiconductor layer, the higher degree of crystallization of the first part is used to optimize the overall cell efficiency of the solar cell, improve the cell efficiency, and at the same time, the lower degree of crystallization of the second part is used to ensure the passivation effect of the second part and prevent leakage.

[0010] In one implementation, the solar cell further includes a second semiconductor layer disposed on the first surface, the first semiconductor layer and the second semiconductor layer are arranged adjacent to each other along the second direction, the first semiconductor layer and the second semiconductor layer have different conductivity types; and along the second direction, the second portion is closer to the second semiconductor layer than the first portion; the second semiconductor layer has an adjacent side surface close to the first semiconductor layer. With the above technical solution, for a back-contact solar cell, the second portion of the first semiconductor layer is closer to the second semiconductor layer, and the crystallization degree of the second portion is relatively low to ensure the passivation effect of the second portion, thereby preventing leakage between the second portion and the second semiconductor layer and reducing the photoelectric conversion efficiency of the solar cell.

[0011] In one implementation, along the second direction, the second portion extends from the edge of the first portion to near the adjacent side surface, but does not contact the adjacent side surface. With this technical solution, the second portion does not contact the second semiconductor layer, and the distance between the second portion and the second semiconductor layer is large, which is conducive to further reducing the leakage risk between the second portion and the second semiconductor layer.

[0012] In one implementation, along the second direction, the second portion extends from the edge of the first portion to the adjacent side surface and contacts the adjacent side surface. With this technical solution, the second portion overlaps at least part of the adjacent side surface of the second semiconductor layer, and the second portion has a lower degree of crystallization, so that a weaker current can be transmitted through the second portion and the adjacent side surface of the second semiconductor layer. When the solar cell is blocked, the current can form a leakage channel through the second portion and the adjacent side surface of the second semiconductor layer, thereby preventing the blocked cell from becoming a load that consumes the energy generated by other illuminated cells, thereby reducing the risk of hot spots.

[0013] In one implementation, along the second direction, the distance between the edge of the first part and the adjacent side surface is greater than or equal to 20 μm. This arrangement can ensure that the first part with stronger transmission circuit capability is farther away from the second semiconductor layer, reducing the risk of leakage between the first part and the second semiconductor layer.

[0014] In one implementation, a portion of the second portion is disposed on the second semiconductor layer to form an overlapping portion, and the second portion extends from the edge of the first portion to the overlapping portion along the second direction. In this technical solution, the second portion is extended from the edge of the first portion to the overlapping portion, which can increase the ability to transmit current between the second portion and the second semiconductor layer. When the solar cell is blocked, the current can form a leakage channel through the second portion and the surface of the second semiconductor layer away from the semiconductor substrate. The leakage channel has a stronger ability to transmit current, further reducing the risk of hot spots.

[0015] In one implementation, the width of the second portion along the second direction is less than or equal to 500 μm and greater than or equal to 20 μm. In this configuration, if the second portion is too large, for example, greater than 500 μm, it will block more of the second semiconductor layer, and it will not be able to form effective current collection of the second semiconductor layer, and the leakage channel will be too large, resulting in a large loss of battery efficiency; if the second portion is too small, for example, less than 20 microns, the laser will be difficult to control and may irradiate other parts (such as the second semiconductor layer), causing damage to other parts.

[0016] In one implementation, the solar cell further includes a first transparent conductive layer covering the first semiconductor layer, and the projection of the first portion on the semiconductor substrate is completely within the projection of the first transparent conductive layer on the semiconductor substrate. In this way, by providing the first transparent conductive layer, the carrier transmission capacity of the first semiconductor layer is improved, and a good ohmic contact can be formed with the electrode, thereby improving the conductivity. The first portion having a crystallized structure does not exceed the boundary of the first transparent conductive layer, thereby reducing the contact resistance within the effective conductive area of ​​the first transparent conductive layer, improving the conductivity, and improving the battery efficiency.

[0017] In one implementation, along the second direction, the first transparent conductive layer extends to the adjacent side surface or to the second portion located on the second semiconductor layer. In this way, the first transparent conductive layer can cover a larger area of ​​the first semiconductor layer, further improving the conductive performance.

[0018] In one implementation, the solar cell further includes a second transparent conductive layer, which covers the second semiconductor layer; a PN isolation region is provided between the second transparent conductive layer and the first transparent conductive layer, and the PN isolation region is located on the second semiconductor layer. The electrical insulation between the P region and the N region is achieved by the PN isolation region, and the projection of the first part is located within the boundary of the first transparent conductive layer, so the first part will not enter the boundary of the PN isolation region, and the irradiation range of the laser will not enter the PN isolation region. Since the PN isolation region does not have a crystallized structure or has a low degree of crystallization, the electrical insulation effect of the PN isolation region is guaranteed.

[0019] In one implementation, a portion of the second portion is disposed on the second semiconductor layer to form an overlapping portion, and the PN isolation region is disposed on the overlapping portion.

[0020] In one implementation, the solar cell further includes a third semiconductor layer disposed on the second surface, the material of the third semiconductor layer includes at least one of polycrystalline silicon, amorphous silicon, nanocrystalline silicon or microcrystalline silicon, and the third semiconductor layer is of a different conductivity type from the first semiconductor layer. In this arrangement, when the third semiconductor layer includes an amorphous silicon layer, both sides of the semiconductor substrate are provided with a full-surface amorphous silicon layer, and the amorphous silicon layers on both sides can form a heterojunction structure, thereby forming a double-sided heterojunction cell. When the third semiconductor layer includes polycrystalline silicon, a polycrystalline silicon layer passivation structure can be formed on the second surface, and an amorphous silicon layer or a nanocrystalline silicon layer passivation structure can be formed on the first surface, thereby forming a double-sided hybrid cell. As long as there is an amorphous silicon layer and / or a nanocrystalline silicon layer, the double-sided heterojunction cell and the double-sided hybrid cell can also be applied to the cell structure in which the edge is an amorphous structure and the middle region is a crystallized structure in the present application to improve the cell efficiency.

[0021] In one implementation, the first part and the second part are both extended in a strip shape along the first direction, and the first direction and the second direction intersect. Specifically, the first part and the second part are arranged in a strip shape that is approximately parallel, so that they can gradually move along the first direction during laser irradiation, which is conducive to the laser irradiation formation of the first part.

[0022] In one implementation, the contact resistance of the first portion is less than the contact resistance of the second portion. Since the first portion may have a crystallized structure and the second portion is an amorphous structure, the effective doping of the crystallized structure of the first portion is increased, and the contact resistance of the first portion may be reduced relative to the second portion, thereby reducing the energy loss during the current collection process of the first portion and improving the battery efficiency.

[0023] In one implementation, the first portion extends along the first direction to the edge of the first surface, so that the area of ​​the first portion can be increased as much as possible, the contact resistance can be reduced, and the current collection capability can be improved.

[0024] In one implementation, the second portion surrounds the first portion. In this configuration, the second portion surrounding the first portion has a lower degree of crystallization, which can further reduce the risk of leakage and ensure the photoelectric conversion efficiency of the solar cell.

[0025] In one implementation, the material of the first part includes amorphous silicon and nanocrystalline silicon, and the material of the second part is amorphous silicon, so that the second part has a better passivation effect, and by setting reasonable crystallization areas and amorphization areas on the first semiconductor layer, the overall cell efficiency of the solar cell is optimized and the cell efficiency is improved.

[0026] In one implementation, the semiconductor substrate includes a concave portion on the first surface, the concave portion is concave relative to the rest of the first surface toward the second surface, and the first portion is located within the concave portion. In this configuration, the concave portion is formed by etching the surface of the semiconductor substrate, and generally has a velvet structure. The first portion having amorphous silicon, nanocrystalline silicon, and / or microcrystalline silicon is disposed in the concave portion to increase the contact area of ​​the first portion, which is beneficial to current collection.

[0027] A photovoltaic assembly comprises a solar cell, wherein the solar cell is any one of the solar cells described above.

[0028] Since the photovoltaic module adopts the solar cell of the first aspect and any one of the above items, the photovoltaic module has the same beneficial effects as the first aspect, which will not be described in detail here.

[0029] The present invention also provides a method for manufacturing a solar cell, comprising:

[0030] Providing a semiconductor substrate, the semiconductor substrate having a first surface and a second surface opposite to each other;

[0031] forming a first semiconductor layer on the first surface, wherein the first semiconductor layer comprises at least one of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon;

[0032] The first part of the first semiconductor layer is irradiated with laser, and the second part of the first semiconductor layer is not irradiated, so that the degree of crystallization of the first part is greater than the degree of crystallization of the second part; the first region is adjacent to the second region along the second direction. In the case of the above technical solution, the region corresponding to the first part of the first semiconductor layer is crystallized by laser, so that the degree of crystallization is improved, and the region corresponding to the second part of the first semiconductor layer adjacent to the first part is not irradiated with laser, and the amorphous structure is retained (it should be noted that when the first semiconductor layer includes nanocrystalline silicon and microcrystalline silicon, the degree of crystallization or crystallinity of the nanocrystalline silicon and microcrystalline silicon of the second part remains unchanged), so that the overall degree of crystallization of the first part of the first semiconductor layer is greater than the overall degree of crystallization of the second part. It can be understood that, under the same other factors, when the degree of crystallization of the semiconductor layer is smaller, the grains in the semiconductor layer are smaller, and even the disorder of amorphous silicon material is presented. The smaller the grains in the semiconductor layer, the more interfaces between the grains in the semiconductor layer, so the resistance of the grain interface will be larger. Therefore, the crystallization structure in the first part of the first semiconductor layer reduces the contact resistance, reduces the contact resistance between the first part and the conductive material (transparent conductive layer or electrode), and thus helps to reduce the transmission loss of the carriers collected in the first semiconductor layer to the conductive material. At the same time, the degree of crystallization of the second part of the first semiconductor layer is less than that of the first part, which ensures the passivation effect of the second part adjacent to the first part along the second direction, and reduces the recombination of the edge of the first semiconductor layer, that is, for the back contact solar cell, the second part of the first semiconductor layer is close to the second semiconductor, and the degree of crystallization of the second part is small to ensure the passivation effect of the second part, and prevent leakage between the second part and the second semiconductor layer. It can be seen from the above that by setting a reasonable crystallization area and amorphization area on the first semiconductor layer, the higher degree of crystallization of the first part is used to optimize the overall cell efficiency of the solar cell, improve the cell efficiency, and at the same time, the lower degree of crystallization of the second part is used to ensure the passivation effect of the second part and prevent leakage.

[0033] In one implementation, the first semiconductor layer is an amorphous silicon layer, and after the first portion is irradiated with laser, a portion of the amorphous silicon layer is partially crystallized to form nanocrystalline grains. If the first semiconductor layer is an amorphous silicon layer, the portion not irradiated with laser has a better passivation effect, and the insulation effect in the isolation region is better.

[0034] In one implementation, before using the laser to irradiate the first portion, a second semiconductor layer is formed on the first surface, the first semiconductor layer and the second semiconductor layer are arranged adjacent to each other along the second direction, the first semiconductor layer and the second semiconductor layer have different conductivity types, and the second semiconductor layer has an adjacent side surface close to the first semiconductor layer, and the second portion is closer to the second semiconductor layer than the first portion. For a back-contact solar cell, the second portion of the first semiconductor layer is closer to the second semiconductor layer, and the second portion has a lower degree of crystallization to ensure the passivation effect of the second portion, thereby preventing leakage between the second portion and the second semiconductor layer and reducing the photoelectric conversion efficiency of the solar cell.

[0035] In one implementation, the first portion extends along a first direction and is in a strip shape, and irradiating the first portion with a laser comprises: irradiating the first portion with a laser along the first direction, and along a second direction, a starting or ending position of the laser has a first distance from an adjacent side surface. An end of the second portion facing away from the first portion is spaced a certain distance from the adjacent side surface. The second portion does not contact the second semiconductor layer, and a large distance between the second portion and the second semiconductor layer is provided, which is conducive to further reducing the leakage risk between the second portion and the second semiconductor layer.

[0036] In one implementation, along the first direction, the starting or ending position of the laser has a second distance from the boundary of the first semiconductor layer. The second distance is the extension distance of the second portion along the first direction, and the second distance prevents the two ends of the first semiconductor layer along the first direction from being irradiated with laser, retaining the amorphous structure, thereby ensuring the passivation effect at the edge portion and reducing the recombination of the edge portion.

[0037] In one implementation, the second distance is greater than the first distance.

[0038] In one implementation, the wavelength of the laser is 325 nm to 532 nm; and / or the energy density of the laser is 200 mJ / cm 2 ~6000mJ / cm 2 . By setting this wavelength range, it can be absorbed by the amorphous semiconductor layer, which is conducive to the crystallization of the amorphous semiconductor layer. If the laser energy density is too high, the high temperature range will expand, and the temperature at the top of the velvet structure will be too high, thereby affecting the passivation of the top area of ​​the velvet structure. If the laser energy density is too small, the energy accumulation time is too long, affecting production efficiency, and the energy may not reach the energy required for crystallization. Therefore, by selecting the laser energy density in this range, it is possible to achieve high temperature only at the top of the velvet structure, achieve morphological changes, and form a crystallized structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0040] Figure 1 A schematic diagram of a solar cell provided in an embodiment of the present application;

[0041] Figure 2 A schematic diagram of another solar cell provided in an embodiment of the present application;

[0042] Figure 3 A schematic diagram of a partial arrangement of a transparent conductive layer on a first surface of a solar cell provided by an embodiment of the present invention;

[0043] Figure 4 Provided in the embodiments of this application Figure 3 A partial enlarged view of

[0044] Figure 5 for Figure 4 Schematic cross-sectional view of the BB section in FIG.

[0045] Figure 6 for Figure 4 Schematic cross-sectional view of section AA in FIG.

[0046] Figure 7-Figure 18 A schematic flow chart of each step of a method for manufacturing a solar cell provided by an embodiment of the present invention;

[0047] Fig.19 A schematic diagram showing a comparison of EL test images of a solar cell provided by an embodiment of the present invention and a conventional solar cell without a crystallization region;

[0048] Fig. 20 A schematic diagram showing a comparison of the P-region contact resistance of a solar cell provided by an embodiment of the present invention and a conventional solar cell without a crystallization region;

[0049] Fig.21 A schematic diagram of the crystallization of the top of a pyramid provided in an embodiment of the present invention.

[0050] Reference numerals:

[0051] 100 is a first semiconductor layer, 1 is a first strip portion, 11 is a first part, 12 is a second part, 13 is an intrinsic amorphous silicon layer, 14 is a p-type amorphous silicon layer, 15 is an overlapping part, 2 is a second semiconductor layer, 21 is a tunneling oxide layer, 22 is an n-type doped polysilicon layer, 23 is an intrinsic polysilicon layer, 24 is a phosphosilicate glass layer, 25 is a silicon nitride mask layer, 3 is an edge isolation region, 4 is a first gate line electrode, 5 is a second gate line electrode, 6 is a semiconductor substrate, 7 is a transparent conductive layer, 71 is a first transparent conductive layer, 72 is a second transparent conductive layer, 73 is a third transparent conductive layer, 8 is a passivation layer, 9 is an anti-reflection layer, and 10 is a PN isolation region. DETAILED DESCRIPTION

[0052] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0053] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0054] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "multiple" means two or more, unless otherwise clearly and specifically defined. "Several" means one or more, unless otherwise clearly and specifically defined.

[0055] In the description of the present application, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", etc., indicating directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present application.

[0056] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0057] like Figure 1-Figure 6 As shown, an embodiment of the present invention provides a solar cell, comprising a semiconductor substrate 6 and a first semiconductor layer 100; wherein the semiconductor substrate 6 has a first surface and a second surface opposite to each other; and the first semiconductor layer 100 is disposed on the first surface of the semiconductor substrate 6. The first semiconductor layer 100 comprises a first portion 11 and a second portion 12, wherein the first portion 11 and the second portion 12 are adjacent to each other along a second direction. That is, along the second direction, both sides of the first portion 11 are adjacent to the second portion 12, or one side of the first portion 11 is adjacent to the second portion 12.

[0058] The degree of crystallization of the first part 11 is greater than the degree of crystallization of the second part 12. The first semiconductor layer 100 includes at least one of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon, that is, the first semiconductor layer 100 can be an amorphous silicon layer, a nanocrystalline silicon layer, or a microcrystalline silicon layer. Alternatively, the first semiconductor layer 100 can also be a combination of any two or three of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon. After laser crystallization, the degree of crystallization of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon can be improved. Exemplarily, when the first semiconductor layer 100 is an amorphous silicon layer, the laser crystallized part will partially crystallize inside the amorphous silicon layer to form nanocrystalline grains. Nanocrystalline silicon refers to a crystallized structure in which most of the grain size is in the nanometer size, for example, the grain size is below 200nm. When the first semiconductor layer 100 includes a nanocrystalline silicon layer or a microcrystalline silicon, the crystallinity or degree of crystallization of the first semiconductor layer 100 will increase in the laser crystallized part.

[0059] In the actual application process, the embodiment of the present invention does not specifically limit the material and conductivity type of the semiconductor substrate 6. For example, the semiconductor substrate 6 can be a silicon substrate. Alternatively, the semiconductor substrate 6 can also be a substrate made of any semiconductor material such as a germanium silicon substrate, a germanium substrate or a gallium arsenide substrate. The conductivity type of the semiconductor substrate 6 can be an N-type semiconductor substrate, a P-type semiconductor substrate or an intrinsic semiconductor substrate.

[0060] Secondly, the semiconductor substrate 6 has a first surface and a second surface opposite to each other. The first surface of the semiconductor substrate 6 may correspond to the light-facing surface of the solar cell, and the second surface of the semiconductor substrate 6 may correspond to the backlight surface of the solar cell; or the first surface of the semiconductor substrate 6 may correspond to the backlight surface of the solar cell, and the second surface of the semiconductor substrate 6 may correspond to the light-facing surface of the solar cell.

[0061] In the case of adopting the above technical solution, a crystallized structure is formed in the first part 11 of the first semiconductor layer 100, so that the first part 11 has a crystallized part and another part that is not crystallized. The first part 11 is not entirely a crystallized structure, but mostly an amorphous structure, and only a part forms a crystallized structure, such as nanocrystal, while the second part 12 of the first semiconductor layer 100 adjacent to the first part 11 along the second direction is not crystallized, and the original amorphous structure is retained (it should be noted that when the first semiconductor layer 100 includes nanocrystalline silicon and microcrystalline silicon, the crystallization degree or crystallinity of the nanocrystalline silicon and microcrystalline silicon of the second part 12 remains unchanged), so that the overall crystallization degree of the first part 11 of the first semiconductor layer 100 is greater than the overall crystallization degree of the second part 12. It can be understood that, under the same other factors, when the crystallization degree of the semiconductor layer is smaller, the grains in the semiconductor layer are smaller, and even the disorder of the amorphous silicon material is presented. The smaller the grains in the semiconductor layer, the more interfaces between the grains in the semiconductor layer, so the resistance of the grain interface will be larger. Therefore, the crystallized structure in the first portion 11 of the first semiconductor layer 100 reduces the contact resistance, reduces the contact resistance between the first portion 11 and the conductive material (transparent conductive layer or electrode), and thus helps to reduce the transmission loss of the carriers collected in the first semiconductor layer 100 to the conductive material. At the same time, the degree of crystallization of the second portion 12 of the first semiconductor layer 100 is less than that of the first portion 11, which ensures the passivation effect of the second portion 12 adjacent to the first portion 11 along the second direction, and reduces the recombination of the edge of the first semiconductor layer 100, that is, for the back contact solar cell, the second portion 12 of the first semiconductor layer 100 is close to the second semiconductor, and the degree of crystallization of the second portion 12 is small to ensure the passivation effect of the second portion 12, and prevent leakage between the second portion 12 and the second semiconductor layer 2. It can be seen from the above that by setting reasonable crystallization areas and amorphization areas on the first semiconductor layer 100, the higher degree of crystallization of the first part 11 is utilized to optimize the overall cell efficiency of the solar cell and improve the cell efficiency. At the same time, the lower degree of crystallization of the second part 12 is utilized to ensure the passivation effect of the second part 12 and prevent leakage.

[0062] It can be understood that when at least a portion of the first surface of the semiconductor substrate 6 is a velvet surface, a plurality of pyramid-like structures are formed on the velvet surface. Fig.21As shown, the first semiconductor layer 100 is conformally disposed on the velvet surface, and the crystallization degree of the portion of the first semiconductor layer 100 covering at least a portion of the top of the pyramid-like surface is greater than the crystallization degree of another portion of the first semiconductor layer 100 covering the base of the pyramid-like surface. In the process of observing the crystallization degree of the first semiconductor layer 100, if the observed area is too small, the crystallization degree of the first semiconductor layer 100 cannot be accurately obtained by observing only the base area of ​​the pyramid-like surface. Therefore, the observed area should contain at least one pyramid-like surface. Preferably, the observed area should be greater than or equal to 5*5μm 2 This is to prevent the crystallization degree of the first semiconductor layer 100 from being inaccurately obtained by observing only the pyramid-like base region.

[0063] In some possible implementations, the contact resistance of the first portion 11 is less than the contact resistance of the second portion 12. Since the first portion 11 has a crystallized structure or a higher degree of crystallization, and the second portion 12 has an amorphous structure or a lower degree of crystallization, the effective doping of the first portion 11 is increased, and the contact resistance of the first portion 11 can be reduced relative to the second portion 12, thereby reducing the energy loss in the current collection process of the first portion 11 and improving the battery efficiency. For example, Fig. 20 As shown, when the first semiconductor layer 100 is set in the P region, through comparing the P region contact resistance of the amorphous region battery and the crystallized region battery, it can be seen that the overall contact resistance of the solar cell in which the first semiconductor layer 100 has the first part 11 is smaller than the overall contact resistance of the solar cell in which the first semiconductor layer 100 does not have the first part 11.

[0064] like Figure 1 As shown, in this embodiment, the solar cell further includes a second semiconductor layer 2 disposed on the first surface, and the first semiconductor layer 100 and the second semiconductor layer 2 are arranged adjacent to each other along the second direction, that is, the solar cell is a back contact solar cell, the first semiconductor layer 100 and the second semiconductor layer 2 are both disposed on the first surface, and the first semiconductor layer 100 and the second semiconductor layer 2 are adjacent to each other along the second direction. Figure 4-Figure 5 As shown, the second semiconductor layer 2 has an adjacent side surface close to the first semiconductor layer 100. Along the second direction, the second portion 12 is closer to the second semiconductor layer 2 than the first portion 11. That is, along the second direction, the second portion 12 is located between the first portion 11 and the second semiconductor layer 2. The first semiconductor layer 100 and the second semiconductor layer 2 have different conductivity types. In order to realize the arrangement of the P region and the N region on the first surface, the first semiconductor layer 100 is one of the P region and the N region, and the second semiconductor layer 2 is the other of the P region and the N region.

[0065] By adopting the above technical solution, for the back-contact solar cell, the second part 12 of the first semiconductor layer 100 is closer to the second semiconductor layer 2, and the degree of crystallization of the second part 12 is relatively low to ensure the passivation effect of the second part 12, thereby preventing leakage between the second part 12 and the second semiconductor layer 2 and reducing the photoelectric conversion efficiency of the solar cell.

[0066] In the above technical solution, if Figure 1 As shown, the first semiconductor layer 100 may include a plurality of first strip portions 1 extending along the first direction, the second semiconductor layer 2 may include a plurality of second strip portions extending along the first direction, the first strip portions 1 and the second strip portions are alternately arranged along the second direction, and the first direction and the second direction intersect. In this embodiment, the first strip portion 1 extends as a whole along the first direction, the width direction of the first strip portion 1 is the same as the second direction, and along the width direction of the first strip portion 1, the first strip portion 1 includes a first portion 11 and a second portion 12 adjacent to each other, that is, the first portion 11 and the second portion 12 are adjacently arranged along the width direction of the first strip portion 1, the second portion 12 is arranged closer to the second strip portion, and the second portion 12 is located between the first portion 11 and the second strip portion, thereby preventing leakage between the second portion 12 and the second strip portion. In this embodiment, in the structure of the first strip portion 1, the second portion 12 can be arranged on both sides of the first portion 11 along the second direction, further reducing the risk of leakage.

[0067] like Figure 1 and Figure 2 As shown, in this embodiment, the first portion 11 and the second portion 12 are both in the shape of strips extending along the first direction, and the first direction and the second direction intersect. Specifically, the first portion 11 and the second portion 12 are arranged in approximately parallel strips, so that they can gradually move along the first direction during laser irradiation, which is conducive to the laser irradiation formation of the first portion 11.

[0068] like Figure 5 As shown, in some embodiments, along the second direction, the second portion 12 extends from the edge of the first portion 11 to near the adjacent side surface, but does not contact the adjacent side surface. Specifically, the second portion 12 extends from the edge of the first portion 11 to Figure 5 In the S3 region, that is, there is a certain distance between the end of the second portion 12 away from the first portion 11 and the adjacent side surface. With this technical solution, the second portion 12 does not contact the second semiconductor layer 2, and the distance between the second portion 12 and the second semiconductor layer 2 is large, which is conducive to further reducing the leakage risk between the second portion 12 and the second semiconductor layer 2.

[0069] like Figure 5As shown, in other embodiments, along the second direction, the second portion 12 extends from the edge of the first portion 11 to the adjacent side surface and contacts the adjacent side surface. Specifically, the second portion 12 extends from the edge of the first portion 11 to the adjacent side surface. Figure 5 In the S2 region, that is, the end of the second portion 12 away from the first portion 11 is in contact with the adjacent side surface, and the second portion 12 overlaps with at least part of the adjacent side surface. With this technical solution, the second portion 12 overlaps with at least part of the adjacent side surface of the second semiconductor layer 2, and the second portion 12 has a lower degree of crystallization. In this way, a weaker current can be transmitted through the second portion 12 and the adjacent side surface of the second semiconductor layer 2. When the solar cell is blocked, the current can form a leakage channel through the second portion 12 and the adjacent side surface of the second semiconductor layer 2, thereby preventing the blocked cell from becoming a load to consume the energy generated by other illuminated cells, thereby reducing the risk of hot spots.

[0070] Further, in the above technical solution, along the second direction, the distance between the edge of the first part 11 and the adjacent side surface is greater than or equal to 20 μm. In this way, it can be ensured that the first part 11 with a strong transmission circuit capability is farther away from the second semiconductor layer 2, reducing the leakage risk between the first part 11 and the second semiconductor layer 2. Exemplarily, the distance between the edge of the first part 11 and the adjacent side surface is 20 μm, 22 μm, 24 μm, 25 μm, 50 μm, 70 μm, 100 μm, etc.

[0071] like Figure 5 As shown, in other embodiments, a portion of the second portion 12 is disposed on the second semiconductor layer 2 to form an overlapping portion 15, that is, a portion of the second portion 12 extends to the upper side of the second semiconductor layer 2, and a portion of the second portion 12 located on the side of the second semiconductor layer 2 away from the semiconductor substrate 6 is the overlapping portion 15. Along the second direction, the second portion 12 extends from the edge of the first portion 11 to the overlapping portion 15. Specifically, the second portion 12 extends from the edge of the first portion 11 to the overlapping portion 15. Figure 5 In the S1 region, that is, the end of the second portion 12 facing away from the first portion 11 is in contact with the side of the second semiconductor layer 2 facing away from the semiconductor substrate 6. Since the current transmission capability of the surface of the second semiconductor layer 2 facing away from the semiconductor substrate 6 is stronger than that of the adjacent side, in this technical solution, the second portion 12 is extended from the edge of the first portion 11 to the overlapping portion 15, which can increase the current transmission capability between the second portion 12 and the second semiconductor layer 2. When the solar cell is blocked, the current can form a leakage channel through the second portion 12 and the surface of the second semiconductor layer 2 facing away from the semiconductor substrate 6. The leakage channel has a stronger current transmission capability, which further reduces the risk of hot spots.

[0072] In some embodiments, the width of the second portion 12 along the second direction is less than or equal to 500 μm and greater than or equal to 20 μm. Figure 5 As shown, along the second direction, the extension distance of the second part 12 is less than or equal to 500μm and greater than or equal to 20μm. In this way, if the width of the second part 12 is set too large, for example, greater than 500μm, it will block more of the second semiconductor layer 2, and it is impossible to form an effective current collection of the second semiconductor layer 2, and the leakage channel is too large, resulting in a large loss of battery efficiency; if the width of the second part 12 is set too small, for example, less than 20 microns, it is difficult to control the crystallization process such as laser, and other parts (such as the second semiconductor layer 2) may be processed, causing damage to other parts. For example, the width of the second part 12 along the second direction can be 100μm, 90μm, 80μm, etc. Preferably, the width of the second part 12 along the second direction is greater than or equal to 100μm and less than or equal to 400μm. In this way, the second part 12 can at least partially contact the second semiconductor layer 2 to form a leakage channel, while not overlapping the second semiconductor layer 2 too much, resulting in a reduction in the current collection area of ​​the second semiconductor layer 2.

[0073] like Figure 3 and Figure 4 As shown, in some possible implementations, the solar cell further includes a first transparent conductive layer 71 covering the first semiconductor layer 100, and the projection of the first portion 11 on the semiconductor substrate 6 is completely located within the projection of the first transparent conductive layer 71 on the semiconductor substrate 6. In this way, by setting the first transparent conductive layer 71, the carrier transmission capacity of the first semiconductor layer 100 is improved, and a good ohmic contact can be formed with the electrode, thereby improving the conductivity. The first portion 11 having a crystallized structure does not exceed the boundary of the first transparent conductive layer 71, thereby reducing the contact resistance in the effective conductive area of ​​the first transparent conductive layer 71, improving the conductivity, and improving the battery efficiency.

[0074] like Figure 5 As shown, further, in the above technical solution, along the second direction, the first transparent conductive layer 71 extends to the adjacent side surface or extends to the second portion 12 located on the second semiconductor layer 2. Specifically, along the second direction, the first transparent conductive layer 71 can extend to Figure 5 Alternatively, the first transparent conductive layer 71 may extend to the S2 region as shown in FIG. Figure 5 In this way, the first transparent conductive layer 71 can cover a larger area of ​​the first semiconductor layer 100, further improving the conductive performance.

[0075] like Figure 3-Figure 4As shown, further, in some embodiments, the solar cell further includes a second transparent conductive layer 72, the second transparent conductive layer 72 covers the second semiconductor layer 2; there is a PN isolation region 10 between the second transparent conductive layer 72 and the first transparent conductive layer 71, and the PN isolation region 10 is located on the second semiconductor layer 2. In the case of adopting the above technical solution, the electrical insulation between the P region and the N region is achieved by the PN isolation region 10, and the projection of the first part 11 is located within the boundary of the first transparent conductive layer 71, so the first part 11 will not enter the boundary of the PN isolation region 10, and the irradiation range of the laser will not enter the PN isolation region 10. Since the PN isolation region 10 does not have a crystallized structure or the degree of crystallization is low, the electrical insulation effect of the PN isolation region 10 is guaranteed.

[0076] like Figure 3-Figure 4 As shown, the solar cell may further include a third transparent conductive layer 73 , which covers a portion of the second portion 12 . In this embodiment, the first transparent conductive layer 71 covers the first portion 11 , and an edge isolation region 3 is provided between the first transparent conductive layer 71 and the third transparent conductive layer 73 .

[0077] like Figure 5-Figure 7 As shown, further, the first transparent conductive layer 71, the second transparent conductive layer 72 and the third transparent conductive layer 73 can be at least one of fluorine-doped tin oxide, aluminum-doped zinc oxide, tin-doped indium oxide, tungsten-doped indium oxide, molybdenum-doped indium oxide, cerium-doped indium oxide and indium hydroxide. The transparent conductive layer can be a single-layer film or a laminated film.

[0078] For example, Figure 5 As shown, a part of the second part 12 is arranged on the second semiconductor layer 2 to form an overlapping part 15, and the PN isolation region 10 is arranged on the overlapping part 15. For example, when the second semiconductor layer 2 includes a stacked tunneling oxide layer 21 and an n-type doped polysilicon layer 22, and the first semiconductor layer 100 includes a stacked intrinsic amorphous silicon layer 13 and a p-type amorphous silicon layer 14, at the junction of the first semiconductor layer 100 and the second semiconductor layer 2, the first semiconductor layer 100 overlaps the second semiconductor layer 2 to form an overlapping part 15, and at this time, the PN isolation region 10 is located across the overlapping part 15. The width of the overlapping part 15 needs to be reasonably set, for example, it can be in the range of 100-300μm, so as to achieve the balance between the leakage channel and the current collection as described above. The width of the second part 12 directly affects the width of the overlapping part 15. Since the first part 11 has a certain distance from the adjacent side of the second semiconductor layer 2, the width of the overlapping part 15 should be in the range of 100-300μm.

[0079] In some embodiments, when the first surface of the solar cell has the first semiconductor layer 100 and the second semiconductor layer 2, that is, when the solar cell is a back contact cell, the second semiconductor layer 2 may include amorphous silicon, nanocrystalline silicon and / or microcrystalline silicon, and the second semiconductor layer 2 has a structure similar to that of the first semiconductor layer 100, but the conductivity type is different, that is, the second semiconductor layer 2 also has a first portion 11 and a second portion 12 adjacent to each other along the second direction. The first portion 11 of the second semiconductor layer 2 may be a laser crystallized region in its entirety, or may not be a laser crystallized region in its entirety, with reference to the above description of the first portion 11 of the first semiconductor layer 100, which will not be described in detail here.

[0080] For example, taking the case where the first semiconductor layer 100 corresponds to the P region and the second semiconductor layer 2 corresponds to the N region, the first semiconductor layer 100 may include a first intrinsic amorphous silicon layer and a p-type amorphous silicon layer stacked, and the second semiconductor layer 2 may include a second intrinsic amorphous silicon layer and an n-type amorphous silicon layer stacked, and the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer are both arranged close to the semiconductor substrate 6. Of course, the conductivity types of the first semiconductor layer 100 and the second semiconductor layer 2 may be interchangeable, which will not be described in detail.

[0081] In this way, for the first semiconductor layer 100 and the second semiconductor layer 2 of different conductivity types arranged on the first surface, the first semiconductor layer 100 and the second semiconductor layer 2 can both form a heterojunction structure, forming a heterojunction back contact battery with both a P-region heterojunction structure and an N-region heterojunction structure on the back, which has the advantages of good passivation effect, high conversion efficiency, long service life, and low energy consumption for preparation of the heterojunction structure. As long as there is an amorphous silicon layer and / or a nanocrystalline silicon layer, the heterojunction back contact battery can also be applied to the battery structure with an amorphous structure at the edge and a crystallized structure in the middle area in this application to improve the battery efficiency.

[0082] like Figure 1-Figure 6 As shown, in some embodiments, when the first surface of the solar cell has a first semiconductor layer 100 and a second semiconductor layer 2, that is, when the solar cell is a back-contact cell, the second semiconductor layer 2 can be at least one of a polycrystalline silicon layer, a nanocrystalline silicon layer and a microcrystalline silicon layer, and the first semiconductor layer 100 can be a heterojunction structure. When the second semiconductor layer 2 is a polycrystalline silicon layer, a tunneling passivation contact structure can be formed, and the second semiconductor layer 2 and the first semiconductor layer 100 have different conductivity types.

[0083] For example, the second semiconductor layer 2 may include a tunneling oxide layer 21 and a doped polysilicon layer stacked on the first surface, the tunneling oxide layer 21 is arranged close to the semiconductor substrate 6, and taking the second semiconductor layer 2 corresponding to the N region and the first semiconductor layer 100 corresponding to the P region as an example, the doped polysilicon layer of the second semiconductor layer 2 is an n-type doped polysilicon layer 22; the first semiconductor layer 100 includes an intrinsic amorphous silicon layer 13 and a p-type amorphous silicon layer 14 stacked on the first surface, and the intrinsic amorphous silicon layer 13 is arranged close to the semiconductor substrate 6. Of course, when the second semiconductor layer 2 corresponds to the P region and the first semiconductor layer 100 corresponds to the N region, the doped polysilicon layer is a p-type doped polysilicon layer, and the doped amorphous silicon layer in the first semiconductor layer 100 is an n-type amorphous silicon layer.

[0084] In this way, by arranging the second semiconductor layer 2 and the first semiconductor layer 100 of different conductivity types on the first surface, a hybrid back contact battery having both a tunnel passivation contact structure and a heterojunction structure on the back is formed, wherein the first semiconductor layer 100 is a heterojunction structure, and the battery has the advantages of high conversion efficiency, good stability, low Auger recombination of the tunnel passivation contact structure and good passivation effect, high conversion efficiency, long service life, and low energy consumption for preparation of the heterojunction structure. As long as there is an amorphous silicon layer and / or a nanocrystalline silicon layer, the hybrid back contact battery can also be applied to the battery structure in which the edge is an amorphous structure and the middle area is a crystallized structure in the present application to improve the battery efficiency. Of course, when the second semiconductor layer 2 is other semiconductor layers, such as microcrystalline silicon or nanocrystalline silicon, a heterojunction structure can also be formed. By selecting different materials for the second semiconductor layer 2, a back contact battery with different structures in the P region and the N region can be formed.

[0085] In other embodiments, the solar cell further includes a third semiconductor layer disposed on the second surface, the material of the third semiconductor layer includes at least one of polycrystalline silicon, amorphous silicon, nanocrystalline silicon or microcrystalline silicon, and the conductivity type of the third semiconductor layer is different from that of the first semiconductor layer 100. For example, if the entire second surface is covered with an amorphous silicon layer, the third semiconductor layer may also form a heterojunction structure, and the structure of the third semiconductor layer may be similar to that of the first semiconductor layer 100, and also have a first portion 11 and a second portion 12, and the degree of crystallization of the first portion 11 is greater than that of the second portion 12.

[0086] In one example, the conductivity type of the first semiconductor layer 100 is P-type, and the conductivity type of the third semiconductor layer is N-type, then the first semiconductor layer 100 includes a first intrinsic amorphous silicon layer and a p-type amorphous silicon layer stacked on the first surface, the first intrinsic amorphous silicon layer is arranged close to the first surface, and the third semiconductor layer includes a third intrinsic amorphous silicon layer and an n-type amorphous silicon layer stacked on the second surface, and the third intrinsic amorphous silicon layer is arranged close to the second surface, forming a double-sided heterojunction battery. Of course, the conductivity type of the first semiconductor layer 100 can also be N-type, and the conductivity type of the third semiconductor layer is P-type, which will not be repeated.

[0087] In another example, a polysilicon layer is disposed on the second surface, and the third semiconductor layer can form a tunnel passivation contact structure. Specifically, the conductivity type of the first semiconductor layer 100 is P-type, and the conductivity type of the third semiconductor layer is N-type. The first semiconductor layer 100 includes a first intrinsic amorphous silicon layer and a p-type amorphous silicon layer stacked on the first surface, the first intrinsic amorphous silicon layer is disposed close to the first surface, and the third semiconductor layer includes an N-type doped polysilicon layer disposed on the second surface, and a tunnel oxide layer is further disposed between the N-type doped polysilicon layer and the second surface, and the tunnel oxide layer and the N-type doped polysilicon layer constitute a tunnel passivation contact structure. The third semiconductor layer can be partially disposed on the second surface, for example, it can be disposed in a plurality of strips, in which case a poly-finger structure is formed, and a doped field region can be selectively formed on the substrate between the poly-finger; or, the third semiconductor layer can be formed on the second surface as a whole, except that the metallized contact area has a thicker portion, and the third semiconductor layer has a thinner portion in the non-metallized area. The first semiconductor layer 100 may be a heterojunction structure, thus forming a double-sided hybrid solar cell. Of course, the conductivity type of the first semiconductor layer 100 may also be N-type, and the conductivity type of the third semiconductor layer may be P-type, which will not be described in detail.

[0088] As long as they have an amorphous silicon layer, a nanocrystalline silicon layer and / or a microcrystalline silicon layer, bifacial heterojunction cells and bifacial hybrid solar cells can also be applied to the cell structure in which the degree of crystallization of the first part 11 is greater than that of the second part 12 in the present application to improve cell efficiency.

[0089] In some possible implementations, such as Figure 1 As shown, the first portion 11 extends to the edge of the first surface along the first direction. That is, along the first direction, both ends of the first portion 11 extend to the edge of the first surface of the semiconductor substrate 6, so that the area of ​​the first portion 11 can be maximized, the contact resistance can be reduced, and the current collection capability can be improved. It should be noted that, since the portion of the first semiconductor layer 100 close to the edge of the semiconductor substrate 6 has large defects, poor passivation effect, large leakage current, and serious recombination, the portion of the first portion 11 close to the edge of the first surface of the semiconductor substrate 6 may not be used as a current collection area.

[0090] In some other possible implementations, such as Figure 2 As shown, the second portion 12 can surround the first portion 11. Specifically, no matter along the first direction or along the second direction, the second portion 12 is arranged on both sides of the first portion 11, and the second portion 12 surrounds the first portion 11 as a whole. In this way, the second portion 12 surrounding the first portion 11 has a lower degree of crystallization, which can further reduce the risk of leakage and ensure the photoelectric conversion efficiency of the solar cell.

[0091] In the above technical solution, the first part 11 is rectangular and the second part 12 is annular. That is, the first part 11 located in the middle area corresponds to a rectangular shape, and the second part 12 located in the edge area corresponds to a rectangular ring. The first semiconductor layer 100 can cover the entire first surface of a continuous whole surface structure. At this time, the first semiconductor layer 100 can form one side of a bifacial solar cell, which can be used as a P region or an N region. Since the first semiconductor layer 100 includes amorphous silicon and / or nanocrystalline silicon, the first semiconductor layer 100 can form a heterojunction structure.

[0092] In the above technical solution, along the direction from the first part 11 to the second part 12 and perpendicular to the side length of the semiconductor substrate 6, the width of the second part is 0.3mm to 12mm. That is, the edge area of ​​0.3mm to 12mm is reserved around the first part 11 without laser crystallization. If the width of the second part 12 is too wide, the area of ​​the first part 11 with the crystallized structure of the solar cell as a whole is small, the reduction of the series resistance is small, and the loss during current collection is large; if the width of the second part 12 is too small, on the one hand, the edge of the first semiconductor layer 100 is limited by the coating process, and the first semiconductor layer 100 in the edge area is thinner. On the other hand, the angle of laser irradiation at the edge of the solar cell is too large, and the energy distribution in the laser spot is deviated, which is easy to cause damage to the passivation of the first semiconductor layer 100 at the edge due to excessive laser energy density. Therefore, considering the reduction of the overall contact resistance of the solar cell and the reduction of damage to the passivation, the width of the second part 12 is selected to be 0.3mm to 12mm.

[0093] Furthermore, the width of the second portion 12 is 0.3 mm to 3 mm, so as to further increase the area of ​​the first portion 11 of the first semiconductor layer 100, reduce the contact resistance, and improve the battery efficiency. Specifically, the width of the second portion 12 can be 0.3 mm, 0.5 mm, 1 mm, 1.5 mm, 2 mm, 2.5 mm, 3 mm, etc.

[0094] Exemplarily, for the first semiconductor layer 100 including a plurality of first strip portions 1, along the extension direction (first direction) of the first strip portions 1, the extension lengths of the second portions 12 at both end edges of the first strip portions 1 are 1 mm, 1.2 mm, 1.5 mm, etc. Along the arrangement direction (second direction) of the plurality of first strip portions 1, the crystallization degree of the two first strip portions 1 close to both side edges of the first surface is the same as the crystallization degree of the second portion 12.

[0095] Optionally, the material of the first portion 11 includes at least one of amorphous silicon and nanocrystalline silicon, that is, the first portion 11 may be an amorphous silicon layer, a nanocrystalline silicon layer, or a combination of nanocrystalline silicon and amorphous silicon, and the degree of crystallization may be improved after laser crystallization. For example, when the first semiconductor layer 100 is an amorphous silicon layer, the laser crystallized portion may partially crystallize inside the amorphous silicon layer to form nanocrystalline grains. When the first semiconductor layer 100 is a nanocrystalline silicon layer or a combination of amorphous silicon and nanocrystalline, the laser crystallized portion may increase the crystallinity or degree of crystallization of the first semiconductor layer 100.

[0096] The material of the second portion 12 can be amorphous silicon, so that the second portion 12 has a better passivation effect. By setting reasonable crystallization areas and amorphization areas on the first semiconductor layer 100, the overall cell efficiency of the solar cell is optimized and the cell efficiency is improved.

[0097] In some embodiments, when the first semiconductor layer 100 includes a plurality of first strip portions 1 extending along the first direction, and the second semiconductor layer 2 includes a plurality of second strip portions extending along the first direction, the degree of crystallization of at least one first strip portion 1 near the edge of the first surface along the second direction is the same as the degree of crystallization of the second portion 12. In this way, for the strip-shaped first strip portions 1, the plurality of first strip portions 1 are arranged along the second direction, and in the arrangement direction, the entire region of at least one first strip portion 1 near the edge of the first surface has the same degree of crystallization as the second portion 12, that is, at least one first strip portion 1 near the edge is not subjected to laser crystallization treatment, and the remaining first strip portions 1 only form amorphized second portions 12 at both side edges in the second direction, thereby realizing the setting of the amorphized structure at both side edges of the first semiconductor layer 100.

[0098] For example, in the second direction, the degree of crystallization of the entire area of ​​the two strip portions respectively located on the two edges of the first surface is the same as the degree of crystallization of the second portion 12, or two, three or more first strip portions 1 having the same degree of crystallization as the second portion 12 are reserved near the edge of each first surface.

[0099] like Figure 5 and Figure 6As shown, in some possible implementations, the semiconductor substrate 6 includes a concave portion on the first surface, the concave portion includes a side wall and a bottom wall, the concave portion is recessed toward the second surface relative to the rest of the first surface, and the first portion 11 is located within the concave portion. In this configuration, the concave portion is formed by etching the surface of the semiconductor substrate 6, and generally has a velvet structure. The first portion 11 having amorphous silicon, nanocrystalline silicon and / or microcrystalline silicon is disposed in the concave portion to increase the contact area of ​​the first portion 11, which is beneficial to current collection.

[0100] In some embodiments, one side of the semiconductor substrate 6 provided with an amorphous semiconductor layer is a velvet structure, the amorphous semiconductor layer is conformal to the velvet structure, the velvet structure has a light trapping effect, increases the collection of light, and the velvet structure can achieve better contact with the electrode. When the first part 11 of the first semiconductor layer 100 is laser crystallized, the laser is irradiated on the velvet structure of the first part 11, and the crystallization temperature can be reached, so that a local area of ​​the first part 11 forms a crystallized microcrystalline structure or nanocrystalline structure. In this way, the crystallized area has both an amorphous structure and a crystallized structure. The crystallized structure reduces the contact resistance, but reduces the passivation effect, and the recombination may increase, which is not conducive to the photoelectric efficiency. Therefore, by forming a crystallized structure in a local area of ​​a part of the velvet structure, the two factors of contact resistance and passivation effect can be balanced, so that the battery efficiency is optimized.

[0101] like Fig.19 As shown, in this embodiment, the EL (Electroluminescent) test of the solar cell is a method for detecting internal defects of the solar cell. In the image obtained by the EL test, the brightness of the first part 11 with a relatively high degree of crystallization is greater than the brightness of the second part 12 with a relatively low degree of crystallization. When the solar cell is subjected to an EL test under the same conditions, in the image obtained, the brightness of the first part 11 is greater than the brightness of the second part 12, indicating that the contact resistance of the first part 11 is smaller than the contact resistance of the second part 12. When the solar cell is powered on for testing, the electroluminescent brightness of the first part 11 with a small contact resistance is larger, and the electroluminescent brightness of the second part 12 is smaller. Fig.19 It can be seen from the image of solar cell B in that the brightness of the first part 11 of solar cell B is greater than the brightness of the second part 12. By comparing with the image of solar cell C, it can be seen that the brightness of the entire surface of solar cell C is consistent, and compared with solar cell B, the overall brightness is lower, indicating that the overall contact resistance of solar cell C is large.

[0102] In some possible implementations, the solar cell further includes a first gate electrode 4 extending along the first direction, and the first gate electrode 4 is conductively disposed on the first portion 11 of the first semiconductor layer 100. The extension direction of the first gate electrode 4 is consistent with the extension direction of the first strip portion 1, and the first gate electrode 4 can collect carriers of the first portion 11 and part of the second portion 12 on the same first semiconductor layer 100, thereby improving the carrier collection capability of the first gate electrode 4 for the first semiconductor layer 100.

[0103] For the solar cell having the second semiconductor layer 2, the solar cell further comprises a second gate electrode 5 conductively disposed on the second semiconductor layer 2, and the extension direction of the second gate electrode 5 is along the first direction, which is consistent with the extension direction of the second semiconductor layer 2. In the case of having the first transparent conductive layer 71 and the second transparent conductive layer 72, the first gate electrode 4 is disposed on the first transparent conductive layer 71, and the second gate electrode 5 is disposed on the second transparent conductive layer 72.

[0104] Further, in the present embodiment, along the second direction, the ratio of the width of the first gate electrode 4 to the width of the first portion 11 is 10% to 120%, specifically 10%, 30%, 50%, 80%, 100%, 120%, etc. The ratio of the width of the first gate electrode 4 to the width of the middle portion is selected according to the material and carrier transmission capability of the first semiconductor layer 100. If the carrier transmission capability of the first semiconductor layer 100 is relatively weak, the ratio of the width of the first gate electrode 4 to the width of the middle portion is increased to increase the contact area between the first gate electrode 4 and the middle portion and reduce the contact resistance. On the contrary, the ratio of the width of the first gate electrode 4 to the width of the middle portion can be reduced to save electrode materials while satisfying the current collection.

[0105] For example, the width of the first gate line electrode 4 can be 30 μm to 600 μm: specifically, when the first gate line electrode 4 is prepared by screen printing, the width of the first gate line electrode 4 is 30 μm to 80 μm; when the first gate line electrode 4 is prepared by deposition such as electroplating, the width of the first gate line electrode 4 is 100 μm to 600 μm. The width of the middle part is 200 μm to 700 μm. The width of the first gate line electrode 4 is selected appropriately according to the width of the middle part and the electrode preparation process.

[0106] Further, in the case where the solar cell includes the first transparent conductive layer 71, the first gridline electrode 4 is extended along the first direction and arranged on the first transparent conductive layer 71; along the second direction, the width of the first gridline electrode 4 is less than or equal to the width of the first transparent conductive layer 71, and the width of the first transparent conductive layer 71 is greater than the width of the middle part. For example, the width of the first transparent conductive layer 71 is 120 μm to 800 μm, the width of the first part 11 is 200 μm to 700 μm, and the ratio of the width of the first transparent conductive layer 71 to the width of the first part 11 is 1.2 to 1.5. According to the width of the first part 11, the width of the first transparent conductive layer 71 is selected appropriately, and according to the width of the first part 11, the width of the first transparent conductive layer 71 and the electrode preparation process, the width of the first gridline electrode 4 is selected appropriately. In this way, the first gridline electrode 4 can be arranged directly opposite to the first part 11, and the width of the first transparent conductive layer 71 is greater than the width of the middle part to improve the current collection capability.

[0107] Based on the solar cell described in any one of the above embodiments, an embodiment of the present invention further provides a photovoltaic assembly, comprising the solar cell described in any one of the above embodiments.

[0108] Since the photovoltaic module adopts the solar cell described in any of the above embodiments, the photovoltaic module has the same beneficial effects as the above solar cell, which will not be described in detail here.

[0109] The present invention also provides a method for manufacturing a solar cell. The method can be used to manufacture Figure 1-Figure 6 , and the solar cell described in any of the above embodiments, the manufacturing method of the solar cell comprises the following steps:

[0110] In step S100 , a semiconductor substrate 6 is provided. The semiconductor substrate 6 has a first surface and a second surface opposite to each other.

[0111] Step S200, forming a first semiconductor layer 100 on the first surface, wherein the first semiconductor layer 100 includes at least one of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon;

[0112] In step S300, a laser is used to irradiate the first portion 11 of the first semiconductor layer 100, but the second portion 12 of the first semiconductor layer 100 is not irradiated, so that the degree of crystallization of the first portion 11 is greater than that of the second portion 12; the first portion 11 and the second portion 12 are adjacent to each other along a second direction.

[0113] In the case of adopting the above technical solution, the area corresponding to the first part 11 of the first semiconductor layer 100 is crystallized by laser, so that the degree of crystallization is improved, while the area corresponding to the second part 12 of the first semiconductor layer 100 adjacent to the first part 11 is not irradiated with laser, and the amorphous structure is retained (it should be noted that when the first semiconductor layer 100 includes nanocrystalline silicon or microcrystalline silicon, the degree of crystallization or crystallinity of the nanocrystalline silicon or microcrystalline silicon of the second part 12 remains unchanged), so that the overall degree of crystallization of the first part 11 of the first semiconductor layer 100 is greater than the overall degree of crystallization of the second part 12. It can be understood that, when other factors are the same, when the degree of crystallization of the semiconductor layer is smaller, the grains in the semiconductor layer are smaller, and even the disorder of amorphous silicon material is presented. The smaller the grains in the semiconductor layer, the more interfaces between the grains in the semiconductor layer, so the resistance of the grain interface will be larger. Therefore, the crystallized structure in the first portion 11 of the first semiconductor layer 100 reduces the contact resistance, reduces the contact resistance between the first portion 11 and the conductive material (transparent conductive layer or electrode), and thus helps to reduce the transmission loss of the carriers collected in the first semiconductor layer 100 to the conductive material. At the same time, the degree of crystallization of the second portion 12 of the first semiconductor layer 100 is less than that of the first portion 11, which ensures the passivation effect of the second portion 12 adjacent to the first portion 11 along the second direction, and reduces the recombination of the edge of the first semiconductor layer 100, that is, for the back contact solar cell, the second portion 12 of the first semiconductor layer 100 is close to the second semiconductor, and the degree of crystallization of the second portion 12 is small to ensure the passivation effect of the second portion 12, and prevent leakage between the second portion 12 and the second semiconductor layer 2. It can be seen from the above that by setting reasonable crystallization areas and amorphization areas on the first semiconductor layer 100, the higher degree of crystallization of the first part 11 is utilized to optimize the overall cell efficiency of the solar cell and improve the cell efficiency. At the same time, the lower degree of crystallization of the second part 12 is utilized to ensure the passivation effect of the second part 12 and prevent leakage.

[0114] Furthermore, before using laser to irradiate the first part 11, the following steps are also included:

[0115] In step S201, a second semiconductor layer 2 is formed on the first surface. The first semiconductor layer 100 and the second semiconductor layer 2 are arranged adjacent to each other along a second direction. The first semiconductor layer 100 and the second semiconductor layer 2 have different conductivity types, and the second semiconductor layer 2 has an adjacent side surface close to the first semiconductor layer 100. Compared with the first portion 11, the second portion 12 is closer to the second semiconductor layer 2.

[0116] In this embodiment, the solar cell is a back contact solar cell, the first semiconductor layer 100 and the second semiconductor layer 2 are both disposed on the first surface, and the first semiconductor layer 100 and the second semiconductor layer 2 are disposed adjacent to each other along the second direction. Figure 4-Figure 5 As shown, the second semiconductor layer 2 has an adjacent side surface close to the first semiconductor layer 100, and the second portion 12 is closer to the second semiconductor layer 2 than the first portion 11. That is, along the second direction, the second portion 12 is located between the first portion 11 and the second semiconductor layer 2. The first semiconductor layer 100 and the second semiconductor layer 2 have different conductivity types. In order to realize the arrangement of the P region and the N region on the first surface, the first semiconductor layer 100 is one of the P region and the N region, and the second semiconductor layer 2 is the other of the P region and the N region.

[0117] By adopting the above technical solution, for the back-contact solar cell, the second part 12 of the first semiconductor layer 100 is closer to the second semiconductor layer 2, and the degree of crystallization of the second part 12 is relatively low to ensure the passivation effect of the second part 12, thereby preventing leakage between the second part 12 and the second semiconductor layer 2 and reducing the photoelectric conversion efficiency of the solar cell.

[0118] In some possible implementations, the first semiconductor layer 100 includes an amorphous silicon layer, and after the middle portion is irradiated with laser, a portion of the amorphous silicon layer is partially crystallized to form nanocrystalline grains. If the first semiconductor layer 100 is an amorphous silicon layer, the portion not irradiated with laser has a better passivation effect, and the insulation effect in the PN isolation region 10 is better.

[0119] Furthermore, the first portion 11 extends along the first direction and is in a strip shape, and the step S300 of irradiating the first portion 11 with a laser specifically includes the following steps:

[0120] Step S301 : a laser irradiates the first portion 11 along a first direction, and along a second direction, a starting position or an ending position of the laser is at a first distance from an adjacent side surface.

[0121] When the above technical solution is adopted, the second portion 12 extends from the edge of the first portion 11 to Figure 5 In the S3 region, the first distance is the width of the S3 region along the second direction, that is, there is a certain distance between the end of the second portion 12 away from the first portion 11 and the adjacent side surface. The second portion 12 does not contact the second semiconductor layer 2, and the distance between the second portion 12 and the second semiconductor layer 2 is large, which is conducive to further reducing the leakage risk between the second portion 12 and the second semiconductor layer 2.

[0122] Further, along the first direction, the starting or ending position of the laser has a second distance from the boundary of the first semiconductor layer 100. Specifically, the second distance is the extension distance of the second portion 12 along the first direction, and the second distance prevents the two ends of the first semiconductor layer 100 along the first direction from being irradiated with laser, and retains the amorphous structure. Due to the non-uniformity of the full width of the laser and the non-uniform thickness of the first semiconductor layer 100, when the laser acts on the edge portion of the first semiconductor layer 100, the laser will damage the passivation of the edge portion, thereby increasing the recombination of the edge portion. Therefore, the present application does not form a crystallized structure at both ends of the first semiconductor layer 100 by laser, and retains the amorphous structure at both ends of the first semiconductor layer 100, thereby ensuring the passivation effect at the edge portion and reducing the recombination of the edge portion.

[0123] In the above embodiment, the second distance is greater than the first distance, that is, the width of the second portion 12 along the first direction (the second portion adjacent to the first portion along the second direction) is greater than the width of the second portion along the second direction. Exemplarily, the first distance is less than or equal to 500 μm, and the second distance is 0.3-12 mm.

[0124] In some embodiments, the wavelength of the laser is 325 nm to 532 nm, specifically, the wavelength of the laser can be 325 nm, 450 nm, 532 nm, etc.; and / or the energy density of the laser is 200 mJ / cm 2 ~6000mJ / cm 2 Specifically, the energy density of the laser can be 200 mJ / cm 2 、500mJ / cm 2 、1000mJ / cm 2 、2000mJ / cm 2 、3000mJ / cm 2 、5000mJ / cm 2 、6000mJ / cm 2 Etc. The pulse width of the laser can be in the order of picoseconds to nanoseconds. By setting this wavelength range, the laser can be absorbed by the first semiconductor layer 100, which is conducive to the crystallization of the first semiconductor layer 100. If the laser energy density is too high, the high temperature range will expand, and the temperature at the top of the velvet structure will be too high, thereby affecting the passivation of the top area of ​​the velvet structure. If the laser energy density is too small, the energy accumulation time is too long, affecting production efficiency, and the energy may not reach the energy required for crystallization. Therefore, by selecting the laser energy density in this range, it is possible to achieve high temperature only at the top of the velvet structure, achieve morphological changes, and form a crystallized structure.

[0125] like Figure 7-Figure 18As shown, this embodiment provides a specific process for manufacturing a solar cell. Taking the preparation of a hybrid back contact cell having a tunnel passivation contact structure and a heterojunction structure on the back as an example, the preparation process of the back contact cell is as follows:

[0126] Step 1: If Figure 7 As shown, the silicon wafer is polished and cleaned. Specifically, the silicon wafer is put into a tank-type polishing and cleaning machine for polishing, the cutting damage layer of the silicon wafer is removed, and the polishing morphology of both sides is regulated by controlling the temperature, time, and concentration of the chemical solution. The obtained silicon wafer is used as a semiconductor substrate 6, and the semiconductor substrate 6 can be an n-type, p-type or intrinsic silicon substrate.

[0127] Step 2: If Figure 8 As shown, a tunneling oxide layer 21 and an intrinsic polysilicon layer 23 are sequentially formed on the backlight surface of the semiconductor substrate 6, wherein the tunneling oxide layer 21 is a SiOx layer. The tunneling oxide layer 21 and the intrinsic polysilicon layer 23 can be formed using one or more processes such as low-pressure chemical vapor deposition, plasma chemical vapor deposition, physical chemical vapor deposition or plasma enhanced atomic layer deposition. In addition, the tunneling oxide layer 21 can be generated by a high-temperature reaction of oxygen with the semiconductor substrate 6, or by a wet chemical method, such as a reaction of silicon with ozone, an oxidation reaction of silicon with nitric acid, and the like. The thickness of the tunneling oxide layer 21 is 1nm to 4nm, and optionally, the thickness is 1.4nm, and the thickness of the intrinsic polysilicon layer 23 is 30nm to 250nm, and optionally, the thickness is 120nm.

[0128] Step 3: If Fig. 9 As shown, the intrinsic polysilicon layer 23 is doped by high temperature diffusion to form an n-type doped polysilicon layer 22, and a phosphorus-containing oxide layer, namely, a phosphorus silicon glass layer 24, is generated. The doping concentration of the n-type doped polysilicon layer 22 is 1×10 19 cm -3 ~5×10 20 cm -3 .

[0129] Step 4: If Fig.10 As shown, the phosphosilicate glass layer 24 formed after phosphorus diffusion is removed by HF solution.

[0130] Step 5: If Fig.11 As shown, a silicon nitride mask layer 25 is deposited on the n-type doped polysilicon layer 22. The silicon nitride mask layer 25 serves as a hydrogen source to provide hydrogen atoms for the interface between the crystalline silicon and the tunnel oxide layer 21, passivating dangling bonds, and also passivating some defects in the crystalline silicon. Another function is to serve as a mask to protect the N-region film layer when the P-region is patterned later.

[0131] Step 6: If Fig.12As shown, the P region is patterned by laser technology, and all P region film layers are laser ablated until the semiconductor substrate 6. The laser can be a 532nm laser, and the pulse width can be a nanosecond or picosecond laser. Optionally, a 532 picosecond laser is used.

[0132] Step 7: If Fig.13 As shown, the semiconductor substrate 6 exposed in the P region is textured by a wet etching process to obtain a textured structure, such as a pyramid structure, and then the silicon nitride mask layer 25 is removed. The wet etching process has the following functions: first, to remove the damaged layer of the semiconductor substrate 6 in the P region after being treated by laser, and to perform interface cleaning; second, to remove the silicon nitride mask layer 25 deposited in the N region.

[0133] Step 8: Fig.14 As shown, an intrinsic amorphous silicon layer 13 and a p-type amorphous silicon layer 14 are sequentially deposited on the backlight surface of the entire semiconductor substrate 6 to form a P-region emitter. The thickness of the intrinsic amorphous silicon layer 13 is 2nm to 20nm, and optionally, the thickness is 8nm; the thickness of the p-type amorphous silicon layer 14 is 5nm to 50nm, and optionally, the thickness is 15nm. At the same time, a passivation layer 8 and an anti-reflection layer 9 are sequentially deposited on the front velvet surface of the semiconductor substrate 6. The anti-reflection layer 9 is any combination of one or more of a silicon nitride layer, a silicon oxide layer, and a silicon oxynitride layer. The passivation layer 8 can be an intrinsic amorphous silicon layer or an aluminum oxide layer.

[0134] Step 9: Fig.15 As shown, the N region is patterned by a laser process, and the intrinsic amorphous silicon layer 13 and the p-type amorphous silicon layer 14 on the n-type doped polysilicon layer 22 are removed to expose the n-type doped polysilicon layer 22. An oxide layer will be generated on the n-type doped polysilicon layer 22, which will be removed by a wet etching process. Among them, the laser can use a 355nm or 532nm laser, and the pulse width can be a nanosecond or picosecond laser. Optionally, a 532 picosecond laser is used. The wet etching process can use a chain device, with the semi-finished product facing up and protected by a water film. The back side is in contact with the HF solution to remove the oxide layer and the silicon nitride plated on the back side.

[0135] Step 10: If Fig.15As shown, a laser process is used to irradiate the corresponding area of ​​the first part 11 of the p-type amorphous silicon layer 14 in the P region, so that the p-type amorphous silicon layer 14 forms a first part 1111 with a crystallized structure, and the edge of the p-type amorphous silicon layer 14 along the second direction is not irradiated with laser, and the original amorphous structure is retained to form a second part 12. Among them, the laser can use a 355nm or 532nm laser, and the pulse width can be a nanosecond or picosecond laser. Optionally, a 532 picosecond laser is used. Specifically, the pulsed laser spot moves and irradiates along the extension direction of the p-type amorphous silicon layer 14. It should be noted that the laser processes in the ninth step and the tenth step can be performed in the same step, and can be performed in no particular order. In order to save laser processing time, after the P region is patterned by laser, irradiation is performed for crystallization.

[0136] Step 11: If Fig.16 As shown, a transparent conductive layer 7 is deposited on the backlight surface of the semiconductor substrate 6, which can be one or more of fluorine-doped tin oxide, aluminum-doped zinc oxide, tin-doped indium oxide, tungsten-doped indium oxide, molybdenum-doped indium oxide, cerium-doped indium oxide and indium hydroxide, in a stacked or single layer. Optionally, a tin-doped indium oxide film layer is used.

[0137] Step 12: If Fig.17 As shown, the transparent conductive layer 7 on the N region and the P region is disconnected to form a PN isolation region 10, so that the transparent conductive layer 7 forms a first transparent conductive layer 71 located on the P region and a second transparent conductive layer 72 located on the N region, so as to achieve insulation between the P region and the N region, and the transparent conductive layer 7 is disconnected at a position of the N region and the P region close to the edge of the semiconductor substrate 6 to form a third transparent conductive layer 73 located on the edge. The PN isolation region 10 located between the P region and the N region spans the overlapping region between the N region and the P region and part of the p region to achieve better insulation.

[0138] Step 13: If Fig.18 As shown, the first gate line electrode 4 and the second gate line electrode 5 are deposited on the first transparent conductive layer 71 in the P region and the second transparent conductive layer 72 in the N region, respectively, wherein the two ends of the first gate line electrode 4 extend to the positions shown in FIG. Figure 1 The second parts 12 on both sides are shown. The material of the first gate line electrode 4 and the second gate line electrode 5 can be silver, copper, aluminum or a combination thereof.

[0139] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0140] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A solar cell, characterized in that: include: A semiconductor substrate having a first surface and a second surface opposite to each other; A first semiconductor layer is arranged on the first surface, the first semiconductor layer includes a first part and a second part adjacent to the first part along a second direction, the degree of crystallization of the first part is greater than the degree of crystallization of the second part, and the first semiconductor layer includes at least one of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon.

2. The solar cell according to claim 1, characterized in that The solar cell further includes a second semiconductor layer disposed on the first surface, the first semiconductor layer and the second semiconductor layer are arranged adjacent to each other along a second direction, and the first semiconductor layer and the second semiconductor layer have different conductivity types; And along the second direction, compared with the first portion, the second portion is closer to the second semiconductor layer; The second semiconductor layer has an adjacent side surface close to the first semiconductor layer.

3. The solar cell according to claim 2, characterized in that: Along the second direction, the second portion extends from an edge of the first portion to approach the adjacent side surface but does not contact the adjacent side surface.

4. The solar cell according to claim 2, characterized in that: Along the second direction, the second portion extends from an edge of the first portion to the adjacent side surface and contacts the adjacent side surface.

5. The solar cell according to claim 4, characterized in that: Along the second direction, a distance between an edge of the first portion and the adjacent side surface is greater than or equal to 20 μm.

6. The solar cell according to claim 2, characterized in that: A portion of the second portion is disposed on the second semiconductor layer to form an overlapping portion, and along the second direction, the second portion extends from an edge of the first portion to the overlapping portion.

7. The solar cell according to claim 1, characterized in that The width of the second portion along the second direction is less than or equal to 500 μm and greater than or equal to 20 μm.

8. The solar cell according to claim 2, characterized in that: The solar cell further includes a first transparent conductive layer covering the first semiconductor layer, and a projection of the first portion on the semiconductor substrate is completely located within a projection of the first transparent conductive layer on the semiconductor substrate.

9. The solar cell according to claim 8, characterized in that Along the second direction, the first transparent conductive layer extends to the adjacent side surface or extends to a second portion located on the second semiconductor layer.

10. The solar cell according to claim 8, characterized in that The solar cell further comprises a second transparent conductive layer, wherein the second transparent conductive layer covers the second semiconductor layer; A PN isolation region is provided between the second transparent conductive layer and the first transparent conductive layer, and the PN isolation region is located on the second semiconductor layer.

11. The solar cell according to claim 10, characterized in that A portion of the second portion is disposed on the second semiconductor layer to form an overlapping portion, and the PN isolation region is disposed on the overlapping portion.

12. The solar cell according to claim 1, characterized in that The solar cell further includes a third semiconductor layer disposed on the second surface, wherein a material of the third semiconductor layer includes at least one of polycrystalline silicon, amorphous silicon, nanocrystalline silicon or microcrystalline silicon, and the third semiconductor layer has a different conductivity type from the first semiconductor layer.

13. The solar cell according to claim 1, characterized in that The first portion and the second portion both extend in a strip shape along a first direction, and the first direction intersects with the second direction.

14. The solar cell according to claim 1, characterized in that A contact resistance of the first portion is smaller than a contact resistance of the second portion.

15. The solar cell according to claim 1, characterized in that The first portion extends along a first direction to an edge of the first surface.

16. The solar cell according to claim 1, characterized in that The second portion surrounds the first portion.

17. The solar cell according to claim 1, characterized in that The material of the first part includes amorphous silicon and nanocrystalline silicon, and the material of the second part is amorphous silicon.

18. The solar cell according to claim 1, characterized in that The semiconductor substrate includes a concave portion on the first surface, wherein the concave portion is concave relative to the remaining portion of the first surface toward the second surface, and the first portion is located within the concave portion.

19. A photovoltaic module, comprising a solar cell, characterized in that: The solar cell is the solar cell according to any one of claims 1 to 18.

20. A method for manufacturing a solar cell, characterized in that: include: Providing a semiconductor substrate, the semiconductor substrate having a first surface and a second surface opposite to each other; forming a first semiconductor layer on the first surface, wherein the first semiconductor layer comprises at least one of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon; irradiating a first portion of the first semiconductor layer with a laser, and not irradiating a second portion of the first semiconductor layer, so that a crystallization degree of the first portion is greater than a crystallization degree of the second portion; The first portion is adjacent to the second portion along a second direction.

21. The method for manufacturing a solar cell according to claim 20, characterized in that: The first semiconductor layer is an amorphous silicon layer. After the first portion is irradiated with the laser, a portion of the amorphous silicon layer is crystallized to form nanocrystalline grains.

22. The method for manufacturing a solar cell according to claim 20, characterized in that: Before using laser to irradiate the first part, it also includes forming a second semiconductor layer on the first surface, the first semiconductor layer and the second semiconductor layer are arranged adjacent to each other along a second direction, the first semiconductor layer and the second semiconductor layer have different conductivity types, and the second semiconductor layer has an adjacent side surface close to the first semiconductor layer, and compared with the first part, the second part is closer to the second semiconductor layer.

23. The method for manufacturing a solar cell according to claim 22, characterized in that: The first portion extends along a first direction and is in a strip shape, and irradiating the first portion with laser includes: irradiating the first portion along the first direction with the laser, and along a second direction, a starting or ending position of the laser has a first distance from an adjacent side surface.

24. The method for manufacturing a solar cell according to claim 23, characterized in that: Along the first direction, a starting position or an ending position of the laser is at a second distance from a boundary of the first semiconductor layer.

25. The method for manufacturing a solar cell according to claim 24, characterized in that: The second distance is greater than the first distance.

26. The method for manufacturing a solar cell according to claim 20, characterized in that: The wavelength of the laser is 325nm to 532nm; And / or, the energy density of the laser is 200 mJ / cm 2 ~6000mJ / cm 2 .

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