Host, information processing method, electronic system and readable storage medium

Abstract

Embodiments of the present disclosure disclose a host, an information processing method, an electronic system and a readable storage medium. The host comprises a processor, the processor comprises a first central processing unit (CPU) core bound with a first thread and a second CPU core bound with a second thread. The first CPU core is configured to send an input / output (I / O) request to a storage device coupled with the host in response to control of the first thread. The second CPU core is configured to receive feedback information related to the I / O request sent by the storage device in response to control of the second thread.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of storage, and in particular, to a host, an information processing method, an electronic system and a readable storage medium. BACKGROUND

[0002] At present, an electronic system usually includes a host and a storage device including a memory system, wherein a central processing unit (CPU) core included in the host can send data to the storage device or receive feedback of the storage device. At present, the data sending manner adopted by the CPU core needs a large number of lock protections, resulting in a large lock overhead of the electronic system; and the feedback receiving manner adopted by the CPU core needs to use an interrupt context switching, which needs to spend a large amount of time to save and restore data, resulting in a large time overhead of the electronic system, so that the operation performance of the host to the storage device in the electronic system is poor. SUMMARY

[0003] Therefore, the present disclosure provides a host, an information processing method, an electronic system and a readable storage medium.

[0004] In a first aspect, the present disclosure provides a host, comprising: a first central processing unit (CPU) core bound with a first thread and a second CPU core bound with a second thread; wherein,

[0005] The first CPU core is configured to send an input / output (I / O) request to a storage device coupled with the host in response to control of the first thread.

[0006] The second CPU core is configured to receive feedback information related to the I / O request sent by the storage device in response to control of the second thread.

[0007] In the above scheme, the processor further comprises: a device interface; the device interface comprises: a host controller interface; the host controller interface comprises an interrupt register;

[0008] The second CPU core is further configured to poll the interrupt register to receive the feedback information in response to control of the second thread.

[0009] In the above scheme, the second CPU core is specifically configured to access the interrupt register at a preset time interval periodically to determine whether the feedback information is received in the interrupt register in response to control of the second thread; if the feedback information is received, the feedback information is obtained from the interrupt register.

[0010] In the above scheme, wherein, the host further comprises a memory; the memory is configured to store a request command queue; the request command queue comprises: one or more request commands; the one or more request commands correspond to one or more I / O requests;

[0011] The first CPU core is configured to: in response to control of the first thread, obtain the one or more request commands from the request command queue, and send the one or more request commands to the storage device.

[0012] In the above scheme, the host controller interface further comprises: a doorbell register;

[0013] The second CPU core is further configured to: access the doorbell register to determine the I / O request corresponding to the feedback information.

[0014] In the above scheme, the first CPU core is further configured to: access the doorbell register, and allocate a required transmission channel for the I / O request in a ready state.

[0015] In the above scheme, the access mode of the doorbell register is a lock access mode, wherein the lock access mode comprises that the doorbell register is accessed by only the first CPU core or the second CPU core at the same time.

[0016] In the above scheme, the I / O request is generated by an application program running on the processor, and the I / O request is converted by a device driver running on the processor into one or more request commands in a format supported by the storage device.

[0017] In the above scheme, the device interface further comprises: a joint protocol circuit and an M-physical interface circuit, wherein;

[0018] The joint protocol circuit and the M-physical interface circuit are connected with the host controller interface, and are configured to: send a request command to the storage device or receive the feedback information sent by the storage device, wherein the request command is generated based on the I / O request.

[0019] In the above scheme, the storage device is a universal flash storage (UFS) device.

[0020] In the above scheme, an operating system running in the host is a Linux operating system.

[0021] In the above scheme, the processor includes a plurality of CPU cores, the first CPU core is any one of the plurality of CPU cores, and the second CPU core is any one of the plurality of CPU cores except the first CPU core.

[0022] In a second aspect, the disclosure also provides an information processing method of a host, including:

[0023] binding a first thread to a first central processing unit (CPU) core included in the host;

[0024] binding a second thread to a second CPU core included in the host;

[0025] wherein, when the first thread is running, the first CPU core is controlled to send an input / output (I / O) request to a storage device coupled to the host, and when the second thread is running, the second CPU core is controlled to receive feedback information related to the I / O request sent by the storage device.

[0026] In the above scheme, when the second thread is running, the second CPU core is controlled to receive the feedback information related to the I / O request sent by the storage device, further including:

[0027] when the second thread is running, the second CPU core is controlled to poll an interrupt register included in the host to receive the feedback information.

[0028] In the above scheme, the second CPU core is controlled to poll the interrupt register included in the host to receive the feedback information, including: periodically accessing the interrupt register at a preset time interval to determine whether the feedback information is received in the interrupt register; and if the feedback information is received, obtaining the feedback information from the interrupt register.

[0029] In the above scheme, when the first thread is running, the first CPU core is controlled to send an input / output (I / O) request to a storage device coupled to the host, including:

[0030] when the first thread is running, the first CPU core is controlled to obtain one or more request commands from a request command queue stored in a memory of the host, and send the one or more request commands to the storage device;

[0031] wherein the one or more request commands correspond to one or more I / O requests.

[0032] In the above scheme, the method further includes:

[0033] when the first thread is running, controlling the first CPU core to access a doorbell register contained by the host, and assigning a required transmission channel for the I / O request in a ready state;

[0034] when the second thread is running, controlling the second CPU core to access the doorbell register to determine the I / O request corresponding to the feedback information.

[0035] In the above scheme, the access mode of the doorbell register is a locking access mode, wherein the locking access mode includes that the doorbell register is only accessed by the first CPU core or the second CPU core at the same time.

[0036] In a third aspect, the present disclosure relates to an electronic system, comprising:

[0037] a host; the host comprises a processor; the processor is configured to: bind a first thread to a first central processing unit (CPU) core contained by the processor; and bind a second thread to a second CPU core contained by the processor; run the first thread to control the first CPU core to send an input / output (I / O) request to a storage device;

[0038] and a storage device coupled with the host; the storage device is configured to: receive and process the I / O request; generate feedback information related to the I / O request; and send the feedback information to the host;

[0039] The processor is further configured to: run the second thread to control the second CPU core to receive the feedback information sent by the storage device.

[0040] In the above scheme, the processor further comprises: a device interface; the device interface comprises a host controller interface; the host controller interface comprises an interrupt register;

[0041] The second CPU core is further configured to: in response to the control of the second thread, periodically send a first access command to the interrupt register at a preset time interval;

[0042] The interrupt register is configured to: in response to the first access command, when the feedback information sent by the storage device is received, send the feedback information to the second CPU core.

[0043] In the above scheme, the host further comprises a memory; the memory is configured to store a request command queue; the request command queue comprises one or more request commands; the one or more request commands correspond to one or more I / O requests;

[0044] The first CPU core is further configured to send a second access command to the memory in response to control of the first thread.

[0045] The memory is configured to obtain the one or more request commands from the request command queue and send the one or more request commands to the first CPU core in response to the second access command.

[0046] The first CPU core is further configured to send the one or more request commands to the storage device.

[0047] In a fourth aspect, the disclosure also provides a computer readable storage medium having stored thereon a computer program, the computer program being executed by a processor to implement the method of any of the preceding aspects.

[0048] Embodiments of the disclosure provide a host, an information processing method, an electronic system and a readable storage medium. The host comprises a first central processing unit (CPU) core bound with a first thread and a second CPU core bound with a second thread. The first CPU core is configured to send an input / output (I / O) request to a storage device coupled with the host in response to control of the first thread. The second CPU core is configured to receive feedback information related to the I / O request sent by the storage device in response to control of the second thread. In the host provided by the embodiments of the disclosure, the first thread is bound with the first CPU core and the second thread is bound with the second CPU core, and the two special CPU cores are used to process the I / O request between the host and the storage device, thereby reducing a large amount of lock overhead. BRIEF DESCRIPTION OF DRAWINGS

[0049] In the drawings, which are not necessarily drawn to scale, like numerals can describe similar components in different views. Like numerals having different letter suffixes can represent different instances of similar components. The drawings illustrate generally, by way of example, various embodiments discussed in the present document.

[0050] Figure 1 A system block diagram illustrating an example electronic device with a memory system is shown;

[0051] Figure 2 A system block diagram illustrating an example electronic device with a memory system is shown; Figure 1 A system block diagram illustrating an example electronic device with a memory system is shown;

[0052] Figure 3 A system block diagram illustrating an example electronic device with a memory system is shown; Figure 1 A system block diagram illustrating an example electronic device with a memory system is shown;

[0053] Figure 4 A system block diagram illustrating an example electronic device with a memory system is shown;

[0054] Figure 5 A schematic diagram showing a process flow of a host sending an I / O request to a storage device and receiving feedback of the I / O request from the storage device;

[0055] Figure 6 A schematic diagram showing a structure of a host provided in an embodiment of the present disclosure Figure 1 ;

[0056] Figure 7 A schematic diagram showing a logical structure of a Linux-based operating system provided in an embodiment of the present disclosure;

[0057] Figure 8 A schematic diagram showing a structure of a Linux kernel provided in an embodiment of the present disclosure;

[0058] Figure 9 A schematic diagram showing a mapping relationship between a user thread and a kernel thread provided in an embodiment of the present disclosure;

[0059] Figure 10 A schematic diagram showing scheduling between processes when a user thread is not mapped to a kernel thread provided in an embodiment of the present disclosure;

[0060] Figure 11 A schematic diagram showing scheduling between threads when a user thread is mapped to a kernel thread provided in an embodiment of the present disclosure;

[0061] Figure 12 A schematic diagram showing scheduling when threads in a same process run on a same CPU core provided in an embodiment of the present disclosure;

[0062] Figure 13 A schematic diagram showing scheduling when different processes run on different CPU cores provided in an embodiment of the present disclosure;

[0063] Figure 14 A schematic diagram showing scheduling when threads in a same process run on different CPU cores provided in an embodiment of the present disclosure;

[0064] Figure 15 A schematic diagram showing a structure of a Linux-based storage system provided in an embodiment of the present disclosure;

[0065] Figures 16-20 A schematic diagram showing an interaction relationship between layers in a Linux-based storage system provided in an embodiment of the present disclosure;

[0066] Figure 21 A schematic diagram showing a structure of a host provided in an embodiment of the present disclosure Figure 1 ;

[0067] Figure 22This illustration shows a schematic diagram of the structure of a host provided in an embodiment of this disclosure. Figure 3 ;

[0068] Figure 23 This illustration shows a schematic diagram of the structure of a host provided in an embodiment of this disclosure. Figure 4 ;

[0069] Figure 24 This illustration shows a flowchart of a host sending I / O requests to a storage device and receiving feedback information, as provided in an embodiment of this disclosure.

[0070] Figure 25 A flowchart illustrating an information processing method for a host provided in an embodiment of this disclosure is shown.

[0071] Figure 26 A schematic diagram of the structure of an electronic system provided in an embodiment of this disclosure is shown. Detailed Implementation

[0072] Various embodiments of the present disclosure are described in more detail below with reference to the accompanying drawings. Other embodiments, variations of any disclosed embodiment, can be formed by different configurations or arrangements of the elements and features in the embodiments of the present disclosure. Therefore, the embodiments of the present disclosure are not limited to those set forth herein. Rather, the described embodiments are provided so that the embodiments of the present disclosure are thorough and complete, and fully convey the scope of the embodiments of the present disclosure to those skilled in the art to which the embodiments of the present disclosure pertain. It should be noted that references to “embodiment,” “another embodiment,” etc., do not necessarily indicate only one embodiment, and different references to any such phrases do not necessarily refer to the same embodiment. It should be understood that although the terms “first,” “second,” “third,” etc., may be used herein to identify various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element having the same or similar name. Therefore, a first element in one embodiment may also be referred to as a second or third element in another embodiment without departing from the spirit and scope of the embodiments of the present disclosure.

[0073] The accompanying drawings are not necessarily drawn to scale, and in some cases, the scale may be enlarged to clearly show the features of the embodiments. When an element is referred to as a connection or coupling to another element, it should be understood that the former may be directly connected to or coupled to the latter, or may be electrically connected to or coupled to the latter via one or more intermediate elements between the two. Furthermore, it should be understood that when an element is referred to as being "between" two elements, the element may be the only element between the two elements, or there may be one or more intermediate elements.

[0074] The terminology used in the context of the present disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used in this context, the singular forms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises," "comprising," "includes," and / or "including," as used herein, specify the presence of the stated elements and do not preclude the presence or addition of one or more other elements. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items. Unless otherwise defined, all terms used in the present disclosure, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art in the field of the present disclosure, and the terms should be interpreted as having a meaning that is consistent with their meaning in the context of the present disclosure and the relevant art. It will be further understood that the use of relational terms, if any, such as "first," "second," "third," and / or the like, are used solely to distinguish one from another entity or action without necessarily implying an actual such relationship or order.

[0075] In the following description, numerous specific details are set forth to provide a thorough understanding of the present disclosure. The present disclosure can be practiced without some or all of these specific details. In other instances, well-known process structures and / or processes have not been described in detail, so as not to unnecessarily obscure the present disclosure. It will be understood that, although the terms "first," "second," etc. can be used herein to describe various elements or

[0076] The embodiments of the present disclosure will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0077] Figure 1 A system block diagram of an exemplary electronic device having a storage system is shown. In Figure 1 The electronic device can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory system therein. As Figure 1As shown, system 100 is a system in an electronic device, which may include a host 108 and a memory system 102, the memory system being contained in a storage device; wherein,

[0078] Specifically, such as Figure 2 As shown, the host 108 may include a first processor 201, which may be such as a Central Processing Unit (CPU) or a System-on-a-Chip (SoC), wherein the SoC may be, for example, an Application Processor (AP). The first processor 201 may include a multi-core processor 2011 and a peripheral interface (or device interface) 2012. The multi-core processor 2011 may include multiple CPU cores (CPU core 2011-1 to CPU core 2011-N, where N is an integer greater than 1), wherein each CPU core may include logic circuits (or modules) with logical operation and control capabilities. The peripheral interface 2012 is a channel for communication with the memory system to enable the host to read data from the memory system or write data to the memory system.

[0079] The host 108 also includes at least one operating system (OS) that can generally manage and control functions and operations performed in the host 108. The OS can enable the host 108 coupled with the memory system 102 and a user requiring and using the memory system 102 to interoperate. The OS can support functions and operations corresponding to a request of the user, such as, without limitation, depending on whether the host 102 is a mobile host, the OS can be classified as a general-purpose operating system and a mobile operating system, wherein the general-purpose operating system can include a personal operating system that can be an operating system for supporting services for general purposes including Windows and Chrome, and an enterprise operating system that can be an operating system dedicated to ensuring and supporting high performance including Windows Server, Linux, Unix, etc. The mobile operating system can refer to an operating system for mobility or functions such as a power saving function, and generally, the mobile operating system can be an operating system such as Android, I / OS, Windows Mobile, etc. In some embodiments, the host 108 can include a plurality of OSs; correspondingly, the host 108 can run a plurality of operating systems related to the memory system 102. In other embodiments, the host 108 converts a request of the user into one or more commands and transmits the one or more commands to the memory system 102 to cause the memory system 102 to perform operations related to the one or more commands. It should be appreciated that the OS is used in a CPU core, such as a mobile electronic device including UFS can be applied under an Android platform, and a CPU core included therein uses Linux.

[0080] The memory system 102 can be capable of operating or performing a specific function in response to a request of the host 108 or performing various operations internally. In some embodiments, the memory system 102 can be capable of storing data accessed by the host 108. The memory system 102 can be used as a main memory system or an auxiliary memory system of the host 108. The memory system 102 and the host 108 can be electrically coupled and communicate according to a corresponding protocol. The memory system 102 can be implemented and packaged into different types of terminal electronic products, such as, without limitation, a solid state drive (SSD), a multimedia card (MMC), an embedded MMC (eMMC), a reduced size MMC (RSMMC), a micro- MMC, a secure digital (SD) card, a mini-SD, a micro-SD, a universal serial bus (USB) memory device, a universal flash (UFS) device, a compact flash (CF) card, a smart media (SM) card, a memory stick, etc.

[0081] In some embodiments, the memory system 102 may also be configured as part of, for example, a computer, an ultra-mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a network tablet, a tablet computer, a wireless telephone, a mobile phone, a smartphone, an e-book reader, a portable multimedia player (PMP), a portable game console, a navigation system, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a three-dimensional (3D) television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage device configured for a data center, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices configured for a home network, one of various electronic devices configured for a computer network, one of various electronic devices configured for a telematics network, a radio frequency identification (RFID) device, or one of various components configured for a computing system.

[0082] Return as Figure 1 As shown, the memory system 102 may have one or more memory devices 104 and a memory controller 106. The memory controller 106 can respond to requests from the host 108 and control the memory devices 104. For example, the memory controller 106 can read data from the memory devices 104 and transfer the read data to the host 108; it can also receive data to be stored from the host 108 and store the data to be stored in the memory devices 104. In other words, the memory controller 106 can control the write (or programming) operations, read operations, erase operations, and background operations of the memory devices 104, etc.

[0083] Specifically, such as Figure 3As shown, the memory controller 106 can include a front-end interface 301, a back-end interface 302, a processor 303, and a memory 304, where the above components 301, 302, 303, 304 in the memory controller 106 can share transmission signals inside the memory controller 106 through an internal bus. In some embodiments, the front-end interface 301 can interface the host 108 with the memory system 102 in response to a protocol of the host 108, and the front-end interface 301 exchanges transmission commands and data operations between the host 108 and the memory system 102. The front-end interface 301 can process commands and data sent by the host 108, and can include at least one of a universal serial bus (USB), a multimedia card (MMC), a peripheral component interconnect express (PCI-e or PCIe), a small computer system interface (SCSI), a serial attached SCSI (SAS), a serial advanced technology attachment (SATA), a parallel advanced technology attachment (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), and an electronic integrated drive (IDE). In some embodiments, the front-end interface 301 is a component of the memory system 102 for exchanging data with the host 108, which can be implemented through firmware called a host interface layer (HIL).

[0084] The back-end interface 302 can be an interface of commands and data transmitted between the memory controller 106 and the memory device 104, allowing the memory controller 106 to control the memory device 104 in response to a request transferred from the host 108. The back-end interface 302 can generate control signals for controlling the memory device 104. In some embodiments, if the memory device 104 is a NAND flash memory, the back-end interface 302 can write data to or read data from the memory device 104 under the control of the second processor 303. The back-end interface 302 can process commands and data between the memory controller 106 and the memory device 104, such as operations of a NAND flash interface, and in particular, operations between the memory controller 106 and the memory device 104. According to embodiments, the back-end interface 302 can be implemented as a component for exchanging data with the memory device 104 through firmware called a flash interface layer (FIL).

[0085] The second processor 303 can be implemented as a microprocessor or a central processing unit (CPU). The memory system 102 can include one or more second processors 303. The second processor 303 can control overall operations of the memory system 102. As an example and not by way of limitation, the second processor 303 can control a program operation or a read operation of the memory device 104 in response to a write request or a read request from the host 108. According to an embodiment, the second processor 303 can use or run firmware to control overall operations of the memory system 102. In this disclosure, the firmware can be referred to as a flash translation layer (FTL). The FTL can perform operations as an interface between the host 108 and the memory device 104. The host 108 can transmit requests related to write operations and read operations to the memory device 104 through the FTL. For example, the memory controller 106 uses the second processor 303 when performing operations requested from the host 108 in the memory device 104. The second processor 303 coupled with the memory device 104 can process instructions or commands related to commands from the host 108. The memory controller 106 can perform foreground operations such as command operations corresponding to commands input from the host 108, for example, a program operation corresponding to a write command, a read operation corresponding to a read command, an erase / discard operation corresponding to an erase / discard command, and a parameter setting operation corresponding to a set parameter command or a set feature command with a set command.

[0086] For another example, the memory controller 106 can perform background operations on the memory device 104 through the second processor 303. As an example and not by way of limitation, these background operations can include a garbage collection (GC) operation, a wear leveling (WL) operation, a mapping clean operation, and a bad block management operation that checks or searches for bad blocks. The garbage collection operation can include moving data of the memory device 104 (e.g., data of the memory device 104) to another location in the memory device 104, for example, to a location where data is less likely to be used. The wear leveling operation can include moving data of the memory device 104 to another location in the memory device 104 to balance the number of program / erase cycles of the memory device 104. The mapping clean operation can include cleaning a mapping table of the memory device 104 to remove an entry of a block that is no longer used. Figure 4The wear leveling operation can include an operation of copying and processing data stored in a certain memory block of the memory device 104 to another memory block. The mapping flush operation can include an operation of storing mapping data stored in the memory controller 106 in the memory blocks MEMORY BLOCK<0, 1, 2, …> of the memory device 104. The bad block management operation can include an operation of checking and processing a bad block in the memory blocks MEMORY BLOCK<0, 1, 2, …> of the memory device 104. The memory controller 106 can respond to an operation of accessing the memory blocks MEMORY BLOCK<0, 1, 2, …> of the memory device 104, wherein the operation of accessing the memory blocks MEMORY BLOCK<0, 1, 2, …> of the memory device 104 can include a foreground operation or a background operation performed on the memory blocks MEMORY BLOCK<0, 1, 2, …> of the memory device 104.

[0087] The memory 304 can be a working memory of the memory controller 106 configured to store data for driving the memory controller 106. More specifically, when the memory controller 106 controls the memory device 104 in response to a request of the host 108, the memory 304 can store firmware driven by the second processor 303 and data (e.g., metadata) required for driving the firmware. The memory 304 can also be a buffer memory of the memory controller 106 configured to temporarily store write data transmitted from the host 108 to the memory device 104 and read data transmitted from the memory device 104 to the host 108. The memory 304 can include program memory, data memory, write buffer / cache, read buffer / cache, data buffer / cache, and mapping buffer / cache for storing the write data and the read data. The memory 304 can be implemented with volatile memory. The memory 304 can be implemented with static random access memory (SRAM), dynamic random access memory (DRAM), or both.

[0088] Although Figure 3 It is illustrated that the memory 304 is included in the memory controller 106, but the present disclosure is not limited thereto. In an embodiment, the memory 304 can be included outside the memory controller 106, and the memory controller 106 can input and output data to and from the memory 304 through a separate memory interface (not shown).

[0089] Referring back to Figure 1The memory device 104 can be a non-volatile memory device that can retain data stored therein even if not supplied with power. The memory device 104 can store data provided from the host 108 by a write operation; the memory device 104 can also provide stored data to the host 108 by a read operation. In embodiments of the present disclosure, the memory device 104 can be any memory disclosed, such as a volatile memory device of dynamic random access memory (DRAM) and static RAM (SRAM), or a non-volatile memory device such as read only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), ferroelectric RAM (FRAM), phase change RAM (PRAM), magnetoresistive RAM (MRAM), resistive RAM (RRAM or ReRAM), and flash memory (e.g., 3D NAND flash).

[0090] As Figure 4As shown, the memory device 104 can include a plurality of memory blocks MEMORY BLOCK<0, 1, 2,...>. Each memory block can include a plurality of pages P<0, 1, 2, 3, 4,...>. Further, although not specifically shown in the figures, each of the pages P<0, 1, 2, 3, 4,...> can include a plurality of memory cells. Among others, depending on the number of bits that can be stored or represented in a single memory cell, the memory cells are classified into any one of different types of memory blocks such as a single level cell (SLC) memory block and a multi level cell (MLC) memory block. Here, the SLC memory block includes a plurality of pages implemented by memory cells each storing one bit of data. The SLC memory block can have a higher data I / O operation performance and a higher endurance. The MLC memory block includes a plurality of pages implemented by memory cells each storing a plurality of bits of data (e.g., two or more bits). The MLC memory block can have a greater storage capacity for the same space as compared to the SLC memory block. The MLC memory block can be highly integrated in terms of storage capacity. In embodiments, the memory device 104 can be implemented with memory blocks such as a double level cell (DLC) memory block, a trinary level cell (TLC) memory block, a quad level cell (QLC) memory block, or a combination of the above types of level cells. The MLC memory block can include a plurality of pages implemented by memory cells each capable of storing 2 bits of data. The triple level cell (TLC) memory block can include a plurality of pages implemented by memory cells each capable of storing 3 bits of data. The quad level cell (QLC) memory block can include a plurality of pages implemented by memory cells each capable of storing 4 bits of data. In other embodiments, the memory device 104 can include memory blocks composed of memory cells each capable of storing 5 bits or more of data.

[0091] Based on the foregoing system of the exemplary electronic device with the memory system, as Figure 5 As shown, a schematic diagram showing an interaction between a host and a memory system is shown. In Figure 5In the prior art, the process of sending an I / O request from the host to the memory system includes two processes: a process of sending an I / O request from the host to the memory system by a sending thread (i.e., a sending kernel thread), and a process of receiving data related to the I / O request from the memory system to the host by a receiving thread (i.e., a receiving kernel thread). In the former process, the host uses multiple sending kernel threads to send the I / O request to the memory system through the doorbell register. Each sending kernel thread needs a large amount of lock protection to protect shared data at runtime, which has a large lock overhead and takes a lot of time in the locking and unlocking processes, and the efficiency of accessing the memory system is not high. In the latter process, the host receives the data related to the I / O request from the memory system through the interrupt register and the doorbell register. In this process, the host operating system uses an interrupt mechanism to achieve the receiving mode by using interrupt context switching. This receiving mode needs to spend a large amount of time in processing operations such as saving and restoring registers and memory page tables, updating kernel-related data structures, and the like, resulting in a large system overhead. Because the host operating system manages peripherals (including the memory system, such as a storage device) connected to the host, and the speed of the peripherals is much lower than the running speed of the first processor of the host, the first processor of the host cannot monitor the state of the peripherals at all times, and therefore an interrupt mechanism is introduced. The interrupt mechanism can be understood as follows: when the peripherals need the operating system to process peripheral-related events (reading or writing), the peripherals can actively notify the operating system, i.e., interrupt the normal execution between the operating system and an application (APP) contained in the host, let the operating system complete the related processing of the peripherals, and then restore the normal execution between the operating system and the APP. In the above interrupt process, interrupt context switching needs to be applied, for example, the above-described interrupting of the normal execution between the operating system and the APP contained in the host, letting the operating system complete the related processing of the peripherals is an example of interrupt context switching. For another example, restoring the normal execution between the operating system and the APP after the operating system completes the related processing of the peripherals is also an example of interrupt context switching. The interrupt context switching needs to spend a large amount of time in processing operations such as saving and restoring registers and memory page tables, updating kernel-related data structures, and the like, resulting in a large system overhead.

[0092] Therefore, in order to solve the above technical problems, the embodiments of the present disclosure provide a host, which binds a first thread and a second thread (sending kernel thread and receiving thread) on two CPU cores of a processor contained in the host, respectively, to use a dedicated sending kernel thread to send an I / O request, and use a dedicated receiving thread to receive a feedback value of the I / O request, so as to greatly reduce the lock and time overheads.

[0093] As Figure 6As shown, it shows a structural diagram of a host provided by an embodiment of the present disclosure. Specifically, the host 600 includes a processor 601; the processor 601 includes a first central processing unit (CPU) core 6011-1 bound with a first thread and a second CPU core 6011-2 bound with a second thread; wherein

[0094] The first CPU core 6011-1 is configured to, in response to control of the first thread, send an input / output (I / O) request to a storage device coupled with the host;

[0095] The second CPU core 6011-2 is configured to, in response to control of the second thread, receive feedback information related to the I / O request sent by the storage device 800.

[0096] It should be noted that the operating system of the host 600 can be a Linux operating system, that is, the processor 601 herein can run the Linux operating system. The Linux operating system is an interactive system developed from UNIX, which is the first layer of software running on the host 600 and is mainly responsible for the allocation and control of all hardware contained in the host. It also provides services for the running of upper-layer software (such as system software and application software). In actual application, from smartphones to cars, supercomputers and household appliances; from home desktops to enterprise servers, the Linux operating system is widely used. In some embodiments, the storage device can be, but is not limited to, a universal flash storage (UFS) device.

[0097] For understanding of the Linux operating system, please refer to Figures 7-8 . Among them, Figure 7 shows a structural diagram of the Linux operating system; Figure 8 shows a kernel structure diagram of the Linux operating system.

[0098] In Figure 7 , a complete Linux operating system mainly has four parts: hardware, Linux kernel program, operating system service program and user APP, wherein the user APP mainly refers to word processing programs, Internet browser programs or user-developed APPs (such as Taobao and Alipay); the operating system service program mainly refers to programs that provide services to users and are regarded as part of the functions of the operating system. On the Linux operating system, these programs include shell command analysis and Linux kernel programming interface system programs; the Linux kernel program is mainly used for abstraction and access scheduling of hardware resources. The hardware includes but is not limited to CPU, memory, hard disk, storage device (or peripheral device) and the like.

[0099] For the Linux kernel structure, asFigure 8 The Linux kernel is the part of the operating system that is always resident in hardware memory, and its main roles are I / O interaction, memory management, and controlling CPU access. Figure 8 The interrupt and scheduler are also included in the Linux kernel, where the interrupt is the main way for the Linux operating system to interact with peripherals. The scheduler comes into play when an interrupt occurs. The low-level code stops the running process, saves its state in the kernel process structure, and starts the driver. Process scheduling also occurs when the kernel has finished some operations and starts a user process. Figure 8 The scheduler in the Linux kernel is the dispatcher. Note that the scheduler here is the dispatcher, not the scheduler. Both scheduler and dispatcher are concepts related to process (or thread) scheduling, but the difference is that the scheduler randomly selects a process from several processes; while the dispatcher assigns the CPU to the process selected by the scheduler.

[0100] As shown in Figure 8 The Linux kernel is divided into three parts: I / O components, memory components, and process components.

[0101] Among them, the I / O component is responsible for interacting with peripherals and performing network and storage I / O operations. From Figure 8 As shown in the structure diagram of the Linux kernel, the I / O component includes: the highest layer of the virtual file system (VFS), that is, whether the file is from the memory or the disk (or other storage devices) it needs to be processed first through the virtual file system; The bottom layer of the character device driver structure, block device driver structure and network driver structure, where the character device driver structure includes terminals that transmit in characters (such as keyboard, printer, etc.) and character device drivers (programs) that drive these terminals; The block device driver structure includes the file system, the I / O scheduler, and the block (BLOCK) device driver (program); The network driver structure includes the socket network protocol and the network driver device.

[0102] Here, the file system refers to the Linux system used to explicitly define files on storage devices (such as disks, NAND flash, etc.) or partitions. It provides a layer of mapping and translation from files to the physical block layer of the storage device; in other words, it's the system for organizing files on the storage device. The I / O scheduler can refer to a program or structure that performs scheduling processing on the I / O requests provided by the file system. The main difference between character device drivers and block device drivers lies in whether random access is allowed. Character device drivers cannot perform random access; they read and write sequentially in byte streams. Block device drivers use fixed-size blocks and can perform random access. The network driver here is not a separate driver device; it is actually a type of character device, but the processing methods differ. Socket network protocols can include, but are not limited to, TCP / IP, UDP, etc.

[0103] The memory unit is where programs are loaded into and executed by the CPU. The program loading process involves virtual memory, page replacement, and page caching, among other things.

[0104] The process component is responsible for the creation, termination, and scheduling of processes (that is, the process of allocating processes to the corresponding CPU). The Linux kernel treats both processes and threads as runnable entities and uses a unified scheduling policy for scheduling.

[0105] from Figure 8 As shown in the Linux kernel diagram, at the top level of the Linux kernel structure is the system call interface, through which all system calls pass. When a system call is made, it passes the I / O requests from the application running in user mode to the Linux kernel running in kernel mode. The Linux kernel then calls the corresponding kernel function to complete the necessary processing and returns the result to the application.

[0106] For Linux operating system, Linux is a multi-programming system in which processes run independently of each other. Each process owns the necessary resources independently and runs independently. Linux operating system implements multitasking by running these processes in turn at short time intervals, which are called time slices. Here, the way of running processes in turn is called process scheduling, and the program that completes this process scheduling is called a scheduler. Each process runs exclusively on the processor 601. Because of the large switching cost between processes and the slow creation speed and the large resource consumption, the use of threads is generated. In some embodiments, a process can include at least one thread. A thread can be an execution path of a process, which is the smallest unit of program execution and the basic unit of processor core scheduling. In the operating system, compared with the process independently owning various necessary resources, the thread does not exclusively own any additional resources except for some resources necessary for execution (such as the program counter, registers, and stack of the CPU core, etc.), but shares all resources in the same process with other threads in the process. For threads, according to whether the scheduler of the thread is in the Linux kernel or outside the Linux kernel, threads can be divided into user threads (ULT, User Level Thread) and kernel threads (KLT, Kernel Level Thread), wherein the scheduler of the ULT is outside the Linux kernel, and the scheduler of the KLT is in the Linux kernel. Among them, the ULT can be a thread created by a thread library in the user space, and its creation, scheduling, destruction, and communication are all completed in the user space. The Linux kernel does not perceive the ULT and does not directly schedule the ULT. The scheduling object of the Linux kernel is still a process. That is, the Linux kernel does not allocate resources to the ULT, and the ULT only competes for resources in the same process. In this way, if a certain ULT blocks in the Linux kernel, it will cause all other threads in the same process to block, limiting the degree of concurrency of the ULT.

[0107] Based on this, the KLT is created in the Linux kernel, and the Linux kernel can perceive and manipulate the KLT through the data structure contained in the KLT, so the Linux kernel can realize the concurrency between the ULTs in the same process through the KLT.

[0108] Specifically, referring to Figure 9 which shows the mapping relationship between the ULT and the KLT in the Linux operating system. As Figure 9As shown in the figure, in the Linux operating system, a one-to-one mapping relationship is usually adopted between the ULT and the KLT, that is, one ULT is mapped to one KLT, and the running of the ULT must rely on the KLT, that is, the operating system scheduler contained in the Linux kernel allocates the KLT mapped with the ULT to the corresponding CPU core for running. As shown in the figure, Figure 9 As shown in the figure, it is assumed that the process contains CPU core 0 and CPU core 1; three processes A, process B and process C are created in the user space, wherein the process A contains three user threads ULT1 to ULT3; the process B contains two user threads ULT4 and ULT5; and the process C contains one user thread ULT6. In the kernel space, one of the KLTs corresponds to each ULT, that is, ULT1 to ULT6 correspond to KLT1 to KLT6 respectively. In this case, the processor can run two kernel threads mapped with user threads at the same time, for example, KLT2 is run on the CPU core 0; and KLT3 is run on the CPU core 1. Here, the user space can refer to a space that can be operated by a user, such as the user APP and the operating system service program (layer) shown in the figure Figure 7 The user APP and the operating system service program (layer) belong to the user space. The kernel space can refer to a space that cannot be operated by a user and is completed by the Linux kernel, such as the Linux kernel program (layer) shown in the figure Figure 7 The Linux kernel program (layer) belongs to the kernel space.

[0109] By adopting the above mapping mode, the Linux kernel can perceive and manipulate the KLT through the data structure contained in the KLT, and then the Linux kernel can realize the concurrency between the ULTs in the same process through the KLT.

[0110] For example, as shown in the figures Figure 10 and Figure 11 Among them, Figure 10 the figure shows the ULT call relationship diagram when the KLT is not contained; Figure 11 the figure shows the ULT call relationship diagram when the KLT is contained. As shown in the figure, Figure 10 ULT1 of the process 1 will send a data download request to a website through a network card, and the network card is driven and managed by the operating system, so that the ULT1 sends the data download request (GetData) to enter the Linux kernel through a system call to complete. When waiting for the network connection, the operating system will control the CPU to switch to the process 2, and will not switch to the ULT2 of the process 1. The reason is that the operating system cannot perceive the existence of the ULT2 (the thread control module (TCB, Thread Control Block) information corresponding to the ULT is in the user space), and can only call the schedule function to complete the process switching. Therefore, if one ULT is blocked in the Linux kernel, all ULTs of the process will be blocked, which limits the concurrency degree of the ULT.

[0111] As shown in Figure 11 , KLT is created in Linux kernel. The TCB of KLT and other information are created in Linux kernel. Linux kernel can perceive and manipulate KLT through these data structures to realize the concurrency between ULTs in the same process. That is, without KLT, Linux kernel can only switch between processes, as shown in Figure 10 . With KLT, Linux kernel can switch between ULTs in the same process, as shown in 11. The creation of KLT in Linux kernel realizes the concurrency between ULTs.

[0112] In some embodiments, KLT is more suitable for multi-CPU core processors than processes. Specifically, as shown in Figures 12-14 .

[0113] 1. If there are two ULTs. As shown in Figure 12 , a process 1 contains two threads ULT1 and ULT2. Because the operating system cannot perceive ULT, it cannot schedule two ULTs and can only squeeze into one CPU core (such as CPU core 1) to work, and the other CPU core (such as CPU core 2) is always idle. Here, Yield is a Yield function that saves the stack of the thread executed by the current CPU core and takes out the stack pointer of the thread to be executed and assigns it to the register to start execution. The Yield function is a very important concept in concurrent programming. For the memory management unit and the bus as shown in Figure 12 , the bus and the memory management unit in the present disclosure can not be limited, and the bus and the memory management unit that can support the technical solutions of the present disclosure can be used.

[0114] 2. If there are two processes. As shown in Figure 13 , process 1 and process 2, where process 1 contains ULT1 and process 2 contains ULT3. In this case, the Linux operating system can schedule and run the two processes on two CPU cores, which can be parallel on the surface, but the memory resources of the multi-CPU core processor are shared, and it is impossible to simultaneously check the mapping table of the two processes, so in fact the two processes are not parallel but concurrent. In this way, the advantages of multi-CPU core processors are not brought into play.

[0115] 3. If there are two KLTs. As shown in Figure 14 , a process 1 contains two threads ULT1 and ULT2, and each ULT corresponds to a KLT. Because KLT is created in the Linux kernel, the Linux operating system can schedule KLT; because the threads in the same process can share memory resources and there is no bottleneck of the process, the hardware processing speed is accelerated to realize parallelism.

[0116] For a multi-CPU core processor, when a KLT in the Linux kernel is scheduled, which CPU core it is assigned to run is determined by a scheduling algorithm in the dispatcher in the Linux kernel, and the KLT is not fixed to a CPU core. Furthermore, since an ULT is an execution unit in a process, it can run in parallel with other ULTs in the same process through multiple KLTs in different CPU cores, and because the ULTs share the resources of the same process, such as memory, address space, and open file resources, mechanisms such as mutual exclusion, locking, serialization, etc. between KLTs need to be implemented to ensure the consistency and synchronization of shared data (such as global data). In other words, when multiple KLTs are assigned to multiple CPU cores to run, in order to avoid multiple KLTs on multiple CPU cores accessing global data at the same time, when a KLT on a CPU core accesses global data, a lock needs to be added to ensure that the KLT on the CPU core can access the global data, and other CPU cores cannot access the global data. Therefore, the technical problem shown in Figure 5 is that when multiple KLTs are used, a large number of lock protections need to be added, resulting in a large amount of lock overhead.

[0117] To solve the above technical problems, the present disclosure provides a host as shown in Figure 6 binds a first thread to a first CPU core to send an I / O request using a dedicated sending kernel thread; and binds a second thread to a second CPU core to receive a feedback value of the I / O request using a dedicated receiving thread, thereby reducing the lock overhead required when using shared global data. Wherein the first CPU core and the second CPU core can be included in the processor core 6011, that is, Figure 6 The processor 601 shown in may be a first processor 201 as described above, which can be a multi-CPU core processor. Based on this, in some embodiments, the first CPU core and the second CPU core can refer to two of the multiple CPU cores described above, and the first CPU core can be any one of the multiple CPU cores; the second CPU core can be any one of the multiple CPU cores except the first CPU core. The first thread described here can be a sending kernel thread in the Linux kernel; the second thread described can be a receiving kernel thread in the Linux kernel.

[0118] The understanding of the binding can be as follows: the first thread is bound to the first CPU core, that is, the first CPU core is dedicated to processing the first thread, and the first thread is only allocated to the first CPU core for running, in other words, the first CUP core is only controlled by the first thread. Similarly, the second thread is bound to the second CPU core, that is, the second CPU core is dedicated to processing the second thread, and the second thread is only allocated to the second CPU core for running. By adopting such a kernel thread binding to a dedicated CPU core for running, the number of first threads (such as sending kernel threads) and second threads can be reduced, and the number of lock protections for global data can be reduced, thereby reducing the lock overhead; and reducing the time overhead required for lock protection.

[0119] In some embodiments, the I / O request can be generated by an application running on the processor, and the I / O request is converted by a device driver running on the processor into one or more request commands in a format supported by the storage device.

[0120] That is, the I / O request can be generated by an APP. And converted by a device driver into one or more request commands in a format supported by the storage device, and sent to the storage device. Wherein, the device driver can refer to the block device driver shown in Figure 8 .

[0121] For how the I / O request is transmitted from the APP to the device driver. Take a Linux-based storage system as an example for illustration.

[0122] Referring to Figure 15 , the Linux-based storage system includes a VFS layer, a file system layer, a Page Cache cache layer, a general Block layer, an I / O scheduling layer, a Block device driver layer, and a Block device layer. Wherein, the interaction relationship between each layer of the Linux-based storage system, please refer to Figures 16-20 .

[0123] Specifically, the interaction process can be as follows: When the host initiates a random read / write operation on a data page or a sequential read / write operation on a log file, the host's processor actually hands over the I / O requests generated by the application to the Linux operating system's VFS layer. The VFS layer's role is to determine the I / O request based on the host's processor's operation on files in the selected directory, and then assign the I / O request to the specific file system. For example, in Linux, some directories, such as / AA1 / AA2, are actually managed by the NFS file system, while others, such as / AA3 / AA4, are managed by the Ext3 file system. In this case, the VFS layer needs to determine the read / write I / O request initiated on files in the selected directory (e.g., / AA1 / AA2) and forward the request to the corresponding file system (such as NFS). Figure 16 As shown.

[0124] Next, the file system will first check if the required data is in the Page Cache, a memory-based cache. If it is, the read / write operation will be performed based on the memory cache. If not, it will continue to the next layer. At this point, the I / O request will be handed over to the general Block layer, where the file I / O request will be converted into a Block I / O request, such as... Figure 17 As shown.

[0125] After the I / O request is converted into a Block I / O request, this Block I / O request is handed over to the I / O scheduling layer, such as... Figure 18 As shown. The function of this layer is to sort multiple Block I / O requests and determine the order in which each Block I / O request is sent. The scheduling algorithm used can be either the Completely Fair Scheduler (CFQ) algorithm or the deadline I / O scheduling algorithm.

[0126] After the I / O requests are finally scheduled, it's determined which Block I / O requests will execute first and which will execute later. The executable Block I / O requests are then handed over to the Block device driver layer (which runs device drivers). Finally, the Block device driver layer translates the I / O requests into one or more request commands and sends them to the actual storage hardware (storage device), which is the Block device layer itself. Figure 19 As shown.

[0127] After the storage device completes its I / O read / write operation (either a write operation or a rewrite operation), it returns the response in reverse order through the hierarchical structure described above. Finally, the host side receives the result of this I / O read / write operation.Figure 20 as shown.

[0128] In some embodiments, the I / O request can be, but not limited to, a read request, a data storage (or write) request, a data discard request.

[0129] In some embodiments, as shown, the processor 601 further comprises a device interface 6012; the device interface comprises a host controller interface (HCI) 6012A; the host controller interface comprises an interrupt register 6012A-1; Figure 21

[0130] The second CPU core 6011-2 is further configured to, in response to the control of the second thread, poll the interrupt register to receive the feedback information.

[0131] In some embodiments, the second CPU core 6011-2 is specifically configured to, in response to the control of the second thread, periodically access the interrupt register at a preset time interval to determine whether the feedback information is received in the interrupt register; if the feedback information is received, obtain the feedback information from the interrupt register.

[0132] It should be noted that the above describes some operations of the second CPU core when the second thread is running. When the second thread is a receiving kernel thread, the second CPU core polls the interrupt register contained in the HCI in response to the control of the second thread, so as to receive the aforementioned feedback information related to the I / O request. The feedback information can be, for example, the return data as shown. Figure 20

[0133] The process of polling the interrupt register by the second CPU core in response to the control of the second thread described herein can include that the second CPU core periodically accesses the interrupt register at a preset time interval. The preset time interval can be set according to actual conditions.

[0134] The present disclosure adopts a polling strategy when receiving the feedback information, so that the entire process of receiving the feedback information can be processed in one thread. Compared with the interrupt handling mechanism, the polling strategy eliminates the large overhead caused by the interrupt context switching in the interrupt handling mechanism.

[0135] In some embodiments, as shown, the host 60 further comprises a memory 602; the memory 602 is configured to store a request command queue; the request command queue comprises one or more request commands; the one or more request commands correspond to one or more I / O requests; Figure 22

[0136] ​​​The first CPU core 6011-1 is configured to obtain one or more request commands from the request command queue and send the one or more request commands to the storage device in response to control of the first thread.

[0137] It should be noted that the one or more request commands are formed after the I / O request is converted by the device driver, and the request command queue is formed by storing the request commands in the memory in the form of a queue. The request command queue can be a sequential queue or a linked list queue. The sequential queue adopts a first-in first-out constraint. The linked list queue can adopt a first-in first-out constraint or other constraints, such as first-in last-out.

[0138] Specifically, the disclosure only illustrates the role of the request command queue and how to use it in the queue with a first-in first-out constraint. That is, the first CPU core 6011-1 obtains the request commands from the memory according to the order in which the request commands are stored, and sends the request commands. Here, the memory 602 can be the same as the memory 304 described above, and can include program memory, data memory, write buffer / cache, read buffer / cache, data buffer / cache, and mapping buffer / cache for storing write data and read data. The memory 602 can be implemented by using volatile memory. The memory 602 can be implemented by using static random access memory (SRAM), dynamic random access memory (DRAM), or both.

[0139] In some embodiments, as shown in FIGS. 6A and 6B, the host controller interface 6012A further includes a doorbell register 6012A-2. Figure 21 and 22 The doorbell register 6012A-2 is configured to store feedback information corresponding to the I / O request.

[0140] The second CPU core 6011-2 is further configured to access the doorbell register to determine the I / O request corresponding to the feedback information.

[0141] In some embodiments, the first CPU core is further configured to access the doorbell register to assign a required transmission channel to the I / O request in the ready state.

[0142] It should be noted that the doorbell register is also referred to as a Doorbell register. The Doorbell register provides a request command issuing channel (including a transmission channel of the request command from the host side to the storage device side) for multiple CPU cores, and each CPU core can send a request command to the storage device through the Doorbell register or receive feedback information of the request command through the Doorbell register and determine the I / O request corresponding to the received feedback information. That is, the first CPU core and the second CPU core both need to obtain a transmission channel of data or the source of data by accessing the Doorbell register.

[0143] In the present disclosure, for the access to the Doorbell register, in some embodiments, the access to the Doorbell register is in a lock access manner, wherein the lock access manner includes that the Doorbell register is only accessed by the first CPU core or the second CPU core at the same time.

[0144] That is, the Doorbell register is only accessed by the first CPU core or the second CPU core at the same time. Taking the first CPU core as an example, when the first CPU core sends a request command through the Doorbell register, the Doorbell register will be locked, and at this time the second CPU core will not be able to access the Doorbell register.

[0145] Specifically, the Doorbell register can include 32 bits, and each bit represents a delivery channel of an I / O request sent by a host to a storage device. In some embodiments, the bits corresponding to the delivery channels used in the Doorbell register are set to 1, and the remaining bits are maintained as 0. Based on this, the specific process of the first CPU core accessing the Doorbell register described in the present disclosure to assign the required transmission channel for the I / O request in the ready state can be as follows: the first CPU core first traverses the 32 delivery channels (also transmission channels) included in the Doorbell register to determine a delivery channel that is not occupied by other CPU cores, wherein the identification bit of the unoccupied delivery channel can be 0; the identification bit of the occupied delivery channel can be 1. The first CPU core sets the identification bit of the selected unoccupied delivery channel from 0 to 1, thereby indicating that the delivery channel is occupied. The first CPU core sends a request command to the storage device through the delivery channel. After completing the sending of the request command, the first CPU core releases the lock on the Doorbell register, so that other CPU cores (such as the second CPU core) can also access the Doorbell register.

[0146] For the specific process of the second CPU core 6011-2 accessing the Doorbell register described in the present disclosure to determine the I / O request corresponding to the feedback information, the following can be performed: compare the current value of the Doorbell register with the list of previously issued but not completed commands of the host, wherein since each bit in the Doorbell register is 0 indicates that the request command has been completed, and each bit in the Doorbell register is 1 indicates that the request command has not been completed. Since the Doorbell register is in a lock access manner, only one bit in the Doorbell register is 1 for each sending of a request command, so the I / O request corresponding to the feedback information can be determined.

[0147] In some embodiments, as Figure 23As shown, the device interface further includes: a UniPro circuit and an M-PHY circuit 6012B, wherein;

[0148] The UniPro circuit and the M-PHY circuit are connected with the host controller interface and are configured to: send a request command to the storage device or receive feedback information sent by the storage device, wherein the request command is generated based on the I / O request.

[0149] It should be noted that the UniPro circuit and the M-PHY circuit 6012B can be a UFS interconnect (UIC) layer on the host side, which is an interface for the host to directly connect with the storage device. The specific implementation of the UniPro circuit and the M-PHY circuit can refer to the UniPro protocol and the M-PHY protocol, and will not be described here.

[0150] For the purpose of understanding the present disclosure, reference is made to Figure 24 which shows a flowchart of sending an I / O request by a host to a storage device and receiving feedback information according to an embodiment of the present disclosure. In Figure 24 , a sending thread is bound to a CPU core X and a receiving thread is bound to a CPU core Y. When the host sends a request command to the storage device, the sending thread on the CPU core X acquires the request command from a request command queue stored in the memory in a first-in-first-out manner, and sends the acquired request command to the storage device. When the host receives feedback information sent by the storage device, the receiving thread on the CPU core Y accesses the interrupt register in a polling manner, and processes the feedback information when the interrupt register receives the feedback information. That is, two special CPU cores are used to process the I / O request between the host and the storage device, which reduces a large amount of overhead.

[0151] Based on the same inventive concept, an information processing method of a host is also provided according to an embodiment of the present disclosure, as shown in Figure 25 , the method can include:

[0152] S2501: binding a first thread to a first central processing unit (CPU) core included in the host;

[0153] S2502: binding a second thread to a second CPU core included in the host; wherein when the first thread is running, the first CPU core is controlled to send an input / output (I / O) request to a storage device coupled to the host; and when the second thread is running, the second CPU core is controlled to receive feedback information related to the I / O request sent by the storage device.

[0154] In some embodiments, the controlling the second CPU core to receive the feedback information related to the I / O request from the storage device when the second thread is running further includes:

[0155] The controlling the second CPU core to poll an interrupt register included in the host to receive the feedback information when the second thread is running.

[0156] In some embodiments, the controlling the second CPU core to poll the interrupt register included in the host to receive the feedback information includes: periodically accessing the interrupt register according to a preset time interval to determine whether the feedback information is received in the interrupt register; and if the feedback information is received, obtaining the feedback information from the interrupt register.

[0157] In some embodiments, the controlling the first CPU core to send the I / O request to the storage device coupled to the host when the first thread is running includes:

[0158] The controlling the first CPU core to obtain one or more request commands from a request command queue stored in a memory of the host and send the one or more request commands to the storage device when the first thread is running.

[0159] The one or more request commands correspond to the one or more I / O requests.

[0160] In some embodiments, the method further includes:

[0161] The controlling the first CPU core to access a doorbell register included in the host to assign a required transmission channel for the I / O request in the ready state when the first thread is running.

[0162] The controlling the second CPU core to access the doorbell register to determine the I / O request corresponding to the feedback information when the second thread is running.

[0163] In some embodiments, the doorbell register is accessed in a lock access mode, where the lock access mode includes that the doorbell register is only accessed by the first CPU core or the second CPU core at the same time.

[0164] It should be noted that the information processing method of the host provided by the embodiments of the present disclosure and the host provided above belong to the same inventive concept. The specific implementation of each step described herein has been described in detail above, and can be understood by referring to the foregoing description, which will not be described here.

[0165] The embodiments of the present disclosure also provide an electronic system 2600, as shown in Figure 26 may include:

[0166] The host 2601 comprises a processor; the processor is configured to: bind a first thread to a first central processing unit (CPU) core included in the processor; and bind a second thread to a second CPU core included in the processor; run the first thread to control the first CPU core to send an input / output (I / O) request to a storage device;

[0167] The storage device 2602 coupled to the host; the storage device is configured to: receive and process the I / O request; generate feedback information related to the I / O request; and send the feedback information to the host;

[0168] The processor is further configured to: run the second thread to control the second CPU core to receive the feedback information sent by the storage device.

[0169] In some embodiments, the processor further comprises: a device interface; the device interface comprises a host controller interface; the host controller interface comprises an interrupt register;

[0170] The second CPU core is further configured to: in response to the control of the second thread, periodically send a first access command to the interrupt register at a preset time interval;

[0171] The interrupt register is configured to: in response to the first access command, send the feedback information to the second CPU core when the feedback information sent by the storage device is received.

[0172] In some embodiments, the host further comprises a memory; the memory is configured to store a request command queue; the request command queue comprises one or more request commands; the one or more request commands correspond to one or more I / O requests;

[0173] The first CPU core is further configured to: in response to the control of the first thread, send a second access command to the memory;

[0174] The memory is configured to: in response to the second access command, obtain the one or more request commands from the request command queue, and send the one or more request commands to the first CPU core;

[0175] The first CPU core is further configured to: send the one or more request commands to the storage device.

[0176] It should be noted that the "first" and "second" in the first access command and the second access command appearing herein are only for the convenience of describing the access commands in different processes, and are not used for the limitation of quantity. That is, the first access command is the access command sent by the second CPU core when accessing the interrupt register; and the second access command is the access command sent by the first CPU core when accessing the memory. The electronic system provided in the embodiments of the present disclosure comprises the host provided in the foregoing, and the description of the host can be referred to the foregoing description of the host, which will not be described herein again. The storage device comprises, for example, the foregoingFigures 1-5 The storage system shown is not described again here.

[0177] The embodiments of the present disclosure further provide a computer readable storage medium, which stores a computer program. The computer program is executed by a processor to implement the steps of any of the above methods. The aforementioned storage medium includes: a mobile storage device, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0178] It should be noted that, in several embodiments provided by the present disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. In actual implementation, another division mode can be used, such as: a plurality of units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the various components shown or discussed can be indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0179] The units described above as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e. they can be located in one place or distributed on multiple network units; some or all of the units can be selected according to actual needs to achieve the purpose of the present embodiment.

[0180] In addition, each functional unit in each embodiment of the present disclosure can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be realized in the form of hardware or in the form of hardware plus software functional unit.

[0181] Those of ordinary skill in the art can understand that all or part of the steps of the above method embodiments can be completed by program instruction related hardware, and the aforementioned program can be stored in a computer readable storage medium. The program is executed to perform steps including the above method embodiments; and the aforementioned storage medium includes: a mobile storage device, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0182] Alternatively, the above-mentioned integrated units of the present disclosure, if implemented in the form of software function modules and sold or used as independent products, can also be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present disclosure can be embodied in the form of a software product in essence or in the form of a contribution to the prior art. The computer software product is stored in a storage medium, and includes a number of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in the various embodiments of the present disclosure. The aforementioned storage medium includes: mobile storage devices, ROM, RAM, magnetic disks or optical disks, and various media that can store program codes.

[0183] The above is merely specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A host comprising: A processor; The processor comprises a first CPU core bound with a first thread and a second CPU core bound with a second thread; wherein, The first CPU core is dedicated to processing the first thread; the first CPU core is configured to send an I / O request to a storage device coupled with the host in response to the control of the first thread; The second CPU core is dedicated to processing the second thread; the second CPU core is configured to receive feedback information related to the I / O request sent by the storage device in response to the control of the second thread; wherein the processor further comprises a device interface; the device interface comprises a host controller interface; the host controller interface comprises an interrupt register; The second CPU core is further configured to poll the interrupt register to receive the feedback information in response to the control of the second thread.

2. The host of claim 1, wherein, The second CPU core is particularly configured to access the interrupt register at a preset time interval to determine whether the feedback information is received in the interrupt register in response to the control of the second thread; if the feedback information is received, the feedback information is obtained from the interrupt register.

3. The host of claim 1, wherein, The host further comprises a memory; the memory is configured to store a request command queue; The request command queue comprises one or more request commands; the one or more request commands correspond to one or more I / O requests; The first CPU core is configured to obtain the one or more request commands from the request command queue and send the one or more request commands to the storage device in response to the control of the first thread.

4. The host of claim 1, wherein, The host controller interface further comprises a doorbell register; The second CPU core is further configured to access the doorbell register to determine the I / O request corresponding to the feedback information.

5. The host of claim 4, wherein, The first CPU core is further configured to access the doorbell register to allocate a required transmission channel for the I / O request in a ready state.

6. The host of claim 5, wherein, The access mode of the doorbell register is a locking access mode, wherein the locking access mode comprises that the doorbell register is accessed by only the first CPU core or the second CPU core at the same time.

7. The host of claim 1, wherein, The I / O request is generated by an application program running on the processor, and the I / O request is converted into one or more request commands in a format supported by the storage device by a device driver running on the processor.

8. The host of claim 1, wherein, The device interface further comprises a joint protocol circuit and an M-physical interface circuit, wherein; The joint protocol circuit and the M-physical interface circuit are connected with the host controller interface and are configured to send a request command to the storage device or receive the feedback information sent by the storage device, wherein the request command is generated based on the I / O request.

9. The host of claim 1, wherein, The storage device is a universal flash storage (UFS) device.

10. The host of claim 1, wherein, The operating system running in the host is a Linux operating system.

11. The host of claim 1, wherein, The processor includes a plurality of CPU cores, wherein the first CPU core is any one of the plurality of CPU cores; and the second CPU core is any one of the plurality of CPU cores except the first CPU core.

12. An information processing method of a host, comprising: binding a first thread to a first central processing unit (CPU) core included in the host, the first CPU core being dedicated to processing the first thread; binding a second thread to a second CPU core included in the host, the second CPU core being dedicated to processing the second thread; wherein, when the first thread is running, the first CPU core is controlled to send an input / output (I / O) request to a storage device coupled to the host; and when the second thread is running, the second CPU core is controlled to receive feedback information related to the I / O request sent by the storage device; wherein, when the second thread is running, the second CPU core is controlled to receive the feedback information, further comprising: when the second thread is running, the second CPU core is controlled to poll an interrupt register included in the host to receive the feedback information.

13. The method of claim 12, wherein, The control of the second CPU core to poll the interrupt register included in the host to receive the feedback information comprises: periodically accessing the interrupt register at a preset time interval to determine whether the feedback information is received in the interrupt register; and if the feedback information is received, obtaining the feedback information from the interrupt register.

14. The method of claim 12, wherein, The control of the first CPU core to send an I / O request to a storage device coupled to the host when the first thread is running comprises: when the first thread is running, the first CPU core is controlled to obtain one or more request commands from a request command queue stored in a memory of the host, and send the one or more request commands to the storage device; wherein the one or more request commands correspond to one or more I / O requests.

15. The method of claim 12, wherein, The method further comprises: when the first thread is running, the first CPU core is controlled to access a doorbell register included in the host to allocate a required transmission channel for the I / O request in a ready state; when the second thread is running, the second CPU core is controlled to access the doorbell register to determine the I / O request corresponding to the feedback information.

16. The method of claim 15, wherein, The access mode of the doorbell register is a lock access mode, wherein the lock access mode comprises that the doorbell register is accessed by only the first CPU core or the second CPU core at the same time.

17. An electronic system, comprising: a host; the host comprises a processor; the processor is configured to: bind a first thread to a first central processing unit (CPU) core included in the processor, the first CPU core being dedicated to processing the first thread; and bind a second thread to a second CPU core included in the processor, the second CPU core being dedicated to processing the second thread; run the first thread to control the first CPU core to send an input / output (I / O) request to a storage device; and a storage device coupled with the host; the storage device is configured to: receive and process the I / O request; generate feedback information related to the I / O request; and send the feedback information to the host; the processor is further configured to run the second thread to control the second CPU core to receive the feedback information sent by the storage device; wherein the processor further comprises a device interface; the device interface comprises a host controller interface; and the host controller interface comprises an interrupt register; the second CPU core is further configured to, in response to the control of the second thread, periodically send a first access command to the interrupt register at a preset time interval; the interrupt register is configured to, in response to the first access command, send the feedback information to the second CPU core when the feedback information sent by the storage device is received.

18. The electronic system of claim 17, wherein, the host further comprises a memory; the memory is configured to store a request command queue; the request command queue comprises one or more request commands; and the one or more request commands correspond to one or more I / O requests; the first CPU core is further configured to, in response to the control of the first thread, send a second access command to the memory; the memory is configured to, in response to the second access command, obtain the one or more request commands from the request command queue and send the one or more request commands to the first CPU core; the first CPU core is further configured to send the one or more request commands to the storage device.

19. A computer readable storage medium having stored thereon a computer program, the computer program being executed by a processor to implement the method of any one of claims 12 to 16.

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