Method and apparatus for branch instruction security

Abstract

Aspects of the present disclosure relate to an apparatus. The instruction receiving circuitry receives a branch instruction as part of a program stream, the branch instruction identifying a function. The instruction authentication circuit determines an instruction authentication value based at least in part on the function. The instruction authentication circuit then combines the instruction authentication value with the branch instruction to produce an authenticable branch instruction. The branch circuit authenticates the authenticable branch instruction based on the functional authentication value. In response to successful authentication of the authenticatable branch instruction, the branch circuit performs a jump to the function in the program stream.

Description

Background Art

[0001] The present technology relates to the field of authentication of pointers and branch instructions.

[0002] In some processing systems, pointers are vulnerable to malicious attacks. For example, pointers may be maliciously modified to modify the operation of a program, such as redirecting program flow in an unintended manner.

[0003] Similarly, branch instructions, which cause program flow to jump to a different point in a series of instructions, may be maliciously modified to redirect program flow.

[0004] There are methods for mitigating such malicious attacks. For example, a pointer can be cryptographically signed, and the signature used to verify the pointer. Similarly, the security of branch instructions can be improved by providing a way to verify branch instructions.

[0005] However, such mitigations may not provide overall security and thus may still present a risk of malicious attacks.Therefore, methods for improving the security of pointer and branch instructions are needed. Summary of the invention

[0006] At least some examples provide an apparatus comprising:

[0007] An instruction receiving circuit, the instruction receiving circuit is used to receive a branch instruction as part of a program flow, wherein the branch instruction identifies a function;

[0008] A command authentication circuit, the command authentication circuit is used to:

[0009] determining an instruction authentication value based at least in part on the function; and

[0010] combining the instruction authentication value with the branch instruction to generate an authenticatable branch instruction, and

[0011] A branch circuit is used for:

[0012] authenticating the authenticatable branch instruction based on the function authentication value; and

[0013] A jump in the program flow to the function is performed in response to successful authentication of the authenticatable branch instruction.

[0014] Another example provides a method comprising:

[0015] receiving a branch instruction as part of a program flow, the branch instruction identifying a function;

[0016] determining a command authentication value based at least in part on the function;

[0017] combining the instruction authentication value with the branch instruction to generate an authenticatable branch instruction;

[0018] authenticating the authenticatable branch instruction based on the function authentication value; and

[0019] A jump in the program flow to the function is performed in response to successful authentication of the authenticatable branch instruction.

[0020] Another example provides a non-transitory computer-readable medium for storing a computer-readable code for manufacturing the above-mentioned apparatus.

[0021] Another example provides a computer program for controlling a host data processing device to provide an instruction execution environment, the computer program comprising:

[0022] Instruction receiving logic, the instruction receiving logic is used to receive a branch instruction as part of a program flow, the branch instruction identifying a function;

[0023] Instruction authentication logic, which is used to:

[0024] determining an instruction authentication value based at least in part on the function; and

[0025] combining the instruction authentication value with the branch instruction to generate an authenticatable branch instruction, and

[0026] Branching logic, which is used to:

[0027] authenticating the authenticatable branch instruction based on the function authentication value; and

[0028] A jump in the program flow to the function is performed in response to successful authentication of the authenticatable branch instruction.

[0029] Further aspects, features and advantages of the present technology will be apparent from the following description of examples read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figures 1A to 1C An apparatus according to an example is schematically depicted.

[0031] FIG. 2A to FIG. 2C Depicted is pointer authentication in a comparative example.

[0032] FIG. 3A to FIG. 3C Pointer authentication according to an example is depicted.

[0033] Figure 4A and Figure 4B Branch instruction authentication according to an example is depicted.

[0034] Figure 5A and Figure 5B Depicted is the generation and authentication of a signed cryptographic pointer according to an example.

[0035] Figure 6 and Figure 7 An example method is depicted.

[0036] Figure 8 Computer readable media according to examples are depicted.

[0037] Fig. 9 An example simulator implementation is depicted. DETAILED DESCRIPTION

[0038] In an example of the present disclosure, a device has an interface circuit and a pointer processing circuit. These circuits can be dedicated circuit components or logic units implemented by general circuits such as a central processing unit or other processor. For example, the device described herein can be implemented by a component of a processor responsible for processing pointers.

[0039] The interface circuit is configured to receive a pointer. The pointer includes a plurality of address bits that identify a memory location to which the pointer points. For example, the pointer may be generated as part of the execution of a series of processing instructions.

[0040] The pointer processing circuit is configured to extract a plurality of address bits from the pointer. The pointer processing circuit then encrypts the plurality of address bits to generate a plurality of encrypted address bits.

[0041] The pointer processing circuit is further configured to determine a pointer authentication value based at least in part on the plurality of address bits. This may be based on, for example, hashing and / or encrypting the plurality of address bits.

[0042] The pointer processing circuitry then combines the pointer authentication value with a plurality of encrypted address bits to produce a signed encrypted pointer. In effect, the pointer authentication value serves as a signature for the pointer, which can be used to authenticate the pointer. For example, if the address bits have been maliciously modified, the pointer authentication value will no longer match the address bits.

[0043] Encryption of address bits is used to improve security. In particular, in some comparative examples that do not implement the present disclosure, address bits may be modified and corresponding pointer signature values ​​may be guessed. This is particularly dangerous in systems where relatively few bits are available for signatures, such as where a given size is available for storing pointers and signatures are stored in spare bits not used for addresses.

[0044] In contrast, in this example, encryption of the address bits significantly reduces the risk of an attacker modifying the address bits and correctly guessing the corresponding authentication value. This improves system security. This is particularly effective in systems where pointer address bits are not expected to change once they are set. This approach is also particularly effective in systems where it is architecturally unnecessary for the address portion of the signature pointer to be the actual address: in such cases, the signed encrypted pointer can be stored in the same manner as the unencrypted signed pointer.

[0045] In an example, the pointer processing circuit performs a cryptographic shuffle on the combined pointer authentication value and the encrypted address bits. This further improves security because a malicious attacker will not be able to determine which bits (and in what order) correspond to the address and which bits correspond to the pointer authentication value. This can be performed particularly efficiently by performing the shuffle based on the same cryptographic key used to encrypt multiple address bits. This cryptographic key can be a pointer authentication code (PAC) key that is kept secret by the device and stored in a software-inaccessible memory (such as a system register). Key security can be improved by limiting access to the key to processes with a high privilege level. In addition to the key, a cryptographic modifier can also be applied to increase the difference of the key.

[0046] As described above, the actual address bits are obfuscated by means of encryption. In some examples, the pointer processing circuit is further configured to obfuscate the pointer authentication value, thereby further improving security. This can be performed, for example, by means of at least one of hashing and encrypting the pointer authentication value. Such encryption can be efficiently performed using the same encryption key used to encrypt the address bits.

[0047] The above description sets forth various ways in which a signed encrypted pointer may be generated. Various ways will now be described for decrypting and authenticating such a signed encrypted pointer, for example as part of a subsequent processing instruction requiring the address to which the pointer points.

[0048] In an example, the apparatus includes a pointer decryption circuit configured to extract a pointer authentication value and authenticate the signed encrypted pointer based on the extracted pointer authentication value. In some examples where cryptographic shuffling is performed on the combined authentication value and the pointer, the extracting may include performing cryptographic deshuffling of the signed encrypted pointer and extracting a block of bits corresponding to the pointer authentication value from the deshuffled signed encrypted pointer.

[0049] In order to authenticate the signed encrypted pointer, the pointer decryption circuit confirms that the pointer authentication value correctly matches the address bits. For example, the pointer decryption circuit can extract multiple encrypted address bits and decrypt the multiple encrypted address bits. The above process for initially determining the pointer authentication value can then be repeated to determine the recalculated pointer authentication value. It can then be verified whether the extracted (and decrypted) pointer authentication value matches the recalculated pointer authentication value. If they match, it can be determined that the signed encrypted pointer is authenticated and the extracted address bits are safe for further processing. For example, the pointer decryption circuit can respond to the successful authentication of the signed encrypted pointer to execute processing instructions based on the address bits of the pointer.

[0050] Conversely, the pointer decryption circuit identifies an error in response to a failed authentication of a signed encrypted pointer. For example, this may mean that the pointer has been maliciously altered and should be discarded.

[0051] In the description above, the address bits of the pointer are encrypted before being combined with the pointer authentication value. However, in other examples, the unencrypted address bits are combined with the pointer authentication value and the combination is then encrypted. In such examples, the pointer processing circuit is configured to extract multiple address bits from the pointer and determine the pointer authentication value based at least in part on the address bits. The pointer processing circuit then combines the pointer authentication value with the multiple address bits and encrypts the combination to generate a signed encrypted pointer. Similar to the previous example, this has the final result of generating a signed encrypted pointer that is resilient to malicious attacks. In some systems (e.g., depending on the specific configuration of a given device), this example may be particularly efficient in computation.

[0052] The above description relates to pointer security. However, similar processes can be applied to improve the security of branch instructions. Examples of such processes will now be described. These processes can optionally be performed in combination with the above-described pointer security processes: this synergistically improves security and improves efficiency relative to applying one process or the other alone (particularly where the same circuit or logic component can be used for both processes).

[0053] In one such example, an apparatus includes instruction receiving circuitry for receiving a branch instruction as part of a program flow. The branch instruction directs the program flow to jump to another location within a series of processing instructions. In this example, the branch instruction identifies a function, for example, by identifying a branch target (or "landing pad") that is the first instruction in the function.

[0054] The apparatus also includes an instruction authentication circuit configured to determine an instruction authentication value based at least in part on a function. Similar to the pointer authentication value described above, the instruction authentication value can be based on data indicating at least a portion of the code corresponding to the function. For example, this data can be a hash or digest of the code.

[0055] The instruction authentication circuit is configured to combine the instruction authentication value with the branch instruction to generate an authenticatable branch instruction. Specifically, the branch instruction can be authenticated with reference to the instruction authentication value.

[0056] The device also includes a branch circuit that is configured to authenticate a verifiable branch instruction based on a function authentication value. This can be performed, for example, before executing a branch instruction to confirm that the branch instruction has not been tampered with. The instruction can be authenticated by comparing the instruction authentication value with the function authentication value. For example, the function authentication value can be a known value that will be equal to the correct instruction authentication value. In this example, the branch circuit can be configured to determine the successful authentication of the verifiable branch instruction in response to the instruction authentication value matching the function authentication value. This provides an effective way to authenticate the branch instruction.

[0057] In response to successful authentication of the authenticatable branch instruction, the branch circuitry executes a jump in program flow to the aforementioned function.

[0058] In this way, the present apparatus provides additional security for branch instructions relative to comparative examples where branch instructions are not authenticatable. In such comparative examples, branch instructions may be tampered with, for example, to cause a jump to malicious code. In this example, such tampering will cause the branch instruction to correspond longer to the instruction authentication value, which will be detected as a failed authentication of an authenticatable branch instruction.

[0059] In some examples, a function authentication value may be stored in the code corresponding to the function. In particular, this function authentication value may be stored in the code corresponding to the function immediately after a branch target indicator (or "landing pad"). A branch target indicator is an instruction type for providing a potential target for a branch target instruction. In such examples, it is possible to force a branch instruction to not define a branch to an arbitrary code location, but only to effectively target a branch target instruction. This improves security, but a comparative example that implements a branch target instruction without using the currently described technology may still have security weaknesses. For example, a malicious attacker may modify a branch instruction to identify a branch target instruction in an incorrect function. The present technology significantly improves security relative to such comparative examples because the present technology provides a guarantee that the branch target instruction still identifies the correct function it originally targeted: the instruction authentication value is compared with the function authentication value immediately after the branch target instruction pointed to by the branch instruction.

[0060] As described above, the branch circuit responds to successful authentication by executing the branch instruction. Conversely, the branch circuit may respond to unsuccessful authentication of the authenticatable branch instruction to identify an error. The error may be resolved by refusing to follow the branch instruction and / or reporting an error and stopping execution of the processing instruction stream.

[0061] In an example, the aforementioned combination of a branch instruction and an instruction authentication value includes performing a cryptographic shuffle on the branch instruction and the instruction authentication value. This obscures the identity of the bits corresponding to the instruction and the bits corresponding to the authentication value, thereby increasing the difficulty of successfully tampering with the authenticatable instruction. In particular, this makes it significantly more difficult to tamper with the instruction in a manner that will still pass the authentication process.

[0062] Alternatively or additionally, the instruction authentication circuit may be configured to encrypt the branch instruction or the combination of the branch instruction and the authentication value using a cryptographic key. This improves security by reducing the likelihood that the branch instruction may be tampered with in the manner in which it will pass the authentication process. The encryption and the aforementioned cryptographic shuffling may be efficiently performed using the same cryptographic key.

[0063] In an example, the branch circuit is configured to extract an instruction authentication value from the authenticatable instruction, and to perform authentication of the authenticatable branch instruction based on the extracted function authentication value. This provides an efficient way to authenticate the instruction. This can be performed by cryptographically deshuffling the authenticatable branch instruction (i.e., the inverse of the shuffling described above), after which a block of bits corresponding to the instruction authentication value can be extracted from the deshuffled authenticatable branch instruction.

[0064] Similarly, the branch circuit can be configured to identify an address associated with a function (i.e., a target address of a branch instruction) by extracting a plurality of address bits from an authenticatable branch instruction. The branch circuit then performs a jump based on the plurality of address bits. This provides an efficient way to execute low-level branch instructions.

[0065] Examples of the present disclosure will now be described with reference to the accompanying drawings.

[0066] Figures 1A to 1C Schematically illustrates apparatuses 100a, 100b, 100c according to examples of the present disclosure. These apparatuses may be implemented using dedicated circuit components, such as elements of a processing device such as a central processing unit (CPU). Alternatively, one or more of the components of these apparatuses may be implemented as logical function units executed by general-purpose processing circuits.

[0067] Figure 1A An apparatus 100a configured to implement the above-described method for improving pointer security is shown.

[0068] The apparatus 100a comprises an interface 105 configured to receive a pointer having an address (the address to which the pointer points).

[0069] The device 100a also includes a pointer processing circuit 110 configured to process a pointer. Specifically, the pointer processing circuit extracts an address from the pointer and encrypts the address. The pointer processing circuit also determines a pointer authentication code (PAC) based on the address. Finally, the pointer processing circuit combines the encrypted address with the PAC to generate a signed encrypted pointer. This pointer can then be stored in a storage element such as a register, cache memory, or memory for subsequent use.

[0070] Figure 1B An apparatus 100b configured to implement the above method for improving the safety of branch instructions is shown.

[0071] The apparatus 100b comprises an instruction receiving circuit 115 configured to receive a branch instruction as part of a program flow, the branch instruction identifying a function (eg by means of an address corresponding to a first instruction within the function).

[0072] The device 100b also includes an instruction authentication circuit 120, which is configured to determine an instruction authentication value based on a function. The branch circuit 125 then combines the instruction authentication value with the branch instruction to generate a verifiable branch instruction. The verifiable branch instruction can be stored in a storage element (such as one of the aforementioned registers) or a cache memory or memory for subsequent execution.

[0073] The apparatus 100c additionally includes a branch circuit 125 configured to authenticate an authenticatable branch instruction (eg, when stored in a register) based on the function authentication value. In response to a successful authentication, the branch circuit 125 executes a jump in program flow to the function.

[0074] Figure 1C A device 100c is depicted that is configured to perform the functionality of both devices 100a, 100b. Thus, the device includes shared interfaces 105, 115 configured to receive pointers and branch instructions. This can alternatively be achieved by means of separate interfaces. Device 100c also includes pointer processing circuitry 110, instruction authentication circuitry 120, and branch circuitry 125, as described above. Device 100c therefore provides increased security for pointers and branch instructions. This is particularly collaborative if elements 110, 120, 125 can share components (i.e., if, although depicted separately, the same circuitry is used to determine and authenticate pointers and branch instructions).

[0075] FIG. 2A to FIG. 2CPointer authentication in a comparative example that does not implement aspects of the present disclosure is depicted.

[0076] Figure 2A The generation of a signed pointer is shown. The address bits of the (not yet signed) pointer are cryptographically combined with the PAC key to generate the PAC. The PAC is then combined with the pointer to generate a combined pointer and PAC that is used as the signed pointer.

[0077] Figure 2B Shows the Figure 2A The signature pointer is cryptographically combined with the PAC key to regenerate the PAC. For example, the address bits can be extracted and used with Figure 2A The new PAC is recalculated in the same way. It is then confirmed whether the recalculated PAC matches the PAC of the signature pointer. If it matches, the pointer is considered valid. Otherwise, the pointer is considered invalid.

[0078] Figure 2C One possible configuration of a signature pointer is shown, where the PAC is appended to the address bits. In some examples, other information is also included in the signature pointer, such as tag bits or other metadata.

[0079] This method provides a measure of security: if the address is modified (e.g., to redirect program flow to malicious code), the regenerated PAC will not match the original PAC. However, in some examples, there are not many bits available to store the PAC (e.g., the PAC may be stored in "leftover" bits in a pointer that are not used to store addresses or other information). Therefore, the correct PAC may be guessable, resulting in a maliciously altered pointer that will appear to be authentic.

[0080] FIG. 3A to FIG. 3C Depicted is an improved pointer authentication according to an example. This improved pointer authentication can be performed, for example, by Figure 1A and Figure 1C The method is performed by devices 100a and 100c.

[0081] Figure 3A The generation of a signed encrypted pointer is shown. The address bits are extracted from the (not yet signed) pointer and encrypted based on a cryptographic key (which may be the aforementioned PAC key). The address bits are also used to Figure 2A The PAC is generated in the same way. The encrypted address is then combined with the PAC to produce a signed encrypted pointer.

[0082] Figure 3B Shows the Figure 3A The address portion of the signed encrypted pointer is decrypted to produce the decrypted address bits. The PAC is also extracted. The decrypted address is then cryptographically combined with the key to generate the decrypted address bits. Figure 2BThe PAC is recalculated in the same way. This recalculated PAC is compared with the PAC extracted from the signed encrypted pointer. Figure 2B If the recomputed PAC matches the PAC extracted from the signed encrypted pointer, the decrypted pointer is considered valid. If the recomputed PAC does not match the PAC extracted from the signed encrypted pointer, the decrypted pointer is considered invalid.

[0083] Figure 3C Depicts a possible configuration of a signed cryptographic pointer, where the PAC is appended to the cryptographic address. Figure 3C As in , pointers can also include other information.

[0084] Thus, this example also allows for detection of pointer modifications based on the PAC. However, security is significantly improved by encrypting the address: it is significantly more difficult to modify a pointer in such a way that it (effectively) appears to point to malicious code. The inventors have realized that this is particularly effective in architectures where the "address" of a pointer does not actually have to be the actual address and can be replaced by an encrypted address.

[0085] Figure 4A and Figure 4B Depicted is a branch instruction authentication according to an example. This branch instruction authentication can be performed, for example, by Figure 1B and Figure 1C It is executed by devices 100b and 100c.

[0086] Figure 4A The generation of a verifiable branch instruction is shown. Those skilled in the art will appreciate that this is different from Figure 3A The process shown in is similar to that shown in . The function that the instruction may point to is processed to determine a function authentication value. This function authentication value may be, for example, a hash of the function. This hash is then stored in the instruction. For example, the instruction may immediately follow a branch target instruction.

[0087] Receive a (not yet authenticatable) branch instruction, the branch instruction corresponding to a branch to the aforementioned function. Determine an instruction authentication value based on the function. For example, this instruction authentication value can be the same as the function authentication value. The instruction authentication value is combined with the branch instruction to generate an authenticatable branch instruction. This authenticatable branch instruction can be stored, for example, in a register or other storage device for subsequent execution.

[0088] Figure 4B 2 shows authentication of a certifiable branch instruction. This authentication may be performed, for example, before executing the branch instruction or as part of executing the branch instruction. Those skilled in the art will appreciate that this is different from Figure 3AThe process is similar to that shown in . The above-mentioned authenticatable branch instruction is processed to extract an instruction authentication value. The function authentication value is retrieved from the function, and the function authentication value is compared with the instruction authentication value. If the function authentication value matches the instruction authentication value, the branch instruction is considered authenticated and a jump to the address identified in the instruction can be safely performed. Conversely, if the function authentication value does not match the instruction authentication value, the instruction may have been maliciously modified, so the jump is not performed.

[0089] Therefore, significantly improved branch instruction security is provided. Figure 3A and Figure 3B The described method encrypts at least a portion of a branch instruction to improve the security of the branch instruction.

[0090] Now refer to Figure 5A and Figure 5B A more detailed method for providing further pointer security is described in detail below. Those skilled in the art will appreciate that the same method can be applied to the present technology to improve branch instruction security.

[0091] Figure 5A A method for generating a signed encrypted pointer is shown.

[0092] Initially, the (not yet signed and encrypted) pointer includes the address and optionally some other information. The address is extracted and encrypted based on the PAC key to produce an encrypted address. The address is also hashed to produce a PAC of the appropriate size (e.g., a size that will fit into the "unused" bits of the pointer, in systems where pointers have a given size defined by the architecture). The encrypted address is combined with the PAC, producing the same address as in Figure 3A The pointer generated in is similar to the pointer.

[0093] The encrypted address and PAC are then cryptographically shuffled based on the PAC key to produce an obfuscated address-PAC combination. This improves security because a malicious actor will not be able to determine which bits correspond to the address and which bits correspond to the PAC.

[0094] The obfuscated address-PAC combination (and optionally the other information described above) is then output as a signed, encrypted pointer.

[0095] Figure 5B Describes the Figure 5A Method for decrypting and authenticating the encrypted signature pointer.

[0096] The obfuscated address-PAC combination is extracted from the cryptographic signature pointer and cryptographically deshuffled based on the PAC key. This operation is used to separate the encrypted address from the PAC.

[0097] The encrypted address is decrypted based on the PAC to recover the address. Figure 5A The recovered address is hashed in the same manner as the hash of the deshuffled PAC, and it is confirmed whether this hash is equal to the deshuffled PAC. If so, the pointer is considered authenticated and safe to use. However, if the hash does not match the deshuffled PAC, the pointer is determined to be invalid and an error is reported. This is effective because any modification to the obfuscated address-PAC combination will produce an "address" and "PAC" that do not correspond correctly.

[0098] If the hash check succeeds, the address is used as the address of the decrypted authentication pointer.

[0099] Therefore, the above method provides significantly improved security of pointer authentication. For the sake of brevity, these figures are not repeated for the case of branch instruction security. However, those skilled in the art will appreciate that the same method can be applied to generate (and authenticate) securely authenticatable branch instructions.

[0100] Figure 6 A method according to an example is depicted.

[0101] Initially, a pointer is received (605).

[0102] The address bits are extracted (610) from the pointer.

[0103] The address bits are encrypted (615).

[0104] Determine (620) the PAC.

[0105] The PAC is combined (625) with the encrypted address bits to produce a signed encrypted pointer.

[0106] Figure 7 A method according to an example is depicted.

[0107] A branch instruction is received (705).

[0108] A command authentication value is determined (710).

[0109] The instruction authentication value is combined (715) with the instruction to produce an authenticatable branch instruction.

[0110] The authenticatable branch instruction is authenticated based on the function authentication value (720).

[0111] In response to successful authentication, a jump to the address defined in the instruction is performed (725).

[0112] The concepts described herein may be embodied in computer readable code for manufacturing devices embodying the described concepts. For example, the computer readable code may be used at one or more stages of a semiconductor design and manufacturing process, including an electronic design automation (EDA) stage, to manufacture integrated circuits including devices embodying the concepts. The computer readable code may additionally or alternatively enable the definition, modeling, simulation, verification, and / or testing of devices embodying the concepts described herein.

[0113] For example, computer readable code for making an apparatus embodying the concepts described herein may be embodied in code defining a hardware description language (HDL) representation of the concepts. For example, the code may define a register-transfer-level (RTL) abstraction of one or more logic circuits for defining an apparatus embodying the concepts. The code may define an HDL representation of one or more logic circuits embodying the apparatus in Verilog, SystemVerilog, Chisel, or VHDL (Very High Speed ​​Integrated Circuit Hardware Description Language), as well as intermediate representations such as FIRRTL. The computer readable code may provide definitions of concepts embodying concepts or other behavioral representations of concepts using system-level modeling languages ​​such as SystemC and SystemVerilog that may be interpreted by a computer to enable simulation, functional and / or formal verification, and testing of the concepts.

[0114] Additionally or alternatively, the computer readable code may define a low-level description of an integrated circuit component embodying the concepts described herein, such as one or more netlists or integrated circuit layout definitions, including representations such as GDSII. One or more netlists or other computer readable representations of integrated circuit components may be generated by applying one or more logic synthesis processes to the RTL representation to generate definitions for manufacturing devices embodying the present invention. Alternatively or additionally, one or more logic synthesis processes may generate from the computer readable code a bitstream to be loaded into a field programmable gate array (FPGA) to configure the FPGA to embody the described concepts. The FPGA may be deployed for the purpose of verifying and testing concepts prior to manufacturing the integrated circuit, or the FPGA may be deployed directly in a product.

[0115] The computer readable code may include a mixture of code representations for making a device, such as a mixture including one or more of an RTL representation, a netlist representation, or another computer readable definition used in a semiconductor design and manufacturing process to make a device embodying the invention. Alternatively or additionally, concepts may be defined in a combination of a computer readable definition used in a semiconductor design and manufacturing process to make a device and computer readable code defining instructions to be executed by the defined device once manufactured.

[0116] Such computer readable code may be provided in any known transient computer readable medium (such as wired or wireless transmission of code over a network) or non-transitory computer readable medium such as a semiconductor, a magnetic disk, or an optical disk. An integrated circuit fabricated using the computer readable code may include components such as one or more of the following: a central processing unit, a graphics processing unit, a neural processing unit, a digital signal processor, or other components that embody the concept individually or collectively.

[0117] Figure 8 An example of such a computer-readable medium 805 is shown including code 810 for making one or more of the devices described herein.

[0118] Fig. 9 The simulator that can be used is illustrated. Although the previously described embodiments implement the present invention in terms of the apparatus and method for operating the specific processing hardware supporting the technology involved, an instruction execution environment according to the embodiments described herein can also be provided, which is implemented by using a computer program. Such computer programs are generally referred to as simulators, to a certain extent because such computer programs provide a specific implementation based on software of a hardware architecture. The types of simulator computer programs include emulators, virtual machines, models, and binary converters, which include dynamic binary converters. Typically, the simulator is specifically implemented and can be run on the host hardware (such as a host processor 930 that optionally runs a host operating system 920) that supports the simulator program 910. In some arrangements, there may be multiple simulation layers between the hardware and the provided instruction execution environment and / or a plurality of different instruction execution environments provided on the same host processor. Historically, a powerful processor is required to provide a simulator that is executed at a reasonable speed, but this method may be reasonable in certain circumstances, such as when it is desired to run another processor local code for compatibility or reuse reasons. For example, the simulator is specifically implemented to provide additional functionality that is not supported by the host processor hardware to the instruction execution environment, or to provide an instruction execution environment that is generally associated with different hardware architectures. An overview of simulation is given in: "Some Efficient Architecture Simulation Techniques", Robert Bedichek, Winter 1990 USENIX Conference, pp. 53-63.

[0119] To the extent that embodiments have been previously described with reference to specific hardware constructs or features, in simulated embodiments, equivalent functionality may be provided by suitable software constructs or features. For example, specific circuits may be implemented as computer program logic in simulated embodiments. Similarly, memory hardware such as registers or cache memory may be implemented as software data structures in simulated embodiments. In arrangements where one or more of the hardware elements referenced in previously described embodiments are present on host hardware (e.g., host processor 930), some simulated embodiments may utilize host hardware, where appropriate.

[0120] The simulator program 910 may be stored on a computer-readable storage medium (which may be a non-transitory medium) and provides a program interface (instruction execution environment) to the target code 900 (which may include an application, an operating system, and a hypervisor) that is the same as the interface of the hardware architecture modeled by the simulator program 910. Therefore, the simulator program 910 may be used to execute program instructions of the target code 900 from within the instruction execution environment, so that a host computer 930 that does not actually have the hardware features of the apparatus discussed above can emulate these features.

[0121] Therefore, an apparatus and method for improving the security of pointers and branch instructions is provided.

[0122] As will be seen from the above description, the techniques described herein provide a number of significant benefits. In particular, the risk of undetected malicious modification of pointers and branch instructions is significantly reduced.

[0123] In this application, the words "configured to..." are used to mean that elements of a device have a configuration that enables the performance of a defined operation. In this context, "configuration" means the arrangement or manner of interconnection of hardware or software. For example, the device may have dedicated hardware that provides the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured to" does not mean that the device elements need to be changed in any way in order to provide the defined operation.

[0124] Although exemplary embodiments of the present invention have been described in detail herein with reference to the accompanying drawings, it should be understood that the invention is not limited to those precise embodiments and that various changes and modifications may be effected therein by those skilled in the art without departing from the scope of the invention as defined in the appended claims.

Claims

1. A device, comprising: An instruction receiving circuit, the instruction receiving circuit is used to receive a branch instruction as part of a program flow, the branch instruction identifies a function; An instruction authentication circuit, the instruction authentication circuit is used to: determining an instruction authentication value based at least in part on the function; and combining the instruction authentication value with the branch instruction to produce an authenticatable branch instruction, and A branch circuit, the branch circuit being used for: authenticating the authenticatable branch instruction based on the function authentication value; and A jump in the program flow to the function is performed in response to successful authentication of the authenticatable branch instruction. 2 . The apparatus of claim 1 , wherein the function authentication value is stored within a code corresponding to the function. 3 . The apparatus of claim 2 , wherein the function authentication value is stored in the code corresponding to the function immediately following a branch target indicator.

4. An apparatus as claimed in any preceding claim, wherein the instruction authentication circuit is configured to determine the instruction authentication value based on data indicative of at least a portion of the code corresponding to the function.

5. Apparatus according to any preceding claim, wherein the branch circuitry is configured to authenticate the authenticatable branch instruction by comparing the instruction authentication value with the function authentication value.

6. The apparatus of claim 5, wherein the branch circuit is configured to determine successful authentication of the authenticatable branch instruction in response to the instruction authentication value matching the function authentication value.

7. An apparatus as claimed in claim 5 or claim 6, wherein the branch circuit identifies an error in response to unsuccessful authentication of the authenticatable branch instruction.

8. An apparatus as claimed in any preceding claim, wherein the instruction authentication circuit is configured to encrypt the branch instruction based on a cryptographic key.

9. Apparatus according to any preceding claim, wherein the combining performed by the instruction authentication circuit comprises cryptographically shuffling the instruction authentication value and the branch instruction.

10. Apparatus according to claim 9 when dependent on claim 8, wherein the instruction authentication circuit is configured to perform the cryptographic shuffling based on the key.

11. The apparatus of any preceding claim, wherein the branch circuit is configured to: Extracting the instruction authentication value from the authenticatable instruction; and The authentication of the authenticatable branch instruction is performed based on the extracted function authentication value.

12. The apparatus of claim 11 when dependent on claim 9 or claim 10, wherein the branch circuit is configured to extract the instruction authentication value by: performing cryptographic deshuffling of the authenticatable branch instructions; and A block of bits corresponding to the instruction authentication value is extracted from the deshuffled authenticatable branch instructions.

13. The apparatus of claim 11 or claim 12, wherein the branch circuit is configured to: identifying an address associated with the function by extracting a plurality of address bits from the certifiable branch instruction; and The jumping is performed based on the plurality of address bits.

14. The apparatus according to any preceding claim, further comprising: An interface circuit configured to receive a pointer including a plurality of address bits; and A pointer processing circuit, the pointer processing circuit is used for: extracting the plurality of address bits from the pointer; encrypting the plurality of address bits to produce a plurality of encrypted address bits; determining a pointer authentication value based at least in part on the plurality of address bits; as well as The pointer authentication value is combined with the plurality of encrypted address bits to produce a signed encrypted pointer.

15. A method comprising: receiving a branch instruction as part of a program flow, the branch instruction identifying a function; determining an instruction authentication value based at least in part on the function; combining the instruction authentication value with the branch instruction to generate an authenticatable branch instruction; authenticating the authenticatable branch instruction based on the function authentication value; as well as A jump in the program flow to the function is performed in response to successful authentication of the authenticatable branch instruction. 16 . A non-transitory computer readable medium for storing a computer readable code for manufacturing the apparatus according to claim 1 .

17. A computer program for controlling a host data processing device to provide an instruction execution environment, the computer program comprising: Instruction receiving logic, the instruction receiving logic is used to receive a branch instruction as part of a program flow, the branch instruction identifies a function; Instruction authentication logic, the instruction authentication logic is used to: determining an instruction authentication value based at least in part on the function; and combining the instruction authentication value with the branch instruction to produce an authenticatable branch instruction, and Branching logic, the branching logic is used to: authenticating the authenticatable branch instruction based on the function authentication value; as well as A jump in the program flow to the function is performed in response to successful authentication of the authenticatable branch instruction.

Images