Array substrate, display panel and display device

Abstract

The invention provides an array substrate, a display panel and a display device, and relates to the technical field of display, the array substrate comprises a display area and a peripheral area on at least one side of the display area, the array substrate of the display area comprises a substrate, and a plurality of data lines, a plurality of gate signal lines and a plurality of common signal lines which are arranged on one side of the substrate, the data lines and the grid signal lines are crossed to form a plurality of sub-pixels; wherein the common signal line comprises a first common signal line and a second common signal line, and the first common signal line and the second common signal line are respectively connected with different signal input terminals; moreover, the plurality of sub-pixels comprise first sub-pixels and second sub-pixels, the first common signal lines are electrically connected with the first sub-pixels, and the second common signal lines are electrically connected with the second sub-pixels.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of display technology, and in particular, to an array substrate, a display panel, and a display device. Background Art

[0002] With the continuous development of display technology, thin film transistor liquid crystal display (TFT-LCD) liquid crystal display panels have occupied a dominant position in the field of flat panel displays due to their low power consumption and no radiation.

[0003] The liquid crystal display panel usually includes an array substrate and a color filter substrate which are placed together and sandwich the liquid crystal. The array substrate includes a base substrate and gate signal lines, data lines, common signal lines, common electrodes, and TFTs (Thin Film Transistors) and pixel electrodes arranged in a matrix. However, since different pixel units cannot simultaneously reach the optimal pixel common voltage corresponding to each pixel unit, the display device may have gamma drift, afterimages, shaking head lines and other undesirable phenomena, which reduces the display performance of the array substrate. Summary of the invention

[0004] The embodiments of the present application provide an array substrate, a display panel and a display device, aiming to solve the problem of how to improve gamma drift, afterimage, head shaking wrinkles and other undesirable phenomena.

[0005] According to a first aspect of an embodiment of the present application, an array substrate is provided, comprising a display area and a peripheral area on at least one side of the display area, wherein the array substrate of the display area comprises:

[0006] A base substrate, and a plurality of data lines, a plurality of gate signal lines and a plurality of common signal lines arranged on one side of the base substrate, wherein the data lines and the gate signal lines cross to form a plurality of sub-pixels;

[0007] The common signal line includes a first common signal line and a second common signal line, the first common signal line and the second common signal line are connected to different signal input terminals respectively; and

[0008] The plurality of sub-pixels include a first sub-pixel and a second sub-pixel, the first common signal line is electrically connected to the first sub-pixel, and the second common signal line is electrically connected to the second sub-pixel.

[0009] In an optional implementation, the array substrate is a single-gate line array substrate, and the plurality of sub-pixels further include a third sub-pixel.

[0010] In an optional embodiment, the common signal line extends along a first direction, and the common signal line also includes a third common signal line, and the third common signal line is electrically connected to the third sub-pixel; the first common signal line, the second common signal line and the third common signal line are respectively connected to different signal input terminals.

[0011] In an optional implementation, the array substrate includes:

[0012] The first common signal line and the first data line connected to the first sub-pixel are respectively arranged on two opposite sides of the first sub-pixel;

[0013] The second common signal line and the second data line connected to the second sub-pixel are respectively arranged on two opposite sides of the second sub-pixel;

[0014] The third common signal line and the third data line connected to the third sub-pixel are respectively arranged on two opposite sides of the third sub-pixel.

[0015] In an optional implementation, the common signal line and the data line are arranged in the same layer.

[0016] In an optional implementation, the common signal line extends along the second direction, and the first common signal line and the second common signal line are respectively arranged on two opposite sides of the first sub-pixel and / or the second sub-pixel.

[0017] In an optional implementation, the third sub-pixel is electrically connected to the first common signal line or the second common signal line.

[0018] In an optional implementation, adjacent first sub-pixels are connected via a first jumper structure, and adjacent second sub-pixels are connected via a second jumper structure, and the first jumper structure and the second jumper structure are disposed on the same layer as the data line.

[0019] In an optional implementation, the common signal line and the gate signal line are arranged in the same layer.

[0020] In an optional implementation, the array substrate is a dual-gate line array substrate, and the first sub-pixel and the second sub-pixel are connected to the same data line and are located on the same side of the same data line.

[0021] In an optional implementation, the common signal line extends along a first direction, and the common signal line and the data line are arranged in the same layer.

[0022] In an optional implementation, the first common signal line is located at a side of the first sub-pixel away from the same data line, and the second common signal line is located at a side of the second sub-pixel close to the same data line.

[0023] In an optional embodiment, the array substrate is a three-gate line array substrate, and the multiple sub-pixels also include a third sub-pixel; wherein the data line extends along a first direction, the gate signal line extends along a second direction, each of the data lines is arranged between adjacent sub-pixels of the same type, and each of the gate signal lines is arranged between adjacent sub-pixels of different types.

[0024] In an optional embodiment, the common signal line is arranged along the second direction in the display area, and the common signal line also includes a third common signal line, and the third common signal line is electrically connected to the third sub-pixel; the first common signal line, the second common signal line and the third common signal line are respectively connected to different signal input terminals.

[0025] In an optional implementation, the array substrate includes:

[0026] The first common signal line and the first gate signal line connected to the first sub-pixel are respectively arranged on two opposite sides of the first sub-pixel;

[0027] The second common signal line and the second gate signal line connected to the second sub-pixel are respectively arranged on two opposite sides of the second sub-pixel;

[0028] The third common signal line and the third gate signal line connected to the third sub-pixel are respectively arranged on two opposite sides of the third sub-pixel.

[0029] In an optional implementation, the common signal line and the gate signal line are arranged in the same layer.

[0030] In an optional embodiment, each sub-pixel includes a first electrode and a second electrode, the first electrode is arranged on a side of the gate signal line close to the base substrate, and the second electrode is arranged on a side of the data line away from the base substrate, wherein one of the first electrode and the second electrode is a pixel electrode, and the other is a common electrode.

[0031] In an optional implementation, the array substrate further comprises a thin film transistor disposed in the same layer as the data line, the common electrode is electrically connected to the common signal line, and the pixel electrode is electrically connected to the data line via the thin film transistor.

[0032] In an optional embodiment, the array substrate in the peripheral area further includes: a lead arranged on a side of the base substrate close to the common signal line, the common signal line extends from the display area to the peripheral area and is electrically connected to the lead through a transfer structure.

[0033] In an optional implementation, the data line extends along a first direction, and the gate signal line extends along a second direction; one of the lead line and the common signal line is arranged along the first direction, and the other is arranged along the second direction.

[0034] A second aspect of an embodiment of the present application provides a display panel, comprising a liquid crystal layer, a cell substrate, and an array substrate as described in any one of the first aspects, wherein the liquid crystal layer is located between the cell substrate and the array substrate.

[0035] A third aspect of the embodiments of the present application provides a display device, comprising a backlight module and a display panel as described in the second aspect, wherein the backlight module is located on the backlight side of the display panel.

[0036] Beneficial effects:

[0037] The embodiments of the present application provide an array substrate, a display panel and a display device, comprising a display area and a peripheral area on at least one side of the display area, wherein the array substrate of the display area comprises: a base substrate, and a plurality of data lines, a plurality of gate signal lines and a plurality of common signal lines arranged on one side of the base substrate, wherein the data lines and the gate signal lines cross to form a plurality of sub-pixels; wherein the common signal lines comprise a first common signal line and a second common signal line, wherein the first common signal line and the second common signal line are respectively connected to different signal input terminals; and wherein the plurality of sub-pixels comprise a first sub-pixel and a second sub-pixel, wherein the first common signal line is electrically connected to the first sub-pixel, and the second common signal line is electrically connected to the second sub-pixel.

[0038] The embodiment of the present application sets a common signal line connecting different sub-pixels, so that different sub-pixels of the array substrate can be adjusted to the optimal pixel common voltage corresponding to each sub-pixel, thereby improving the gamma drift, afterimage, shaking head wrinkles and other undesirable phenomena caused by the inability of a single common signal line to simultaneously meet the optimal pixel common voltage differences between multiple different sub-pixels.

[0039] The above description is only an overview of the technical solution of the present disclosure. In order to more clearly understand the technical means of the present disclosure, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present disclosure more obvious and easy to understand, the specific implementation methods of the present disclosure are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0041] Figure 1 This is a schematic diagram of a single-grid array substrate structure proposed in one embodiment of the present application;

[0042] Figure 2 This is a schematic diagram of the structure of a first sub-pixel region of a single-gate line array substrate proposed in one embodiment of the present application;

[0043] Figure 3 This is a schematic diagram of a lead structure of a single-grid array substrate proposed in an embodiment of the present application;

[0044] Figure 4 This is a schematic diagram of another single-grid array substrate structure proposed in one embodiment of the present application;

[0045] Figure 5a This is a schematic diagram of a connection between sub-pixels and common signal lines in another single-gate line array substrate proposed in an embodiment of the present application;

[0046] Figure 5b This is another connection diagram between sub-pixels and common signal lines in another single-gate line array substrate proposed in one embodiment of the present application;

[0047] Figure 6 This is a schematic diagram of a dual-gate linear array substrate structure proposed in one embodiment of the present application;

[0048] Figure 7 This is a schematic diagram of a lead structure of a dual-gate line array substrate proposed in an embodiment of the present application;

[0049] Figure 8 This is a schematic diagram of the structure of multiple sub-pixels in a dual-gate linear array substrate proposed in one embodiment of the present application;

[0050] Fig. 9 This is a schematic diagram of a three-gate linear array substrate structure proposed in an embodiment of the present application;

[0051] Fig.10 It is a schematic diagram of the lead structure of a three-gate line array substrate proposed in an embodiment of the present application.

[0052] Explanation of the reference numerals: 101, data line; 1011, first data line; 1012, second data line; 1013, third data line; 102, gate signal line; 1021, first gate signal line; 1022, second gate signal line; 1023, third gate signal line; 103, common signal line; 1031, first common signal line; 1032, second common signal line; 1033, third common signal line; 104, first sub-pixel; 1041, first electrode; 1042, second electrode; 105, second sub-pixel; 106, third sub-pixel; 107, support column; 108, support column partition structure; 1091, first jumper structure; 1092, second jumper structure; 110, active layer; 111, source and drain; 201, lead; 202, transfer structure. DETAILED DESCRIPTION

[0053] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0054] In the embodiments of the present application, unless otherwise specified, the term "same-layer arrangement" used means that two layers, parts, components, elements or parts can be formed by the same composition process, and the two layers, parts, components, elements or parts are generally formed of the same material.

[0055] With the continuous development of display technology, thin film transistor liquid crystal display (TFT-LCD) liquid crystal display panels have occupied a dominant position in the field of flat panel displays due to their low power consumption and no radiation.

[0056] The liquid crystal display panel generally includes an array substrate and a color filter substrate which are assembled together and sandwich the liquid crystal. The array substrate includes a base substrate and gate signal lines, data lines, common signal lines, common electrodes, and TFTs (Thin Film Transistors) and pixel electrodes arranged in a matrix on the base substrate.

[0057] In the related art, different sub-pixels are electrically connected to the same common signal line, and the pixel common voltage of each sub-pixel remains consistent. However, due to factors such as the cross-connection structure between pixels and the position of support columns, the optimal pixel common voltages between different sub-pixels are different. Therefore, the pixel common voltage provided by a single common signal line cannot simultaneously reach the optimal pixel common voltage corresponding to each sub-pixel, causing the display device to experience gamma drift, afterimages, shaking head lines and other undesirable phenomena, thereby reducing the display performance of the array substrate.

[0058] In view of this, an embodiment of the present application provides an array substrate, wherein the array substrate comprises a display area and a peripheral area on at least one side of the display area. Figure 1 FIG. 1 shows a schematic diagram of a single-grid array substrate structure proposed in an embodiment of the present application. Figure 1 As shown, the array substrate of the display area includes: a base substrate; data lines 101, multiple data lines 101 are arranged on one side of the base substrate, and the data lines 101 extend along a first direction; gate signal lines 102, multiple gate signal lines 102 are arranged on one side of the base substrate, and the gate signal lines 102 extend along a second direction, and multiple sub-pixels are formed by crossing the data lines 101 and the gate signal lines 102; common signal lines 103, multiple common signal lines 103 are arranged on one side of the base substrate.

[0059] In an embodiment of the present application, the multiple sub-pixels include at least a first sub-pixel 104 and a second sub-pixel 105. In an optional embodiment, the first sub-pixel 104 can be a first color sub-pixel, and the second sub-pixel 105 can be a second color sub-pixel. The first color sub-pixel and the second color sub-pixel are any two of a red sub-pixel, a green sub-pixel, and a blue sub-pixel. In another optional embodiment, one of the first sub-pixel 104 and the second sub-pixel 105 is a long-connection sub-pixel, and the other is a short-connection sub-pixel.

[0060] In an embodiment of the present application, the common signal line 103 includes a first common signal line 1031 and a second common signal line 1032, and the first common signal line 1031 and the second common signal line 1032 are respectively connected to different signal input terminals; and the first common signal line 1031 is electrically connected to the first sub-pixel 104, and the second common signal line 1032 is electrically connected to the second sub-pixel 105.

[0061] Optionally, the data line 101 and the gate signal line 102 may be made of metal or alloy materials, such as copper, molybdenum, aluminum, and titanium, to ensure that the data line 101 and the gate signal line 102 have good electrical conductivity. It should be noted that the substrate in the embodiment of the present application may be a single-layer structure or a multi-layer structure; the substrate may be a rigid substrate, such as a substrate made of glass or other materials; or a flexible substrate, such as a substrate made of polyimide (PI) or other materials. The specific type and material of the substrate may be determined according to actual conditions, and the embodiment of the present application specifically defines it.

[0062] In an optional embodiment, the array substrate is a single-gate array substrate, the data line 101 extends along a first direction, the gate signal line 102 extends along a second direction, and the common signal line 103 extends in the same direction as the data line 101, both extending along the first direction. Figure 1 As shown in the figure, a single-grid array substrate structure is taken as an example. Figure 1 As shown, in a single-gate line array substrate, a plurality of sub-pixels of different types located in a display area are arranged horizontally, each column of sub-pixels corresponds to a data line 101, and a gate signal line 102 is arranged between two adjacent rows of sub-pixels.

[0063] In the single-gate linear array substrate, the plurality of sub-pixels further include a third sub-pixel 106, the common signal line 103 further includes a third common signal line 1033, and the third common signal line 1033 is electrically connected to the third sub-pixel 106. Optionally, the first sub-pixel 104 may be a first color sub-pixel, the second sub-pixel 105 may be a second color sub-pixel, the third sub-pixel 106 may be a third color sub-pixel, and the first color sub-pixel, the second color sub-pixel and the third color sub-pixel are a red sub-pixel, a green sub-pixel and a blue sub-pixel.

[0064] The data line 101 includes a first data line 1011 connected to the first sub-pixel 104, a second data line 1012 connected to the second sub-pixel 105, and a third data line 1013 connected to the third sub-pixel 106. The first data line 1011, the second data line 1012, and the third data line 1013 are electrically connected to the corresponding sub-pixels through thin film transistors. In the embodiment of the present application, the first common signal line 1031 and the first data line 1011 are respectively arranged on two opposite sides of the first sub-pixel 104; the second common signal line 1032 and the second data line 1012 are respectively arranged on two opposite sides of the second sub-pixel 105; and the third common signal line 1033 and the third data line 1013 are respectively arranged on two opposite sides of the third sub-pixel 106.

[0065] In the single-gate line array substrate, a support column (PS column) 107 and a support column partition structure 108 corresponding to the support column 107 are further provided. The orthographic projection of the support column 107 on the substrate substrate is located inside the orthographic projection of the gate signal line 102 on the substrate substrate, and the orthographic projection of the support column partition structure 108 on the substrate substrate is located inside the orthographic projection of the sub-pixel on the substrate substrate ( Figure 1 It is exemplarily shown that the orthographic projection of the support column partition structure 108 on the substrate is located inside the orthographic projection of the third sub-pixel 106 on the substrate, and the support column partition structure 108 is used to isolate the support column from the area where the sub-pixel is located.

[0066] Optionally, the support column partition structure 108 includes a first partition layer and a second partition layer stacked, wherein the first partition layer is disposed on a side close to the base substrate, and the second partition layer is disposed on a side of the first partition layer away from the base substrate. The first partition layer is disposed on the same layer as the gate signal line 102, and the second partition layer is disposed on the same layer as the data line 101.

[0067] In the embodiment of the present application, for a single-gate array substrate, due to the position of the support column 107 and the support column partition structure 108 corresponding to the support column 107, there are certain differences between the multiple sub-pixels in the array substrate located in the display area. Figure 1 For example, the area where the third sub-pixel is located is reduced due to the occupation factor of the support column 107 and the support column partition structure 108, so that the parasitic capacitance C of the third sub-pixel 106 gs The third sub-pixel 106 is too small, resulting in a greater coupling effect when the gate signal is turned off (jump voltage ΔV pWhen the same voltage is charged, the voltage maintained on the third sub-pixel 106 is lower, so the optimal pixel common voltage of the third sub-pixel 106 is lower than that of the first sub-pixel 104 and the second sub-pixel 105. Therefore, the difference in the space factor between the multiple sub-pixels makes the storage capacitors C between different sub-pixels st And the parasitic capacitance C gs There are differences between them, which leads to the jump voltage ΔV between different sub-pixels p There are differences. The differences in storage capacitance, parasitic capacitance and jump voltage between the above sub-pixels are manifested as different optimal pixel common voltages for different sub-pixels.

[0068] The single-gate line array substrate provided in the embodiment of the present application is provided with a first sub-pixel 104, a second sub-pixel 105 and a third sub-pixel 106. By providing a first common signal line 1031, a second common signal line 1032 and a third common signal line 1033 which are separated from each other and electrically connected to each sub-pixel, each sub-pixel is individually controlled. Specifically, the first common signal line 1031 provides the first sub-pixel 104 with an optimal pixel common voltage corresponding to the first sub-pixel 104, the second common signal line 1032 provides the first sub-pixel 105 with an optimal pixel common voltage corresponding to the second sub-pixel 105, and the third common signal line 1033 provides the third sub-pixel 106 with an optimal pixel common voltage corresponding to the third sub-pixel 106, so that the first sub-pixel 104, the second sub-pixel 105 and the third sub-pixel 106 can all reach their corresponding optimal pixel common voltages, thereby improving the undesirable phenomena such as Gamma drift, afterimage, and shaking head lines of the array substrate, and optimizing the monochrome Gamma and viewing angle.

[0069] Optionally, the common signal lines 103 (including the first common signal line 1031 , the second common signal line 1032 and the third common signal line 1033 ) and the data lines 101 (including the first data line 1011 , the second data line 1012 and the third data line 1013 ) are arranged in the same layer.

[0070] In the embodiment of the present application, the first sub-pixel 104, the second sub-pixel 105 and the third sub-pixel 106 in the array substrate have the same structure. Taking the first sub-pixel 104 as an example, the composition structure of the sub-pixel is further introduced. Figure 2 FIG. 4 shows a schematic diagram of the structure of a first sub-pixel region of a single-gate array substrate according to an embodiment of the present application. Figure 2As shown, the first sub-pixel 104 includes: a first electrode 1041, the first electrode 1041 is arranged on the side of the gate signal line 102 close to the base substrate; a second electrode 1042, the second electrode 1042 is arranged on the side of the data line 101 away from the base substrate. Optionally, the materials of the first electrode and the second electrode can be transparent materials such as ITO (indium tin oxide), IZO (indium zinc oxide), ZnO (zinc oxide), etc. Among them, one of the first electrode 1041 and the second electrode 1042 is a pixel electrode, and the other is a common electrode, for example, the first electrode 1041 is a pixel electrode, and the second electrode 1042 is a common electrode, or the first electrode 1041 is a common electrode, and the second electrode 1042 is a pixel electrode.

[0071] In the embodiment of the present application, the sub-pixel is electrically connected to the data line 101 through a thin film transistor disposed in the same layer as the data line 101, and the sub-pixel is electrically connected to the common signal line 103. Figure 2 Taking the first sub-pixel shown as an example, the thin film transistor includes a source and a drain electrode 111 (including a source electrode and a drain electrode, the source electrode and the drain electrode are arranged in the same layer) and an active layer 110, and the active layer 110 is arranged on the side of the source and drain electrode 111 close to the base substrate. The pixel electrode in the first sub-pixel 104 is arranged on the side of the thin film transistor away from the base substrate, and the pixel electrode is electrically connected to the drain electrode of the thin film transistor; the common electrode is electrically connected to the first common signal line 1031 through a transfer structure.

[0072] An insulating layer may be provided between the active layer 110 and the gate signal line 102 to insulate the gate signal line 102 from the active layer 110. The insulating layer may be an inorganic material, such as silicon oxide, silicon nitride, etc. The material of the active layer 110 may be amorphous silicon (a-Si), and the materials of the source electrode and the drain electrode may be a metal material or an alloy material, such as a metal single layer or multilayer structure formed by molybdenum, aluminum, and titanium, etc. Preferably, the material of the source electrode and the drain electrode is a stacked structure of three layers of titanium, aluminum, and titanium (Al / Ti / Al), etc.

[0073] In an embodiment of the present application, the first common signal line 1031, the second common signal line 1032 and the third common signal line 1033 extend from the display area to the peripheral area along the first direction, and the peripheral area is provided with signal input terminals corresponding to the common signal lines, and the first common signal line 1031, the second common signal line 1032 and the third common signal line 1033 are respectively connected to different signal input terminals in the peripheral area. Figure 3FIG. 1 shows a schematic diagram of a lead structure of a single-grid array substrate proposed in an embodiment of the present application. Figure 3 As shown, the signal input terminal includes a lead 201 and a transfer structure 202, wherein the lead 201 is arranged on the side of the substrate close to the common signal line 103, wherein the lead 201 extends along the second direction in the peripheral area and forms an electrical connection with the corresponding common signal line 103 through the transfer structure 202.

[0074] In an optional embodiment, the array substrate is a single gate array substrate, the data line 101 extends along a first direction, the gate signal line 102 extends along a second direction, and the common signal line 103 extends in the same direction as the gate signal line 102, both extending along the second direction. Figure 4 FIG. 4 shows another schematic diagram of a single-grid array substrate structure proposed in an embodiment of the present application. Figure 4 As shown, in a single-gate linear array substrate, the plurality of sub-pixels include a first sub-pixel 104, a second sub-pixel 105 and a third sub-pixel 106. Optionally, the first sub-pixel 104 may be a first color sub-pixel, the second sub-pixel 105 may be a second color sub-pixel, the third sub-pixel 106 may be a third color sub-pixel, and the first color sub-pixel, the second color sub-pixel and the third color sub-pixel may be a red sub-pixel, a green sub-pixel and a blue sub-pixel.

[0075] The common signal line 103 includes a first common signal line 1031 and a second common signal line 1032, and the first common signal line 1031 and the second common signal line 1032 are respectively arranged on two opposite sides of the first sub-pixel 104 and / or the second sub-pixel 105. Specifically, for the first sub-pixel 104, the second sub-pixel 105 and the third sub-pixel 106 arranged in the same row in the array substrate, the first common signal line 1031 is arranged on the same side of the first sub-pixel 104, the second sub-pixel 105 and the third sub-pixel 106, and the first common signal line 1031 extends along the second direction; the second common signal line 1032 is arranged on a side of the first sub-pixel 104, the second sub-pixel 105 and the third sub-pixel 106 opposite to the first common signal line 1031, and the second common signal line 1032 also extends along the second direction.

[0076] In the case where the array substrate is a single-gate array substrate, and the common signal line 103 and the gate signal line 102 extend in the same direction, that is, both extend along the second direction, Figure 5a A schematic diagram showing a connection between sub-pixels and common signal lines in another single-gate line array substrate proposed in an embodiment of the present application is shown. Figure 5b FIG. 4 shows another schematic diagram of connecting sub-pixels and common signal lines in another single-gate line array substrate proposed in an embodiment of the present application. Figure 5a as well as Figure 5b As shown, the first common signal line 1031 is electrically connected to the first sub-pixel 104, the second common signal line 1032 is electrically connected to the second sub-pixel 105, and the third sub-pixel 106 is electrically connected to the first common signal line 1031 or the second common signal line 1032. Specifically, Figure 5a As shown, the third sub-pixel 106 can be electrically connected to the first common signal line 1031; Figure 5b As shown, the third sub-pixel 106 may be electrically connected to the second common signal line 1031 .

[0077] In the embodiment of the present application, the array substrate is provided with a first common signal line 1031 and a second common signal line 1032 extending along the second direction, so as to realize the separate control of the pixel common voltages of the first sub-pixel 104 and the second sub-pixel 105, so that the common signal line of the array substrate can simultaneously meet the optimal pixel common voltages of the first sub-pixel 104 and the second sub-pixel 105; at the same time, in the actual use scenario, according to the different requirements of the brightness relationship of different types of sub-pixels, no common signal line is provided to connect the third sub-pixel 106 separately, but the third sub-pixel 106 can be connected to the first common signal line 1031 or the second common signal line 1032 according to the actual situation, so as to obtain the same pixel common voltage as the first sub-pixel or the same pixel common voltage as the second sub-pixel, so as to effectively reduce the wiring difficulty and the preparation cost, meet the needs of different scenarios, and at the same time, set fewer common signal lines, so as to ensure that the first sub-pixel and the second sub-pixel reach the optimal pixel common voltage, and at the same time, improve the aperture ratio and light transmittance of the array substrate, and in addition, make the gate signal line layer metal design data line load smaller, which is more conducive to charging. It should be noted that the specific electrical connection between the third sub-pixel and the common signal line can be determined according to actual conditions. It can be electrically connected to the first common signal line, or it can also be electrically connected to the second common signal line, and this application does not limit this.

[0078] Optionally, when the array substrate is a single-gate array substrate, and the common signal line 103 and the gate signal line 102 extend in the same direction, that is, both extend along the second direction, Figure 4As shown, the array substrate is provided with a first crossover structure 1091 and a second crossover structure 1092, adjacent first sub-pixels 104 are connected via the first crossover structure 1091, and adjacent second sub-pixels 105 are connected via the second crossover structure 1092, and the first crossover structure 1091 and the second crossover structure 1092 are provided at the same layer as the data line. By providing the first crossover structure 1091 and the second crossover structure 1092 for the sub-pixels (the first sub-pixels 104 and the second sub-pixels 105) provided with corresponding common signal lines, the uniformity of the pixel common voltage provided by the first common signal line 1031 between the first sub-pixels 104 on the array substrate and the uniformity of the pixel common voltage provided by the second common signal line 1032 between the second sub-pixels 105 on the array substrate are ensured.

[0079] Optionally, the common signal line 103 (including the first common signal line 1031 and the second common signal line 1032 ) is disposed in the same layer as the gate signal line 102 .

[0080] In an optional embodiment, the array substrate is a single-gate array substrate, and the common signal line 103 and the gate signal line 102 have the same extension direction, both extending along the second direction, the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel. Adjacent red sub-pixels are connected by a first jumper structure 1091, and adjacent green sub-pixels are connected by a second jumper structure 1092. The first jumper structure 1091 and the second jumper structure 1092 are arranged on the same layer as the data line. The first common signal line 1031 and the second common signal line 1032 are respectively arranged on opposite sides of the red sub-pixel, the green sub-pixel and / or the blue sub-pixel. The first common signal line 1031 is electrically connected to the red sub-pixel, the second common signal line is electrically connected to the green sub-pixel, and the blue sub-pixel is electrically connected to the first common signal line 1031 or the second common signal line 1032.

[0081] In an optional embodiment, the array substrate is a single-gate array substrate, and the common signal line 103 and the gate signal line 102 have the same extension direction, both extending along the second direction, the first sub-pixel is a red sub-pixel, the second sub-pixel is a blue sub-pixel, and the third sub-pixel is a green sub-pixel. Adjacent red sub-pixels are connected by a first jumper structure 1091, and adjacent blue sub-pixels are connected by a second jumper structure 1092. The first jumper structure 1091 and the second jumper structure 1092 are arranged on the same layer as the data line. The first common signal line 1031 and the second common signal line 1032 are respectively arranged on opposite sides of the red sub-pixel, the green sub-pixel and / or the blue sub-pixel. The first common signal line 1031 is electrically connected to the red sub-pixel, the second common signal line is electrically connected to the blue sub-pixel, and the green sub-pixel is electrically connected to the first common signal line 1031 or the second common signal line 1032.

[0082] In an optional embodiment, the array substrate is a single-gate array substrate, and the common signal line 103 and the gate signal line 102 have the same extension direction, both extending along the second direction, the first sub-pixel is a green sub-pixel, the second sub-pixel is a blue sub-pixel, and the third sub-pixel is a red sub-pixel. Adjacent green sub-pixels are connected by a first jumper structure 1091, and adjacent blue sub-pixels are connected by a second jumper structure 1092. The first jumper structure 1091 and the second jumper structure 1092 are arranged on the same layer as the data line. The first common signal line 1031 and the second common signal line 1032 are respectively arranged on opposite sides of the red sub-pixel, the green sub-pixel and / or the blue sub-pixel. The first common signal line 1031 is electrically connected to the green sub-pixel, the second common signal line is electrically connected to the blue sub-pixel, and the red sub-pixel is electrically connected to the first common signal line 1031 or the second common signal line 1032.

[0083] In an optional implementation, the array substrate is a dual gate array substrate. Figure 6 A schematic diagram of a dual-gate linear array substrate structure proposed in an embodiment of the present application is shown. Figure 8 FIG. 4 shows a schematic diagram of a structure of multiple sub-pixels in a dual-gate linear array substrate according to an embodiment of the present application. Figure 6 as well as Figure 8As shown, the array substrate includes: a data line 101, the data line 101 extends along a first direction; a gate signal line 102, the gate signal line 102 extends along a second direction, and the data line 101 and the gate signal line 102 cross to form a first sub-pixel 104 and a second sub-pixel 105. In a dual-gate array substrate, a plurality of sub-pixels of different types located in a display area are arranged horizontally, and the first sub-pixel 104 and the second sub-pixel 105 are connected to the same data line (every two columns of sub-pixels share the same data line 101), and are located on the same side of the same data line. Among them, one of the first sub-pixel 104 and the second sub-pixel is arranged close to the same data line 101, and the other is arranged away from the same data line 101.

[0084] In the embodiment of the present application, one of the first sub-pixel 104 and the second sub-pixel 105 is a long-connection sub-pixel, and the other is a short-connection sub-pixel. The long-connection sub-pixel means that when the long-connection sub-pixel is electrically connected to the same data line on the same side, the connection path between the long-connection sub-pixel and the data line is longer than the connection path between the short-connection sub-pixel and the data line. The short-connection sub-pixel is arranged closer to the same data line 101 than the long-connection sub-pixel, and the long-connection sub-pixel is arranged farther from the same data line 101 than the short-connection sub-pixel. For example, the first sub-pixel 104 is the short-connection sub-pixel, and the second sub-pixel 105 is the long-connection sub-pixel. The first sub-pixel 104 is arranged closer to the same data line 101 than the second sub-pixel 105, and the second sub-pixel 105 is arranged farther from the same data line 101 than the first sub-pixel 104.

[0085] Among them, for a dual-gate linear array substrate, such as Figure 6 As shown, the array substrate further includes a common signal line 103, the common signal line 103 extends along the first direction and is arranged in the same layer as the data line 101. The common signal line 103 includes a first common signal line 1031 and a second common signal line 1032, the first common signal line 1031 and the second common signal line 1032 are arranged between the adjacent first sub-pixel 104 and the second sub-pixel 105, the first common signal line 1031 is arranged on a side close to the first sub-pixel 104, and the second common signal line 1032 is arranged on a side close to the second sub-pixel 105. Specifically, the first common signal line 1031 is located on a side of the first sub-pixel 104 away from the same data line 101, and the second common signal line 1032 is located on a side of the second sub-pixel 105 close to the same data line 101.

[0086] In the embodiment of the present application, the sub-pixel is electrically connected to the data line 101 through a thin film transistor disposed in the same layer as the data line 101, and the sub-pixel is electrically connected to the common signal line 103. Figure 6 Taking the first sub-pixel and the second sub-pixel of the dual-gate linear array substrate shown as an example, the first sub-pixel 104 and the second sub-pixel 105 are electrically connected through the drain electrodes of the thin film transistors located on the opposite sides of the first sub-pixel 104 and / or the second sub-pixel 105, respectively, wherein the pixel electrode of the first sub-pixel 104 is electrically connected to the data line 101 through the shorter electrical connection path of the thin film transistor, and the pixel electrode of the second sub-pixel 105 is electrically connected to the same data line 101 through the longer electrical connection path of the thin film transistor; the common electrode of the first sub-pixel 104 is electrically connected to the first common signal line 1031 through a switching structure, and the common electrode of the second sub-pixel 105 is electrically connected to the common signal line 1032 through a switching structure.

[0087] In the embodiment of the present application, for the dual-gate array substrate, since one of the first sub-pixel 104 and the second sub-pixel 105 is a long-connection sub-pixel and the other is a short-connection sub-pixel, a certain parasitic capacitance C is caused between the first sub-pixel 104 and the second sub-pixel 105 due to the difference in the long and short connections. gs The difference makes the optimal pixel common voltage of the first sub-pixel 104 and the second sub-pixel 105 different. Figure 6 For example, the electrical connection path between the first sub-pixel 104 and the data line 101 is shorter, and the electrical connection path between the second sub-pixel 105 and the data line 101 is longer, so that the parasitic capacitance between the first sub-pixel 104 and the data line 101 is smaller, and the parasitic capacitance between the second sub-pixel 105 and the data line 101 is larger. When the gate signal is turned off, the coupling effect on the second sub-pixel 105 is large (jump voltage ΔV p The coupling effect on the first sub-pixel is small (jump voltage ΔV p Therefore, when the second sub-pixel 105 and the first sub-pixel 104 are charged with the same voltage, they maintain different voltages, which leads to different optimal pixel common voltages for the first sub-pixel 104 and the second sub-pixel 105.

[0088] The dual-gate line array substrate provided in the embodiment of the present application is provided with a first sub-pixel 104 and a second sub-pixel 105 corresponding to a long-connected sub-pixel and a short-connected sub-pixel, and a first common signal line 1031 and a second common signal line 1032 are provided, which are separated from each other and electrically connected to each sub-pixel, so as to realize the individual control of each sub-pixel. Specifically, the first common signal line 1031 is used to provide the first sub-pixel 104 with the best pixel common voltage corresponding to the first sub-pixel 104, and the second common signal line 1032 is used to provide the first sub-pixel 105 with the best pixel common voltage corresponding to the second sub-pixel 105, so that the first sub-pixel 104 and the second sub-pixel 105 can both reach their corresponding best pixel common voltages, thereby improving the undesirable phenomena such as afterimage and shaking head lines of the array substrate.

[0089] In an embodiment of the present application, for a dual-gate line array substrate, the first common signal line 1031 and the second common signal line 1032 extend along the first direction from the display area to the peripheral area, and the peripheral area is provided with signal input terminals corresponding to the common signal lines, and the first common signal line 1031 and the second common signal line 1032 are respectively connected to different signal input terminals in the peripheral area. Figure 7 FIG. 1 shows a schematic diagram of a lead structure of a dual-gate array substrate proposed in an embodiment of the present application. Figure 7 As shown, the signal input terminal includes a lead 201 and a transfer structure 202, wherein the lead 201 is arranged on the side of the substrate close to the common signal line 103, wherein the lead 201 extends along the second direction in the peripheral area and forms an electrical connection with the corresponding common signal line 103 through the transfer structure 202.

[0090] In an optional embodiment, the array substrate is a triple gate array substrate. Fig. 9 FIG. 1 shows a schematic diagram of a three-gate linear array substrate structure proposed in an embodiment of the present application. Fig. 9 As shown, the array substrate includes: a data line 101, the data line 101 extends along a first direction; a gate signal line 102, the gate signal line 102 extends along a second direction, the data line 101 and the gate signal line 102 cross to form a plurality of sub-pixels, the plurality of sub-pixels include a first sub-pixel 104, a second sub-pixel 105 and a third sub-pixel 106. In a three-gate line array substrate, a plurality of sub-pixels of different types located in a display area are arranged longitudinally, and every three columns of sub-pixels share the same data line 101, and each of the data lines 101 is arranged between adjacent sub-pixels of the same type, and each of the gate signal lines is arranged between adjacent sub-pixels of different types. Fig. 9For example, the data line 101 located in the middle is arranged between the two first sub-pixels 104 of the first row (or between the two second sub-pixels 105 of the second row, or between the two third sub-pixels 106 of the third row); the data line 102 is located between the first sub-pixel 104 of the first row and the second sub-pixel 105 of the second row (or between the second sub-pixel 105 of the second row and the third sub-pixel 106 of the third row).

[0091] Among them, for a three-gate linear array substrate, such as Fig. 9 As shown, the array substrate further includes a common signal line 103, and the common signal line 103 extends along the second direction in the display area. The common signal line 103 includes a first common signal line 1031, a second common signal line 1032, and a third common signal line 1033, wherein the first common signal line 1031 is electrically connected to the first sub-pixel 104, the second common signal line 1032 is electrically connected to the second sub-pixel 105, and the third common signal line is electrically connected to the third sub-pixel 106.

[0092] In the three-gate line array substrate, the gate signal line 102 includes a first gate signal line 1021 connected to the first sub-pixel 104, a second gate signal line 1022 connected to the second sub-pixel 105, and a third gate signal line 1023 connected to the third sub-pixel 106. The first common signal line 1031 and the first gate signal line 1021 connected to the first sub-pixel 104 are respectively arranged on two opposite sides of the first sub-pixel 104; the second common signal line 1032 and the second gate signal line 1022 connected to the second sub-pixel 105 are respectively arranged on two opposite sides of the second sub-pixel 105; the third common signal line 1033 and the third gate signal line 1023 connected to the third sub-pixel 106 are respectively arranged on two opposite sides of the third sub-pixel 106.

[0093] Optionally, the common signal line 103 (including the first common signal line 1031 , the second common signal line 1032 and the third common signal line 1033 ) and the gate signal line 102 (including the first gate signal line 1021 , the second gate signal line 1022 and the third gate signal line 1023 ) are arranged in the same layer.

[0094] In the embodiment of the present application, for a three-gate line array substrate, the first common signal line 1031 , the second common signal line 1032 , and the third common signal line 1033 are respectively connected to different signal input terminals. Fig.10 FIG. 1 shows a schematic diagram of a lead structure of a three-gate array substrate proposed in an embodiment of the present application. Fig.10As shown, specifically, the first common signal line 1031, the second common signal line 1032 and the third common signal line 1033 extend from the display area to the peripheral area along the second direction, and the peripheral area is provided with a signal input terminal corresponding to the common signal line 103, and the first common signal line 1031, the second common signal line 1032 and the third common signal line 1033 are respectively connected to different signal input terminals in the peripheral area. The signal input terminal includes a lead 201 and a transfer structure 202, and the lead 201 is provided on the side of the substrate close to the common signal line 103, wherein the lead 201 extends along the first direction in the peripheral area and is electrically connected to the corresponding common signal line 103 through the transfer structure 202.

[0095] In the three-gate line array substrate, a support column (PS column) and a support column partition structure corresponding to the support column are provided, the orthographic projection of the support column on the base substrate is located inside the orthographic projection of the gate signal line on the base substrate, the orthographic projection of the support column partition structure 108 on the base substrate is located inside the orthographic projection of the sub-pixel on the base substrate, and the support column partition structure is used to isolate the support column from the area where the sub-pixel is located. The support column partition structure includes a first partition layer and a second partition layer stacked, the first partition layer is arranged on a side close to the base substrate, and the second partition layer is arranged on a side of the first partition layer away from the base substrate. The first partition layer is arranged on the same layer as the gate signal line, and the second partition layer is arranged on the same layer as the data line.

[0096] Therefore, for the three-gate array substrate in the embodiment of the present application, the support pillars and the support pillar partition structures corresponding to the support pillars also have a placeholder factor, which causes certain differences between the multiple sub-pixels in the array substrate located in the display area. The differences between the multiple sub-pixels due to the placeholder factor cause the storage capacitors C between different sub-pixels to be different. st , parasitic capacitance C gs And the jump voltage ΔV pThere are differences between them, which leads to different optimal pixel common voltages for different sub-pixels. The three-gate line array substrate provided in the embodiment of the present application is provided with a first sub-pixel 104, a second sub-pixel 105 and a third sub-pixel 106, and by providing a first common signal line 1031, a second common signal line 1032 and a third common signal line 1033 which are separated from each other and electrically connected to each sub-pixel, each sub-pixel is individually controlled, so that the first sub-pixel 104, the second sub-pixel 105 and the third sub-pixel 106 can all reach their corresponding optimal pixel common voltages, thereby improving the gamma drift, afterimage, shaking head lines and other undesirable phenomena of the array substrate, and optimizing the monochrome gamma and viewing angle.

[0097] The embodiments of the present application provide an array substrate, a display panel and a display device, comprising a display area and a peripheral area on at least one side of the display area, wherein the array substrate of the display area comprises: a base substrate, and a plurality of data lines, a plurality of gate signal lines and a plurality of common signal lines arranged on one side of the base substrate, wherein the data lines and the gate signal lines cross to form a plurality of sub-pixels; wherein the common signal lines comprise a first common signal line and a second common signal line, wherein the first common signal line and the second common signal line are respectively connected to different signal input terminals; and wherein the plurality of sub-pixels comprise a first sub-pixel and a second sub-pixel, wherein the first common signal line is electrically connected to the first sub-pixel, and the second common signal line is electrically connected to the second sub-pixel.

[0098] The embodiment of the present application sets a common signal line connecting different sub-pixels, so that different sub-pixels of the array substrate can be adjusted to the optimal pixel common voltage corresponding to each sub-pixel, thereby improving the gamma drift, afterimage, shaking head wrinkles and other undesirable phenomena caused by the inability of a single common signal line to simultaneously meet the optimal pixel common voltage differences between multiple different sub-pixels.

[0099] Based on the same inventive concept, an embodiment of the present application discloses a display panel, including a liquid crystal layer, a cell-matching substrate, and an array substrate as provided in the embodiment of the present application, wherein the liquid crystal layer is located between the cell-matching substrate and the array substrate.

[0100] Based on the same inventive concept, an embodiment of the present application discloses a display device, including a backlight module and a display panel as provided in the embodiment of the present application, wherein the backlight module is located on the backlight side of the display panel.

[0101] The display device may be a display or a product including a display. The display may be a flat panel display (Flat Panel Display, FPD), a micro display, etc. If the scene is divided according to whether the user can see the back of the display, the display may be a transparent display or an opaque display. It should be noted that the specific display device can be determined according to actual conditions, and the embodiments of the present application are not limited here.

[0102] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0103] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0104] References herein to "one embodiment," "embodiment," or "one or more embodiments" mean that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present disclosure. In addition, please note that examples of the term "in one embodiment" do not necessarily all refer to the same embodiment.

[0105] In the description provided herein, a large number of specific details are described. However, it is understood that the embodiments of the present disclosure can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0106] In the claims, any reference signs placed between brackets shall not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present disclosure may be implemented by means of hardware comprising a number of different elements and by means of a suitably programmed computer. In a unit claim enumerating a number of means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc. does not indicate any order. These words may be interpreted as names.

[0107] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present disclosure.

[0108] The above is a detailed introduction to an array substrate, a display panel and a display device provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for a person skilled in the art, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. An array substrate, characterized in that: The display area includes a display region and a peripheral region on at least one side of the display region, wherein the array substrate of the display region includes: A base substrate, and a plurality of data lines, a plurality of gate signal lines and a plurality of common signal lines arranged on one side of the base substrate, wherein the data lines and the gate signal lines cross to form a plurality of sub-pixels; The common signal line includes a first common signal line and a second common signal line, the first common signal line and the second common signal line are connected to different signal input terminals respectively; and The plurality of sub-pixels include a first sub-pixel and a second sub-pixel, the first common signal line is electrically connected to the first sub-pixel, and the second common signal line is electrically connected to the second sub-pixel.

2. The array substrate according to claim 1, characterized in that: The array substrate is a single-gate line array substrate, and the plurality of sub-pixels further include a third sub-pixel.

3. The array substrate according to claim 2, characterized in that: The common signal line extends along a first direction, and the common signal line further includes a third common signal line, and the third common signal line is electrically connected to the third sub-pixel; the first common signal line, the second common signal line and the third common signal line are respectively connected to different signal input terminals.

4. The array substrate according to claim 3, characterized in that: include: The first common signal line and the first data line connected to the first sub-pixel are respectively arranged on two opposite sides of the first sub-pixel; The second common signal line and the second data line connected to the second sub-pixel are respectively arranged on two opposite sides of the second sub-pixel; The third common signal line and the third data line connected to the third sub-pixel are respectively arranged on two opposite sides of the third sub-pixel.

5. The array substrate according to claim 3, characterized in that: The common signal line and the data line are arranged in the same layer.

6. The array substrate according to claim 2, characterized in that: The common signal line extends along a second direction, and the first common signal line and the second common signal line are respectively arranged on two opposite sides of the first sub-pixel and / or the second sub-pixel.

7. The array substrate according to claim 6, characterized in that: The third sub-pixel is electrically connected to the first common signal line or the second common signal line.

8. The array substrate according to claim 6, characterized in that: Adjacent first sub-pixels are connected via a first jumper structure, and adjacent second sub-pixels are connected via a second jumper structure. The first jumper structure and the second jumper structure are arranged at the same layer as the data line.

9. The array substrate according to claim 6, characterized in that: The common signal line and the gate signal line are arranged in the same layer.

10. The array substrate according to claim 1, characterized in that: The array substrate is a dual-gate line array substrate, and the first sub-pixel and the second sub-pixel are connected to the same data line and are located on the same side of the same data line.

11. The array substrate according to claim 10, characterized in that: The common signal line extends along a first direction, and the common signal line and the data line are arranged in the same layer.

12. The array substrate according to claim 10, characterized in that: The first common signal line is located at a side of the first sub-pixel away from the same data line, and the second common signal line is located at a side of the second sub-pixel close to the same data line.

13. The array substrate according to claim 1, characterized in that: The array substrate is a three-gate line array substrate, and the multiple sub-pixels also include a third sub-pixel; wherein the data line extends along a first direction, the gate signal line extends along a second direction, each of the data lines is arranged between adjacent sub-pixels of the same type, and each of the gate signal lines is arranged between adjacent sub-pixels of different types.

14. The array substrate according to claim 13, characterized in that: The common signal line is arranged along the second direction in the display area, and the common signal line also includes a third common signal line, and the third common signal line is electrically connected to the third sub-pixel; the first common signal line, the second common signal line and the third common signal line are respectively connected to different signal input terminals.

15. The array substrate according to claim 14, characterized in that: include: The first common signal line and the first gate signal line connected to the first sub-pixel are respectively arranged on two opposite sides of the first sub-pixel; The second common signal line and the second gate signal line connected to the second sub-pixel are respectively arranged on two opposite sides of the second sub-pixel; The third common signal line and the third gate signal line connected to the third sub-pixel are respectively arranged on two opposite sides of the third sub-pixel.

16. The array substrate according to claim 13, characterized in that: The common signal line and the gate signal line are arranged in the same layer.

17. The array substrate according to claim 1, characterized in that: Each sub-pixel includes a first electrode and a second electrode, wherein the first electrode is arranged on a side of the gate signal line close to the base substrate, and the second electrode is arranged on a side of the data line away from the base substrate, wherein one of the first electrode and the second electrode is a pixel electrode, and the other is a common electrode.

18. The array substrate according to claim 17, characterized in that: The array substrate further includes a thin film transistor disposed in the same layer as the data line, the common electrode is electrically connected to the common signal line, and the pixel electrode is electrically connected to the data line via the thin film transistor.

19. The array substrate according to claim 1, characterized in that: The array substrate in the peripheral area further includes: a lead line arranged on a side of the base substrate close to the common signal line, wherein the common signal line extends from the display area to the peripheral area and is electrically connected to the lead line through a transfer structure.

20. The array substrate according to claim 19, characterized in that: The data line extends along a first direction, and the gate signal line extends along a second direction; one of the lead line and the common signal line is arranged along the first direction, and the other is arranged along the second direction.

21. A display panel, characterized in that: It comprises a liquid crystal layer, a cell-matching substrate, and an array substrate as claimed in any one of claims 1 to 20, wherein the liquid crystal layer is located between the cell-matching substrate and the array substrate.

22. A display device, characterized in that: It comprises a backlight module and the display panel as claimed in claim 21, wherein the backlight module is located on the backlight side of the display panel.

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