Span time measuring device and span time measuring system

Abstract

The invention discloses a span time measuring device and a span time measuring system, and belongs to the field of time measurement. Comprising a device control module, a counting time sequence generation module, a low-speed clock counting module, a joint counting module and a counting data caching module, the combined counting module comprises at least one combined counting unit, each combined counting unit comprises a high-speed clock counting unit and a top-speed delay counting unit, the high-speed clock counting unit is coupled with the top-speed delay counting unit, and a counting clock of the high-speed clock counting unit comes from a ring oscillation signal output by the top-speed delay counting unit; the low-speed clock counting module, the high-speed clock counting unit and the top-speed delay counting unit are all electrically connected to the device control module, the counting time sequence generation module and the counting data caching module, and the counting data caching module is electrically connected with the device control module.

Description

Technical Field

[0001] The present application belongs to the field of time measurement, and specifically relates to a span time measurement device and a span time measurement system. Background Art

[0002] With the development of science and technology, the flight time of ultrasound and laser flying in space can be measured by measuring devices, and the pulse span time of pulse signals can also be measured. Among them, the ultrasonic wave can be emitted by an ultrasonic pulse generator, and the ultrasonic wave propagates in the medium, and then the ultrasonic wave is received by the ultrasonic pulse receiver, and then the received ultrasonic wave is transmitted to the time measuring device, and the time measurement device measures the time of ultrasonic wave propagation in the medium, and then determines the span time. However, in the related art, the measurement principle and method of the flight time or span time measurement device are not accurate enough to measure the time. Summary of the invention

[0003] The purpose of the embodiments of the present application is to provide a span time measurement device and a span time measurement system, which at least solves the problem that the time measured by the measurement principle and method of the flight time or span time measurement device is not accurate enough.

[0004] In a first aspect, an embodiment of the present application provides a span time measurement device, the span time measurement device comprising: a device control module, a counting sequence generation module, a low-speed clock counting module, a joint counting module, and a counting data cache module;

[0005] The joint counting module includes at least one joint counting unit, one of the joint counting units includes a high-speed clock counting unit and an extremely fast delay counting unit, the high-speed clock counting unit is coupled with the extremely fast delay counting unit, and the counting clock of the high-speed clock counting unit comes from the ring oscillation signal output by the extremely fast delay counting unit;

[0006] The low-speed clock counting module, the high-speed clock counting unit and the extreme-speed delay counting unit are all electrically connected to the device control module, the counting timing generation module and the counting data buffer module, and the counting data buffer module is electrically connected to the device control module;

[0007] The counting timing generation module is used to receive the signal to be measured, the clock signal and the control signal to generate and send different corresponding measured signals to the low-speed clock counting module, the high-speed clock counting unit and the extremely fast delay counting unit; the low-speed clock counting module is used to detect the corresponding measured signal to obtain the low-speed clock counting module count value of the corresponding measured signal, the high-speed clock counting unit is used to detect the corresponding measured signal to obtain the corresponding high-speed clock counting unit count value of the corresponding measured signal, and the extremely fast delay counting unit is used to detect the corresponding measured signal to obtain the extremely fast delay counting unit count value of the corresponding measured signal;

[0008] The device control module is used to obtain the count value of the low-speed clock counting module, the count value of the high-speed clock counting unit and the count value of the extremely fast delay counting unit from the counting data cache module to determine the span time, or the central operation module obtains the count value of the low-speed clock counting module, the count value of the high-speed clock counting unit and the count value of the extremely fast delay counting unit from the counting data cache module to determine the span time.

[0009] Optionally, the joint counting module includes a first joint counting unit and a second joint counting unit;

[0010] The counting timing generation module is used to receive the signal to be measured, the clock signal and the control signal to generate and send a first signal to the low-speed clock counting module, generate and send a second signal to the first joint counting unit, and generate and send a third signal to the second joint counting unit;

[0011] The low-speed clock counting module is used to detect the first signal to obtain the count value of the low-speed clock counting module, the high-speed clock counting unit in the first joint counting unit is used to detect the second signal to obtain the count value of the high-speed clock counting unit of the head time, and the extremely fast delay counting unit in the first joint counting unit is used to detect the second signal to obtain the extremely fast delay counting unit count value of the head time; the high-speed clock counting unit in the second joint counting unit is used to detect the third signal to obtain the count value of the high-speed clock counting unit of the tail time, and the extremely fast delay counting unit in the second joint counting unit is used to detect the third signal to obtain the extremely fast delay counting unit count value of the tail time;

[0012] The device control module is used to obtain the count value of the low-speed clock counting module, the count value of the high-speed clock counting unit of the head time, the count value of the extremely fast delay counting unit of the head time, the count value of the high-speed clock counting unit of the tail time, and the count value of the extremely fast delay counting unit of the tail time to determine the span time, or the device control module passes the count value of the low-speed clock counting module, the count value of the high-speed clock counting unit of the head time, the count value of the extremely fast delay counting unit of the head time, the count value of the high-speed clock counting unit of the tail time, and the count value of the extremely fast delay counting unit of the tail time to the central computing module, and the central computing module determines the span time.

[0013] Optionally, the joint counting module includes a third joint counting unit;

[0014] The counting timing generation module is used to receive the signal to be measured, the clock signal and the control signal to generate and send a first signal to the low-speed clock counting module, and to generate and send a second signal and a third signal to the third joint counting unit;

[0015] The low-speed clock counting module is used to detect the first signal to obtain the count value of the low-speed clock counting module, the high-speed clock counting unit in the third joint counting unit is used to detect the second signal and the third signal to obtain the count value of the high-speed clock counting unit of the head time and the count value of the high-speed clock counting unit of the tail time, and the extreme-speed delay counting unit in the third joint counting unit is used to detect the second signal and the third signal to obtain the count value of the extreme-speed delay counting unit of the head time and the count value of the extreme-speed delay counting unit of the tail time;

[0016] The device control module is used to obtain the count value of the low-speed clock counting module, the count value of the high-speed clock counting unit of the head time, the count value of the extremely fast delay counting unit of the head time, the count value of the high-speed clock counting unit of the tail time, and the count value of the extremely fast delay counting unit of the tail time to determine the span time, or the device control module passes the count value of the low-speed clock counting module, the count value of the high-speed clock counting unit of the head time, the count value of the extremely fast delay counting unit of the head time, the count value of the high-speed clock counting unit of the tail time, and the count value of the extremely fast delay counting unit of the tail time to the central computing module, and the central computing module determines the span time.

[0017] Optionally, the device control module is used to determine the low-speed clock counting time according to the count value of the low-speed clock counting module, determine the high-speed counting head time according to the count value of the high-speed clock counting unit of the head time, determine the high-speed counting tail time according to the count value of the high-speed clock counting unit of the tail time, determine the extremely fast counting head time according to the count value of the extremely fast delay counting unit of the head time, determine the extremely fast counting tail time according to the count value of the extremely fast delay counting unit of the tail time, and determine the span time according to the low-speed clock counting time, the high-speed counting head time, the high-speed counting tail time, the extremely fast counting head time, and the extremely fast counting tail time;

[0018] Alternatively, the central computing module is used to determine the low-speed clock counting time according to the count value of the low-speed clock counting module, determine the high-speed counting head time according to the count value of the high-speed clock counting unit of the head time, determine the high-speed counting tail time according to the count value of the high-speed clock counting unit of the tail time, determine the extremely fast counting head time according to the count value of the extremely fast delay counting unit of the head time, determine the extremely fast counting tail time according to the count value of the extremely fast delay counting unit of the tail time, and determine the span time according to the low-speed clock counting time, the high-speed counting head time, the high-speed counting tail time, the extremely fast counting head time, and the extremely fast counting tail time.

[0019] Optionally, the device control module or the central operation module is used to add the low-speed clock counting time, the extreme-speed counting head time, and the high-speed counting head time, and subtract the extreme-speed counting tail time and the high-speed counting tail time to obtain the span time.

[0020] Optionally, the device control module or the central computing module is used to multiply the count value of the low-speed clock counting module by the counting clock cycle of the low-speed clock counting module to obtain the low-speed clock counting time; multiply the count value of the high-speed clock counting unit of the head time by the counting clock cycle of the high-speed clock counting unit to obtain the high-speed counting head time; multiply the count value of the high-speed clock counting unit of the tail time by the counting clock cycle of the high-speed clock counting unit to obtain the high-speed counting tail time; multiply the count value of the extreme delay counting unit of the head time by the inherent delay of the delay unit of the extreme delay counting unit to obtain the extreme counting head time; multiply the count value of the extreme delay counting unit of the tail time by the inherent delay of the delay unit of the extreme delay counting unit to obtain the extreme counting tail time.

[0021] Optionally, the extremely fast delay counting unit block includes: a NOR gate, a plurality of buffers, a data acquisition unit and a data processing unit;

[0022] The NOR gate and the plurality of buffers are sequentially connected in series, and along the series connection direction of the plurality of buffers, the first buffer is connected to the NOR gate, the tap of the output end of the last buffer is connected to an input end of the NOR gate, the NOR gate and the plurality of buffers form a delay loop, the NOR gate and each buffer form a delay unit, and a data acquisition unit is electrically connected to the output end taps of each of the delay units, the data acquisition unit is electrically connected to the data processing unit, the data processing unit is electrically connected to the device control module, the tap of the output end of one of the delay units is connected to the high-speed clock counting unit block, and is used as a counting clock of the high-speed clock counting unit;

[0023] Among them, the data acquisition unit is used to collect the state value of the output end of each delay unit in the extremely fast delay loop, and the data processing unit is used to obtain the count value of the extremely fast delay counting unit according to the state value of the output end of each delay unit.

[0024] Optionally, the extremely fast delay counting unit comprises: a NAND gate, an even number of inverters, a data acquisition unit and a data processing unit;

[0025] The NAND gate and the even-numbered inverters are sequentially connected in series, and along the series connection direction of the even-numbered inverters, the first inverter is connected to the NAND gate, and the tap of the output end of the last inverter is connected to an input end of the NAND gate. The NAND gate and the even-numbered inverters form an extremely fast delay loop, the NAND gate and each inverter form a delay unit, and a data acquisition unit is electrically connected to the output end taps of each delay unit, the data acquisition unit is electrically connected to the data processing unit, and the data processing unit is electrically connected to the device control module. The tap of the output end of one of the delay units is connected to the high-speed clock counting unit block and used as a counting clock of the high-speed clock counting unit;

[0026] Among them, the data acquisition unit is used to collect the state value of the output end of each delay unit in the extremely fast delay chain, and the data processing unit is used to obtain the count value of the extremely fast delay counting unit according to the state value of the output end of each delay unit.

[0027] Optionally, the extremely fast delay counting unit comprises: a NOR gate, an even number of inverters, a data acquisition unit and a data processing unit;

[0028] The NOR gate and the even-numbered inverters are sequentially connected in series, and along the series connection direction of the even-numbered inverters, the first inverter is connected to the NOR gate, the tap of the output end of the last inverter is connected to an input end of the NOR gate, the NOR gate and the even-numbered inverters form an extremely fast delay loop, the NOR gate and each inverter form a delay unit, and the data acquisition unit is electrically connected to the output end taps of each delay unit, the data acquisition unit is electrically connected to the data processing unit, the data processing unit is electrically connected to the device control module, the tap of the output end of one of the delay units is connected to the high-speed clock counting unit block, and is used as a counting clock of the high-speed clock counting unit;

[0029] Among them, the data acquisition unit is used to collect the state value of the output end of each delay unit in the extremely fast delay chain, and the data processing unit is used to obtain the count value of the extremely fast delay counting unit according to the state value of the output end of each delay unit.

[0030] Optionally, the extremely fast delay counting unit comprises: a NAND gate, a plurality of buffers, a data acquisition unit and a data processing unit;

[0031] The NAND gate and the plurality of buffers are sequentially connected in series, and along the series connection direction of the plurality of buffers, the first buffer is connected to the NAND gate, the tap of the output end of the last buffer is connected to an input end of the NAND gate, the NAND gate and the plurality of buffers form a delay loop, the NAND gate and each buffer form a delay unit, and a data acquisition unit is electrically connected to the output end taps of each of the delay units respectively, the data acquisition unit is electrically connected to the data processing unit, the data processing unit is electrically connected to the device control module, the tap of the output end of one of the delay units is connected to the high-speed clock counting unit block, and is used as a counting clock of the high-speed clock counting unit;

[0032] Among them, the data acquisition unit is used to collect the state value of the output end of each delay unit in the extremely fast delay loop, and the data processing unit is used to obtain the count value of the extremely fast delay counting unit according to the state value of the output end of each delay unit.

[0033] Optionally, the span time measurement device further comprises: the counting data cache module comprises 1st to Mth level counting data cache units, M≥1;

[0034] The low-speed clock counting module is used to send the count value of the low-speed clock counting module to the counting data cache module, the high-speed clock counting unit is used to send the count value of the high-speed clock counting unit to the counting data cache module, and the extreme-speed delay counting unit is used to send the count value of the extreme-speed delay counting unit to the counting data cache module, and the counting data cache module caches the count value of the low-speed clock counting module, the count value of the high-speed clock counting unit and the count value of the extreme-speed delay counting unit.

[0035] Optionally, the low-speed clock counting module, the high-speed clock counting unit and the extremely fast delay counting unit are all used to measure the measured signal generated by the counting timing generation module corresponding to a pulse or multiple pulses starting from the first pulse in the measured signal, or to measure the measured signal generated by the counting timing generation module corresponding to a pulse or multiple pulses after the first pulse in the measured signal, and the low-speed clock counting module count value, the high-speed clock counting unit count value and the extremely fast delay counting unit count value are respectively formed for the measured signal corresponding to each of the measured pulses, and the counting data cache module caches the low-speed clock counting module count value, the high-speed clock counting unit count value and the extremely fast delay counting unit count value.

[0036] Optionally, the low-speed clock counting module, the high-speed clock counting unit and the extremely fast time delay counting unit are all used to measure the measured signal generated by the counting timing generation module corresponding to the pulse in the measured signal, and the low-speed clock counting module count value, the high-speed clock counting unit count value and the extremely fast time delay counting unit count value are respectively formed for the measured signal corresponding to each pulse measured, until the pulse measurement end mark arrives, or the number of pulses reaches a preset number threshold, the low-speed clock counting module, the high-speed clock counting unit and the extremely fast time delay counting unit all stop measuring the The remaining pulses in the signal to be measured correspond to the measured signal generated by the counting timing generation module, and the count value of the low-speed clock counting module, the count value of the high-speed clock counting unit and the count value of the extreme-speed delay counting unit of the measured signal corresponding to each pulse form a count value group, and the count value group enters the counting data cache module, and the counting data cache module caches the count value group in the order of entry, and after the counting data cache module is full of data, the count value group that first enters the counting data cache module overflows, so that the count value group that enters the counting data cache module later is cached.

[0037] In a second aspect, an embodiment of the present application provides a span time measurement system, the span time measurement system comprising a clock multiplication module, a clock generation module, a signal source selection module, a comprehensive control module, a bus interface module, and the span time measurement device described in any one of the first aspects above;

[0038] The clock multiplication module is electrically connected to the low-frequency clock source and the clock generation module, and the clock multiplication module is used to multiply the low-speed clock signal generated by the low-frequency clock source to a clock signal of the highest frequency required by the span time measurement system, and send the clock signal of the highest frequency to the clock generation module, so that the clock generation module generates clock signals of various frequencies required by the span time measurement system; the integrated control module is electrically connected to the clock multiplication module, and the integrated control module is used to control the working configuration, operation or termination of the clock multiplication module;

[0039] The clock generating module is electrically connected to the low-speed clock counting module and the counting timing generating module, and the clock generating module is used to generate and send corresponding clock signals to the low-speed clock counting module and the counting timing generating module, and is used to drive each module of the span time measuring device to operate;

[0040] The information source selection module is electrically connected to the counting timing generation module. Under the control of the integrated control module, the information source selection module selects a signal from a corresponding source and sends it to the counting timing generation module.

[0041] The bus interface module is electrically connected to the integrated control module, and the bus interface module is electrically connected to the device control module, the bus interface module is used to connect to the central operation module, and the central operation module is used to obtain the count value of the low-speed clock counting module, the count value of the high-speed clock counting unit and the count value of the extreme delay counting unit from the device control module to determine the span time;

[0042] The integrated control module is electrically connected to the clock generation module, and the integrated control module is used to control the working configuration, operation or suspension of the clock generation module;

[0043] The integrated control module is electrically connected to the information source selection module, and the integrated control module is used to control the working configuration, operation or termination of the information source selection module.

[0044] Optionally, the span time measurement system also includes an interrupt control module, the integrated control module is electrically connected to the interrupt control module, and under the control of the integrated control module, the interrupt control module converts the interrupt signal generated by the device control module into an interrupt signal of a unified format, and sends the interrupt signal of the unified format to the central operation module.

[0045] Optionally, the span time measurement system further includes a central operation module, and the central operation module is electrically connected to the bus interface module or the interrupt control module.

[0046] In the embodiment of the present application, since the high-speed clock counting unit is coupled with the extremely fast delay counting unit, during the actual measurement process, the counting clock of the high-speed clock counting unit can come from the ring oscillation signal output by the extremely fast delay counting unit, that is, the counting clock of the high-speed clock counting unit is determined by the extremely fast delay counting unit. Since the low-speed clock counting module, the high-speed clock counting unit and the extremely fast delay counting unit are all electrically connected to the device control module, the counting timing generation module and the counting data cache module, and the counting data cache module is electrically connected to the device control module, once the counting timing generation module receives the signal to be measured, the counting timing generation module can generate different corresponding test signals to be sent to the low-speed clock counting module, the high-speed clock counting unit and the extremely fast delay counting unit, so that the low-speed clock counting module can detect the corresponding test signal to obtain the low-speed clock counting module count value of the corresponding test signal, the high-speed clock counting unit can detect the corresponding test signal to obtain the high-speed clock counting unit count value of the corresponding test signal, and the extremely fast clock counting unit can The corresponding test signal is detected to obtain the count value of the high-speed clock counting unit of the corresponding test signal, and the low-speed clock counting module transmits the low-speed clock counting module count value to the data cache module, the high-speed clock counting unit transmits the high-speed clock counting unit count value to the data cache module, and the high-speed clock counting unit transmits the high-speed clock counting unit count value to the data cache module, so that the device control module can obtain the low-speed clock counting module count value, the high-speed clock counting unit count value and the high-speed delay counting unit count value from the data cache module to determine the span time, or the central operation module obtains the low-speed clock counting module count value, the high-speed clock counting unit count value and the high-speed delay counting unit count value from the counting data cache module to determine the span time. In addition, the counting clock frequency of the low-speed clock counting module is less than the counting clock frequency of the high-speed clock counting unit, and the counting frequency of the high-speed clock counting unit is less than the counting equivalent clock frequency and counting resolution of the extremely fast delay counting unit, so that the counting value of the low-speed clock counting module, the counting value of the high-speed clock counting unit and the counting value of the extremely fast clock counting unit acquired by the device control module are different from each other, and the counting resolutions are different from each other, which can ensure that the determined span time is more accurate. That is, in the embodiment of the present application, by setting the extremely fast delay counting unit, the high-speed clock counting unit and the low-speed clock counting module, the corresponding counting values ​​are determined by the extremely fast delay counting unit, the high-speed clock counting unit and the low-speed clock counting module respectively, and then the device control module or the central operation module can determine the span time based on the counting value of the low-speed clock counting module, the counting value of the high-speed clock counting unit and the counting value of the extremely fast delay counting unit, that is, in the embodiment of the present application, the span time can be determined more accurately. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1A schematic diagram showing that a joint counting module in a span time measurement device provided by an embodiment of the present application includes a first joint counting unit and a second joint counting unit;

[0048] Figure 2 A schematic diagram showing that a joint counting module in a span time measurement device provided by an embodiment of the present application includes a third joint counting unit;

[0049] Figure 3 A schematic diagram showing a principle of span time measurement provided by an embodiment of the present application;

[0050] Figure 4 A schematic diagram showing a span time head time measurement principle provided by an embodiment of the present application;

[0051] Figure 5 A schematic diagram showing a span time trail time measurement principle provided by an embodiment of the present application;

[0052] Figure 6 A schematic diagram showing an extremely fast time counting unit formed based on a NAND gate and a buffer provided in an embodiment of the present application;

[0053] Figure 7 A schematic diagram showing an extremely fast time counting unit formed based on a NOR gate and a buffer provided in an embodiment of the present application;

[0054] Figure 8 A schematic diagram showing an extremely fast time counting unit formed based on a NAND gate and an inverter provided in an embodiment of the present application;

[0055] Fig. 9 A schematic diagram showing an extremely fast time counting unit formed based on a NOR gate and an inverter provided in an embodiment of the present application;

[0056] Fig.10 A schematic diagram showing data storage in a counting data cache module when a span time measurement device provided by an embodiment of the present application is in a measurement mode based on a head response pulse;

[0057] Fig.11 A schematic diagram showing data cached by a counting data cache module when a span time measurement device provided by an embodiment of the present application is in a measurement mode based on a tail response pulse;

[0058] Fig.12 A schematic diagram showing a span time measurement system provided in an embodiment of the present application.

[0059] Reference numerals:

[0060] 001: NAND gate; 002: buffer; 003: data acquisition unit; 004: data processing unit; 005: NOR gate; 006: inverter; 10: device control module; 20: counting timing generation module; 30: low-speed clock counting module; 40: joint counting module; 41: first joint counting unit; 42: second joint counting unit; 43: third joint counting unit; 411: high-speed clock counting unit; 412: extremely fast clock counting unit; 50: counting data cache module; 51: counting data cache unit; 1000: clock generation module; 2000: signal source selection module; 3000: integrated control module; 4000: bus interface module; 5000: interrupt control module; 6000: central operation module; 7000: clock multiplication module. DETAILED DESCRIPTION

[0061] The term "first" or "second" in the specification and claims of this application may include one or more of the features explicitly or implicitly. In the description of this application, unless otherwise specified, "plurality" means two or more. In addition, "and / or" in the specification and claims means at least one of the connected objects, and the character " / " generally means that the objects connected before and after are in an "or" relationship.

[0062] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0063] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0064] like Figures 1 to 11As shown, the span time measurement device includes: a device control module 10, a counting sequence generation module 20, a low-speed clock counting module 30, a joint counting module 40 and a counting data buffer module 50;

[0065] The joint counting module 40 includes at least one joint counting unit, and one joint counting unit includes a high-speed clock counting unit 411 and an extremely fast delay counting unit 412. The high-speed clock counting unit 411 is coupled to the extremely fast delay counting unit, and the counting clock of the high-speed clock counting unit 411 comes from the ring oscillation signal output by the extremely fast delay counting unit 412; the low-speed clock counting module 30, the high-speed clock counting unit 411 and the extremely fast delay counting unit 412 are all electrically connected to the device control module 10, the counting timing generation module 20 and the counting data buffer module 50, and the counting data buffer module 50 is electrically connected to the device control module 10; the counting timing generation module 20 is used to receive the signal to be measured, the clock signal and the control signal to generate and send to the low-speed clock counting module 30, the high-speed clock counting unit 411 and the extremely fast delay counting unit 4 12 sends different corresponding test signals; the low-speed clock counting module 30 is used to detect the corresponding test signal to obtain the low-speed clock counting module count value of the corresponding test signal, the high-speed clock counting unit 411 is used to detect the corresponding test signal to obtain the corresponding high-speed clock counting unit count value of the corresponding test signal, and the extremely fast delay counting unit 412 is used to detect the corresponding test signal to obtain the extremely fast delay counting unit count value of the corresponding test signal; the device control module 10 is used to obtain the low-speed clock counting module count value, the high-speed clock counting unit count value and the extremely fast delay counting unit count value from the counting data cache module 50 to determine the span time, or the central operation module 6000 obtains the low-speed clock counting module count value, the high-speed clock counting unit count value and the extremely fast delay counting unit count value from the counting data cache module 50 and determines the span time.

[0066] In the embodiment of the present application, the counting clock frequency of the low-speed clock counting module 30 is lower than the counting clock frequency of the high-speed clock counting unit 411 , and the counting frequency of the high-speed clock counting unit 411 is lower than the counting equivalent clock frequency and counting resolution of the extreme-speed delay counting unit 412 .

[0067] In addition, in the embodiment of the present application, the low-speed clock counting module 30, the high-speed clock counting unit 411 and the extremely fast delay counting unit 412 are all electrically connected to the device control module 10, the counting timing generation module 20 and the counting data cache module 50, which means: the low-speed clock counting module 30, the high-speed clock counting unit 411 and the extremely fast delay counting unit 412 are all electrically connected to the device control module 10; the low-speed clock counting module 30, the high-speed clock counting unit 411 and the extremely fast delay counting unit 412 are all electrically connected to the counting timing generation module 20; the low-speed clock counting module 30, the high-speed clock counting unit 411 and the extremely fast delay counting unit 412 are all electrically connected to the data cache module.

[0068] In the embodiment of the present application, since the high-speed clock counting unit 411 is coupled with the extremely fast delay counting unit 412, during the actual measurement process, the counting clock of the high-speed clock counting unit 411 can come from the ring oscillation signal output by the extremely fast delay counting unit 412, that is, the counting clock of the high-speed clock counting unit 411 is determined by the extremely fast delay counting unit 412. Since the low-speed clock counting module 30, the high-speed clock counting unit 411 and the extremely fast delay counting unit 412 are all electrically connected to the device control module 10, the counting timing generation module 20 and the counting data cache module 50, and the counting data cache module 50 is electrically connected to the device control module 10, once the counting timing generation module 20 receives the signal to be measured, the counting timing generation module 20 can generate different corresponding measured signals to be sent to the low-speed clock counting module 30, the high-speed clock counting unit 411 and the extremely fast delay counting unit 412, so that the low-speed clock counting module 30 can detect the corresponding measured signal to obtain the low-speed clock counting module count value of the corresponding measured signal, the high-speed clock counting unit 411 can detect the corresponding measured signal to obtain the high-speed clock counting unit count value of the corresponding measured signal, and the extremely fast clock counting The counting unit 412 can detect the corresponding test signal to obtain the counting value of the high-speed clock counting unit 412 of the corresponding test signal, and the low-speed clock counting module 30 transmits the low-speed clock counting module counting value to the data cache module, the high-speed clock counting unit 411 transmits the high-speed clock counting unit counting value to the data cache module, and the high-speed clock counting unit 412 transmits the high-speed clock counting unit counting value to the data cache module, so that the device control module 10 can obtain the low-speed clock counting module counting value, the high-speed clock counting unit counting value and the high-speed delay counting unit counting value from the data cache module to determine the span time, or the central operation module 6000 obtains the low-speed clock counting module counting value, the high-speed clock counting unit counting value and the high-speed delay counting unit counting value from the counting data cache module 50 to determine the span time. In addition, the counting clock frequency of the low-speed clock counting module 30 is lower than the counting clock frequency of the high-speed clock counting unit 411, and the counting frequency of the high-speed clock counting unit 411 is lower than the counting equivalent clock frequency and counting resolution of the extremely fast delay counting unit 412, so that the counting values ​​of the low-speed clock counting module, the high-speed clock counting unit and the extremely fast clock counting unit obtained by the device control module 10 are different from each other, and the counting accuracies are different from each other, which can ensure that the determined span time is more accurate.That is, in the embodiment of the present application, by setting up an extremely fast delay counting unit 412, a high-speed clock counting unit 411 and a low-speed clock counting module 30, the corresponding counting values ​​are respectively determined by the extremely fast delay counting unit 412, the high-speed clock counting unit 411 and the low-speed clock counting module 30, and then the device control module 10 or the central computing module 6000 can determine the span time based on the count value of the low-speed clock counting module, the count value of the high-speed clock counting unit and the count value of the extremely fast delay counting unit, that is, in the embodiment of the present application, the span time can be determined more accurately.

[0069] In addition, in the embodiment of the present application, the device control module 10 may have a computing function, so that the device control module 10 can determine the span time. Of course, the device control module 10 may not have a computing function or may not perform span time computing. In this case, in actual applications, the device control module 10 may be electrically connected to the central computing module 6000, and the device control module 10 sends the acquired data to the central computing module 6000, and the span time is determined by the central computing module 6000. The central computing module 6000 may include but is not limited to a host computer, a central processing unit, etc.

[0070] In addition, in the embodiment of the present application, the joint counting module 40 can have different forms, and the following forms are specifically described as examples:

[0071] Form (1): Figure 1As shown, the joint counting module 40 may include a first joint counting unit 41 and a second joint counting unit 42; the counting timing generation module 20 is used to receive the signal to be measured, the clock signal and the control signal to generate and send a first signal to the low-speed clock counting module 30, generate and send a second signal to the first joint counting unit 41, and generate and send a third signal to the second joint counting unit 42; the low-speed clock counting module 30 is used to detect the first signal to obtain a low-speed clock counting module count value, the high-speed clock counting unit 411 in the first joint counting unit 41 is used to detect the second signal to obtain a high-speed clock counting unit count value of the head time, and the extremely fast delay counting unit 412 in the first joint counting unit 41 is used to detect the second signal to obtain the extremely fast delay counting unit count value of the head time; the high-speed clock counting unit 411 in the second joint counting unit 42 is used to detect the third The signal obtains the high-speed clock counting unit count value of the tail time, and the extremely fast delay counting unit 412 in the second joint counting unit 42 is used to detect the third signal to obtain the extremely fast delay counting unit count value of the tail time; the device control module 10 is used to obtain the low-speed clock counting module count value, the high-speed clock counting unit count value of the head time, the extremely fast delay counting unit count value of the head time, the high-speed clock counting unit count value of the tail time, and the extremely fast delay counting unit count value of the tail time to determine the span time, or the device control module 10 passes the low-speed clock counting module count value, the high-speed clock counting unit count value of the head time, the extremely fast delay counting unit count value of the head time, the high-speed clock counting unit count value of the tail time, and the extremely fast delay counting unit count value of the tail time to the central computing module 6000, and the central computing module 6000 determines the span time.

[0072] Through such a setting, the high-speed clock counting unit 411 in the first joint counting unit 41 can detect the second signal to obtain the high-speed clock counting unit count value of the head time, the extremely fast delay counting unit 412 in the first joint counting unit 41 can detect the second signal to obtain the extremely fast delay counting unit count value of the head time, and the high-speed clock counting unit 411 in the second joint counting unit 42 can detect the third signal to obtain the high-speed clock counting unit count value of the tail time, and the extremely fast delay counting unit 412 in the second joint counting unit 42 is used to obtain the extremely fast delay counting unit count value of the tail time from the third signal. Among them, the counting frequency of the high-speed clock counting unit 411 in the first joint counting unit 41 is less than the counting equivalent clock frequency and counting resolution of the extremely fast delay counting unit 412, and the counting frequency of the high-speed clock counting unit 411 in the second joint counting unit 42 is less than the counting equivalent clock frequency and counting resolution of the extremely fast delay counting unit 412, so that the device control module 10 or the central operation module 6000 is equivalent to obtaining count values ​​of different measurement precisions, so that the determined span time is more accurate.

[0073] Form (2): Figure 2 As shown, the joint counting module 40 may include a third joint counting unit 43; the counting timing generation module 20 is used to receive the signal to be measured, the clock signal and the control signal to generate and send a first signal to the low-speed clock counting module 30, generate and send a second signal and a third signal to the third joint counting unit 43; the low-speed clock counting module 30 is used to detect the first signal to obtain a low-speed clock counting module count value, the high-speed clock counting unit 411 in the third joint counting unit 43 is used to detect the second signal and the third signal to obtain a high-speed clock counting unit count value of the head time and a high-speed clock counting unit count value of the tail time, and the extreme speed delay counting unit 412 in the third joint counting unit 43 is used to detect the second signal and the third signal to obtain a head time The device control module 10 is used to obtain the count value of the low-speed clock counting module, the count value of the high-speed clock counting unit of the head time, the count value of the extremely fast delay counting unit of the head time, the count value of the high-speed clock counting unit of the tail time, and the count value of the extremely fast delay counting unit of the tail time to determine the span time, or the device control module 10 passes the count value of the low-speed clock counting module, the count value of the high-speed clock counting unit of the head time, the count value of the extremely fast delay counting unit of the head time, the count value of the high-speed clock counting unit of the tail time, and the count value of the extremely fast delay counting unit of the tail time to the central computing module 6000, and the central computing module 6000 determines the span time.

[0074] By such a setting, the high-speed clock counting unit 411 in the third joint counting unit 43 can detect the second signal and the third signal to obtain the high-speed clock counting unit count value of the head time and the high-speed clock counting unit count value of the tail time, which is equivalent to the high-speed clock counting unit 411 in the third joint counting unit 43 can obtain the high-speed clock counting unit count value of the head time and the high-speed clock counting unit count value of the tail time, thereby reducing the number of high-speed clock counting units 411, which helps to reduce costs. Similarly, the extremely fast delay counting unit 412 in the third joint counting unit 43 can detect the second signal and the third signal to obtain the extremely fast delay counting unit count value of the head time and the extremely fast delay counting unit count value of the tail time, which is equivalent to the extremely fast clock counting unit 412 in the third joint counting unit 43 can obtain the extremely fast clock counting unit count value of the head time and the extremely fast clock counting unit count value of the tail time, thereby reducing the number of extremely fast clock counting units 412, which helps to reduce costs. Among them, the counting frequency of the high-speed clock counting unit 411 in the third joint counting unit 43 is lower than the counting equivalent clock frequency and counting resolution of the extreme-speed delay counting unit 412, so that the device control module 10 or the central computing module 6000 is equivalent to obtaining counting values ​​with different measurement accuracies, so that the determined span time is more accurate.

[0075] In addition, in the embodiment of the present application, the low-speed clock counting module 30 can significantly reduce the circuit power consumption required for counting, and the clock source of the low-speed clock counting module 30 can be a high-precision crystal oscillator, for example, a 4MHz crystal oscillator with a 20ppm, so that the counting accuracy of the low-speed clock counting module is high and the deviation is small. In addition, the clock frequency range of the low-speed clock counting module 30 can be 4MHz to 20MHz.

[0076] In addition, in the embodiment of the present application, the device control module 10 is used to determine the low-speed clock counting time according to the count value of the low-speed clock counting module, determine the high-speed counting head time according to the count value of the high-speed clock counting unit of the head time, determine the high-speed counting tail time according to the count value of the high-speed clock counting unit of the tail time, determine the extremely fast counting head time according to the count value of the extremely fast delay counting unit of the head time, determine the extremely fast counting tail time according to the count value of the extremely fast delay counting unit of the tail time, and determine the cross according to the low-speed clock counting time, the high-speed counting head time, the high-speed counting tail time, the extremely fast counting head time, and the extremely fast counting tail time. Degree time; or, the central operation module 6000 is used to determine the low-speed clock counting time according to the count value of the low-speed clock counting module, determine the high-speed counting head time according to the count value of the high-speed clock counting unit of the head time, determine the high-speed counting tail time according to the count value of the high-speed clock counting unit of the tail time, determine the extremely fast counting head time according to the count value of the extremely fast delay counting unit of the head time, determine the extremely fast counting tail time according to the count value of the extremely fast delay counting unit of the tail time, and determine the span time according to the low-speed clock counting time, the high-speed counting head time, the high-speed counting tail time, the extremely fast counting head time, and the extremely fast counting tail time.

[0077] In addition, in some embodiments, the device control module 10 or the central operation module 6000 is used to add the low-speed clock counting time, the extremely fast counting head time, and the high-speed counting head time, and subtract the extremely fast counting tail time and the high-speed counting tail time to obtain the span time.

[0078] Among them, Figure 3 , Figure 4 and Figure 5 As shown, in Figure 3 , Figure 4 and Figure 5In the example, TM_EN indicates a span time measurement unit enable signal; START indicates a start signal to be measured; STOP indicates a stop signal to be measured; PULSE indicates a signal to be measured; CLK_LS indicates a low-speed clock; CNT_COMB_HEAD indicates a head joint counting unit for span time measurement of a signal to be measured, including a high-speed clock counting unit count value and a high-speed clock counting unit count value in a first joint counting unit 41, or including a high-speed clock counting unit count value and a high-speed clock counting unit count value in a third joint counting unit 43; CNT_LS_BODY_TAIL indicates a tail joint counting unit count value for span time measurement of a signal to be measured, including a high-speed clock counting unit count value and a high-speed clock counting unit count value in a second joint counting unit 42. Value, or includes the high-speed clock counting unit count value and the high-speed clock counting unit count value in the third joint counting unit 43; CNT_LS_BODY_TAIL represents the low-speed clock counting module count value for span body and tail time measurement of the measured signal; CNT_HS_HEAD represents the high-speed clock counting unit count value for head time measurement of the span time of the measured signal; CNT_US_HEAD represents the high-speed clock counting unit count value for head time measurement of the span time of the measured signal; CNT_HS_TAIL represents the high-speed clock counting unit count value for tail time measurement of the span time of the measured signal; CNT_US_TAIL represents the high-speed clock counting unit count value for tail time measurement of the span time of the measured signal.

[0079] In addition, in some embodiments, the device control module 10 or the central computing module 6000 is used to multiply the count value of the low-speed clock counting module with the counting clock cycle of the low-speed clock counting module 30 to obtain the low-speed clock counting time; multiply the count value of the high-speed clock counting unit of the head time with the counting clock cycle of the high-speed clock counting unit 411 to obtain the high-speed counting head time; multiply the count value of the high-speed clock counting unit of the tail time with the counting clock cycle of the high-speed clock counting unit 411 to obtain the high-speed counting tail time; multiply the count value of the extreme delay counting unit of the head time with the inherent delay of the delay unit of the extreme delay counting unit 412 to obtain the extreme counting head time; multiply the count value of the extreme delay counting unit of the tail time with the inherent delay of the delay unit of the extreme delay counting unit 412 to obtain the extreme counting tail time.

[0080] For example, as shown in the following formula:

[0081] TS_PULSE=TS_COMB_HEAD+TS_LS_BODY_TAIL-TS_COMB_TAIL(1)

[0082] TS_LS_BODY_TAIL =NUM(CNT_LS) * PERIOD_CLK_LS (2)

[0083] TS_COMB_HEAD=TS_HS_HEAD+TS_US_HEAD=NUM(CNT_HS_HEAD)*PERIOD_CLK_HS+NUM(CNT_US_HEAD)*US_CELL_DLY(3)TS_COMB_TAIL=TS_HS_TAIL+TS_US_TAIL=NUM(CNT_HS_TAIL)

[0084] *PERIOD_CLK_HS+NUM(CNT_US_TAIL)*US_CELL_DLY(4)

[0085] In the above formula, TS_LS_BODY_TAIL represents the low-speed clock counting time obtained by the low-speed clock counting module 30; TS_COMB_HEAD represents the joint head counting time obtained by the joint counting module 40; TS_COMB_TAIL represents the joint tail counting time obtained by the joint counting module 40; TS_HS_HEAD represents the head span time counted by the high-speed clock counting unit 411, that is, the high-speed clock counting head time; TS_US_HEAD represents the head span time counted by the extreme delay counting unit 412, that is, the extreme delay counting TS_HS_TAIL represents the tail span time counted by the high-speed clock counting unit 411, that is, the high-speed clock counting tail time; TS_US_TAIL represents the tail span time counted by the extremely fast delay counting unit 412, that is, the extremely fast delay counting tail time; PERIOD_CLK_LS represents the counting clock cycle of the low-speed clock counting module 30; PERIOD_CLK_HS represents the counting clock cycle of the high-speed counting unit; US_CELL_DLY represents the inherent delay of the delay unit of the counting unit; NUM represents the quantity.

[0086] In addition, in the embodiment of the present application, the types of the extremely fast delay counting unit 412 can be different, and the following types are specifically described as examples:

[0087] Type (1): e.g. Figure 6As shown, the extremely fast delay counting unit 412 may include: a NAND gate 001, a plurality of buffers 002, a data acquisition unit 003 and a data processing unit 004; the NAND gate 001 and the plurality of buffers 002 are sequentially connected in series, and along the series connection direction of the plurality of buffers 002, the first buffer 002 is connected to the NAND gate 001, the tap of the output end of the last buffer 002 is connected to an input end of the NAND gate 001, the NAND gate 001 and the plurality of buffers 002 form a delay loop, the NAND gate 001 and each buffer 002 form a delay unit, and the data acquisition unit 003 and the data processing unit 004 ... Unit 003 is electrically connected to the output taps of each delay unit respectively, the data acquisition unit 003 is electrically connected to the data processing unit 004, the data processing unit 004 is electrically connected to the device control module 10, the tap of the output end of one of the delay units is connected to the high-speed clock counting unit block, and is used as the counting clock of the high-speed clock counting unit 411; wherein, the data acquisition unit 003 is used to collect the state value of the output end of each delay unit in the ultra-fast delay loop, and the data processing unit 004 is used to obtain the counting value of the ultra-fast delay counting unit according to the state value of the output end of each delay unit.

[0088] Among them, the NAND gate 001 is equivalent to forming the first delay unit, so that once the signal to be detected is transmitted to the NAND gate 001, the signal to be detected can pass through the NAND gate 001, and then pass through multiple buffers 002 in sequence until the signal is transmitted to the last buffer 002, and the tap of the output end of the last buffer 002 is connected to an input end of the NAND gate 001, so that the signal to be detected can return to the NAND gate 001, so as to form a delay loop. Since the delay loop is composed of a NAND gate 001 and multiple buffers 002 connected in series to form a ring, when the signal of another independent input end of the NAND gate 001 is at a high level, the NAND gate 001 is equivalent to an inverter, and the delay ring is equivalent to a ring oscillator, and the ring oscillator can output a ring oscillation signal. In addition, the tap of the output end of a delay unit in the delay unit is connected to the high-speed clock counting unit block, so that the ring oscillation signal can be transmitted to the high-speed clock counting unit 411, and the counting clock period of the high-speed clock counting unit 411 can be determined. Any delay unit on the delay loop can output a ring oscillation signal, which is not limited in the present embodiment. For the sake of design simplicity and simplicity of description, the present application selects the output end of the last buffer 002 to output the ring oscillation signal to illustrate the principle of the invention.

[0089] Type (2): e.g. Figure 7As shown, the extremely fast delay counting unit comprises: a NOR gate 005, a plurality of buffers 002, a data acquisition unit 003 and a data processing unit 004; the NOR gate 005 and the plurality of buffers 002 are sequentially connected in series, and along the series connection direction of the plurality of buffers 002, the first buffer 002 is connected to the NOR gate 005, the tap of the output end of the last buffer 002 is connected to an input end of the NOR gate 005, the NOR gate 005 and the plurality of buffers 002 form a delay loop, the NOR gate 005 and each buffer 002 form a delay unit, and the data acquisition unit 004 is connected to the plurality of buffers 002. 03 are electrically connected to the output taps of each delay unit respectively, the data acquisition unit 003 is electrically connected to the data processing unit 004, the data processing unit 004 is electrically connected to the device control module 10, the tap of the output end of one of the delay units is connected to the high-speed clock counting unit block, and is used as the counting clock of the high-speed clock counting unit 411; wherein, the data acquisition unit 003 is used to collect the state value of the output end of each delay unit in the ultra-fast delay loop, and the data processing unit 004 is used to obtain the counting value of the ultra-fast delay counting unit according to the state value of the output end of each delay unit.

[0090] The NOR gate 005 is equivalent to forming the first delay unit, so that once the signal to be detected is transmitted to the NOR gate 005, the signal to be detected can pass through the NOR gate 005, and then pass through multiple buffers 002 in sequence until the signal is transmitted to the last buffer 002, and the tap of the output end of the last buffer 002 is connected to an input end of the NOR gate 005, so that the signal to be detected can return to the NOR gate 005, so as to form a delay loop. Since the delay loop is formed by a NOR gate 005 and multiple buffers 002 connected in series into a ring, when the signal of another independent input end of the NOR gate 005 is at a low level, the NOR gate 005 is equivalent to an inverter, and the delay ring is equivalent to a ring oscillator, and the ring oscillator can output a ring oscillation signal. In addition, the tap of the output end of a delay unit in the delay unit is connected to the high-speed clock counting unit block, so that the ring oscillation signal can be transmitted to the high-speed clock counting unit 411, and the counting clock period of the high-speed clock counting unit 411 can be determined. Any delay unit on the delay loop can output a ring oscillation signal, which is not limited in the present embodiment. For the sake of design simplicity and simplicity of description, the present application selects the output end of the last buffer 002 to output the ring oscillation signal to illustrate the principle of the invention.

[0091] Type (3): e.g. Figure 8As shown, the extremely fast delay counting unit 412 may include: a NAND gate 001, an even number of inverters 006, a data acquisition unit 003 and a data processing unit 004; the NAND gate 001 and the even number of inverters 006 are sequentially connected in series, and along the series connection direction of the even number of inverters 006, the first inverter 006 is connected to the NAND gate 001, and the tap of the output end of the last inverter 006 is connected to an input end of the NAND gate 001, and the NAND gate 001 and the even number of inverters 006 form an extremely fast delay loop, and the NAND gate 001 and each inverter 006 form a delay unit, and the number The data acquisition unit 003 is electrically connected to the output taps of each delay unit respectively, the data acquisition unit 003 is electrically connected to the data processing unit 004, the data processing unit 004 is electrically connected to the device control module 10, and the tap of the output end of one of the delay units is connected to the high-speed clock counting unit block and used as the counting clock of the high-speed clock counting unit 411; wherein, the data acquisition unit 003 is used to collect the state value of the output end of each delay unit in the ultra-fast delay chain, and the data processing unit 004 is used to obtain the counting value of the ultra-fast delay counting unit according to the state value of the output end of each delay unit.

[0092] Among them, the NAND gate 001 is equivalent to forming the first delay unit, so that once the signal to be detected is transmitted to the NAND gate 001, the signal to be detected can pass through the NAND gate 001, and then pass through an even number of inverters 006 in sequence until the signal is transmitted to the last inverter 006, and the tap of the output end of the last inverter 006 is connected to an input end of the NAND gate 001, so that the signal to be detected can return to the NAND gate 001, so as to form a delay loop. Since the delay loop is composed of a NAND gate 001 and an even number of inverters 006 connected in series to form a ring, when the signal of another independent input end of the NAND gate 001 is at a high level, the NAND gate 001 is equivalent to an inverter, and the delay ring is equivalent to a ring oscillator, and the ring oscillator can output a ring oscillation signal. In addition, the tap of the output end of a delay unit in the delay unit is connected to the high-speed clock counting unit block, so that the ring oscillation signal can be transmitted to the high-speed clock counting unit 411, and the counting clock period of the high-speed clock counting unit 411 can be determined. Any delay unit on the delay loop can output a ring oscillation signal, which is not limited in the present embodiment. For the sake of design simplicity and simplicity of description, the present application selects the output end of the last inverter 006 to output the ring oscillation signal to illustrate the invention principle.

[0093] Type (4): e.g. Fig. 9As shown, the extremely fast delay counting unit 412 may include: a NOR gate 005, an even number of inverters 006, a data acquisition unit 003 and a data processing unit 004; the NOR gate 005 and the even number of inverters 006 are sequentially connected in series, and along the series connection direction of the even number of inverters 006, the first inverter 006 is connected to the NAND gate 001, and the tap of the output end of the last inverter 006 is connected to an input end of the NAND gate 001, the NOR gate 005 and the even number of inverters 006 form an extremely fast delay loop, the NOR gate 005 and each inverter 006 form a delay unit, and the number The data acquisition unit 003 is electrically connected to the output taps of each delay unit respectively, the data acquisition unit 003 is electrically connected to the data processing unit 004, the data processing unit 004 is electrically connected to the device control module 10, and the tap of the output end of one of the delay units is connected to the high-speed clock counting unit block and used as the counting clock of the high-speed clock counting unit 411; wherein, the data acquisition unit 003 is used to collect the state value of the output end of each delay unit in the ultra-fast delay chain, and the data processing unit 004 is used to obtain the counting value of the ultra-fast delay counting unit according to the state value of the output end of each delay unit.

[0094] Among them, the NOR gate 005 is equivalent to forming the first delay unit, so that once the signal to be detected is transmitted to the NOR gate 005, the signal to be detected can pass through the NOR gate 005, and then pass through an even number of inverters 006 in sequence until the signal is transmitted to the last inverter 006, and the tap of the output end of the last inverter 006 is connected to an input end of the NOR gate 005, so that the signal to be detected can return to the NOR gate 005, so as to form a delay loop. Since the delay loop is connected in series by a NOR gate 005 and an even number of inverters 006 to form a ring, when the signal of another independent input end of the NOR gate 005 is at a low level, the NOR gate 005 is equivalent to an inverter, and the delay ring is equivalent to a ring oscillator, and the ring oscillator can output a ring oscillation signal. In addition, the tap of the output end of a delay unit in the delay unit is connected to the high-speed clock counting unit block, so that the ring oscillation signal can be transmitted to the high-speed clock counting unit 411, and the counting clock cycle of the high-speed clock counting unit 411 can be determined. Any delay unit on the delay loop can output a ring oscillation signal, which is not limited in the present embodiment. For the sake of design simplicity and simplicity of description, the present application selects the output end of the last inverter 006 to output the ring oscillation signal to illustrate the invention principle.

[0095] In addition, in some embodiments, the span time measurement device may further include: the counting data cache module 50 includes 1 to M level counting data cache units 51, M≥1; the low-speed clock counting module 30 is used to send the low-speed clock counting module count value to the counting data cache module 50, the high-speed clock counting unit 411 is used to send the high-speed clock counting unit count value to the counting data cache module 50, the extremely fast delay counting unit 412 is used to send the extremely fast delay counting unit count value to the counting data cache module 50, and the counting data cache module 50 caches the low-speed clock counting module count value, the high-speed clock counting unit count value and the extremely fast delay counting unit count value.

[0096] By setting up the counting data cache module 50, the counting data cache module 50 can cache the count value of the low-speed clock counting module, the count value of the high-speed clock counting unit and the count value of the extremely fast clock counting unit, so that the device control module 10 or the central operation module 6000 can obtain these count values ​​from the counting data cache module 50 when needed, thereby facilitating the central operation module 6000 or the device control module 10 to determine the span time.

[0097] It should be noted that the counting data cache module 50 may include 1 to M level counting data cache units 51, so that after the low-speed clock counting module 30, the high-speed clock counting unit 411 and the extremely fast clock counting unit 412 are electrically connected to the counting data cache module 50, each level of the counting data cache unit 51 in the 1 to M level counting data cache units 51 can cache the low-speed clock counting module count value, the high-speed clock counting unit count value and the extremely fast clock counting unit count value, so that the low-speed clock counting module count value, the high-speed clock counting unit count value and the extremely fast clock counting unit count value can be further processed later, such as performing difference calculation of adjacent data and consistency check of the difference. Among them, in the embodiment of the present application, when M is equal to 3, the counting data cache module 50 can include 1 to 3 level counting data cache units 51, of course, M can also be other values, for example, M is equal to 2, and for another example, M is equal to 5. In this regard, the embodiment of the present application is not limited here.

[0098] In addition, in some embodiments, Fig.10As shown, the low-speed clock counting module 30, the high-speed clock counting unit 411 and the extremely fast clock counting unit 412 are all used to measure the measured signal generated by the counting timing generation module 20 corresponding to a pulse or multiple pulses starting from the first pulse in the measured signal, or to measure the measured signal generated by the counting timing generation module 20 corresponding to a pulse or multiple pulses after the first pulse in the measured signal, and for the measured signal corresponding to each measured pulse, a low-speed clock counting module count value, a high-speed clock counting unit count value and an extremely fast clock counting unit count value are respectively formed, and the counting data cache module 50 caches the low-speed clock counting module count value, the high-speed clock counting unit count value and the extremely fast clock counting unit count value.

[0099] Through such a setting, it is equivalent to that the span time measurement device is in a measurement mode based on the head response for measurement. Among them, the pulse in the signal to be measured is the pulse after the zero-crossing comparison. The low-speed clock counting module 30, the high-speed clock counting unit 411 and the extremely fast clock counting unit 412 are all used to measure the measured signal generated by the counting timing generation module 20 corresponding to a pulse or multiple pulses starting from the first pulse in the signal to be measured, or to measure the measured signal generated by the counting timing generation module 20 corresponding to a pulse or multiple pulses after the first pulse in the signal to be measured, and the low-speed clock counting module count value, the high-speed clock counting unit count value and the extremely fast clock counting unit count value are respectively formed for the measured signal corresponding to each measured pulse. , the low-speed clock counting module 30, the high-speed clock counting unit 411 and the extremely fast clock counting unit 412 stop measuring and sampling the measured signal generated by the counting timing generating module 20 corresponding to the remaining pulses in the measured signal, and the counting data cache module 50 only caches the counting values ​​formed by the low-speed clock counting module 30, the high-speed clock counting unit 411 and the extremely fast clock counting unit 412, that is, after the counting data cache module 50 caches the counting values ​​formed by the low-speed clock counting module 30, the high-speed clock counting unit 411 and the extremely fast clock counting unit 412, it no longer caches data.

[0100] In addition, in some embodiments, Fig.11As shown, the low-speed clock counting module 30, the high-speed clock counting unit 411 and the extremely fast clock counting unit 412 are all used to measure the measured signal generated by the counting timing generation module 20 corresponding to the pulse in the measured signal, and the low-speed clock counting module count value, the high-speed clock counting unit count value and the extremely fast clock counting unit count value are respectively formed for the measured signal corresponding to each pulse measured, until the pulse measurement end mark arrives, or the number of pulses reaches a preset number threshold, the low-speed clock counting module 30, the high-speed clock counting unit 411 and the extremely fast clock counting unit 412 are all stopped The measurement sampling of the measured signal generated by the counting timing generating module 20 corresponding to the remaining pulses in the measured signal, the low-speed clock counting module count value, the high-speed clock counting unit count value and the extreme-speed delay counting unit count value of the measured signal corresponding to each pulse form a counting value group, and the counting value group enters the counting data cache module, and the counting data cache module caches the counting value group in the order of entry, and after the counting data cache module 50 is full of data, the counting value group that first enters the counting data cache module 50 overflows, so that the counting value group that enters the counting data cache module 50 later is cached.

[0101] In the embodiment of the present application, since the high-speed clock counting unit 411 is coupled with the extremely fast delay counting unit 412, during the actual measurement process, the counting clock of the high-speed clock counting unit 411 can come from the ring oscillation signal output by the extremely fast delay counting unit 412, that is, the counting clock of the high-speed clock counting unit 411 is determined by the extremely fast delay counting unit 412. Since the low-speed clock counting module 30, the high-speed clock counting unit 411 and the extremely fast delay counting unit 412 are all electrically connected to the device control module 10, the counting timing generation module 20 and the counting data cache module 50, and the counting data cache module 50 is electrically connected to the device control module 10, once the counting timing generation module 20 receives the signal to be measured, the counting timing generation module 20 can generate different corresponding measured signals to be sent to the low-speed clock counting module 30, the high-speed clock counting unit 411 and the extremely fast delay counting unit 412, so that the low-speed clock counting module 30 can detect the corresponding measured signal to obtain the low-speed clock counting module count value of the corresponding measured signal, the high-speed clock counting unit 411 can detect the corresponding measured signal to obtain the high-speed clock counting unit count value of the corresponding measured signal, and the extremely fast clock counting The counting unit 412 can detect the corresponding test signal to obtain the counting value of the high-speed clock counting unit 412 of the corresponding test signal, and the low-speed clock counting module 30 transmits the low-speed clock counting module counting value to the data cache module, the high-speed clock counting unit 411 transmits the high-speed clock counting unit counting value to the data cache module, and the high-speed clock counting unit 412 transmits the high-speed clock counting unit counting value to the data cache module, so that the device control module 10 can obtain the low-speed clock counting module counting value, the high-speed clock counting unit counting value and the high-speed delay counting unit counting value from the data cache module to determine the span time, or the central operation module 6000 obtains the low-speed clock counting module counting value, the high-speed clock counting unit counting value and the high-speed delay counting unit counting value from the counting data cache module 50 to determine the span time. In addition, the counting clock frequency of the low-speed clock counting module 30 is lower than the counting clock frequency of the high-speed clock counting unit 411, and the counting frequency of the high-speed clock counting unit 411 is lower than the counting equivalent clock frequency and counting resolution of the extremely fast delay counting unit 412, so that the counting values ​​of the low-speed clock counting module, the high-speed clock counting unit and the extremely fast clock counting unit obtained by the device control module 10 are different from each other, and the counting accuracies are different from each other, which can ensure that the determined span time is more accurate.That is, in the embodiment of the present application, by setting up an extremely fast delay counting unit 412, a high-speed clock counting unit 411 and a low-speed clock counting module 30, the corresponding counting values ​​are respectively determined by the extremely fast delay counting unit 412, the high-speed clock counting unit 411 and the low-speed clock counting module 30, and then the device control module 10 or the central computing module 6000 can determine the span time based on the count value of the low-speed clock counting module, the count value of the high-speed clock counting unit and the count value of the extremely fast delay counting unit, that is, in the embodiment of the present application, the span time can be determined more accurately.

[0102] The present application embodiment provides a span time measurement system, such as Fig.12 As shown, the span time measurement system includes a clock multiplication module 7000, a clock generation module 1000, a signal source selection module 2000, an integrated control module 3000, a bus interface module 4000 and a span time measurement device in any of the above embodiments.

[0103] The clock multiplication module 7000 is electrically connected to the low-frequency clock source and the clock generation module 1000. The clock multiplication module 7000 is used to multiply the low-speed clock signal generated by the low-frequency clock source to a clock signal of the highest frequency required by the span time measurement system, and send the clock signal of the highest frequency to the clock generation module 1000, so that the clock generation module 1000 generates clock signals of various frequencies required by the span time measurement system; the integrated control module 3000 is electrically connected to the clock multiplication module 7000, and the integrated control module 3000 is used to control the working configuration, operation or termination of the clock multiplication module 7000; the clock generation module 1000 is electrically connected to the low-speed clock counting module 30 and the counting timing generation module 20, and the clock generation module 1000 is used to generate and send corresponding clock signals to the low-speed clock counting module 30 and the counting timing generation module 20, and is used to drive the operation of each module of the span time measurement device; the signal source selection module 2000 is electrically connected to the counting timing generation module 20. The generating module 20 is electrically connected, and the signal source selection module 2000, under the control of the integrated control module 3000, selects the signal of the corresponding source and sends it to the counting timing generating module 20; the bus interface module 4000 is electrically connected to the integrated control module 3000, and the bus interface module 4000 is electrically connected to the device control module 10, and the bus interface module 4000 is used to connect to the central operation module 6000, and the central operation module 6000 is used to obtain the count value of the low-speed clock counting module, the count value of the high-speed clock counting unit and the count value of the extremely fast delay counting unit from the device control module 10 to determine the span time; the integrated control module 3000 is electrically connected to the clock generating module 1000, and the integrated control module 3000 is used to control the working configuration, and operation or termination of the clock generating module 1000; the integrated control module 3000 is electrically connected to the signal source selection module 2000, and the integrated control module 3000 is used to control the working configuration, and operation or termination of the signal source selection module 2000.

[0104] like Fig. 9As shown, the signal source selection module 2000 is used to receive the signal to be measured, and the signal to be measured can be a pulse type signal, such as a pulse signal PULSE, and the rising edge and falling edge of the pulse signal PULSE are used to transmit the start event and the end event of the span event, that is, the rising edge transmits the start event, and the falling edge transmits the end event; or the falling edge and the rising edge of the pulse signal PULSE are used to transmit the start event and the end event of the span event, that is, the falling edge transmits the start event, and the rising edge transmits the end event; Of course, in the embodiment of the present application, the signal to be measured can also be two independent event type signals, such as event signals START and STOP, and the two independent event signals START and STOP are used to transmit the start event and the end event of the span event respectively. For the convenience of expression in this application, the signal to be measured is described as a pulse signal PULSE. The embodiment of the present application does not limit the type of the signal to be measured.

[0105] In addition, the signal source selection module 2000 can select the signal source and forward the corresponding signal to the counting timing generation module 20. The counting timing generation module 20 generates and sends the corresponding measured signal to the low-speed clock counting module 30, the high-speed clock counting unit 411 and the high-speed clock counting unit 412. In addition, the clock generation module 10001000 can send a clock signal to the low-speed clock counting module 30 and drive the low-speed clock counting module 30 to operate.

[0106] In addition, in practical applications, the central operation module 6000 can be connected to the bus interface module 4000, so that the central operation module 6000 can be connected to the span time measurement device more conveniently.

[0107] In addition, the way in which the central operation module 6000 determines the span time based on the count value of the low-speed clock counting module, the count value of the high-speed clock counting unit and the count value of the high-speed clock counting unit can refer to the way in which the central operation module 6000 determines the span time in the above embodiment, which will not be repeated here.

[0108] In addition, in some embodiments, the span time measurement system may further include an interrupt control module 5000, which is electrically connected to the device control module 10, the integrated control module 3000 is electrically connected to the interrupt control module 5000, and the device control module 10 is electrically connected to the interrupt control module 5000. Under the control of the integrated control module 3000, the interrupt control module 5000 converts the interrupt signal generated by the device control module 10 into an interrupt signal in a unified format, and sends the interrupt signal in a unified format to the central operation module 6000.

[0109] In addition, in some embodiments, Fig. 9As shown, the span time measurement system may further include a central operation module 6000, and the central operation module 6000 is electrically connected to the bus interface module 4000 or the interrupt control module 5000. The central operation module 6000 may be a central processing unit, and of course, the central operation module 6000 may also be other types, for example, the central operation module 6000 is a host computer. This is not limited in the embodiments of the present application.

[0110] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0111] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A span time measurement device, characterized in that: The span time measurement device comprises: a device control module, a counting sequence generation module, a low-speed clock counting module, a joint counting module and a counting data buffer module; The joint counting module includes at least one joint counting unit, one of the joint counting units includes a high-speed clock counting unit and an extremely fast delay counting unit, the high-speed clock counting unit is coupled with the extremely fast delay counting unit, and the counting clock of the high-speed clock counting unit comes from the ring oscillation signal output by the extremely fast delay counting unit; The low-speed clock counting module, the high-speed clock counting unit and the extreme-speed delay counting unit are all electrically connected to the device control module, the counting timing generation module and the counting data buffer module, and the counting data buffer module is electrically connected to the device control module; The counting timing generation module is used to receive the signal to be measured, the clock signal and the control signal to generate and send different corresponding measured signals to the low-speed clock counting module, the high-speed clock counting unit and the extremely fast delay counting unit; the low-speed clock counting module is used to detect the corresponding measured signal to obtain the low-speed clock counting module count value of the corresponding measured signal, the high-speed clock counting unit is used to detect the corresponding measured signal to obtain the corresponding high-speed clock counting unit count value of the corresponding measured signal, and the extremely fast delay counting unit is used to detect the corresponding measured signal to obtain the extremely fast delay counting unit count value of the corresponding measured signal; The device control module is used to obtain the count value of the low-speed clock counting module, the count value of the high-speed clock counting unit and the count value of the extremely fast delay counting unit from the counting data cache module to determine the span time, or the central operation module obtains the count value of the low-speed clock counting module, the count value of the high-speed clock counting unit and the count value of the extremely fast delay counting unit from the counting data cache module to determine the span time.

2. The span time measuring device according to claim 1, characterized in that: The joint counting module includes a first joint counting unit and a second joint counting unit; The counting timing generation module is used to receive the signal to be measured, the clock signal and the control signal to generate and send a first signal to the low-speed clock counting module, generate and send a second signal to the first joint counting unit, and generate and send a third signal to the second joint counting unit; The low-speed clock counting module is used to detect the first signal to obtain the count value of the low-speed clock counting module, the high-speed clock counting unit in the first joint counting unit is used to detect the second signal to obtain the count value of the high-speed clock counting unit of the head time, and the extremely fast delay counting unit in the first joint counting unit is used to detect the second signal to obtain the extremely fast delay counting unit count value of the head time; the high-speed clock counting unit in the second joint counting unit is used to detect the third signal to obtain the count value of the high-speed clock counting unit of the tail time, and the extremely fast delay counting unit in the second joint counting unit is used to detect the third signal to obtain the extremely fast delay counting unit count value of the tail time; The device control module is used to obtain the count value of the low-speed clock counting module, the count value of the high-speed clock counting unit of the head time, the count value of the extremely fast delay counting unit of the head time, the count value of the high-speed clock counting unit of the tail time, and the count value of the extremely fast delay counting unit of the tail time to determine the span time, or the device control module passes the count value of the low-speed clock counting module, the count value of the high-speed clock counting unit of the head time, the count value of the extremely fast delay counting unit of the head time, the count value of the high-speed clock counting unit of the tail time, and the count value of the extremely fast delay counting unit of the tail time to the central computing module, and the central computing module determines the span time.

3. The span time measuring device according to claim 1, characterized in that: The joint counting module includes a third joint counting unit; The counting timing generation module is used to receive the signal to be measured, the clock signal and the control signal to generate and send a first signal to the low-speed clock counting module, and to generate and send a second signal and a third signal to the third joint counting unit; The low-speed clock counting module is used to detect the first signal to obtain the count value of the low-speed clock counting module, the high-speed clock counting unit in the third joint counting unit is used to detect the second signal and the third signal to obtain the count value of the high-speed clock counting unit of the head time and the count value of the high-speed clock counting unit of the tail time, and the extreme-speed delay counting unit in the third joint counting unit is used to detect the second signal and the third signal to obtain the count value of the extreme-speed delay counting unit of the head time and the count value of the extreme-speed delay counting unit of the tail time; The device control module is used to obtain the count value of the low-speed clock counting module, the count value of the high-speed clock counting unit of the head time, the count value of the extremely fast delay counting unit of the head time, the count value of the high-speed clock counting unit of the tail time, and the count value of the extremely fast delay counting unit of the tail time to determine the span time, or the device control module passes the count value of the low-speed clock counting module, the count value of the high-speed clock counting unit of the head time, the count value of the extremely fast delay counting unit of the head time, the count value of the high-speed clock counting unit of the tail time, and the count value of the extremely fast delay counting unit of the tail time to the central computing module, and the central computing module determines the span time.

4. The span time measuring device according to claim 2 or 3, characterized in that: The device control module is used to determine the low-speed clock counting time according to the count value of the low-speed clock counting module, determine the high-speed counting head time according to the count value of the high-speed clock counting unit of the head time, determine the high-speed counting tail time according to the count value of the high-speed clock counting unit of the tail time, determine the extremely fast counting head time according to the count value of the extremely fast delay counting unit of the head time, determine the extremely fast counting tail time according to the count value of the extremely fast delay counting unit of the tail time, and determine the span time according to the low-speed clock counting time, the high-speed counting head time, the high-speed counting tail time, the extremely fast counting head time, and the extremely fast counting tail time; Alternatively, the central computing module is used to determine the low-speed clock counting time according to the count value of the low-speed clock counting module, determine the high-speed counting head time according to the count value of the high-speed clock counting unit of the head time, determine the high-speed counting tail time according to the count value of the high-speed clock counting unit of the tail time, determine the extremely fast counting head time according to the count value of the extremely fast delay counting unit of the head time, determine the extremely fast counting tail time according to the count value of the extremely fast delay counting unit of the tail time, and determine the span time according to the low-speed clock counting time, the high-speed counting head time, the high-speed counting tail time, the extremely fast counting head time, and the extremely fast counting tail time.

5. The span time measuring device according to claim 4, characterized in that: The device control module or the central operation module is used to add the low-speed clock counting time, the extreme-speed counting head time, and the high-speed counting head time, and subtract the extreme-speed counting tail time and the high-speed counting tail time to obtain the span time.

6. The span time measuring device according to claim 4, characterized in that: The device control module or the central operation module is used to multiply the count value of the low-speed clock counting module by the counting clock cycle of the low-speed clock counting module to obtain the low-speed clock counting time; multiply the count value of the high-speed clock counting unit of the head time by the counting clock cycle of the high-speed clock counting unit to obtain the high-speed counting head time; multiply the count value of the high-speed clock counting unit of the tail time by the counting clock cycle of the high-speed clock counting unit to obtain the high-speed counting tail time; multiply the count value of the extreme delay counting unit of the head time by the inherent delay of the delay unit of the extreme delay counting unit to obtain the extreme counting head time; multiply the count value of the extreme delay counting unit of the tail time by the inherent delay of the delay unit of the extreme delay counting unit to obtain the extreme counting tail time.

7. The span time measuring device according to claim 1, characterized in that: The extremely fast delay counting unit comprises: a NAND gate, a plurality of buffers, a data acquisition unit and a data processing unit; The NAND gate and the plurality of buffers are sequentially connected in series, and along the series connection direction of the plurality of buffers, the first buffer is connected to the NAND gate, the tap of the output end of the last buffer is connected to an input end of the NAND gate, the NAND gate and the plurality of buffers form a delay loop, the NAND gate and each buffer form a delay unit, and a data acquisition unit is electrically connected to the output end taps of each of the delay units respectively, the data acquisition unit is electrically connected to the data processing unit, the data processing unit is electrically connected to the device control module, the tap of the output end of one of the delay units is connected to the high-speed clock counting unit block, and is used as a counting clock of the high-speed clock counting unit; Among them, the data acquisition unit is used to collect the state value of the output end of each delay unit in the extremely fast delay loop, and the data processing unit is used to obtain the count value of the extremely fast delay counting unit according to the state value of the output end of each delay unit.

8. The span time measuring device according to claim 1, characterized in that: The extremely fast delay counting unit block includes: a NOR gate, a plurality of buffers, a data acquisition unit and a data processing unit; The NOR gate and the plurality of buffers are sequentially connected in series, and along the series connection direction of the plurality of buffers, the first buffer is connected to the NOR gate, the tap of the output end of the last buffer is connected to an input end of the NOR gate, the NOR gate and the plurality of buffers form a delay loop, the NOR gate and each buffer form a delay unit, and a data acquisition unit is electrically connected to the output end taps of each of the delay units, the data acquisition unit is electrically connected to the data processing unit, the data processing unit is electrically connected to the device control module, the tap of the output end of one of the delay units is connected to the high-speed clock counting unit block, and is used as a counting clock of the high-speed clock counting unit; Among them, the data acquisition unit is used to collect the state value of the output end of each delay unit in the extremely fast delay loop, and the data processing unit is used to obtain the count value of the extremely fast delay counting unit according to the state value of the output end of each delay unit.

9. The span time measuring device according to claim 1, characterized in that: The extremely fast delay counting unit comprises: a NAND gate, an even number of inverters, a data acquisition unit and a data processing unit; The NAND gate and the even-numbered inverters are sequentially connected in series, and along the series connection direction of the even-numbered inverters, the first inverter is connected to the NAND gate, and the tap of the output end of the last inverter is connected to an input end of the NAND gate. The NAND gate and the even-numbered inverters form an extremely fast delay loop, the NAND gate and each inverter form a delay unit, and a data acquisition unit is electrically connected to the output end taps of each delay unit, the data acquisition unit is electrically connected to the data processing unit, and the data processing unit is electrically connected to the device control module. The tap of the output end of one of the delay units is connected to the high-speed clock counting unit block and used as a counting clock of the high-speed clock counting unit; Among them, the data acquisition unit is used to collect the state value of the output end of each delay unit in the extremely fast delay chain, and the data processing unit is used to obtain the count value of the extremely fast delay counting unit according to the state value of the output end of each delay unit.

10. The span time measuring device according to claim 1, characterized in that: The extremely fast delay counting unit comprises: a NOR gate, an even number of inverters, a data acquisition unit and a data processing unit; The NOR gate and the even-numbered inverters are sequentially connected in series, and along the series connection direction of the even-numbered inverters, the first inverter is connected to the NOR gate, the tap of the output end of the last inverter is connected to an input end of the NOR gate, the NOR gate and the even-numbered inverters form an extremely fast delay loop, the NOR gate and each inverter form a delay unit, and the data acquisition unit is electrically connected to the output end taps of each delay unit, the data acquisition unit is electrically connected to the data processing unit, the data processing unit is electrically connected to the device control module, the tap of the output end of one of the delay units is connected to the high-speed clock counting unit block, and is used as a counting clock of the high-speed clock counting unit; Among them, the data acquisition unit is used to collect the state value of the output end of each delay unit in the extremely fast delay chain, and the data processing unit is used to obtain the count value of the extremely fast delay counting unit according to the state value of the output end of each delay unit.

11. The span time measuring device according to claim 1, characterized in that: The span time measurement device further comprises: the counting data cache module comprises 1st to Mth level counting data cache units, M≥1; The low-speed clock counting module is used to send the count value of the low-speed clock counting module to the counting data cache module, the high-speed clock counting unit is used to send the count value of the high-speed clock counting unit to the counting data cache module, and the extreme-speed delay counting unit is used to send the count value of the extreme-speed delay counting unit to the counting data cache module, and the counting data cache module caches the count value of the low-speed clock counting module, the count value of the high-speed clock counting unit and the count value of the extreme-speed delay counting unit.

12. The span time measuring device according to claim 1, characterized in that: The low-speed clock counting module, the high-speed clock counting unit and the extremely fast delay counting unit are all used to measure the measured signal generated by the counting timing generation module corresponding to a pulse or multiple pulses starting from the first pulse in the measured signal, or to measure the measured signal generated by the counting timing generation module corresponding to a pulse or multiple pulses after the first pulse in the measured signal, and the low-speed clock counting module count value, the high-speed clock counting unit count value and the extremely fast delay counting unit count value are respectively formed for the measured signal corresponding to each of the measured pulses, and the counting data cache module caches the low-speed clock counting module count value, the high-speed clock counting unit count value and the extremely fast delay counting unit count value.

13. The span time measuring device according to claim 1, characterized in that: The low-speed clock counting module, the high-speed clock counting unit and the extremely fast time delay counting unit are all used to measure the measured signal generated by the counting timing generation module corresponding to the pulse in the measured signal, and the low-speed clock counting module count value, the high-speed clock counting unit count value and the extremely fast time delay counting unit count value are respectively formed for the measured signal corresponding to each measured pulse, until the pulse measurement end mark arrives, or the number of pulses reaches a preset number threshold, the low-speed clock counting module, the high-speed clock counting unit and the extremely fast time delay counting unit all stop measuring the measured signal generated by the counting timing generation module corresponding to the remaining pulses in the measured signal, the low-speed clock counting module count value, the high-speed clock counting unit count value and the extremely fast time delay counting unit count value of the measured signal corresponding to each pulse form a count value group, the count value group enters the counting data cache module, the counting data cache module caches the count value group according to the entry order, and after the counting data cache module is full of data, the count value group that first enters the counting data cache module overflows, so that the count value group that enters the counting data cache module later is cached.

14. A span time measurement system, characterized in that: The span time measurement system comprises a clock multiplication module, a clock generation module, a signal source selection module, an integrated control module, a bus interface module and a span time measurement device according to any one of claims 1 to 13; The clock multiplication module is electrically connected to the low-frequency clock source and the clock generation module, and the clock multiplication module is used to multiply the low-speed clock signal generated by the low-frequency clock source to a clock signal of the highest frequency required by the span time measurement system, and send the clock signal of the highest frequency to the clock generation module, so that the clock generation module generates clock signals of various frequencies required by the span time measurement system; the integrated control module is electrically connected to the clock multiplication module, and the integrated control module is used to control the working configuration, operation or termination of the clock multiplication module; The clock generating module is electrically connected to the low-speed clock counting module and the counting timing generating module, and the clock generating module is used to generate and send corresponding clock signals to the low-speed clock counting module and the counting timing generating module, and is used to drive each module of the span time measuring device to operate; The information source selection module is electrically connected to the counting timing generation module. Under the control of the integrated control module, the information source selection module selects a signal from a corresponding source and sends it to the counting timing generation module. The bus interface module is electrically connected to the integrated control module, and the bus interface module is electrically connected to the device control module, the bus interface module is used to connect to the central operation module, and the central operation module is used to obtain the count value of the low-speed clock counting module, the count value of the high-speed clock counting unit and the count value of the extreme delay counting unit from the device control module to determine the span time; The integrated control module is electrically connected to the clock generation module, and the integrated control module is used to control the working configuration, operation or suspension of the clock generation module; The integrated control module is electrically connected to the information source selection module, and the integrated control module is used to control the working configuration, operation or termination of the information source selection module.

15. The span time measurement system according to claim 14, characterized in that: The span time measurement system also includes an interrupt control module, the integrated control module is electrically connected to the interrupt control module, and under the control of the integrated control module, the interrupt control module converts the interrupt signal generated by the device control module into an interrupt signal of a unified format, and sends the interrupt signal of the unified format to the central operation module.

16. The span time measurement system according to claim 15, characterized in that: The span time measurement system further comprises a central operation module, and the central operation module is electrically connected to the bus interface module or the interrupt control module.

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