Multi-mode monitoring and awakening circuit

Abstract

The invention discloses a multi-mode monitoring and awakening circuit. The circuit comprises monitoring circuit units and wake-up circuit units, if the monitoring circuit units monitor wake-up signals, the wake-up circuit units perform wake-up, the monitoring circuit units comprise at least two parallel monitoring circuit units used for monitoring different wake-up signals, and the output ends of the at least two monitoring circuit units are connected with the input end of the wake-up circuit unit in parallel. And when any monitoring circuit unit monitors the wake-up signal, the wake-up circuit unit performs wake-up. The multi-mode monitoring and wake-up circuit is provided with at least two monitoring circuit units, the wake-up circuit unit can perform wake-up as long as any monitoring circuit unit monitors the corresponding wake-up signal, and various different wake-up requirements in a complex environment can be met.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and in particular to a multi-mode monitoring and wake-up circuit. Background Art

[0002] In order to reduce energy consumption, many electronic devices are usually designed with a sleep mode, that is, they enter a sleep state when they do not need to work, reducing power consumption; accordingly, a wake-up circuit is set to automatically wake up the electronic device when it needs to work. The wake-up circuit monitors the wake-up signal in real time, and automatically wakes up the electronic device if a wake-up signal is detected. Existing wake-up circuits in the industry can usually only realize wake-up signal monitoring in a single scenario, and cannot meet different wake-up requirements in complex environments. Summary of the invention

[0003] The technical problem to be solved by the present invention is how to realize a wake-up circuit to meet a variety of different wake-up requirements.

[0004] In order to solve the above technical problems, the present invention provides a multi-mode monitoring and wake-up circuit, including a monitoring circuit unit and a wake-up circuit unit. If the monitoring circuit unit detects a wake-up signal, the wake-up circuit unit wakes up. The monitoring circuit unit includes at least two parallel units for monitoring different wake-up signals. The output ends of the at least two monitoring circuit units are connected in parallel to the input ends of the wake-up circuit units. If any one of the monitoring circuit units detects a wake-up signal, the wake-up circuit unit wakes up.

[0005] Furthermore, the monitoring circuit unit specifically includes three, namely: a first monitoring circuit unit for monitoring the wake-up signal whose voltage is higher than a preset low voltage threshold, a second monitoring circuit unit for monitoring the wake-up signal whose voltage is higher than a preset high voltage threshold, and a third monitoring circuit unit for monitoring the wake-up signal whose voltage is within a preset range.

[0006] Furthermore, the first monitoring circuit unit includes a first controlled switch NM2, a control end of which is connected to the first monitoring input end Vin, and the control end of the first controlled switch NM2 is turned on when receiving a wake-up signal whose voltage reaches a preset low voltage threshold, thereby waking up the wake-up circuit unit.

[0007] Furthermore, the second monitoring circuit unit includes a second controlled switch NM1 and a first voltage-dividing resistor R2, the control end of the second controlled switch NM1 is connected to the second monitoring input end Vin1 via the first voltage-dividing resistor R2, the junction between the control end of the second controlled switch NM1 and the first voltage-dividing resistor R2 is grounded via the second voltage-dividing resistor R3, and the control end of the second controlled switch NM1 is turned on when it receives a wake-up signal whose voltage reaches a preset high-voltage threshold, thereby waking up the wake-up circuit unit.

[0008] Furthermore, the second monitoring circuit unit includes a diode D0 for preventing the second controlled switch NM1 from being broken down by high voltage, and a control terminal of the second controlled switch NM1 is grounded via the diode D0.

[0009] Further, the third monitoring circuit unit includes a third controlled switch NM0 and a comparator comp, the control end of the third controlled switch NM0 is connected to the third monitoring input terminal Vin2 via the comparator comp, one input end of the comparator comp is connected to the third monitoring input terminal Vin2 and the other input end is connected to the reference voltage input terminal Vref, the control end of the third controlled switch NM0 is turned on when it receives a wake-up signal with a voltage higher than the reference voltage via the comparator comp, thereby waking up the wake-up circuit unit.

[0010] Furthermore, the input terminal of the comparator comp is specifically connected to the third monitoring input terminal Vin2 via the third voltage-dividing resistor R0 , and the junction between the input terminal of the comparator comp and the third voltage-dividing resistor R0 is grounded via the fourth voltage-dividing resistor R1 .

[0011] Furthermore, the wake-up circuit unit includes a current mirror circuit and a first power switch NM3. The control end of the first power switch NM3 is connected to the power input end Vb via the current mirror circuit. When the monitoring circuit detects the wake-up signal, the current mirror circuit of the wake-up circuit unit is turned on, thereby connecting the first power switch NM3 to the power input end Vb and outputting the voltage Vpre.

[0012] Further, wake up the circuit unit:

[0013] The second power switch NM4 includes a first power switch NM3 connected in series, the control end of the second power switch NM4 is connected to the current mirror circuit via a fifth voltage-dividing resistor R5, a junction between the control end of the second power switch NM4 and the fifth voltage-dividing resistor R5 is grounded via a sixth voltage-dividing resistor R6, and the first power switch NM3 outputs a voltage Vpre via the second power switch NM4;

[0014] And / or include a VGS protection circuit connected across the gate and source of the first power switch NM3.

[0015] Further, the wake-up circuit unit includes: a bandgap reference circuit connected between the gate and source of the first power switch NM3, and / or a VGS protection circuit connected between the gate and source of the first power switch NM3.

[0016] The multi-mode monitoring and wake-up circuit design of the present invention has at least two monitoring circuit units. As long as any monitoring circuit unit detects the corresponding wake-up signal, the wake-up circuit unit will wake up, which can meet a variety of different wake-up requirements in complex environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a structural block diagram of a multi-mode monitoring and wake-up circuit.

[0018] Figure 2 It is a circuit diagram of a first embodiment of a multi-mode monitoring and wake-up circuit.

[0019] Figure 3 It is a circuit diagram of a second embodiment of a multi-mode monitoring and wake-up circuit. DETAILED DESCRIPTION

[0020] The present invention is further described in detail below in conjunction with specific implementation methods.

[0021] Multi-mode monitoring and wake-up circuits such as Figure 1 As shown, it includes a monitoring circuit unit and a wake-up circuit unit 2. The monitoring circuit unit specifically includes three, namely: a first monitoring circuit unit 11 for monitoring a wake-up signal whose voltage is higher than a preset low voltage threshold, a second monitoring circuit unit 12 for monitoring a wake-up signal whose voltage is higher than a preset high voltage threshold, and a third monitoring circuit unit 13 for monitoring a wake-up signal whose voltage is within a preset range. The output ends of the three monitoring circuit units 11, 12, and 13 are connected in parallel to the input ends of the wake-up circuit unit. If any of the monitoring circuit units 11, 12, and 13 detects a wake-up signal, the wake-up circuit unit 2 wakes up. The specific circuit structure of the multi-mode monitoring and wake-up circuit is described in detail below through two embodiments.

[0022] Embodiment 1

[0023] like Figure 2As shown, the first monitoring circuit unit 11 includes a first controlled switch NM2. The control end (i.e., the G pole) of the first controlled switch NM2 is connected to the first monitoring input terminal Vin, the D pole is connected to the input terminal of the wake-up circuit 2 as the output end of the first monitoring unit 11, and the S pole is grounded through a resistor R4. The second monitoring circuit unit 12 includes a second controlled switch NM1 and a first voltage-dividing resistor R2. The control end (i.e., the G pole) of the second controlled switch NM1 is connected to the second monitoring input terminal Vin1 through the first voltage-dividing resistor R2, the junction between the G pole of the second controlled switch NM1 and the first voltage-dividing resistor R2 is grounded through the second voltage-dividing resistor R3, the D pole is connected to the input terminal of the wake-up circuit 2 as the output end of the second monitoring unit 12, and the S pole is grounded through a resistor R4. The first voltage-dividing resistor R2 and the second voltage-dividing resistor R3 form a voltage-dividing circuit, so that the voltage of the G pole of the second controlled switch NM1 is provided by the voltage signal of the second monitoring input terminal Vin1 after being divided by the first voltage-dividing resistor R2 and the second voltage-dividing resistor R3. The second monitoring circuit unit 12 includes a Zener diode D0, and the control end of the second controlled switch NM1 is grounded through the Zener diode D0. In this embodiment, the second controlled switch NM1 is protected by the Zener diode D0. When the high voltage is applied, the Zener diode D0 is turned on to release the current, so as to ensure the stability of the G pole voltage of the second controlled switch NM1 and prevent the second controlled switch NM1 from being broken down by the high voltage. The third monitoring circuit unit 13 includes a third controlled switch NM0 and a comparator comp. The control end (i.e., the G pole) of the third controlled switch NM0 is connected to the third monitoring input terminal Vin2 through the comparator comp. The positive input end of the comparator comp is connected to the third monitoring input terminal Vin2 and the negative input end is connected to the reference voltage input terminal Vref. The positive input end of the comparator comp is specifically connected to the third monitoring input terminal Vin2 through the third voltage-dividing resistor R0, the junction of the positive input end of the comparator comp and the third voltage-dividing resistor R0 is grounded through the fourth voltage-dividing resistor R1, and the output end of the comparator comp is connected to the G pole of the third controlled switch NM0. The D pole of the third controlled switch NM0 is connected to the input terminal of the wake-up circuit 2 as the output terminal of the third monitoring unit 13, and the S pole is grounded via the resistor R4. The third voltage-dividing resistor R0 and the fourth voltage-dividing resistor R1 form a voltage-dividing circuit, so that the voltage at the positive input terminal of the comparator comp is provided by the voltage signal of the third monitoring input terminal Vin2 after being divided by the third voltage-dividing resistor R0 and the fourth voltage-dividing resistor R1.

[0024] The wake-up circuit unit 2 includes a current mirror circuit 21 and a first power switch NM3. The current mirror circuit 21 includes a MOS transistor PM0 and a MOS transistor PM1 connected to each other. The control terminal (i.e., the G pole) of the first power switch NM3 is connected to the power input terminal Vb via the current mirror circuit 21. The wake-up circuit unit 2 includes a VGS protection circuit 23 connected between the gate (G pole) and the source (S pole) of the first power switch NM3. The VGS protection circuit 23 includes a MOS transistor PM2 and a MOS transistor PM3, the S pole of the MOS transistor PM2 is connected to the G pole of the first power switch NM3, the G pole of the MOS transistor PM2 is connected to the D pole thereof, the D pole of the MOS transistor PM2 is connected to the S pole of the MOS transistor PM3, the G pole of the MOS transistor PM3 is connected to the D pole thereof, and the D pole of the MOS transistor PM3 is connected to the S pole of the first power switch NM3. The MOS transistor PM2 and the MOS transistor PM3 perform VGS protection on the first power switch NM3 to prevent the VGS voltage of the first power switch NM3 from exceeding the safety limit, thereby protecting the MOS transistor from damage. The wake-up circuit unit 2 includes a second power switch NM4 connected in series with a first power switch NM3, and the S poles of the first power switch NM3 and the second power switch NM4 are both grounded via a capacitor C0. The control end (i.e., the G pole) of the second power switch NM4 is connected to the current mirror circuit 21 via a fifth voltage-dividing resistor R5, and the junction between the G pole of the second power switch NM4 and the fifth voltage-dividing resistor R5 is grounded via a sixth voltage-dividing resistor R6, and the D pole is connected to the S pole of the first power switch NM3, and the S pole serves as a Vpre voltage output end. The fifth voltage-dividing resistor R5 and the sixth voltage-dividing resistor R6 form a voltage-dividing circuit, and the G pole voltage of the second power switch NM4 is provided by the voltage signal of the power input terminal Vb flowing through PM1 after being divided by the fifth voltage-dividing resistor R5 and the sixth voltage-dividing resistor R6. The voltage-dividing resistors R5 and R6 are used to divide the voltage, so as to limit the voltage range of the G pole of the second power switch NM4, so that the voltage Vpre output by the second power switch NM4 is relatively stable.

[0025] The above multi-mode monitoring and wake-up circuit is applied to electronic devices. Each monitoring circuit unit 11, 12, 13 monitors the relevant voltage monitoring points of the electronic device, and wakes up the wake-up circuit unit 2 after detecting the corresponding wake-up signal. The voltage Vpre output by the wake-up circuit unit 2 supplies power to the relevant modules of the electronic device. Specifically:

[0026] The first monitoring circuit unit 11 is suitable for monitoring low-voltage signals. The first monitoring circuit unit 11 monitors the voltage of the first monitoring input terminal Vin in the electronic device through the first controlled switch NM2. The voltage signal input by the first monitoring input terminal Vin is a low-voltage signal. The voltage signal Vin input by the first monitoring input terminal Vin is the G pole voltage of the first controlled switch NM2. If the Vin voltage is higher than the preset low-voltage threshold Vth, that is, a wake-up signal with a voltage higher than the preset low-voltage threshold Vth is received, and the G pole voltage VGS of the first controlled switch NM2 is greater than Vth, then the first controlled switch NM2 starts to turn on, driving PM0 and PM1 to form a current mirror, that is, the current mirror circuit 21 is turned on, raising the G pole voltage of the first power switch NM3 and the G pole voltage of the second power switch NM4, so that the first power switch NM3 outputs the voltage Vpre through the S pole of the second power switch NM4, and supplies power to the relevant modules of the electronic device to wake up the electronic device. If the Vin voltage is lower than the preset low voltage threshold Vth, the G pole voltage VGS of the first controlled switch NM2 is less than Vth, the first controlled switch NM2 is not turned on, so that the current mirror circuit 21 is not turned on, and the first power switch NM3 and the second power switch NM4 are not turned on, so the voltage Vpre is not output, and the relevant modules of the electronic device are not powered and therefore are not awakened.

[0027] The second monitoring circuit unit 12 is suitable for monitoring high-voltage signals. The second monitoring circuit unit 12 monitors the voltage of the second monitoring input terminal Vin1 in the electronic device through the second controlled switch NM1. The voltage signal input to the second monitoring input terminal Vin1 is a high-voltage signal. The voltage signal Vin1 input to the second monitoring input terminal Vin1 is divided by the first voltage-dividing resistor R2 and the second voltage-dividing resistor R3, and then input to the G pole of the second controlled switch NM1. If the voltage of Vin1 increases, the voltage of the G pole of the second controlled switch NM1 also increases accordingly. If the voltage of Vin1 after being divided by the first voltage-dividing resistor R2 and the second voltage-dividing resistor R3 is higher than the preset high-voltage threshold, that is, a wake-up signal with a voltage higher than the preset high-voltage threshold is received, and the G-pole voltage of the second controlled switch NM1 is higher than the preset high-voltage threshold, the second controlled switch NM1 starts to turn on, driving PM0 and PM1 to form a current mirror, that is, the current mirror circuit 21 is turned on, raising the G-pole voltage of the first power switch NM3 and the G-pole voltage of the second power switch NM4, so that the first power switch NM3 outputs the voltage Vpre through the S-pole of the second power switch NM4, and supplies power to the relevant modules of the electronic device to wake up the electronic device.

[0028] The third monitoring circuit unit 13 is suitable for monitoring a voltage signal whose voltage value is in a certain voltage range. The third monitoring circuit unit 13 monitors the voltage of the third monitoring input terminal Vin2 in the electronic device through the comparator comp and the third controlled switch NM0. The voltage value of the voltage signal input by the third monitoring input terminal Vin2 is in a certain voltage range. The voltage signal (Vin2 voltage) input by the third monitoring input terminal Vin2 is input to the positive input terminal of the comparator comp after being divided by the third voltage-dividing resistor R0 and the fourth voltage-dividing resistor R1. The comparator comp compares the voltage after the voltage division of Vin2 with the reference voltage Vref. If the voltage after the voltage division of Vin2 is higher than the reference voltage Vref, that is, a wake-up signal that the voltage is within a preset range is detected, the voltage after the voltage division of Vin2 is allowed to flow through the comparator comp and input to the G pole of the third controlled switch NM0. The third controlled switch NM0 starts to turn on, driving PM0 and PM1 to form a current mirror, that is, the current mirror circuit 21 is turned on, raising the G pole voltage of the first power switch NM3 and the G pole voltage of the second power switch NM4, so that the first power switch NM3 outputs the voltage Vpre through the S pole of the second power switch NM4, and supplies power to the relevant modules of the electronic device to wake up the electronic device.

[0029] The multi-mode monitoring and wake-up circuit design of this embodiment has three monitoring circuit units. As long as any monitoring circuit unit detects the corresponding wake-up signal, the wake-up circuit unit will wake up, which can meet a variety of different wake-up requirements in complex environments.

[0030] Embodiment 2

[0031] like Figure 3 As shown, compared with the first embodiment, the monitoring circuit units 11, 12, and 13 of this embodiment have the same structure, and only the structure of the awakening circuit unit 2 is different. The following only describes the specific structure of the awakening circuit unit 2, and the specific structure of the monitoring circuit units 11, 12, and 13 can refer to the first embodiment above.

[0032] like Figure 3As shown, the wake-up circuit unit 2 includes a current mirror circuit 21 and a first power switch NM3. The current mirror circuit 21 includes a MOS transistor PM0 and a MOS transistor PM1 connected to each other. The control terminal (i.e., the G pole) of the first power switch NM3 is connected to the power input terminal Vb via the current mirror circuit 21. The wake-up circuit unit 2 includes a VGS protection circuit 23 connected across the gate (G pole) and the source (S pole) of the first power switch NM3. The VGS protection circuit 23 includes a MOS transistor NM4 and a MOS transistor NM5. The D pole of the MOS transistor NM4 is connected to the G pole of the first power switch NM3, the G pole of the MOS transistor NM4 is connected across its D pole, the S pole of the MOS transistor NM4 is connected to the D pole of the MOS transistor NM5, the G pole of the MOS transistor NM5 is connected across its D pole, and the S pole of the MOS transistor NM5 is connected to the S pole of the first power switch NM3. MOS tube NM4 and MOS tube NM5 perform VGS protection on the first power switch NM3 to prevent the VGS voltage of the first power switch NM3 from exceeding the safety limit, thereby protecting the MOS tube from damage. The wake-up circuit unit 2 of the first embodiment connects the second power switch NM4 in series on the basis of the first power switch NM3 and uses the voltage-dividing resistors R5 and R6 to keep the output voltage Vpre stable. Although the second power switch NM4 and the voltage-dividing resistors R5 and R6 can maintain the output voltage Vpre temperature to a certain extent, the G-pole voltage of the second power switch NM4 is affected by the resistance voltage division, resulting in the output voltage Vpre having a temperature coefficient, which will affect the working stability of the relevant modules of the electronic device. Therefore, this embodiment adopts a bandgap reference circuit 22 to replace the second power switch NM4 and the voltage-dividing resistors R5 and R6 of the first embodiment, and the bandgap reference circuit 22 is connected across the G pole and the S pole of the first power switch NM3. Figure 3 As shown, the bandgap reference circuit 22 includes transistors Q0, Q1, Q2, Q3 and resistors R5, R6, R7, and R8. The transistors Q0 and Q3 are connected in series, the base of the transistor Q3 is connected across its collector, the emitter of the transistor Q3 is grounded, the bases of the transistors Q1 and Q2 are connected to each other, the emitters of the transistors Q3 and Q2 are connected to the emitter of the transistor Q1 through the resistor R8, the collector of the transistor Q1 is connected to the collector of the transistor Q2 through the resistors R6 and R7, the base of the transistor Q2 is connected across its collector, the base of the transistor Q0 is connected to the collector of the transistor Q1, the junction of the resistors R6 and R7 is connected to the S pole of the first power switch NM3 through the resistor R5, and the collector of the transistor Q0 is connected to the G pole of the first power switch NM3. The principle of the bandgap reference circuit is to use the sum of a voltage with a positive temperature coefficient and a voltage with a negative temperature coefficient. The temperature coefficients of the two cancel each other out to achieve a voltage reference that is independent of temperature. In this embodiment, when the current mirror circuit 21 of the wake-up circuit unit 2 is turned on, the current flowing through the resistor R8 is I1, and the current flowing through the resistor R7 is I2. The voltage V output by the wake-up circuit is PRE=VBG+(I1+I2)R5, where VBG=2VBE+I1*R6, I1=ΔVBE / R8, I2=(VBG-VBE) / R7. Due to the temperature characteristics of the bipolar transistor (BJT), VBE is proportional to the absolute temperature and exhibits a negative temperature coefficient, while ΔVBE is proportional to the absolute temperature and exhibits a positive temperature coefficient. The voltage V with a positive temperature coefficient R6 (i.e. I1*R6) and the negative temperature coefficient voltage 2VBE are superimposed to obtain a zero temperature coefficient voltage VBG. The current I1 has a positive temperature coefficient, and the current I2 also has a positive temperature coefficient. Therefore, in this embodiment, a resistor R5 with a negative temperature coefficient is selected so that the temperature coefficients of the currents I1 and I2 and the resistor R are offset. That is, the voltage obtained by (I1+I2)R5 is a voltage with a zero temperature coefficient. Therefore, the zero temperature coefficient voltage VBG is superimposed on the zero temperature coefficient (I1+I2)R5 to obtain a zero temperature coefficient V PRE It can be seen that after the bandgap reference circuit is introduced, the first power switch NM3 outputs a voltage V with a zero temperature coefficient. PRE , ensuring that the relevant modules of electronic equipment can work stably.

[0033] The above is only an implementation method of the invention, and does not limit the scope of patent protection. Those skilled in the art can make non-substantial changes or substitutions based on the invention, which still fall within the scope of patent protection.

Claims

1. A multi-mode monitoring and wake-up circuit, comprising a monitoring circuit unit and a wake-up circuit unit (2), wherein if the monitoring circuit unit detects a wake-up signal, the wake-up circuit unit (2) performs wake-up, wherein: The monitoring circuit unit comprises at least two parallel monitoring circuits for monitoring different wake-up signals. The output ends of the at least two monitoring circuit units are connected in parallel to the input end of the wake-up circuit unit. When any one of the monitoring circuit units detects a wake-up signal, the wake-up circuit unit (2) wakes up.

2. The multi-mode monitoring and wake-up circuit as claimed in claim 1, characterized in that: The monitoring circuit units specifically include three, namely: a first monitoring circuit unit (11) for monitoring a wake-up signal whose voltage is higher than a preset low voltage threshold, a second monitoring circuit unit (12) for monitoring a wake-up signal whose voltage is higher than a preset high voltage threshold, and a third monitoring circuit unit (13) for monitoring a wake-up signal whose voltage is within a preset range.

3. The multi-mode monitoring and wake-up circuit as claimed in claim 2, characterized in that: The first monitoring circuit unit (11) comprises a first controlled switch NM2, the control end of the first controlled switch NM2 is connected to the first monitoring input end Vin, and the control end of the first controlled switch NM2 is turned on when receiving a wake-up signal whose voltage reaches a preset low voltage threshold, thereby waking up the wake-up circuit unit (2).

4. The multi-mode monitoring and wake-up circuit as claimed in claim 2, characterized in that: The second monitoring circuit unit (12) comprises a second controlled switch NM1 and a first voltage-dividing resistor R2, wherein the control end of the second controlled switch NM1 is connected to the second monitoring input end Vin1 via the first voltage-dividing resistor R2, and the junction between the control end of the second controlled switch NM1 and the first voltage-dividing resistor R2 is grounded via the second voltage-dividing resistor R3. When the control end of the second controlled switch NM1 receives a wake-up signal whose voltage reaches a preset high-voltage threshold, the control end is turned on, thereby waking up the wake-up circuit unit (2).

5. The multi-mode monitoring and wake-up circuit as claimed in claim 4, characterized in that: The second monitoring circuit unit (12) comprises a diode D0 for preventing the second controlled switch NM1 from being broken down by high voltage, and the control end of the second controlled switch NM1 is grounded via the diode D0.

6. The multi-mode monitoring and wake-up circuit as claimed in claim 2, characterized in that: The third monitoring circuit unit (13) comprises a third controlled switch NM0 and a comparator comp, wherein a control terminal of the third controlled switch NM0 is connected to a third monitoring input terminal Vin2 via the comparator comp, one input terminal of the comparator comp is connected to the third monitoring input terminal Vin2 and the other input terminal is connected to a reference voltage input terminal Vref, and the control terminal of the third controlled switch NM0 is turned on when receiving a wake-up signal having a voltage higher than the reference voltage via the comparator comp, thereby waking up the wake-up circuit unit (2).

7. The multi-mode monitoring and wake-up circuit as claimed in claim 6, characterized in that: The input terminal of the comparator comp is specifically connected to the third monitoring input terminal Vin2 via the third voltage-dividing resistor R0 , and a junction between the input terminal of the comparator comp and the third voltage-dividing resistor R0 is grounded via the fourth voltage-dividing resistor R1 .

8. The multi-mode monitoring and wake-up circuit as claimed in claim 1, characterized in that: The wake-up circuit unit (2) comprises a current mirror circuit (21) and a first power switch NM3. The control end of the first power switch NM3 is connected to a power input end Vb via the current mirror circuit (21). When the monitoring circuit detects a wake-up signal, the current mirror circuit of the wake-up circuit unit (2) is turned on, thereby connecting the first power switch NM3 to the power input end Vb and outputting a voltage Vpre.

9. The multi-mode monitoring and wake-up circuit as claimed in claim 8, characterized in that: Wake-up circuit unit (2): It comprises a second power switch NM4 connected in series with a first power switch NM3, the control end of the second power switch NM4 is connected to a current mirror circuit (21) via a fifth voltage-dividing resistor R5, a junction between the control end of the second power switch NM4 and the fifth voltage-dividing resistor R5 is grounded via a sixth voltage-dividing resistor R6, and the first power switch NM3 outputs a voltage Vpre via the second power switch NM4; And / or includes a VGS protection circuit (23) connected across the gate and source of the first power switch NM3.

10. The multi-mode monitoring and wake-up circuit as claimed in claim 8, characterized in that: The wake-up circuit unit (2) comprises: a bandgap reference circuit (22) connected across the gate and source of the first power switch NM3, and / or a VGS protection circuit (23) connected across the gate and source of the first power switch NM3.

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