Low-power-consumption interrupt processing method and electronic equipment thereof

Abstract

The invention provides a low-power-consumption interrupt processing method and electronic equipment thereof. The low-power-consumption interrupt processing method comprises the following steps: running an ultra-low-power-consumption framework by a coprocessor; wherein the ultra-low power consumption framework comprises an interrupt alignment and activity group, a memory prediction monitor and a task dynamic migration monitor; aligning a plurality of interrupts through the interrupt alignment and active group such that the coprocessor is waken up based on the aligned interrupts to perform all expired low power functions, and the application processor is waken up in alignment based on the wakeup of the coprocessor; running the memory prediction monitor to predict the next time point when the memory access monitor and the memory protection unit access the global memory, and determining whether to close the global memory through the memory access monitor; and selecting one of the global memory or the local memory for access by the task dynamic migration monitor according to the task load and the operation frequency.

Description

Technical Field

[0001] The present invention generally relates to an electronic device, and in particular to an electronic device with an ultra-low power consumption framework and an interrupt and task processing method. Background Art

[0002] A coprocessor in the always-on domain may take over the system's low-power functions, such as voice wake-up monitoring, location tracking, motion detection, cameras, etc. As the first wake-up source, the always-on coprocessor can respond to various user behaviors with extremely low power consumption. The coprocessor handles the decision of whether to wake up the application processor to notify the application to continue subsequent processing. In most cases, the coprocessor can handle many wake-up operations without notifying the application processor, thereby reducing power consumption.

[0003] An external interrupt or timer interrupt method is usually used to wake up the coprocessor from an idle state to an active state. After the coprocessor wakes up, in the interrupt service routine, it wakes up the corresponding task to perform subsequent sampling and low-power functions. However, waking up the coprocessor discretely causes the coprocessor to be woken up frequently, thereby increasing power consumption.

[0004] If the coprocessor determines that the application processor needs to be awakened, the application processor will also be discretely activated for subsequent operations, thereby increasing the power consumption of the application processor. Summary of the invention

[0005] The content disclosed below is only exemplary and is not meant to be limited in any way. In addition to the illustrative aspects, embodiments and features, other aspects, embodiments and features will also be apparent by reference to the accompanying drawings and the following detailed description. That is, the content disclosed below is provided to introduce concepts, key points, benefits and novel and non-obvious technical advantages described herein. Optional but not all, the embodiments will be further described in detail as follows. Therefore, the content disclosed below is not intended to be a necessary feature of the claimed subject matter, nor is it intended to be used in determining the scope of the claimed subject matter.

[0006] One embodiment of the present invention provides an electronic device with an ultra-low power framework. The electronic device with the ultra-low power framework further includes a coprocessor, an application processor, a memory protection unit, a memory access monitor, a local memory, and multiple global memories. The coprocessor runs the ultra-low power framework. The ultra-low power framework includes interrupt alignment and activity groups, a memory prediction monitor, and a task dynamic migration monitor. Interrupt alignment and activity groups are executed by the coprocessor. Interrupt alignment and activity groups align multiple interrupts so that the coprocessor is awakened based on the aligned interrupts to execute all expired low-power functions, and the application processor is awakened based on the awakening of the coprocessor. The memory prediction monitor is executed by the memory protection unit and the memory access monitor. The memory prediction monitor predicts the next time point to access the global memory, and determines whether to close the global memory through the memory access monitor. The task dynamic migration monitor is executed by the coprocessor. The task dynamic migration monitor selects a global memory or a local memory to access according to the task load and the operating frequency.

[0007] According to the electronic device, when the coprocessor accesses the global memory for the first time, the memory protection unit sends an interrupt to the coprocessor to open the global memory. When the coprocessor does not access the global memory within a predetermined time, the memory access monitor is electrically connected to the memory protection unit and sends an interrupt to the coprocessor to close the global memory.

[0008] The electronic device further includes an interrupt controller which is electrically connected between the memory access monitor and the coprocessor and bypasses an interrupt from the memory protection unit or the memory access monitor to the coprocessor.

[0009] According to the above electronic device, the global memory includes a dynamic random-access memory (DRAM) and a global static random access memory (SRAM).

[0010] According to the above electronic device, the local memory includes a local static random-access memory (SRAM for short).

[0011] According to the above electronic device, the interruption includes an external interruption and a timer interruption.

[0012] According to the electronic device, the coprocessor generates a timer wheel by classifying the timer interrupts into a plurality of timer vectors according to the triggering frequency, thereby aligning the timer interrupts from the heartbeat timer. The timer wheel includes timer vectors corresponding to different triggering frequencies in sequence. The coprocessor further aligns the plurality of interrupts by selecting the most recently expired timer vector, triggering an interrupt in the timer vector to execute a corresponding task, and triggering an interrupt in a subsequent timer vector in the timer wheel.

[0013] According to the above electronic device, the coprocessor generates a timer wheel by aligning the external interrupt from the inertial processing unit into the timer vector according to the triggering frequency of the timer interrupt and the external interrupt.

[0014] According to the electronic device, the coprocessor calibrates the trigger frequency of the external interrupt in the timer vector by reducing noise, thereby aligning the plurality of interrupts.

[0015] According to the above electronic device, the noise includes white noise, temperature drift, other interrupts with different trigger frequencies, and interrupt processing errors from the inertial processing unit.

[0016] According to the electronic device, the coprocessor uses a local statistical filter or a Kalman filter to reduce noise.

[0017] According to the electronic device, the memory access monitor includes a timeout counter. When the memory access monitor determines through the memory protection unit that there is an access to the global memory, the memory access monitor resets the count value of the timeout counter.

[0018] According to the above electronic device, when the memory access monitor determines through the memory protection unit that there is no access to the global memory, the memory access monitor reduces the count value of the timeout counter by one.

[0019] According to the above electronic device, when the count value of the timeout counter is equal to zero, the memory access monitor sends an interrupt to the coprocessor to close the global memory.

[0020] According to the electronic device, when the memory protection unit determines that the coprocessor accesses the global memory for the first time, the coprocessor turns on the memory access monitor.

[0021] According to the above electronic device, after the memory access monitor sends an interrupt to the coprocessor to shut down the global memory, the coprocessor shuts down the memory access monitor.

[0022] According to the electronic device, the memory access monitor includes a state machine. When the memory protection unit determines that the coprocessor accesses the global memory for the first time, the coprocessor sets the state machine to an enabled state so that the memory access monitor is turned on.

[0023] According to the above electronic device, after the memory access monitor sends an interrupt to the coprocessor to shut down the global memory, the coprocessor sets the state machine to a disabled state so that the memory access monitor is shut down.

[0024] According to the electronic device, when the coprocessor accesses the global memory for the first time, the memory protection unit sends an interrupt to the coprocessor to open the global memory. When the coprocessor does not access the global memory within a predetermined time, the memory access monitor sends an interrupt to the coprocessor to close the global memory.

[0025] An embodiment of the present invention also provides a low-power interrupt processing method. The method is applied to an electronic device having a local memory, a global memory, a coprocessor, a memory access monitor, and a memory protection monitor. The method includes the following steps. The ultra-low power framework is run by the coprocessor. The ultra-low power framework includes interrupt alignment and activity groups, a memory prediction monitor, and a task dynamic migration monitor. The interrupt alignment and activity groups align multiple interrupts so that the coprocessor is awakened based on the aligned interrupts to execute all expired low-power functions, and the application processor is awakened based on the wake-up of the coprocessor. The memory prediction monitor runs to predict the next time point when the memory access monitor and the memory protection unit access the global memory, and determines whether to shut down the global memory through the memory access monitor. The task dynamic migration monitor selects a global memory or a local memory for access based on the task load and the operating frequency. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are included in the content of the present invention to provide a further understanding of the content of the present invention and constitute a part of the content of the present invention. The accompanying drawings show embodiments of the content of the present invention and, together with the description, are used to explain the principles of the content of the present invention. It should be understood that the drawings are not necessarily drawn to scale. Due to the need to clearly illustrate the concepts of the content of the present invention, some components may be displayed out of proportion to the size in actual implementation.

[0027] Figure 1 A schematic diagram of an electronic device 110 is shown in accordance with some embodiments of the present invention.

[0028] Figure 2 A schematic diagram of a normally-on domain 130, a global static random access memory (SRAM) 146, and a dynamic random access memory (DRAM) 148 in an electronic device 110 is shown according to some embodiments of the present invention.

[0029] Figure 3 The embodiment of the present invention is shown Figure 1 FIG. 1 is a schematic diagram of a low power timer 300 and an inertial processing unit 302 in the coprocessor 100 .

[0030] Figure 4 A schematic diagram of interrupts from a low power timer 300 and an inertial processing unit 302 is shown according to an embodiment of the present invention.

[0031] Figures 5A-5D A schematic diagram showing noise in an interrupt according to an embodiment of the present invention is shown.

[0032] Fig. 6A The embodiment of the present invention is shown Figure 1 Schematic diagram of the memory access monitor 102 in FIG.

[0033] Figure 6B The embodiment of the present invention is shown Fig. 6A Schematic diagram of state machine 602 in .

[0034] Figure 7 The embodiment of the present invention is shown. Figure 1 146 or DRAM 148 according to an interrupt.

[0035] Figure 8 The embodiment of the present invention is shown. Figure 1 FIG. 1 is a schematic diagram of the operation of the coprocessor 100 in FIG. ... predicts the next time point when the global SRAM 146 or DRAM 148 is enabled according to an interrupt.

[0036] Fig. 9 FIG. 1 is a schematic diagram showing an operation of selectively accessing the local SRAM 108 , the global SRAM 146 , or the DRAM 148 according to a task load and an operating frequency according to an embodiment of the present invention.

[0037] Fig.10 The embodiment of the present invention is shown Figure 1 Schematic diagram of the normally-on domain 130, SRAM 146 and DRAM 148 in the electronic device 110 in FIG.

[0038] Fig.11 A flow chart of a low power interrupt processing method according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0039] Certain words are used in the specification and claims to refer to specific components. It should be understood by those skilled in the art that hardware manufacturers may use different terms to refer to the same component. This specification and claims do not use differences in names as a way to distinguish components, but rather use differences in the functions of the components as the criteria for distinction. The term "including" mentioned throughout the specification and claims is an open-ended term and should be interpreted as "including but not limited to". In addition, the term "coupled" herein includes any direct and indirect means of electrical connection. Therefore, if the text describes a first device coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices or connection means.

[0040] The following description is intended to illustrate the general principles of the invention and is not to be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

[0041] The following description is intended to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications to the embodiments and general principles and features described herein will be apparent to those skilled in the art. Therefore, the present invention is not intended to be limited to the embodiments shown, but rather to the widest scope consistent with the principles and features described herein.

[0042] Figure 1 1 shows a schematic diagram of an electronic device 110 according to an embodiment of the present invention. Figure 1 As shown, the electronic device 110 includes a system-on-chip (SoC) 150, a DRAM 148, an audio device 152, a location information device 154, a camera 156, and a sensor 158. In some embodiments, the electronic device 110 may be a tablet, a laptop, a smart phone, or a wearable device, but the present invention is not limited thereto. The SoC 150 includes an application processor 140 having a plurality of central processing units, for example, CPU0, CPU1, and CPU2. The SoC 150 also includes a global bus 142, a DRAM controller 144, a global SRAM 146, and a normally open domain 130. In some embodiments, the application processor 140 is electrically connected to the global bus 142. The global bus 142 is electrically connected to the DRAM controller 144, the global SRAM 146, the audio device 152, the location information device 154, the camera 156, and the sensor 158. The DRAM controller 144 is electrically connected to the DRAM 148.

[0043] In the always-on domain 130 of the SoC 150, the electronic device 110 includes a coprocessor 100, a memory access monitor 102, a memory protection unit 104, a local SRAM 108, and a local bus 112. The coprocessor 100 is electrically connected to the local bus 112. The local bus 112 is electrically connected to the global bus 142, the memory access monitor 102, the memory protection unit 104, and the local SRAM 108. In some embodiments, the coprocessor 100 executes audio software 114 to handle interrupts of an audio device 152. The coprocessor 100 executes location information software 116 to handle interrupts of a location information device 154. The coprocessor 100 executes camera software 118 to handle interrupts of a camera 156. The coprocessor 100 executes sensor software 122 to handle interrupts of a sensor 158. The coprocessor 100 also executes other software 124 to handle interrupts of other devices.

[0044] In some embodiments, the coprocessor 100 runs an ultra-low power framework 120. The ultra-low power framework 120 includes interrupt alignment and activity groups, a memory prediction monitor, and a task dynamic migration monitor. The interrupt alignment and activity groups align multiple interrupts so that the coprocessor 100 is awakened based on the aligned interrupts to execute all expired low power functions, and the application processor 140 is awakened based on the wakeup of the coprocessor 100. The memory protection unit 104 and the memory access monitor 102 run the memory prediction monitor to predict the next time point when the global SRAM 146 or DRAM 148 is accessed, and determine whether to shut down the global SRAM 146 or DRAM 148 through the memory access monitor 102. The task dynamic migration monitor selects to access one of the global SRAM 146, DRAM 148, or local SRAM 108 according to the load and operating frequency of the task executed by the coprocessor 100. The memory access monitor 102 is electrically connected to the global SRAM 146, DRAM 148, and the coprocessor 100. When the global SRAM 146 or DRAM 148 is accessed for the first time, the memory protection unit 104 sends an interrupt to the coprocessor 100. The memory access monitor 102 also sends an interrupt to the coprocessor 100 when the global SRAM 146 or DRAM 148 is not accessed for a predetermined period of time.

[0045] In some embodiments, the coprocessor 100 aligns external interrupts and timer interrupts to avoid frequent wake-up of the coprocessor 100. The coprocessor 100 can execute all expired low-power functions at one time, so the present invention can reserve more idle time or sleep time for the coprocessor 100 to save power consumption. At the same time, the present invention can also wake up the application processor 140 in an aligned manner. In some embodiments, the coprocessor 100 predicts the next usage time of the global SRAM 146 and DRAM 148, and determines whether to turn off the global SRAM 146 or DRAM 148 according to the ultra-low power framework through the memory access monitor 102 to save power consumption. In some embodiments, the coprocessor 100 selects to access one of the global SRAM 146, DRAM 148 or local SRAM 108 according to the task load and operating frequency to optimize power consumption.

[0046] Figure 2 The embodiment of the present invention is shown Figure 1 Schematic diagram of the normally-on domain 130, the global static random access memory (SRAM) 146 and the dynamic random access memory (DRAM) 148 in the electronic device 110 in FIG. Figure 2 As shown, the always-on domain 130 includes the coprocessor 100, the memory access monitor 102, the memory protection unit 104, the local SRAM 108, the global SRAM 146, the DRAM 148, the interrupt controller 200, the L1 instruction cache 202, the L1 data cache 204, and the L2 cache 206. The L1 instruction cache 202 and the L1 data cache 204 are electrically connected between the coprocessor 100 and the L2 cache 206. The L2 cache is electrically connected to the local SRAM 108, the global SRAM 146, and the DRAM 148. In some embodiments, when the coprocessor 100 accesses the global SRAM 146 or the DRAM 148 for the first time, the memory protection unit 104 sends an interrupt to the coprocessor 100 through the interrupt controller 200 to turn on the global SRAM 146 or the DRAM 148. In some embodiments, when the coprocessor 100 does not access the global SRAM 146 or the DRAM 148 within a predetermined period of time, the memory access monitor 102 sends an interrupt to the coprocessor 100 through the interrupt controller 200 to shut down the global SRAM 146 or the DRAM 148. The interrupt controller 200 is electrically connected between the memory access monitor 102 and the coprocessor 100. The interrupt controller 200 bypasses the interrupt from the memory protection unit 104 or the memory access monitor 102 to the coprocessor 100.

[0047] Figure 3 The embodiment of the present invention is shown Figure 1Schematic diagram of a low power timer 300 and an inertial processing unit 302 in a coprocessor 100 in FIG. The interrupts include external interrupts and timer interrupts. In some embodiments, the audio software 114, the location information software 116, the camera software 118, and the sensor software 122 generate timer interrupts, and the timer interrupts are received by the coprocessor 100. The inertial processing unit 302 generates external interrupts, and the external interrupts are received by the coprocessor 100. In some embodiments, the coprocessor 100 classifies interrupts (including external interrupts and timer interrupts) into multiple timer vectors according to the triggering frequency of the interrupts to generate a timer wheel 304. The timer wheel 304 includes timer vectors corresponding to different triggering frequencies in sequence. For example, as Figure 3 As shown, timer vector 310 may correspond to a trigger frequency of 200 Hz. Timer vector 312 may correspond to a trigger frequency of 100 Hz. Timer vector 314 may correspond to a trigger frequency of 50 Hz. Timer vector 316 may correspond to a trigger frequency of 40 Hz. Timer vector 318 may correspond to a trigger frequency of 20 Hz. Timer vector 320 may correspond to a trigger frequency of 10 Hz. Timer vector 322 may correspond to a trigger frequency of 5 Hz.

[0048] like Figure 3 As shown, timer vector 310 may include an interrupt from low power timer 332 and an interrupt from low power timer 334. Timer vector 314 may include an interrupt from low power timer 336 and an interrupt from low power timer 338. Timer vector 318 may include an interrupt from low power timer 340 and an interrupt from low power timer 342. In some embodiments, low power timers 332, 334, 336, 338, 340, and 342 may be configured by audio software 114, location information software 116, camera software 118, and sensor software 122. Figure 3 An index array 306 is also shown to represent the timer vectors 310 , 312 , 314 , 316 , 318 , 320 , and 322 . Figure 3 A list array 308 is also shown to represent low power timers 332 , 334 , 336 , 338 , 340 , and 342 .

[0049] Afterwards, the coprocessor 100 selects the latest one of the timer vectors 310, 312, 314, 316, 318, 320, or 322. The coprocessor 100 triggers an interrupt in the timer vector 310, 312, 314, 316, 318, 320, or 322 to execute the corresponding task. The coprocessor 100 triggers an interrupt in a subsequent timer vector in the timer wheel 304. For example, it is assumed that there are users in the timer vector 310 and the timer vector 314. For example, at 10 milliseconds, the timer vectors 310 and 314 are triggered. At 15 milliseconds, the timer vector 310 is triggered. At 20 milliseconds, the timer vector 310 is triggered. At 25 milliseconds, the timer vector 310 is triggered. At 30 milliseconds, the timer vectors 310 and 314 are triggered. The trigger source for triggering the timer wheel 304 may be a heartbeat timer or the inertia processing unit 302. Assume that the operating frequency of the inertial processing unit is 200 Hz, and there is a user of the low power timer 332 in the timer vector 310. There is a user of the low power timer 336 in the timer vector 314. Since 200 Hz is an integer multiple of the trigger frequency of the timer vectors 310 and 314, the heartbeat timer or the inertial processing unit 302 is switched to the inertial processing unit 302 as the trigger source. For example, at 10 milliseconds, the inertial processing unit 302, the timer vector 310, and the timer vector 314 are triggered. At 15 milliseconds, the inertial processing unit and the timer vector 310 are triggered. At 20 milliseconds, the inertial processing unit 302 and the timer vector 310 are triggered. At 25 milliseconds, the inertial processing unit 302 and the timer vector 310 are triggered. At 30 milliseconds, the inertial processing unit 302, the timer vector 310, and the timer vector 314 are triggered. Therefore, the coprocessor 100 is awakened to perform the expired low power function. That is, the interrupts of the audio software 114 , the position information software 116 , the camera software 118 , the sensor software 122 , and the inertial processing unit 302 are aligned.

[0050] Figure 4 FIG. 3 shows a schematic diagram of the interruption of the low power consumption timer 300 and the inertia processing unit 302 according to an embodiment of the present invention. Figure 4 As shown, frequency y(n) is the trigger frequency of the interrupt of the inertial processing unit 302 at the current time point. Frequency y(n-1) is the trigger frequency of the interrupt of the inertial processing unit 302 at the previous time point. Frequency x(n) is the trigger frequency of the interrupt of the low power timer 300 at the current time point. Frequency x(n-1) is the trigger frequency of the interrupt of the low power timer 300 at the previous time point. Frequency z(n) is the error frequency between frequency y(n) and frequency x(n-1). Figure 4 As shown, frequency x(n), frequency x(n-1), frequency y(n) and frequency y(n-1) can be close to 50 Hz.

[0051] Specifically, the coprocessor 100 executes the ultra low power framework 120 to generate an observer equation, a state equation, and an error analysis equation, and calibrates the frequency of the inertial processing unit 302 using the observer equation, the state equation, and the error analysis equation.

[0052] The observer equation is shown below.

[0053] X(n)=[x(n)y(n)z(n)] T

[0054] E(n)=X(n)-X(n-1)

[0055] E(0)=[ΔTΔT0] T

[0056]

[0057] X(n) is a matrix whose elements consist of frequency x(n), frequency y(n), and frequency z(n). E(n) is an error matrix obtained by the difference between matrix X(n) and matrix X(n-1). ΔT is a user-defined predetermined period, for example, 0.02 seconds ( Figure 4 50Hz in the video).

[0058] The state equation is shown below.

[0059] x(n)=x(n-1)+y(n)-y(n-1)

[0060] y(n)=y(n-1)+T(t)

[0061] z(n)=y(n)-x(n-1)

[0062] T(t) is the actual trigger period of the interruption of the inertial processing unit 302 .

[0063] The error analysis equation is shown below.

[0064] T(t)=AT+α(t)+B(t)+y(t)+δ(t)

[0065] α(t) is white noise. β(t) is temperature drift. γ(t) is other interrupts from the inertial processing unit 302 with different trigger frequencies. δ(t) is the interrupt handling error of the coprocessor 100.

[0066] Figures 5A-5D A schematic diagram of interrupt noise according to an embodiment of the present invention is shown. Figure 5AWhite noise α(t) and temperature drift β(t) are shown. In some embodiments, white noise α(t) is determined by the hardware structure of the inertial processing unit 302. White noise α(t) and temperature drift β(t) can be reduced by algorithms. Figure 5B Other interrupts γ(t) with different trigger frequencies from the inertial processing unit 302 are shown. In some embodiments, the other interrupts γ(t) may include a data ready interrupt (DRI), but the invention is not limited thereto. Figure 5C An example of an interrupt handling error δ(t) is shown. After the coprocessor receives a data ready interrupt (DRI), the coprocessor 100 may delay processing for a period of time. The delay time may be equal to ISR-DRI. An example of an interrupt handling error δ(t) may be eliminated by a hardware latch. Figure 5D Another example of an interrupt handling error δ(t) is shown. The coprocessor 100 turns off interrupts for a long time, resulting in the loss of an interrupt from the inertial processing unit 302. This error can be eliminated by the algorithm.

[0067] In some embodiments, the coprocessor 100 uses a local statistical filter or a Kalman filter to reduce noise. For example, when the coprocessor 100 eliminates noise through a local statistical filter, the coprocessor 100 executes the ultra-low power framework 120 to generate state equations, bounds on absolute error equations, local statistical filters, and prediction equations.

[0068] The state equation is shown below.

[0069] y(n)=y(n-1)+AT(n-1)

[0070] AT(n)=y(n)-y(n-1)

[0071] Frequency y(n) is the trigger frequency of interrupts from the inertial processing unit 302 at the current time point. Frequency y(n-1) is the trigger frequency of interrupts from the inertial processing unit 302 at the previous time point. Frequency error ΔT(n) is the frequency difference between frequency y(n) and frequency y(n-1).

[0072] The bounds on the absolute error equation are given below.

[0073]

[0074] The local statistical filter is shown below.

[0075]

[0076] The prediction equation is shown below.

[0077]

[0078] In some embodiments, the coprocessor 100 calculates the average trigger frequency by using the bounds of the absolute error equation and a local statistical filter and average trigger frequency The average frequency error between The coprocessor 100 eliminates other interrupts γ(t) and interrupt processing errors δ(t) through the bounds of the absolute error equation, and eliminates white noise a(t) and temperature drift β(t) through a local statistical filter. Afterwards, the coprocessor 100 predicts the trigger frequency x(n) of the interrupt from the low power timer 300 at the next time point to enable the local SRAM 146 or DRAM 148 according to the interrupt.

[0079] When the coprocessor 100 reduces noise through the Kalman filter, the coprocessor 100 executes the ultra low power framework 120 to generate a state equation, a Kalman filter, and a prediction equation.

[0080] The state equation is shown below.

[0081] y(n)=y(n-1)+ΔT(n-1)+Q γ

[0082] ΔT(n)=ΔT(n-1)+Q ΔT

[0083] z(n)=y(n)+R

[0084]

[0085] Z n =HX n +R,(Z n =[z] n , H = [1 0])

[0086] The Kalman filter is shown below.

[0087]

[0088] The prediction equation is shown below.

[0089] x(n)=x(n-1)+ΔT(n)

[0090] The coprocessor 100 modifies the matrix Q and the matrix R to calculate the average frequency error ΔT(n). After obtaining the average frequency error ΔT(n), the coprocessor 100 predicts the interrupt trigger frequency x(n) of the low power timer 300 at the next time point according to the interrupt to enable the local SRAM 146 or DRAM 148.

[0091] Fig. 6A The embodiment of the present invention is shown Figure 1 Schematic diagram of the memory access monitor 102 in FIG. Figure 6B The embodiment of the present invention is shown Fig. 6A Schematic diagram of state machine 602. Fig. 6A and 6B As shown, the memory access monitor 102 includes a timeout counter 600 and a state machine 602. When the memory protection unit 104 determines that the coprocessor 100 accesses the global SRAM 146 or the DRAM 148 for the first time, the coprocessor 100 sets the state machine 602 to an enabled state (step S1) to turn on the memory access monitor 102. When the memory access monitor 102 determines through the memory protection unit 104 that the global SRAM 146 or the DRAM 148 is not accessed, the memory access monitor 102 reduces the count value of the timeout counter 600 by one. When the count value of the timeout counter 600 is equal to zero (step S3), the state machine 602 receives a timeout message from the timeout counter so that the memory access monitor 102 sends an interrupt to the coprocessor 100 to shut down the global SRAM 146 or the DRAM 148. In some embodiments, after the memory access monitor 102 sends an interrupt to the coprocessor 100 to shut down the global SRAM 146 or the DRAM 148 , the coprocessor 100 sets the state machine 602 to a disabled state (step S2 ) to shut down the memory access monitor 102 .

[0092] Figure 7 The embodiment of the present invention is shown in Figure 1 FIG. 1 is a flowchart of the operation of the coprocessor 100 in which the coprocessor 100 determines whether to shut down the global SRAM 146 or the DRAM 148 according to the interrupt. Figure 7 As shown, the coprocessor starts operating (step S700). In step S702, the coprocessor 100 determines that the global SRAM 146 or DRAM 148 is accessed for the first time through the memory protection unit 104, and the coprocessor 100 turns on the memory access monitor 102 in step S704. In step S706, the coprocessor 100 determines whether the global SRAM 146 or DRAM 148 is accessed through the memory protection unit 104. If the answer in step S708 is affirmative, the memory access monitor 102 resets the timeout counter 600, and the coprocessor 100 executes step S706 again. If the answer in step S708 is negative, the memory access monitor 102 reduces the count value of the timeout counter 600 by one in step S710. In step S712, the memory access monitor 102 determines whether the count value of the timeout counter 600 is equal to zero.

[0093] If the answer in step S712 is negative, the coprocessor 100 performs step S706 again. If the answer in step S712 is positive, the memory access monitor 102 sends an interrupt to the coprocessor 100 in step S714. After receiving the interrupt from the memory access monitor 102, the coprocessor 100 turns off the global SRAM 146 or DRAM 148 in step S716. After the memory access monitor 102 sends an interrupt to the coprocessor 100 to turn off the global SRAM 146 or DRAM 148, the coprocessor 100 sets the state machine 602 to the disabled state so as to turn off the memory access monitor 102 in step S718.

[0094] Figure 8 The embodiment of the present invention is shown in Figure 1 The operation diagram of the coprocessor 100 predicting the next time point according to the interrupt to open the global SRAM 146 or DRAM 148 is shown. Figure 8 As shown, the coprocessor 100 executes the memory access monitor timeout control 800 to predict the next time point. In some embodiments, the coprocessor 100 predicts the next time point to turn on the global SRAM 146 or DRAM 148. Because it takes some time to turn on the DRAM 148 and the global SRAM 146, in order to achieve better performance, the coprocessor 100 executes the idle frame 812 and the scheduler run queue 804 to predict when the next task will start. The timer is used to wake up the coprocessor 100 to turn on the DRAM 148 or the global SRAM 146.

[0095] In some embodiments, the coprocessor 100 predicts the next time point to shut down the global SRAM 146 or DRAM 148. In order to achieve better power consumption, the count value of the timeout counter 600 should change dynamically to accurately control the shutdown of DRAM 148 and the global SRAM in different scenarios. The coprocessor 100 integrates the power consumption related modules in the system (such as the idle frame 812, the software monitor 802, the scheduler run queue 804, the wakeup lock 806, etc.), and uses artificial intelligence (AI) prediction 808 to predict what the next timeout should be. In some embodiments, because some application program interfaces (APIs) provided by the system are frequently used, they are arranged to be placed in the local SRAM 108 or the global SRAM 146. For example, if the DRAM task calls these APIs in a loop, the timeout counter 600 in the memory access monitor 102 will not time out to shut down the DRAM 148 or the global SRAM 146.

[0096] In some embodiments, the count value of the timeout counter 600 in the memory access monitor 102 is corrected by combining the load of the DRAM or global SRAM task and the load of the entire coprocessor 100. If the load of the DRAM or global SRAM task is very high, the count value of the timeout counter 600 can be set to a large value, or the memory access monitor 102 can be directly turned off. In some embodiments, in order to achieve better performance, some high-frequency SRAM tasks will hold the wakeup lock 806 to prevent the coprocessor 100 from executing the idle frame 812, which will also affect the count value of the timeout counter 600.

[0097] Fig. 9 FIG. 1 shows an operation diagram of selecting a local static random access memory (SRAM) 108, a global SRAM 146 or a dynamic random access memory (DRAM) 148 to be accessed according to a task load and an operating frequency according to an embodiment of the present invention. Fig. 9 As shown, the coprocessor 100 includes a task dynamic migration monitor 900. The task dynamic migration monitor 900 first receives a plurality of tasks 902. The task dynamic migration monitor 900 selects the local SRAM 108, the global SRAM 146 or the DRAM 148 to be accessed according to the task load 904 and the operating frequency 906. In some embodiments, if the operating frequency of the task is high (for example, higher than 200 Hz), the task dynamic migration monitor 900 selects to access the local SRAM 108 to obtain better power consumption. If the operating frequency of the task is low (for example, lower than 5 Hz), the task dynamic migration monitor 900 selects to access the DRAM 148, because the operating frequency is low, the DRAM 148 occupancy time is short, and the average power consumption is not high. If the operating frequency of the task is between 5 Hz and 200 Hz, the task dynamic migration monitor 900 selects to access the global SRAM 146. In some embodiments, if a low-frequency task is selected to be executed in the DRAM 148, but because the load of the task is very high, it is not suitable to continue to be executed in the DRAM 148. For better power consumption, the task dynamic migration monitor 900 chooses to execute the task in the local SRAM 108 .

[0098] Fig.10 The normally open domain 130, Figure 1 146 and DRAM 148 in FIG. Figure 2 and Fig.10 . Figure 2 and Fig.10 The main difference between Fig.10 There is no memory protection unit 104, so the memory access monitor 102 is directly electrically connected to the DRAM 148 and the global SRAM 146.

[0099] Fig.11 The flowchart of the low power consumption interrupt processing method according to the embodiment of the present invention is shown. The low power consumption interrupt processing method of the present invention is applied to Figure 1 An electronic device 110 in the present invention has a local SRAM 108, a global SRAM 146, a DRAM 148, a coprocessor 100, a memory access monitor 102 and a memory protection unit 104. The method includes the following steps. An ultra-low power framework is executed (step S1100). The ultra-low power framework includes interrupt alignment and activity groups, a memory prediction monitor and a task dynamic migration monitor. Interrupt alignment and activity groups align multiple interrupts (step S1104). The memory prediction monitor predicts the next time point to access the global SRAM 146 and DRAM 148, and determines whether to turn off the power of the global SRAM 146 and DRAM 148 through the memory access monitor 102 (step S1106). The task dynamic migration monitor selects the global memory (e.g., global SRAM 146 or DRAM 148) or local memory (e.g., local SRAM 108) to be accessed according to the task load and operating frequency of the task executed by the coprocessor 100 (step S1108).

[0100] The step of aligning interrupts includes the following steps. The interrupts are classified into a plurality of timer vectors according to the triggering frequency of the interrupts to generate a timer wheel. The timer wheel includes timer vectors corresponding to different triggering frequencies in sequence. The last timer vector to expire is selected. An interrupt in the timer vector is triggered to perform a corresponding task. An interrupt in a subsequent timer vector in the timer wheel is triggered. In some embodiments, the interrupt triggering frequency in the timer vector is calibrated by eliminating noise.

[0101] Any specific order or hierarchy of steps in the procedures disclosed herein is purely by way of example. Based on design preferences, it should be understood that any specific order or hierarchy of steps in the procedures may be rearranged within the scope of this document. The accompanying method claims present various steps in an exemplary order and therefore should not be limited to the specific order or hierarchy shown herein.

[0102] The use of ordinal numbers such as "first", "second", "third", etc. to modify components in the claims does not itself imply any priority, precedence, sequence between components, or order of steps performed by the method, but is only used as an identifier to distinguish different components with the same name (with different ordinal numbers).

[0103] Although the present disclosure has been disclosed as above by way of implementation examples, it is not intended to limit the present case. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present case shall be determined by the definition of the claims.

Claims

1. An electronic device for low-power interrupt processing, characterized in that: include: Local storage; Global memory; Application processor; a coprocessor electrically connected to the local memory, the global memory and the application processor, and configured to run the ultra-low power framework; wherein the ultra-low power framework includes an interrupt alignment and activity group, a memory prediction monitor and a task dynamic migration monitor; wherein the interrupt alignment and activity group align a plurality of interrupts, so that the coprocessor is awakened based on the aligned interrupt to execute all expired low power functions, and the application processor is awakened based on the awakening of the coprocessor by alignment; and A memory protection unit and a memory access monitor, electrically connected to the global memory and the coprocessor, for running a memory prediction monitor to predict the next time point of accessing the global memory, and determining whether to close the global memory through the memory access monitor; The task dynamic migration monitor selects one of the global memory or the local memory for access according to the task load and the running frequency.

2. The electronic device according to claim 1, wherein: When the coprocessor accesses the global memory for the first time, the memory protection unit sends an interrupt to the coprocessor to open the global memory, and when the coprocessor does not access the global memory within a predetermined time, the memory access monitor is electrically connected to the memory protection unit and sends the interrupt to the coprocessor to close the global memory.

3. The electronic device according to claim 1, wherein: Further including: An interrupt controller is electrically connected between the memory access monitor and the coprocessor, and is used for bypassing the interrupt of the memory protection unit or the memory access monitor to the coprocessor.

4. The electronic device according to claim 1, wherein: The global memory includes a dynamic random access memory DRAM and a global static random access memory SRAM.

5. The electronic device according to claim 1, wherein: The local memory includes a local static random access memory SRAM.

6. The electronic device according to claim 1, wherein: The interrupts include external interrupts and timer interrupts.

7. The electronic device according to claim 6, characterized in that: The coprocessor aligns the multiple interrupts by: Classifying the timer interrupt from the heartbeat timer into a plurality of timer vectors according to a trigger frequency to generate a timer wheel, wherein the timer wheel includes timer vectors corresponding to different trigger frequencies in sequence; Select the most recently expired timer vector; Trigger an interrupt in the timer vector to execute the corresponding task; and Triggers this interrupt in the subsequent timer vector in this timer round.

8. The electronic device according to claim 7, characterized in that: The coprocessor aligns the plurality of interrupts by classifying the external interrupt from the inertial processing unit into the timer vector according to the triggering frequency of the timer interrupt and the external interrupt to generate the timer wheel.

9. The electronic device according to claim 8, characterized in that: The coprocessor aligns the plurality of interrupts in the following manner: calibrating the trigger frequency of the external interrupt in the timer vector by reducing noise.

10. The electronic device according to claim 9, characterized in that: The noise includes white noise, temperature drift, other interrupts with different trigger frequencies, or interrupt handling errors from the inertial processing unit.

11. The electronic device according to claim 10, characterized in that: The coprocessor uses a local statistical filter or a Kalman filter to reduce noise.

12. The electronic device according to claim 2, characterized in that: The memory access monitor includes a timeout counter; and when the memory access monitor determines that the global memory is accessed through the memory protection unit, the memory access monitor resets the count value of the timeout counter.

13. The electronic device according to claim 12, characterized in that: When the memory access monitor determines that the global memory is not accessed through the memory protection unit, the memory access monitor reduces the count value of the timeout counter by one.

14. The electronic device according to claim 13, characterized in that: When the count value of the timeout counter is equal to zero, the memory access monitor sends an interrupt to the coprocessor to close the global memory.

15. The electronic device according to claim 2, characterized in that: When the memory protection unit determines that the coprocessor accesses the global memory for the first time, the coprocessor enables the memory access monitor.

16. The electronic device according to claim 15, characterized in that: After the memory access monitor sends the interrupt to the coprocessor to close the global memory, the coprocessor closes the memory access monitor.

17. The electronic device according to claim 16, characterized in that: The memory access monitor includes a state machine; and when the memory protection unit determines that the coprocessor accesses the global memory for the first time, the coprocessor sets the state machine to an enabled state so as to turn on the memory access monitor.

18. The electronic device according to claim 17, characterized in that: After the memory access monitor sends the interrupt to the coprocessor to close the global memory, the coprocessor sets the state machine to a disabled state so as to close the memory access monitor.

19. The electronic device according to claim 1, wherein: When the coprocessor accesses the global memory for the first time, the memory protection unit sends the interrupt to the coprocessor to enable the global memory; and when the coprocessor does not access the global memory within the predetermined time, the memory access monitor sends the interrupt to the coprocessor to disable the global memory.

20. A low-power interrupt processing method, applied to an electronic device having a local memory, a global memory, a coprocessor, a memory access monitor and a memory protection monitor, comprising: The coprocessor runs an ultra-low power framework; wherein the ultra-low power framework includes interrupt alignment and activity groups, memory prediction monitors, and task dynamic migration monitors; Aligning a plurality of interrupts by the interrupt alignment and the activity group, so that the coprocessor is awakened based on the aligned interrupt to execute all expired low power functions, and the application processor is awakened by the alignment based on the wakeup of the coprocessor; Running the memory prediction monitor to predict a next time point at which a memory access monitor and a memory protection unit access a global memory, and determining whether to close the global memory through the memory access monitor; and According to the task load and the running frequency, the task dynamic migration monitor selects one of the global memory or the local memory for access.

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