FPGA program parallel updating method and system based on PCIE

Abstract

The invention belongs to the technical field of communication, and relates to a PCIE (peripheral component interface express)-based FPGA (field programmable gate array) parallel updating method and a PCIE-based FPGA parallel updating system, which are characterized in that ID (identity) information of all FPGAs is acquired through the PCIE, a to-be-updated FGPA is selected according to the ID information, a to-be-updated file is selected, and the to-be-updated file is transmitted to the to-be-updated FPGA frame by frame after the FPGA erases flash sectors one by one to a sector corresponding to the size of the The to-be-updated FPGA solidifies the data in the update file into the flash frame by frame, and the FPGA end program can be updated without redundant equipment, so that the cost is saved, the equipment maintenance is convenient, the parallel update of a plurality of FPGAs is realized, the update time is greatly shortened, and the operation difficulty is reduced.

Description

Technical Field

[0001] The present invention belongs to the field of communication technology, and relates to FPGA program update technology, and in particular to a PCIE-based FPGA program parallel update method and system. Background Art

[0002] In the railway industry, the launch of a formal product or the verification of a control algorithm requires a long testing process, and even requires the use of all the resources of a high-speed train. This testing mode has a high time and economic cost, slowing down the speed of product upgrades and iterations. The emergence of real-time simulators effectively solves this problem. As a controlled object, real-time simulators can completely replace real components. Real-time simulators can be flexibly applied to the design of semi-physical simulation (HIL) or rapid controller prototyping (RCP), in which FPGA is a key component. During the development process, component models need to be updated frequently, so the update strategy of the FPGA program affects the testing and release process of the entire product.

[0003] At present, the existing real-time simulator FPGA program solidification mainly adopts JTAG method. On the one hand, since most model programs are larger than 10MB and only one FPGA can be updated at a time, it takes a long time. On the other hand, each time the FPGA program is updated, the machine needs to be disassembled and assembled, and the simulator needs to be plugged in and out multiple times, which greatly increases the error probability and is not conducive to equipment maintenance. Some real-time simulators use SLAVE configuration method, with FPGA as a slave device, and the configuration process is controlled by other chips such as ARM and CPLD. This configuration method greatly increases the development cost and causes a waste of resources. Summary of the invention

[0004] In view of the above-mentioned problems of the prior art such as long update time and high update cost, the present invention provides a PCIE-based FPGA program parallel update method and system, which can realize multi-channel parallel update of FPGA program, greatly shorten the update time, and update FPGA program without redundant equipment, which is convenient for equipment maintenance and saves costs.

[0005] In a first aspect, the present invention provides a method for updating FPGA programs in parallel based on PCIE, comprising the following steps: Information acquisition steps: The host computer obtains the ID information of all FPGAs through PCIE; Selection steps: The host computer selects the FPGA to be updated based on the ID information and selects the update file; Information sending step: The host computer sends the erase start signal and update file size information generated by the host computer to the FPGA to be updated through PCIE; Erasing step: The FPGA to be updated receives the erase start signal and erases the flash sector by sector until it reaches the sector corresponding to the update file size; Update steps: The host computer sends the update file frame by frame to the FPGA to be updated. Each time a frame of data is sent, the host computer calculates the CRC check result value based on the frame data, and sends the CRC check result value and the frame data together to the FPGA to be updated; after receiving a frame of data, the FPGA to be updated reversely checks, and when it is determined that the reverse check result is equal to the CRC check result value sent by the host computer, the frame data is written to the flash. After the writing of the frame data is completed, the address is pointed to the next frame address, and the above steps are repeated until all frame data are sent; Reconfiguration steps: After all frame data are written, the host computer sends a reload signal and waits for the updated FPGA to complete the flash program reload.

[0006] In some embodiments, in the erasing step, each time a sector is erased, the FPGA to be updated generates a sector erase completion signal, the sector erase count value is increased by 1, and the sector erase count value is sent to the host computer, and the host computer displays the erase progress according to the sector erase count value.

[0007] In some embodiments, in the update step, after receiving a frame of data, the FPGA to be updated is reversed and checked. When it is determined that the reverse check result is not equal to the CRC check result value sent by the host computer, the frame data will not be written to the flash, and the host computer will repeatedly send the frame data at a set interval until the reverse check result is equal to the CRC check result value sent by the host computer.

[0008] In some embodiments, in the update step, after writing a frame of data, the FPGA to be updated generates a page completion signal, the page write count value is increased by 1, and the page write count value is sent to the host computer, and the host computer displays the write progress according to the page write count value.

[0009] According to a second aspect of the present invention, a PCIE-based FPGA program parallel update system is provided, which is used to implement the PCIE-based FPGA program parallel update method described in the first aspect of the present invention, including a host computer and multiple FPGAs, and the FPGAs are provided with a PCIE physical interface; The host computer is equipped with: A storage module storing FPGA update files and update file size information; An information acquisition module is connected to the PCIE physical interface to obtain the ID information of all FPGAs; Select the module, select the FPGA to be updated according to the ID information, and select the update file; The control module is configured to: generate an erase start signal and send it to the FPGA to be updated through the PCIE physical interface, and control the storage module to send the update file size information and the update file to the FPGA to be updated; The FPGA also has: The receiving module receives the data frame, performs anti-checking to generate anti-checking results, and writes the frame data into the FIFO after receiving the write enable signal; The state feedback module receives the CRC check result value, and when it is determined that the reverse check result is equal to the CRC check result value, generates a write enable signal and sends it to the receiving module; The reading and reconfiguration module reads the ID information of the FPGA and sends it to the host computer. After all frame data of the update file are written, it receives the reconfiguration command sent by the host computer and loads all frame data of the update file from the flash. The Flash control module is configured to: upon receiving an erase start signal and update file size information, erase the Flash sector by sector until the sector corresponding to the update file size is erased, and when the FIFO data volume reaches a set byte, control the writing of data into the Flash.

[0010] In some embodiments, when the state feedback module determines that the reverse check result is not equal to the CRC check result value, it generates an error message and sends it to the control module of the host computer.

[0011] In some embodiments, the control module is further configured to: after receiving error information, repeatedly send frame data at set intervals.

[0012] In some embodiments, the Flash control module generates a sector erase completion signal and sends it to the status feedback module each time a sector is erased. After the status feedback module receives the sector erase completion signal, the sector erase counter value set in the status feedback module is increased by 1. The status feedback module sends the sector erase count value to the display module of the host computer to display the erase progress through the display module.

[0013] In some embodiments, after writing a frame of data, the Flash control module generates a completion signal and sends it to the status feedback module. After the status feedback module receives the completion signal, the page write counter value set in the status feedback module is increased by 1, and the status feedback module sends the page write count value to the display module of the host computer to display the writing progress through the display module.

[0014] In some embodiments, the FPGA further includes a bridge module, wherein the bridge module includes: A PCIE bridge module is connected to the PCIE physical interface and is used to convert the PCIE data stream into an AXI bus data stream; the PCIE bridge module is provided with an AXI_LITE interface connected to the status feedback module and an AXI interface connected to the receiving module, the AXI_LITE interface is used to transmit control and status information, and the AXI interface is used to transmit the data stream of the update file; The AXI bus bridge module connects the AXI interface and the receiving module to isolate normal business data and update data.

[0015] Compared with the prior art, the advantages and positive effects of the present invention are: (1) The PCIE-based FPGA parallel update method and system provided by the present invention transmits the update file frame by frame to the FPGA to be updated through PCIE, and the FPGA to be updated solidifies the data in the update file into the flash frame by frame. The FPGA-side program can be updated without redundant equipment, which saves costs and facilitates equipment maintenance. It also realizes the parallel update of multiple FPGAs, greatly shortens the update time, and reduces the difficulty of operation.

[0016] (2) The PCIE-based FPGA parallel update method and system provided by the present invention automatically loads the program downloaded to the flash and reconfigures it after the FPGA program is updated, without shutting down and restarting.

[0017] (3) The PCIE-based FPGA parallel update method and system provided by the present invention also introduces a verification mechanism and a retransmission mechanism, and has strong anti-interference ability. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a flow chart of a PCIE-based FPGA parallel update method according to an embodiment of the present invention; Figure 2 This is a control flow chart of the PCIE-based FPGA parallel update method according to an embodiment of the present invention; Figure 3 It is a structural block diagram of the PCIE-based FPGA parallel update system according to an embodiment of the present invention; Figure 4 This is a structural block diagram of the host computer described in an embodiment of the present invention; Figure 5 It is a structural block diagram of the FPGA described in the embodiment of the present invention; Figure 6 This is a control flow chart of the Flash control module described in an embodiment of the present invention.

[0019] In the figure, 1. host computer, 11. storage module, 12. information acquisition module, 13. selection module, 14. control module, 15. display module, 2. FPGA, 21. PCIE physical interface, 22. receiving module, 23. status feedback module, 24. reading and reconfiguration module, 25. Flash control module, 26. PCIE bridge module, 27. AXI bus bridge module, A1, A2, A3, A4, B1, B2, B3 are signal transmission lines. DETAILED DESCRIPTION

[0020] Below, the present invention is described in detail by exemplary embodiments. However, it should be understood that the elements, structures and features in one embodiment may also be beneficially incorporated into other embodiments without further description. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings need not be drawn to scale unless otherwise specified.

[0021] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0022] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0023] In view of the problems existing in updating FPGA programs in existing real-time simulators, such as long updating time, increased error probability, and the need to add additional configuration chips, the present invention provides a PCIE-based FPGA program parallel updating method and system, which does not require the addition of configuration chips, uses PCIE communication to complete the burning of FPGA programs, can realize multi-channel parallel updating, shorten the update time, and facilitate equipment maintenance.

[0024] The PCIE-based FPGA program parallel update method and system of the present invention are described in detail below in conjunction with embodiments.

[0025] like Figure 1 , Figure 2 As shown, a PCIE-based FPGA program parallel update method provided by an embodiment of the first aspect of the present invention includes the following steps: S1, information acquisition step: the host computer obtains the ID information of all FPGAs through PCIE.

[0026] S2, selection step: The host computer selects the FPGA to be updated according to the ID information and selects the update file.

[0027] S3, information sending step: the host computer sends the erase start signal and update file size information generated by the host computer to the FPGA to be updated through PCIE.

[0028] S4, erasing step: the FPGA to be updated receives an erase start signal and erases the flash sector by sector until the sector corresponding to the update file size is erased.

[0029] Specifically, each time a sector is erased, the FPGA to be updated generates a sector erase completion signal, the sector erase count value is increased by 1, and the sector erase count value is sent to the host computer, and the host computer displays the erase progress according to the sector erase count value. Through the above operation, the erase progress can be known in real time.

[0030] S5, update step: the host computer sends the update file frame by frame to the FPGA to be updated. Each time a frame of data is sent, the host computer calculates the CRC check result value according to the frame data, and sends the CRC check result value and the frame data together to the FPGA to be updated; after receiving a frame of data (256 bytes), the FPGA to be updated reversely checks, and when it is determined that the reverse check result is equal to the CRC check result value sent by the host computer, the frame data is written to the flash. After the writing of the frame data is completed, the address is pointed to the next frame address, and the above steps are repeated until all frame data are sent.

[0031] Specifically, the update file is a binary update file, that is, a file with the suffix bin.

[0032] Specifically, in some embodiments, after receiving a frame of data, the FPGA is updated for reverse checking. When it is determined that the reverse checking result is not equal to the CRC check result value sent by the host computer, the frame data will not be written to the flash, and the host computer will repeatedly send the frame data at a set interval until the reverse checking result is equal to the CRC check result value sent by the host computer.

[0033] Through the verification mechanism and retransmission mechanism, data transmission errors are prevented, the accuracy of data transmission is improved, and the anti-interference ability is strong.

[0034] Specifically, in some embodiments, in the updating step, after writing a frame of data, the FPGA to be updated generates a page completion signal, the page write count value is increased by 1, and the page write count value is sent to the host computer, and the host computer displays the writing progress according to the page write count value. Through the above operation, the update progress can be known in real time.

[0035] S6, reconfiguration step: After all frame data are written, the host computer sends a reload signal, and the updated FPGA completes the flash program reload. The FPGA program can be automatically reconfigured without shutting down and restarting, saving time.

[0036] The PCIE-based FPGA program parallel update method of the embodiment of the present invention can realize multi-channel parallel update of the FPGA program, greatly shorten the update time, and update the FPGA program without redundant equipment, which is convenient for equipment maintenance and saves costs.

[0037] like Figure 3-6 As shown, a PCIE-based FPGA program parallel update system provided by the second embodiment of the present invention is used to implement the PCIE-based FPGA program parallel update method described in the first embodiment of the present invention, including a host computer 1 and multiple FPGAs 2, and the FPGAs 2 are provided with a PCIE physical interface 21; The host computer 1 is provided with: The storage module 11 stores FPGA update files and update file size information; The information acquisition module 12 is connected to the PCIE physical interface to obtain the ID information of all FPGAs; Selection module 13, selects the FPGA to be updated according to the ID information, and selects the update file; The control module 14 is configured to: generate an erase start signal and send it to the FPGA to be updated through the PCIE physical interface, and control the storage module to send the update file size information and the update file to the FPGA to be updated; The FPGA 2 also has: The receiving module 22 receives the data frame, performs an anti-check to generate an anti-check result, and writes the frame data into the FIFO after receiving a write enable signal; The state feedback module 23 receives the CRC check result value, and when it is determined that the reverse check result is equal to the CRC check result value, generates a write enable signal and sends it to the receiving module; The reading and reconfiguration module 24 reads the ID information of the FPGA and sends it to the host computer. After all frame data of the update file are written, it receives the reconfiguration command sent by the host computer to complete the reloading of the flash program. The Flash control module 25 is configured to: upon receiving an erase start signal and update file size information, erase the Flash sector by sector until the sector corresponding to the update file size is erased, and when the FIFO data volume reaches a set byte, control the writing of data into the Flash.

[0038] Specifically, in some embodiments, when the state feedback module 23 determines that the reverse check result is not equal to the CRC check result value, it generates an error message and sends it to the control module 14 of the host computer 1 .

[0039] Specifically, in some embodiments, the control module 14 is further configured to: after receiving error information, repeatedly send frame data at set intervals. By introducing a check mechanism and a retransmission mechanism, data transmission errors are prevented, the accuracy of data transmission is improved, and the anti-interference performance is strong.

[0040] Specifically, in some embodiments, the Flash control module generates a sector erasure completion signal and sends it to the state feedback module after erasing a sector. After the state feedback module receives the sector erasure completion signal, the sector erasure counter value set in the state feedback module is increased by 1, and the state feedback module sends the sector erasure count value to the host computer to display the erasure progress through the host computer. The display of the erasure progress by accumulating the sector erasure count value can know the erasure progress in real time.

[0041] In some embodiments, after writing a frame of data, the Flash control module 25 generates a completion signal and sends it to the state feedback module 23. After the state feedback module 23 receives the completion signal, the page write counter value set in the state feedback module is increased by 1, and the state feedback module sends the page write count value to the display module 15 of the host computer 1 to display the writing progress through the display module 15. By displaying the writing progress in a manner of accumulating the page write count value, the update progress can be known in real time.

[0042] Specifically, in some embodiments, the above-mentioned update system also includes a workstation chassis 3, and a plurality of PCIE slots are provided on the mainboard of the workstation chassis, and each slot corresponds to a fixed FPGA. In a specific embodiment, the mainboard model of the workstation chassis is Advantech's ASMB-976, which contains 11 PCIE 4.0 slots, can install 11 FPGAs, and can update the programs of 11 FPGAs at the same time without redundant equipment. The FPGA is the AV7K325 development board of Heijin, and the main chip is the KINTEX-7 series chip of Xilinx, model XC7K325TFFG900. The FPGA has 1 PCIE 2.0 interface, and the program solidification flash model is N25Q128, with a capacity of 16MB. The FPGA has rich logic resources, 326080 logic units, 50950 lookup tables, 407600 triggers, 840 DSP processing units, and a block RAM size of 16020Kb, which can fully meet the requirements of serving as a model carrier.

[0043] After the host computer selects the FPGA and update file of the model program to be updated, the host computer transmits the binary update file frame by frame to the FPGA through the PCIE physical interface of the corresponding board. The FPGA solidifies the update file frame data into the flash chip frame by frame. After the FPGA receives all the update files, the host computer sends a reconfiguration signal, and the FPGA automatically loads the program downloaded to the flash without powering off and restarting. In addition, multiple FPGA programs can be updated in parallel through different PCIE card slots, greatly reducing time consumption and operation difficulty.

[0044] Specifically, in some embodiments, the FPGA further includes a bridge module, and the bridge module includes: A PCIE bridge module is connected to the PCIE physical interface and is used to convert the PCIE data stream into an AXI bus data stream; the PCIE bridge module is provided with an AXI_LITE interface connected to the status feedback module and an AXI interface connected to the receiving module, the AXI_LITE interface is used to transmit control and status information, and the AXI interface is used to transmit the data stream of the update file; The AXI bus bridge module connects the AXI interface and the receiving module to isolate normal business data and update data.

[0045] Specifically, in some embodiments, the PCIE bridge module uses XDMA (full name: DMA / Bridge Subsystem for PCI Express (PCIE)), and XDMA selects two interfaces, namely, AXI interface and AXI LITE interface. For the specific configuration of XDMA, see Table 1.

[0046] Table 1

[0047] It should be noted that the AXI bus bridge module connects one or more AXI memory-mapped master devices to one or more AXI memory-mapped slave devices. By using different slave addresses, the master device can send data to different targets, thereby achieving isolation between normal business data and update data.

[0048] Specifically, in some embodiments, the PCIE physical interface adopts a PCIE 2.0 x8 physical interface, providing a 100Mhz clock, reset and data transmission channel.

[0049] Specifically, in some embodiments, the flash capacity is 16MB. In order to expand the capacity later, referring to Table 2, the length of the receiving module read / write address is defined as 4 bytes. The burst size is equal to the XDMA AXI data width. If the parameters are set according to Table 2, a single burst transfer can transfer exactly one page of flash data (256 bytes).

[0050] Table 2

[0051] Specifically, in some embodiments, the state feedback module opens up 30 4-byte registers, of which the first 10 registers can only be written by the FPGA, the last 20 registers can only be written by the host computer, and all registers can be read by both. The specific definition of the registers is shown in Table 3.

[0052] Table 3

[0053] Specifically, in some embodiments, the read and reconfiguration module uses the ICAPE2 primitive to allow the user to complete automatic reconfiguration without turning off the power. After the module receives the reload signal, the IPROG instruction sequence is converted into SelectMap format data, and then transmitted to the ICAPE2 primitive in sequence according to the timing. The FPGA will automatically trigger reconfiguration according to the specified flash address (default 0). The IPROG instruction sequence is shown in Table 4.

[0054] Table 4

[0055] Specifically, the reading and reconfiguration module obtains the level state of the ID pin of the FPGA through the DIP switch to obtain the ID information of the FPGA.

[0056] In the above-mentioned PCIE-based FPGA program parallel update system, FPGA program update is implemented through the following steps.

[0057] The host computer information acquisition module obtains the FPGA ID information by scanning. Each FPGA transmits the FPGA ID information to the host computer's information acquisition module through the reading and reconfiguration module—A2—status feedback module—A1—PCIE bridge module—PCIE physical interface. The host computer's information acquisition module sends the information to the display module, and the display module displays the FPGA list.

[0058] Select the FPGA of the program to be updated. After the host computer selects the update file and sends the update file information, the host computer sends the erase start signal and file size information to the flash controller through the PCIE physical interface - PCIE bridge module - A1 - status feedback module - A3. The flash control module starts to erase the flash sector by sector until it erases the sector corresponding to the update file size.

[0059] Each time the flash control module finishes erasing a sector, it sends a sector erase completion signal through A3. The status feedback module adds 1 to the corresponding sector erase counter value, and then sends it to the host computer through A1—PCIE bridge module—PCIE physical interface. The host computer reads the counter value and displays the erase progress through the display module.

[0060] After the flash is erased, the host computer starts to automatically send data frame by frame, including a 256-byte data frame and a CRC check result value. In order to maximize the use of the AXI interface bandwidth and reduce the filling of invalid data, the CRC check result value is written to the CRC register corresponding to the status feedback module through A1, and the data frame is transmitted to the receiving module through B1.

[0061] The host computer transmits the 256-byte data frame to the receiving module through the PCIE physical interface—PCIE bridge module—B1—AXI bus bridge module—B2, and the CRC check result value of the corresponding frame is written into the CRC register of the status feedback module through A1. After receiving a frame of data (256 bytes), the receiving module automatically performs a reverse check and sends the reverse check result to the status feedback module through A4. If the two check values ​​are equal, the status feedback module sends a FIFO write enable signal through A4. After receiving the signal, the receiving module writes the frame data into the FIFO. When the FIFO data volume reaches 256 bytes, the flash control module starts writing the flash. If the two check values ​​are not equal, the frame data will not be written into the FIFO. At the same time, the FPGA feeds back the check result information to the host computer through the status feedback module—A1—PCIE bridge module—PCIE physical interface. If the check results are not equal, the host computer will repeat sending the frame data at intervals. If the check results are equal, the host computer reads the page write counter in the status feedback module, waits for the frame to be written, and then sends the next frame data.

[0062] Each time the flash finishes writing a page (256 bytes), the flash control module transmits the page completion signal to the status feedback module through A3. The status feedback module adds 1 to the page write counter register. The host computer can read the write progress information through the PCIE physical interface—PCIE bridge module—A1, and display the update progress through the display module.

[0063] After all frames are written, the host computer sends a reload signal to the reading and reconfiguration module through the PCIE physical interface—PCIE bridge module—A1—status feedback module—A2. The reconfiguration module completes the reloading of the flash program based on the ICAPE2 primitive.

[0064] The PCIE-based FPGA program parallel update system of the embodiment of the present invention can realize multi-channel parallel update of FPGA programs, greatly shorten the update time, and update the FPGA program without redundant equipment, which is convenient for equipment maintenance and saves costs.

[0065] It should be noted that the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the FPGA parallel update method based on PCIE and the update system product according to multiple embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of an instruction, and the module, a program segment or a part of an instruction contains one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or the flowchart, and the combination of boxes in the block diagram and / or the flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0066] The above embodiments are used to explain the present invention rather than to limit the present invention. Any modification and change made to the present invention within the spirit of the present invention and the protection scope of the claims shall fall within the protection scope of the present invention.

Claims

1. A PCIE-based FPGA parallel update method, characterized in that: The steps are: Information acquisition steps: The host computer obtains the ID information of all FPGAs through PCIE; Selection steps: The host computer selects the FPGA to be updated based on the ID information and selects the update file; Information sending step: The host computer sends the erase start signal and update file size information generated by the host computer to the FPGA to be updated through PCIE; Erasing step: The FPGA to be updated receives the erase start signal and erases the flash sector by sector until it reaches the sector corresponding to the update file size; Update steps: The host computer sends the update file frame by frame to the FPGA to be updated. Each time a frame of data is sent, the host computer calculates the CRC check result value based on the frame data, and sends the CRC check result value and the frame data together to the FPGA to be updated; after receiving a frame of data, the FPGA to be updated reversely checks, and when it is determined that the reverse check result is equal to the CRC check result value sent by the host computer, the frame data is written to the flash. After the writing of the frame data is completed, the address is pointed to the next frame address, and the above steps are repeated until all frame data are sent; Reconfiguration steps: After all frame data are written, the host computer sends a reload signal and waits for the updated FPGA to complete the flash program reload.

2. The PCIE-based FPGA parallel update method according to claim 1, characterized in that: In the erasing step, each time a sector is erased, the FPGA to be updated generates a sector erase completion signal, the sector erase count value is increased by 1, and the sector erase count value is sent to the host computer, and the host computer displays the erase progress according to the sector erase count value.

3. The PCIE-based FPGA parallel update method according to claim 1, characterized in that: In the update step, after receiving a frame of data, the FPGA to be updated is reversed and checked. When it is determined that the reverse check result is not equal to the CRC check result value sent by the host computer, the frame data will not be written to the flash, and the host computer will repeatedly send the frame data at a set interval until the reverse check result is equal to the CRC check result value sent by the host computer.

4. The PCIE-based FPGA parallel update method according to claim 1, characterized in that: In the updating step, after writing a frame of data, the FPGA to be updated generates a page completion signal, the page write count value is increased by 1, and the page write count value is sent to the host computer, and the host computer displays the writing progress according to the page write count value.

5. A PCIE-based FPGA parallel update system, used to implement the PCIE-based FPGA parallel update method according to any one of claims 1 to 4, characterized in that: It includes a host computer and multiple FPGAs, and the FPGA is provided with a PCIE physical interface; The host computer is equipped with: A storage module storing FPGA update files and update file size information; An information acquisition module is connected to the PCIE physical interface to obtain the ID information of all FPGAs; Select the module, select the FPGA to be updated according to the ID information, and select the update file; The control module is configured to: generate an erase start signal and send it to the FPGA to be updated through the PCIE physical interface, and control the storage module to send the update file size information and the update file to the FPGA to be updated; The FPGA also has: The receiving module receives the data frame, performs anti-checking to generate anti-checking results, and writes the frame data into the FIFO after receiving the write enable signal; The state feedback module receives the CRC check result value, and when it is determined that the reverse check result is equal to the CRC check result value, generates a write enable signal and sends it to the receiving module; The reading and reconfiguration module reads the ID information of the FPGA and sends it to the host computer. After all frame data of the update file are written, it receives the reconfiguration command sent by the host computer and loads all frame data of the update file from the flash. The Flash control module is configured to: upon receiving an erase start signal and update file size information, erase the Flash sector by sector until the sector corresponding to the update file size is erased, and when the FIFO data volume reaches a set byte, control the writing of data into the Flash.

6. The PCIE-based FPGA parallel update method according to claim 5, characterized in that: When the state feedback module determines that the reverse check result is not equal to the CRC check result value, it generates an error message and sends it to the control module of the host computer.

7. The PCIE-based FPGA parallel update method according to claim 6, characterized in that: The control module is also configured to: after receiving the error information, repeatedly send the frame data at a set interval.

8. The PCIE-based FPGA parallel update system according to claim 5, characterized in that: After erasing each sector, the Flash control module generates a sector erase completion signal and sends it to the status feedback module. After the status feedback module receives the sector erase completion signal, the sector erase counter value set in the status feedback module is increased by 1. The status feedback module sends the sector erase count value to the display module of the host computer to display the erase progress through the display module.

9. The PCIE-based FPGA parallel update method according to claim 5, characterized in that: After writing a frame of data, the Flash control module generates a completion signal and sends it to the status feedback module. After the status feedback module receives the completion signal, the page write counter value set in the status feedback module is increased by 1, and the status feedback module sends the page write count value to the display module of the host computer to display the writing progress through the display module.

10. The PCIE-based FPGA parallel update system according to claim 5, characterized in that: The FPGA also includes a bridge module, and the bridge module includes: A PCIE bridge module is connected to the PCIE physical interface and is used to convert the PCIE data stream into an AXI bus data stream; the PCIE bridge module is provided with an AXI_LITE interface connected to the status feedback module and an AXI interface connected to the receiving module, the AXI_LITE interface is used to transmit control and status information, and the AXI interface is used to transmit the data stream of the update file; The AXI bus bridge module connects the AXI interface and the receiving module to isolate normal business data and update data.

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