Data processing method, robot and nonvolatile storage medium

Abstract

The invention discloses a data processing method, a robot and a nonvolatile storage medium. The method comprises the following steps: receiving an updating instruction from a control master station through an Ethernet communication protocol; in response to the update instruction, preparing a storage area in the off-chip memory; receiving an update data packet sent by the control master station through an Ethernet communication protocol, and storing the update data packet in a storage area; the first processor is updated according to the update data packet, an update prompt instruction is sent to the second processor, and the second processor reads the update data packet from the storage area according to the update prompt instruction. According to the method and the device, the technical problem that the efficiency is relatively low when the slave station equipment with a plurality of MCUs is upgraded in the prior art is solved.

Description

Technical Field

[0001] The present invention relates to the field of robot technology, and in particular to a data processing method, a robot and a non-volatile storage medium. Background Art

[0002] In the field of industrial automation, EtherCAT (Ethernet for Control Automation Technology) has been widely used as a high-performance real-time industrial Ethernet technology. Slave devices in an EtherCAT network are usually responsible for performing specific control tasks. These slave devices may contain microcontroller units (MCUs) to implement complex control logic. However, in existing EtherCAT systems, slave upgrade solutions are often designed only for a single CPU and cannot effectively cope with scenarios where there are multiple MCUs on the board, which greatly limits the flexibility and efficiency of system upgrades.

[0003] To address the above-mentioned problems, no effective solution has been proposed yet. Summary of the invention

[0004] The embodiments of the present invention provide a data processing method, a robot and a non-volatile storage medium, so as to at least solve the technical problem of low efficiency in upgrading a slave device having multiple MCUs in the related art.

[0005] According to one aspect of an embodiment of the present invention, a data processing method is provided, comprising: receiving an update instruction from a control master station via an Ethernet communication protocol; preparing a storage area in an off-chip memory in response to the update instruction; receiving an update data packet sent by the control master station via an Ethernet communication protocol, and storing the update data packet in the storage area; updating a first processor according to the update data packet, and sending an update prompt instruction to a second processor, wherein the second processor reads the update data packet from the storage area according to the update prompt instruction.

[0006] Optionally, sending an update prompt instruction to the second processor includes: sending an update instruction to the second processor through a communication connection between the first processor and the second processor, wherein the second processor reads an update data packet from a storage area and updates data according to the update prompt instruction, and after the second processor is updated successfully, the second processor sends an update completion signal to the first processor; receiving the update completion signal sent by the second processor; and running an application based on the updated data in response to the update completion signal.

[0007] Optionally, updating the first processor according to the update data packet includes: detecting integrity of the update data packet; and when the update data packet is complete, reading the update data packet from a storage area to perform data updating.

[0008] Optionally, detecting the integrity of the update data packet includes: reading first image update data and first cyclic redundancy check data from a storage area; and determining that the update data packet is complete when the first image update data and the first cyclic redundancy check data match.

[0009] According to another aspect of an embodiment of the present invention, a data processing method is also provided, including: receiving an update prompt instruction sent by a first processor; reading an update data packet from a storage area of ​​an off-chip memory in response to the update prompt instruction; updating a second processor according to the update data packet; after the update is completed, sending an update end signal to the first processor, wherein the first processor ends the update process in response to the update end signal.

[0010] Optionally, updating the second processor according to the update data packet includes: detecting the integrity of the update data packet; and when the update data packet is complete, reading the update data packet from the storage area to perform data updating.

[0011] Optionally, detecting the integrity of the update data packet includes: reading second image update data and second cyclic redundancy check data from a storage area; and determining that the update data packet is complete if the second image update data and the second cyclic redundancy check data match.

[0012] According to another aspect of an embodiment of the present invention, a robot is also provided, comprising: a slave station controller, and multiple motion control nodes, wherein the slave station controller comprises a first processor and a second processor, the first processor receiving an update instruction issued by a control master station via an Ethernet communication protocol, and preparing a storage area in an off-chip memory in response to the update instruction; the first processor is also used to receive an update data packet sent by the control master station via an Ethernet communication protocol, and store the update data packet in a storage area; the first processor is also used to update the first processor according to the update data packet, and send an update prompt instruction to the second processor; the second processor receives the update prompt instruction sent by the first processor; the second processor is also used to read the update data packet from the storage area of ​​the off-chip memory in response to the update prompt instruction; the second processor is also used to update the second processor according to the update data packet; the first processor is also used to send an update end signal to the first processor after the update is completed, wherein the first processor ends the update process in response to the update end signal.

[0013] According to another aspect of an embodiment of the present invention, a non-volatile storage medium is provided, the non-volatile storage medium including a stored program, wherein when the program is running, the device where the non-volatile storage medium is located is controlled to execute any one of the above data processing methods.

[0014] According to yet another aspect of an embodiment of the present invention, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, any one of the above data processing methods is implemented.

[0015] In an embodiment of the present invention, an update instruction is received from a control master station through an Ethernet communication protocol; in response to the update instruction, a storage area is prepared in an off-chip memory; an update data packet sent by the control master station is received through the Ethernet communication protocol, and the update data packet is stored in the storage area; the first processor is updated according to the update data packet, and an update prompt instruction is sent to the second processor, wherein the second processor reads the update data packet from the storage area according to the update prompt instruction, thereby achieving the purpose of setting up a memory outside the chip, enabling multiple processors to access the memory in time-sharing, and upgrading according to the data packets in the memory, thereby achieving the technical effect of improving the upgrading efficiency of slave devices of multiple MCUs, and further solving the technical problem of low efficiency in upgrading slave devices with multiple MCUs in the related art. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0017] Figure 1 A hardware structure block diagram of a computer terminal for implementing a data processing method is shown;

[0018] Figure 2 is a flow chart of a data processing method provided according to an embodiment of the present invention;

[0019] Figure 3 is a flow chart of another data processing method provided according to an embodiment of the present invention;

[0020] Figure 4 is a schematic diagram of the structure of a slave station controller provided according to an optional embodiment of the present invention;

[0021] Figure 5 is a schematic diagram of an interaction process between a master station and a slave station provided according to an optional embodiment of the present invention;

[0022] Figure 6 It is a schematic diagram of the interaction flow between the first processor and the second processor provided according to an optional embodiment of the present invention. DETAILED DESCRIPTION

[0023] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0024] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0025] First, some nouns or terms that appear in the description of the embodiments of the present application are subject to the following interpretations:

[0026] EtherCAT (Ethernet Control Automation Technology) is an open architecture, Ethernet-based fieldbus system. The CAT in its name is the abbreviation of Control Automation Technology. Automation generally requires shorter data update time (or cycle time), low communication jitter during data synchronization, and low hardware cost for communication. The purpose of EtherCAT development is to allow Ethernet to be used in automation applications.

[0027] According to an embodiment of the present invention, a method embodiment of data processing is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0028] The method embodiment provided in the first embodiment of the present application can be executed in a mobile terminal, a computer terminal or a similar computing device. Figure 1 FIG. 1 shows a hardware structure block diagram of a computer terminal for implementing a data processing method. Figure 1 As shown, the computer terminal 10 may include one or more (102a, 102b, ..., 102n are used to illustrate) processors (the processor may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA), a memory 104 for storing data. In addition, it may also include: a display, an input / output interface (I / O interface), a universal serial bus (USB) port (which may be included as one of the ports of the BUS bus), a network interface, a power supply and / or a camera. It can be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the above electronic device. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations shown.

[0029] It should be noted that the one or more processors and / or other data processing circuits described above may generally be referred to herein as "data processing circuits". The data processing circuits may be embodied in whole or in part as software, hardware, firmware, or any other combination thereof. In addition, the data processing circuit may be a single independent processing module, or may be incorporated in whole or in part into any of the other components in the computer terminal 10. As described in the embodiments of the present application, the data processing circuit acts as a processor control (e.g., selection of a variable resistor terminal path connected to an interface).

[0030] The memory 104 can be used to store software programs and modules of application software, such as program instructions / data storage devices corresponding to the data processing method in the embodiment of the present invention. The processor executes various functional applications and data processing by running the software programs and modules stored in the memory 104, that is, realizing the data processing method of the above-mentioned application program. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely arranged relative to the processor, and these remote memories may be connected to the computer terminal 10 via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0031] The display may be, for example, a touch screen liquid crystal display (LCD) that enables a user to interact with a user interface of the computer terminal 10 .

[0032] Specifically, the traditional EtherCAT slave upgrade solution based on file transfer (File Over EtherCAT, FOE) provides an effective way to update the slave firmware by transferring data files over Ethernet, but this solution usually only supports the upgrade of a single CPU. When multiple MCUs are integrated into the slave device, the traditional FOE upgrade solution is inadequate because it cannot efficiently update the firmware of multiple MCUs simultaneously or sequentially. This limitation not only increases the complexity of the upgrade operation, but may also affect production efficiency due to the extended downtime caused by upgrading one by one.

[0033] In addition, in the related art, the firmware data used for upgrading is often not backed up. This means that during the upgrade process, once the original firmware data is erased and the transmission of the new firmware data is interrupted due to an abnormal situation such as an error, disconnection, power failure, etc., the device will no longer be able to work normally because the original program has been erased. This situation not only brings great inconvenience to the maintenance of the equipment, but may also cause significant economic losses due to the sudden shutdown of the production line.

[0034] Figure 2 is a flow chart of a data processing method provided according to an embodiment of the present invention. Figure 2 As shown, the method comprises the following steps:

[0035] Step S202, receiving an update instruction from the control master station via the Ethernet communication protocol.

[0036] Step S204, in response to the update instruction, preparing a storage area in the off-chip memory.

[0037] Step S206, receiving the update data packet sent by the control master station through the Ethernet communication protocol, and storing the update data packet in the storage area.

[0038] Step S208, updating the first processor according to the update data packet, and sending an update prompt instruction to the second processor, wherein the second processor reads the update data packet from the storage area according to the update prompt instruction.

[0039] The data processing method provided by the embodiment of the present invention is mainly used in an EtherCAT system, involving an upgrade process of multiple MCUs (microcontroller units). The second processor may include multiple processors, and the first processor may have only one. First, the first processor may receive an update instruction from the control master station through the Ethernet communication protocol. Once the update instruction is received, the first processor prepares a storage area in the off-chip memory for storing the update data packet to be received. Subsequently, the first processor receives the update data packet sent by the control master station through the Ethernet communication protocol, and stores it in the previously prepared storage area. Finally, the first processor updates itself according to the update data packet, and sends an update prompt instruction to the second processor. After receiving the update prompt instruction, the second processor reads the update data packet from the storage area for updating.

[0040] This method effectively solves the problem of how to update efficiently and orderly when there are two MCUs in the slave station that need to be upgraded in the EtherCAT system. Data transmission through the Ethernet communication protocol ensures the fast and accurate transmission of update instructions and update data packets. At the same time, the use of off-chip memory as the intermediate storage medium avoids the impact on the normal operation of the system during the update process.

[0041] Through the above steps, the purpose of setting up a memory outside the chip can be achieved, so that multiple processors can access the memory in time-sharing manner and upgrade according to the data packets in the memory, thereby achieving the technical effect of improving the upgrade efficiency of slave station devices with multiple MCUs, and further solving the technical problem of low efficiency in upgrading slave station devices with multiple MCUs in the related technology.

[0042] As an optional embodiment, sending an update prompt instruction to a second processor includes: sending an update instruction to the second processor through a communication connection between the first processor and the second processor, wherein the second processor reads an update data packet from a storage area and updates data according to the update prompt instruction, and after the second processor is updated successfully, the second processor sends an update completion signal to the first processor; receiving the update completion signal sent by the second processor; and running an application based on the updated data in response to the update completion signal.

[0043] Optionally, in the process of sending the update prompt instruction to the second processor, the first processor sends the update instruction through the communication connection between the two. After receiving the update prompt instruction, the second processor reads the update data packet from the storage area and updates the data. After the update is successful, the second processor sends an update completion signal to the first processor. After receiving the update completion signal, the first processor runs the application based on the updated data.

[0044] This step ensures that the second processor can be updated in time after receiving the update instruction, and notifies the first processor after the update is successful. After confirming that the second processor has been updated successfully, the first processor runs the application based on the updated data, ensuring the orderliness and stability of the system update.

[0045] As an optional embodiment, updating the first processor according to the update data packet includes: detecting the integrity of the update data packet; and when the update data packet is complete, reading the update data packet from the storage area to perform data updating.

[0046] Optionally, during the process of updating the first processor, the integrity of the update data packet is first detected. If the update data packet is complete, subsequent update operations can be performed. This step ensures the integrity and correctness of the update data packet and avoids update failure or system abnormality caused by data packet damage or errors.

[0047] As an optional embodiment, detecting the integrity of the update data packet includes: reading first image update data and first cyclic redundancy check data from a storage area; and determining that the update data packet is complete when the first image update data and the first cyclic redundancy check data match.

[0048] Optionally, checking the integrity of the update data packet is a key step to ensure that the update process proceeds smoothly. Through a check method such as a cyclic redundancy check (CRC), it is possible to effectively detect whether an error occurs during data transmission or storage. In a specific implementation, the first image update data and the first cyclic redundancy check data are read from the storage area and compared. If the two match, it means that there is no error in the update data packet during transmission and storage, and it is complete, and subsequent update operations can be performed.

[0049] The importance of this step is that it guarantees the correctness and integrity of the update data package, thus ensuring the smooth progress of the update process. If an error occurs in the update data package during transmission or storage, it may cause update failure or system abnormality, and may even cause irreversible damage to the system. Therefore, this step is indispensable.

[0050] Figure 3 is a flow chart of another data processing method provided according to an embodiment of the present invention. Figure 3 As shown, the method comprises the following steps:

[0051] Step S302: receiving an update prompt instruction sent by the first processor.

[0052] Step S304, in response to the update prompt instruction, reading the update data packet from the storage area of ​​the off-chip memory.

[0053] Step S306: updating the second processor according to the update data packet.

[0054] Step S308, after the update is completed, sending an update completion signal to the first processor, wherein the first processor terminates the update process in response to the update completion signal.

[0055] Another data processing method provided by an embodiment of the present invention mainly relates to an update process of a second processor. First, the second processor receives an update prompt instruction sent by the first processor. Then, in response to the update prompt instruction, an update data packet is read from a storage area of ​​an off-chip memory. Then, the second processor updates itself according to the update data packet. Finally, after the update is completed, an update end signal is sent to the first processor to notify the first processor that the update process of the second processor has ended.

[0056] This method implements an independent update process of the second processor, which is independent of but interrelated with the update process of the first processor. The update process is triggered by receiving the update prompt instruction of the first processor, which ensures the orderliness and synchronization of the update. At the same time, by sending an update end signal to the first processor to notify the end of the update process, the integrity and stability of the entire system update process are ensured.

[0057] Through the above steps, the purpose of setting up a memory outside the chip can be achieved, so that multiple processors can access the memory in time-sharing manner and upgrade according to the data packets in the memory, thereby achieving the technical effect of improving the upgrade efficiency of slave station devices with multiple MCUs, and further solving the technical problem of low efficiency in upgrading slave station devices with multiple MCUs in the related technology.

[0058] As an optional embodiment, updating the second processor according to the update data packet includes: detecting the integrity of the update data packet; and when the update data packet is complete, reading the update data packet from the storage area to perform data updating.

[0059] Optionally, during the process of updating the second processor, the integrity of the update data packet is also checked. If the update data packet is complete, subsequent update operations can be performed. This step is similar to the integrity check step when updating the first processor, both of which are to ensure the correctness and integrity of the update data packet. Cyclic redundancy check and other methods are used to detect whether errors occur during data transmission or storage, thereby avoiding update failures or system abnormalities caused by data packet damage or errors.

[0060] As an optional embodiment, detecting the integrity of the update data packet includes: reading second image update data and second cyclic redundancy check data from a storage area; and determining that the update data packet is complete when the second image update data and the second cyclic redundancy check data match.

[0061] Optionally, detecting the integrity of the second processor update data packet is a key step to ensure that the second processor update process is carried out smoothly. In specific implementation, the second image update data and the second cyclic redundancy check data are read from the storage area and compared. If the two match, it means that there is no error in the update data packet during the transmission and storage process, and it is complete, and subsequent update operations can be performed.

[0062] The importance of this step is similar to the integrity check step when updating the first processor. It ensures the correctness and integrity of the update data packet of the second processor, thereby ensuring the smooth progress of the update process of the second processor. If an error occurs in the transmission or storage process of the update data packet, it may cause the update of the second processor to fail or the system to be abnormal, so this step is also indispensable.

[0063] Figure 5 is a schematic diagram of the interaction process between the master station and the slave station according to an optional embodiment of the present invention, combined with Figure 4 ,like Figure 5 As shown in the figure, the EthereCAT master sends the FOE data packet (update data packet) to the P0 port of core1 (the first processor) through the EthereCAT bus. After a series of processing, core1 stores it in the off-chip memory. The EthereCAT slave starts and then executes the application task. The master switches the slave state to the boot program. The slave receives the FOE command written by the host (if not, it detects whether the slave is switched to the initial state). If it receives it, it can determine whether the password is correct (if the password is wrong, the error is sent to the master and the FOE transmission is terminated). If the password is correct, it erases the command. Except for the corresponding area of ​​the external flash memory, and send an ACK signal to the master; then it can receive a FOE data packet from the host and write it to the external flash memory; secondly, it determines whether the data packet is received and the integrity (if incomplete, an error code is sent to the host); if complete, the slave receives and writes (if the slave does not receive it, it re-executes receiving a FOE data packet from the host and writing it to the external flash memory), then determines whether the data packet is received and the integrity (if incomplete, an error code is sent to the host); if complete, the slave receives and writes) Finally, the data information and upgrade flag are written to the external flash memory and an ACK signal is sent to the master, and finally the microcontroller is reset.

[0064] Figure 6is a schematic diagram of an interaction flow between a first processor and a second processor according to an optional embodiment of the present invention. Figure 6 As shown, Core1 is reset and started, and the Croe1 upgrade flag is read from the flash memory outside the chip. If it is upgraded, the Core1 program image data and CRC data are read from the external flash memory, and it is determined whether the image data matches the CRC data (if they do not match, it is inferred that there is an error in the updated data); if they match, the old image data is erased and the new image data is written to the chip flash memory, and the new CRC data is written, the Core1 upgrade flag is updated, and it is restarted; if it is not upgraded, the CAN upgrade program is executed; the correct image data and CRC data are read from the external flash memory; it is determined whether the image data matches the CRC data (if they do not match, it is inferred that there is an error in the data packet); a wake-up signal is sent to Croe2 (the second processor); it is determined whether the signal is received (if not, it is resent), and jumps to the application. Among them, the image is a specific file storage form that can convert programs or other data into a single file for easy storage, downloading and uploading.

[0065] Similarly, the upgrade process of the second processor is roughly the same. The difference is that Core2 will receive the wake-up signal from Core1 and determine whether the wake-up signal is received (if not, it will be received again). If the wake-up signal is received (update prompt instruction), the Croe2 upgrade flag will be read from the flash memory outside the chip and the corresponding process will be followed. After the process is completed, a reply signal (update reception signal) will be sent to Croe1 and jump to the application.

[0066] It should be noted that, for the above-mentioned method embodiments, for the sake of simplicity, they are all described as a series of action combinations, but those skilled in the art should know that the present invention is not limited by the described action sequence, because according to the present invention, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present invention.

[0067] Through the description of the above implementation methods, those skilled in the art can clearly understand that the data processing method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, a magnetic disk, or an optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present invention.

[0068] According to an embodiment of the present invention, a robot for implementing the above data processing method is also provided, the robot comprising: a slave station controller, and multiple motion control nodes, wherein the slave station controller comprises a first processor and a second processor. The robot is described below.

[0069] The first processor receives the update instruction sent by the control master station through the Ethernet communication protocol, and prepares a storage area in the off-chip memory in response to the update instruction; it is also used to receive the update data packet sent by the control master station through the Ethernet communication protocol, and store the update data packet in the storage area; it is also used to update the first processor according to the update data packet, and send an update prompt instruction to the second processor; the second processor receives the update prompt instruction sent by the first processor; it is also used to read the update data packet from the storage area of ​​the off-chip memory in response to the update prompt instruction; it is also used to update the second processor according to the update data packet; it is also used to send an update end signal to the first processor after the update is completed, wherein the first processor ends the update process in response to the update end signal.

[0070] The robot includes a slave controller and a plurality of motion control nodes. The slave controller includes a first processor and a second processor. The first processor receives an update instruction sent by a control master station through an Ethernet communication protocol, and prepares a storage area in an off-chip memory in response to the update instruction. Then, the first processor receives an update data packet sent by the control master station through an Ethernet communication protocol, and stores it in a storage area. Next, the first processor updates itself according to the update data packet, and sends an update prompt instruction to the second processor. After receiving the update prompt instruction, the second processor reads the update data packet from the storage area of ​​the off-chip memory for updating. After the update is completed, the second processor sends an update end signal to the first processor to notify the first processor that the update process has ended.

[0071] Figure 4 is a schematic diagram of the structure of a slave station controller provided according to an optional embodiment of the present invention, such as Figure 4As shown, the slave controller of the robot includes a first processor and a second processor. The first processor communicates with the control master station through the P0 interface and the P1 interface using the Ethernet communication protocol. The first processor and the second processor communicate with each other through the communication port. At the same time, a memory is provided outside the chip, and the two processors can independently transmit data with the memory. The robot realizes efficient and orderly updating by dividing the updating process of the slave controller into independent updating processes of the first processor and the second processor. At the same time, the data transmission and storage area preparation are carried out through the Ethernet communication protocol, which ensures the fast and accurate transmission and storage of the update instructions and update data packets. Finally, by sending and receiving the update prompt instruction and the update end signal, the synchronization and coordination of the update process between the first processor and the second processor are realized, and the stability and reliability of the entire system update process are ensured.

[0072] It should be noted here that the method implemented by the first processor and the second processor corresponds to steps S202-S206 and steps S302-S308 in the embodiment, and is the same as the instances and application scenarios implemented by the corresponding steps, but is not limited to the contents disclosed in the above embodiment.

[0073] A person of ordinary skill in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing the hardware related to the terminal device through a program, and the program can be stored in a non-volatile storage medium, and the storage medium may include: a flash drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0074] The embodiment of the present invention further provides a non-volatile storage medium. Optionally, in this embodiment, the non-volatile storage medium can be used to store the program code executed by the data processing method provided by the above embodiment.

[0075] Optionally, in this embodiment, the non-volatile storage medium may be located in any computer terminal in a computer terminal group in a computer network, or in any mobile terminal in a mobile terminal group.

[0076] Optionally, in this embodiment, the non-volatile storage medium is configured to store program code for executing the following steps: receiving an update instruction from a control master station via an Ethernet communication protocol; preparing a storage area in an off-chip memory in response to the update instruction; receiving an update data packet sent by the control master station via an Ethernet communication protocol, and storing the update data packet in a storage area; updating the first processor according to the update data packet, and sending an update prompt instruction to the second processor, wherein the second processor reads the update data packet from the storage area according to the update prompt instruction.

[0077] Optionally, in this embodiment, the non-volatile storage medium is configured to store program code for executing the following steps: sending an update prompt instruction to the second processor, including: sending an update instruction to the second processor through a communication connection between the first processor and the second processor, wherein the second processor reads an update data packet from a storage area and performs a data update according to the update prompt instruction, and after the second processor is updated successfully, the second processor sends an update completion signal to the first processor; receiving the update completion signal sent by the second processor; and running an application based on the updated data in response to the update completion signal.

[0078] Optionally, in this embodiment, the non-volatile storage medium is configured to store program code for performing the following steps: updating the first processor according to the update data packet, including: detecting the integrity of the update data packet; and when the update data packet is complete, reading the update data packet from the storage area to update the data.

[0079] Optionally, in this embodiment, the non-volatile storage medium is configured to store program code for performing the following steps: detecting the integrity of the update data packet, including: reading first image update data and first cyclic redundancy check data from the storage area; and determining that the update data packet is complete when the first image update data and the first cyclic redundancy check data match.

[0080] In this embodiment, the non-volatile storage medium is configured to store program code for executing the following steps: including: receiving an update prompt instruction sent by the first processor; reading an update data packet from a storage area of ​​an off-chip memory in response to the update prompt instruction; updating the second processor according to the update data packet; after the update is completed, sending an update end signal to the first processor, wherein the first processor ends the update process in response to the update end signal.

[0081] Optionally, in this embodiment, the non-volatile storage medium is configured to store program code for performing the following steps: updating the second processor according to the update data packet, including: detecting the integrity of the update data packet; and when the update data packet is complete, reading the update data packet from the storage area to update the data.

[0082] Optionally, in this embodiment, the non-volatile storage medium is configured to store program code for performing the following steps: detecting the integrity of the update data packet, including: reading second image update data and second cyclic redundancy check data from the storage area; and determining that the update data packet is complete when the second image update data and the second cyclic redundancy check data match.

[0083] An embodiment of the present invention further provides a computer program product, including a computer program, which implements the steps of the data processing method in each embodiment of the present application when the computer program is executed by a processor.

[0084] The serial numbers of the above embodiments of the present invention are only for description and do not represent the advantages or disadvantages of the embodiments.

[0085] In the above embodiments of the present invention, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0086] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only schematic. For example, the division of the units can be a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0087] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0088] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0089] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a non-volatile storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, server or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, magnetic disk or optical disk and other media that can store program codes.

[0090] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A data processing method, characterized in that: include: Receive update instructions from the control master station through Ethernet communication protocol; In response to the update instruction, preparing a storage area in an off-chip memory; Receiving an update data packet sent by the control master station through an Ethernet communication protocol, and storing the update data packet in the storage area; The first processor is updated according to the update data packet, and an update prompt instruction is sent to the second processor, wherein the second processor reads the update data packet from the storage area according to the update prompt instruction.

2. The method according to claim 1, characterized in that The sending of the update prompt instruction to the second processor includes: Sending the update instruction to the second processor through the communication connection between the first processor and the second processor, wherein the second processor reads the update data packet from the storage area and updates the data according to the update prompt instruction, and after the second processor is updated successfully, the second processor sends an update completion signal to the first processor; receiving the update completion signal sent by the second processor; In response to the update completion signal, the application program is executed based on the updated data.

3. The method according to claim 2, characterized in that The updating of the first processor according to the update data packet comprises: detecting the integrity of the update data packet; When the update data packet is complete, the update data packet is read from the storage area to perform data updating.

4. The method according to claim 3, characterized in that The detecting the integrity of the update data packet comprises: Reading first image update data and first cyclic redundancy check data from the storage area; In a case where the first image update data and the first cyclic redundancy check data match, it is determined that the update data packet is complete.

5. A data processing method, characterized in that: include: receiving an update prompt instruction sent by the first processor; In response to the update prompt instruction, reading an update data packet from a storage area of ​​an off-chip memory; updating the second processor according to the update data packet; After the update is completed, an update completion signal is sent to the first processor, wherein the first processor terminates the update process in response to the update completion signal.

6. The method according to claim 5, characterized in that The updating of the second processor according to the update data packet comprises: detecting the integrity of the update data packet; When the update data packet is complete, the update data packet is read from the storage area to perform data updating.

7. The method according to claim 6, characterized in that The detecting the integrity of the update data packet comprises: Reading second image update data and second cyclic redundancy check data from the storage area; In a case where the second image update data and the second cyclic redundancy check data match, it is determined that the update data packet is complete.

8. A robot, characterized in that: include: A slave station controller, and a plurality of motion control nodes, wherein the slave station controller comprises a first processor and a second processor, The first processor receives an update instruction sent by the control master station through an Ethernet communication protocol, and prepares a storage area in an off-chip memory in response to the update instruction; is also used to receive an update data packet sent by the control master station through an Ethernet communication protocol, and stores the update data packet in the storage area; is also used to update the first processor according to the update data packet, and send an update prompt instruction to the second processor; The second processor receives an update prompt instruction sent by the first processor; is also used to read an update data packet from a storage area of ​​an off-chip memory in response to the update prompt instruction; is also used to update the second processor according to the update data packet; is also used to send an update end signal to the first processor after the update is completed, wherein the first processor ends the update process in response to the update end signal.

9. A non-volatile storage medium, characterized in that: The non-volatile storage medium includes a stored program, wherein when the program is executed, the device where the non-volatile storage medium is located is controlled to execute the data processing method according to any one of claims 1 to 7.

10. A computer program product comprising computer instructions, characterized in that: The computer instructions are executed by a processor to execute the data processing method according to any one of claims 1 to 7.

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