Storage device, method of operating storage device, and host system

Abstract

A storage device, a method of operating the storage device, and a host system are provided. The method of operating a storage device includes receiving a clock signal corresponding to a plurality of data bits and acknowledgement (ACK) bits from a host device through a clock line during a read operation; outputting a data signal including a plurality of data bits and an ACK bit from the storage device through the data line during the read operation; generating an interrupt signal when the clock signal is at a low level prior to outputting the last data bit of the plurality of data bits; transmitting the interrupt signal to a host device through a data line; and receiving a negative acknowledgement (NACK) signal from the host device through the data line in response to the interrupt signal when there is a clock loss of the clock signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority from Korean Patent Application No. 10-2023-0101448 filed on August 3, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments of the present disclosure relate to a storage device for outputting an interrupt and a method of operating the storage device. Background Art

[0004] Typically, the System Management Bus (SMBus) is based on the Inter-Integrated Circuit (I 2 SMBus is a 2-wire interface for the SMBus bus that enables simple communication between the hardware components of the system. SMBus is commonly used in PCs for system-level management tasks such as power management, system settings, battery charging, temperature sensors, and fan control. Although the data transfer rate of these interfaces is not fast, they are reliable, easy to use, and can be connected using a relatively small number of pins. However, in some clock transfer processes of SMBus operations, it is damaged or ignored by the receiver. Therefore, it is desirable to detect whether there are any errors in the communication. Summary of the invention

[0005] Example embodiments of the present disclosure provide a storage device for outputting an interrupt and a method of operating the storage device.

[0006] According to an example embodiment of the present disclosure, a method of operating a storage device includes: receiving a clock signal corresponding to a plurality of data bits and an acknowledgement (ACK) bit from a host device via a clock line during a read operation; outputting a data signal including a plurality of data bits and an ACK bit from the storage device via a data line during a read operation; generating an interrupt signal when the clock signal is at a low level before outputting a last data bit of the plurality of data bits; sending the interrupt signal to the host device via the data line; and receiving a negative acknowledgement (NACK) signal from the host device via the data line in response to the interrupt signal when there is a clock loss of the clock signal.

[0007] According to an example embodiment of the present disclosure, a storage device includes: at least one non-volatile memory device; and a controller configured to control the at least one non-volatile memory device and receive a clock signal from a host device. The controller communicates with the host device through a first interface or outputs environmental information to the host device through a second interface. During a read operation for environmental information, when the clock signal is at a low level, the controller generates an interrupt signal and outputs the interrupt signal to the host device through a data line.

[0008] According to an example embodiment of the present disclosure, a host system includes: a storage device; and a host device connected to the storage device via a clock line and a data line. The host device is configured to send a clock signal corresponding to a plurality of data bits and an ACK bit to the storage device via the clock line, to receive an interrupt signal via the data line in a section where the clock signal is at a low level before receiving the last data bit of the plurality of data bits, to first determine whether the data bit position is 0 in response to the interrupt signal, and to secondly determine to generate a NACK signal according to the result of the first determination.

[0009] According to an example embodiment of the present disclosure, a method of operating a communication system includes: outputting a byte clock signal from a master device to a slave device through a clock line during a read operation; outputting a last bit ready (LBR) interrupt from the slave device to the master device through a data line in response to the byte clock signal; and outputting an ACK / NACK signal from the master device to the slave device through the data line in response to the LBR interrupt. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1A is a diagram showing timing according to clock omission during a write operation of a normal SMBus communication;

[0012] Figure 1B is a diagram showing a communication failure due to clock missing during a read operation of a normal SMBus;

[0013] Figure 2 is a diagram illustrating a communication operation of an SMBus according to an example embodiment of the present disclosure;

[0014] Figure 3 is a diagram illustrating an LBR interrupt operation of SMBus communication according to an example embodiment of the present disclosure;

[0015] Figure 4 is a diagram illustrating AC parameters of LBR interruption according to an example embodiment of the present disclosure;

[0016] Figure 5 is a diagram illustrating AC parameters for LBR interruption according to an example embodiment of the present disclosure;

[0017] Fig. 6A is a timing diagram illustrating SMBus operation when clock loss occurs according to an example embodiment of the present disclosure;

[0018] Figure 6Bis a timing diagram illustrating SMBus operation when clock loss does not occur according to an example embodiment of the present disclosure;

[0019] Figure 7 is a diagram illustrating a host system according to an example embodiment of the present disclosure;

[0020] Figure 8 is a diagram showing a method according to an example embodiment Figure 7 A diagram of the storage device shown; and

[0021] Fig. 9 is a ladder diagram illustrating a temperature information output operation of a storage device according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0022] Hereinafter, embodiments of the present disclosure will be described as follows with reference to the accompanying drawings.

[0023] According to an embodiment of the present invention, a storage device and an operating method can immediately sense and correct a situation in which some clock transfer processes of SMBus (System Management Bus) operations are damaged or ignored by the receiver through interrupts. The storage device can periodically send an interrupt based on the SMBDAT signal at a specific point for each byte transmitted. The host device can synchronize by generating additional clocks based on the interrupts received from the storage device to match the data output points and comparing them in the event of a mismatch.

[0024] Typically, the SMBus interface supports a packet error detection feature, a timeout determination feature, and a low power mode feature. The packet error detection feature checks if there are any errors in packet transmission. The timeout determination feature allows the SMBus controller to reset the device if an operation is not completed within a specific time, allowing the bus to continue operating. The low power mode feature allows the SMBus device to save energy by switching to a low power mode. Because of these features, the SMbus supports stable and efficient communication between hardware systems and is used in a variety of applications, including power management, firmware updates, supply chain management, and temperature monitoring.

[0025] The following is a simple explanation of the terms used in the SMBus interface. The SMBus includes a physical layer that communicates with system management information, and includes its operation method and content. The SMBus includes two signals for controlling clock and data. The SMBus master (hereinafter, the master) is an entity with communication rights in this regard. It has full control over clock generation and control and can generate a start (START) / stop (STOP) condition. The SMBus slave (hereinafter, the slave) reads or controls the SMBDAT signal according to the clock signal generated by the master. In the section where SMBCLK is high, the level of SMBDAT cannot be changed by the slave. SMBCLK is a signal controlled by the master to generate a clock signal. The logical value of SMBDAT corresponding to the section where SMBCLK is high is read or written. SMBDAT is a signal controlled to generate a logical value according to the clock signal. During a read operation, the slave controls SMBDAT. During a write operation, the master controls SMBDAT. The acknowledgement / negative acknowledgement (ACK / NACK) bit is controlled by the receiver. The ACK / NACK bit is the ninth bit attached to each data byte. By the value of this bit (1: NACK / 0: ACK), it can be confirmed that the corresponding part has received the corresponding data. Here, for ease of description, the terms "ACK bit" and "ACK signal" and the terms "NACK bit" and "NACK signal" are used interchangeably.

[0026] A START condition may be generated only by a master. A START condition is an interrupt that signals the start of an SMBus command. A START condition is generated by changing SMBDAT from high to low in a segment where SMBCLK is high. A START condition is generated based on a falling edge trigger of SMBDAT. A STOP condition may be generated only by a master. A STOP condition is an interrupt that signals the end of an SMBus command. A STOP condition may be generated by changing SMBDAT from low to high in a segment where SMBCLK is high. In other words, a STOP condition is generated based on a rising edge trigger of SMBDAT.

[0027] Typically, only signals can be generated by the master. The slave simply outputs or reads data accordingly. There is no way to check for omissions of signals. This means that data can be output only without distinguishing whether the corresponding signal is a bit address that is pulled forward due to a previous omission. Even if the signal that the master wants to create is lost, it cannot notice this situation and continues to receive delayed data values ​​from the slave. Therefore, SMBus reads can be performed with invalid values. Ultimately, it can receive device failure judgments from the master.

[0028] Typically, the master device regularly accesses and records status flags or critical warning areas such as error reports through the SMBus, for example, every second. During this process, some critical warnings may be considered to have been set, delayed data values ​​may be read, or the device may fail by reading abnormal temperatures. Many situations are processed as errors by one detection. In this way, even an in-band communication area that is operating normally may be limited or terminated.

[0029] Normally, the SMBus continues to communicate until the master generates a STOP condition. Ultimately, although the problem situation continues until the next byte, it cannot end the process. It persists in communicating to receive invalid data without knowing when it ends. In addition, since the SMBus master can communicate with only one slave at a time, it cannot communicate with other slaves during this segment, resulting in communication failures and delays.

[0030] Figure 1A is a diagram showing the timing according to clock omission during a write operation of a normal SMBus communication. Basically, since the above-mentioned communication problem due to clock omission may not occur in a write operation, this may mean that when a signal loss occurs in a write operation, at the time point when the master device sets SMBDAT to receive ACK / NACK, the slave device may wait to receive data without knowing whether there is a signal loss, and may keep SMBDAT high, so that, from the perspective of the master device, SMBDAT being high may be automatically determined as a write failure by receiving NACK from the slave device.

[0031] Figure 1B is a diagram showing a communication failure due to clock missing during a read operation of a normal SMBus. Figure 1B As shown in FIG. 1 , when the slave device outputs "0b" at the time point when the master device wants to respond with ACK, it may overlap with the ACK sent from the perspective of the master device. Therefore, even if the clock signal is lost, the master device cannot recognize this situation and may regard this situation as normal operation. Then, invalid data may continue to be read from the slave device.

[0032] According to the storage device and the method of operating the storage device of the example embodiment, the situation in which a part of the SMBCLK is not sent or received can be identified, and the termination and bus idle commands can be executed, thereby preventing the situation in which the system bus is occupied by unnecessary communication, preventing communication delays and conflicts with other slave devices. In the example embodiment, as the slave device discards the communication due to an error in the clock, the problem of continuously reading incorrect data (e.g., "0xFF") can be solved. In addition, in the example embodiment, the continuity of the clock supply can be obtained by deploying an alternative module to maintain the supply of the clock temporarily deactivated in the low power mode in real time. In the example embodiment, for clock transmission / reception defects occurring between operations, the two communication entities can recover the clock by communicating and identifying defective conditions based on interrupts rather than modules, and the communication can be terminated based on the interrupt criteria.

[0033] Figure 2 is a diagram showing the communication operation of the SMBus according to an example embodiment. In an example embodiment, two communicating entities can identify a loss in a signal corresponding to 9 bits (8 data bits + 1 ACK / NACK bit) forming each byte. Therefore, when a loss problem occurs, the master device (or slave device) can send information to the slave device (or master device) through a signal, or at least provide an independently identifiable standard. Here, the receiving side can be an entity that responds with ACK / NACK, and can be a side that attempts to read during a read operation, and can be a side that receives data between write operations.

[0034] In an example embodiment, the slave device may send an interrupt via SMBDAT so that the master device checks for signal loss. To introduce this new interrupt, the following two points may be considered: Basically, it is prohibited to change the SMBDAT level in a segment where SMBCLK is high. In a segment where SMBCLK is low, changes in the SMBDAT level may not be recognized as an interrupt and may not affect existing communications. With SMBDAT being recognized for transmission and reception in bytes, the slave device may use the time before and after the boundary between bytes as a standard point to send an interrupt at that point in time. Therefore, in the segment before the transmission of the eighth-to-last bit (bit 0) between the transmission of each byte, by “suspending the slave device while SMBCLK is low (t_ LOW )”, an interrupt may be sent to the host device. Here, bit 0 may mean the data bit position of the eighth-to-last bit. In the following description, the interrupt may be referred to as a last bit ready (hereinafter, LBR) interrupt.

[0035] Figure 3is a diagram showing the LBR interrupt operation of SMBus communication according to an example embodiment. From the perspective of the master device, determining whether there is a signal loss based solely on the data value may have uncertainty. For example, when the device temperature is read as abnormally high, the master device does not arbitrarily determine whether the temperature is really high (due to signal loss) or a misread value. In addition, even if the signal is lost, the pushed data value may be accidentally read as a value within the normal range. Therefore, it is possible to ensure that the physical signal is lost by receiving an interrupt from the slave device to ensure high reliability. The master device may receive an interrupt that occurs between the ends of each byte from the slave device, and the master device may use the interrupt as a standard to determine synchronization with the generated signal. Ultimately, the LBR interrupt may become a standard that can periodically check for each byte whether the time point desired by the master device matches the time point identified by the slave device.

[0036] In an example embodiment, the master device may keep SMBDAT low for at least 4.7 μs before outputting the last bit and after generating one clock.

[0037] When the signal is lost, the boundary time point between bytes recognized by the slave device and the boundary time point between bytes desired by the master device may differ by several bits. At the same time, since the slave device expects to receive an interrupt at the previously recognized boundary time point, when receiving an interrupt at a different time point, the device can detect an error through the interrupt.

[0038] The slave device may need to transfer control of the SMBDAT to the master device to receive ACK / NACK immediately after the output reaches the 8th bit. Therefore, from this point in time, the slave device may not randomly generate interrupts. Therefore, in the 0 to 7 bit output segment in which the slave device has control of the SMBDAT, an LBR interrupt may be generated just before the last bit is output. Therefore, the data address identified by the slave device may be sent to the master device. The master device can determine subsequent operations based on whether the time point matches by comparing the time point with the criteria of the generated clock signal.

[0039] The LBR interrupt generated as described above may be used solely for timing synchronization between two communicating entities. As the interrupt is used in a section where no data is output, the interrupt may not affect existing SMBus communications.

[0040] When it is determined that the byte transfer has not yet completed, the slave device may maintain SMBDAT. Therefore, the master device may not be able to generate a STOP condition. Therefore, it may be necessary to temporarily adjust the byte alignment standard for the slave device. Once an error has been determined, it may be important to terminate the communication as soon as possible. Therefore, when this problem occurs during a read, the master device may generate an additional clock signal according to the slave device standard and may terminate the read operation under NACK and STOP conditions.

[0041] Figure 4 is a diagram showing AC parameters of LBR interruption according to an example embodiment. Unlike the Peripheral Component Interconnect Express (PCIe) interface in which two communicating entities operate through their own transceivers, the SMBus interface can physically share a transmitter (SMBDAT output control). Therefore, the control right of SMBDAT can be changed according to the communication time point. This control right can be presented through AC parameters. Unlike ACK / NACK, the slave device can have SMBDAT control right over the entire segment between bits. Figure 4 As shown, at t_ LOW Within the range of a segment, an LBR interrupt can be generated by setting SMBDAT as high as the desired segment and again holding SMBDAT low.

[0042] Figure 5 is a diagram illustrating AC parameters for LBR interruption according to an example embodiment. Figure 5 Various AC parameters for control transfer at various frequencies are shown.

[0043] LBR interrupt generation according to example embodiments may need to satisfy the following equation.

[0044] [Equation 1]

[0045] t_ LOW >t HD：DAT +t SU：DAT +t LBR_HIGH

[0046] To set the LBR interrupt time t LBR_HIGH range, can be targeted for data retention time t HD：DAT and data setting time t SU：DAT By substituting the upper and lower limits and starting from the clock low period t_ LOW Subtract it from the LBR interruption time t LBR_HIGH Operational stability can be ensured by providing an arbitrary margin to the calculated values.

[0047] Fig. 6Ais a timing diagram showing SMBus operation when clock loss occurs according to an example embodiment. Between read operations, just before the 8th bit (the last bit) is output, the slave device may send an LBR interrupt via SMBDAT. The master device may compare the byte alignment with the LBR interrupt standard, and when the time point of the predetermined data bit (i.e., bit 0) is different from the expected time point, the master device may immediately respond with NACK, and the read operation may be terminated. In an example embodiment, the master device may terminate the read operation with a STOP condition corresponding to the NACK signal (or NACK bit). For example, when the predetermined data bit position (i.e., bit 0) is not 0 (that is, the data bit position before termination is not the expected time point) in response to the LBR interrupt, the master device may output a NACK signal to the slave device via the data line. The master device may additionally generate SMBCLK according to the standard of the slave device and may terminate the read operation with a NACK signal and under a STOP condition.

[0048] Figure 6B is a timing diagram showing SMBus operation when clock loss does not occur according to an example embodiment. The bit address desired by the master device may match the time point expected by the slave device based on the generated interrupt. The master device may send an ACK and may maintain the read operation normally. For example, when the predetermined data bit position (i.e., bit 0) is 0 in response to the LBR interrupt (that is, the data bit position before termination is the expected time point), the master device may output an ACK signal (or ACK bit) to the slave device through the data line.

[0049] When a communication-related problem occurs, the normal SMBus may not initialize interfaces other than the SMBCLK 25ms low hold timeout or SMBRST#. Unlike the above example, in an example embodiment, by immediately identifying a clock loss situation, unnecessary communication delays and error reports caused by incorrect data values ​​can generally be resolved. In an example embodiment, by introducing an interrupt to switch another SMBDAT without adding a HW module, the operational reliability and problem recovery function of the slave device can be improved without adding additional costs.

[0050] Typically, the bandwidth of a high-speed interface increases. As the amount of data processed for a storage device increases, the related management interface information also increases. Therefore, the storage device may basically support the Management Component Transport Protocol (MCTP). Here, MCTP may be basically used to exchange function and setting information, and may play an important role in managing and monitoring the storage device. MCTP may be the main technology supporting the Intelligent Platform Management Interface (IPMI). IPMI may provide a standardized management interface for servers, storage devices, network devices, etc. Through the interface, a system manager may remotely monitor the status of servers and storage devices, may diagnose problems, and may perform management functions. MCTP may be mainly used to transfer data between various management sessions, and may encapsulate and transmit IPMI messages. Therefore, interaction and management between servers and storage devices may be effectively performed. MCTP may be one of the management interface functions of the storage device and may be operated through IPMI and may support effective communication between the server and the storage device. Therefore, the system manager may remotely monitor and manage the storage device. In addition, the size of the data structure of the Vital Product Data (VPD) also increases. The VPD may include important information about the product embedded in the storage device. Typically, a VPD may include the following data: Product identification data, which may include product identification information such as manufacturer, product name, serial number, model number, etc. Device information may include basic information about the device, such as device capacity and interface type, speed, etc. Configuration data may be device configuration information and may include functions supported by the device, options, and settings information. Vital product pages VPP may include multiple vital product pages in the VPD. Each VPP may have information about a specific section and may contain information from various aspects (e.g., logical devices, physical devices, fans, and temperatures).

[0051] Recently, in addition to the existing simple operation of only periodically reading the minimum device information from the BMC, the SMBus can support the entire fast non-volatile memory (NVMe) command and related management interface commands processed in-band. Therefore, as the amount of data to be processed increases, when the SMBus for a specific slave device becomes congested, other slave devices in the same environment may also experience communication delays. From the perspective of the host environment, the management interface system delay caused by the slave device may be more valued than the in-band problem. This is because, unlike the in-band physical layer that exists separately for each slave device, in the SMBus, other slave devices and a single host can occupy a single bus in many-to-one communication. Therefore, on a high-speed communication system of 32.0GT / s or higher, the self-error recovery and early termination functions for the out-of-band system based on SMBus according to the example embodiment can ensure high stability.

[0052] In an example embodiment, the SMbus master device may be a host device, and the SMbus slave device may be a storage device.

[0053] Figure 7 is a diagram illustrating a host system according to an example embodiment. Figure 7 , the host system 1 may include a storage device 10 (SSD) and a host device 20 .

[0054] The host device 20 can store data in the storage device 10 or read data from the storage device 10 through the main channel CH. Here, the main channel CH can send and receive data according to various host interfaces. For example, the host interface can be at least one of a non-volatile memory express (NVMe) interface, a peripheral component interconnect express (PCIe), a serial attachment (SATA), a small computer system interface (SCSI), a serial attached SCSI (SAS), a universal storage bus (USB) attached SCSI (UAS), an Internet small computer system interface (iSCSI), a Fibre Channel, and a Fibre Channel over Ethernet (FCoE).

[0055] The host device 20 may communicate with the storage device 10 through an auxiliary channel. Here, the auxiliary channel may send and receive data according to an SMBus interface supporting a management component transfer protocol (MCTP). In a read operation, the host device 20 may send an SMBCLK signal to the storage device 10 through a clock line and may receive a plurality of data bits and an ACK bit from the storage device 10 through a data line in response to the SMBCLK signal, and in a section in which the SMBCLK signal is at a low level before the last data bit of the plurality of data bits is sent, an LBR (Last Bit Ready) interrupt signal may be received through the data line, it may be determined whether the data bit position in response to the LBR interrupt signal is 0 (i.e., bit 0), and a NACK signal may be generated according to the determination result.

[0056] In an example embodiment, when the data bit position in response to the LBR interrupt signal is 0, the host device 20 may output an ACK signal to the storage device 10 through the data line. In an example embodiment, when the data bit position in response to the LBR interrupt signal is not 0, the host device 20 may output a NACK signal to the storage device 10 through the data line. In an example embodiment, the read operation may be terminated in response to the NACK signal. In an example embodiment, the host device 20 may additionally generate an SMBCLK signal according to the standard of the storage device 10, and may terminate the read operation by the NACK signal and the STOP condition.

[0057] Figure 8 is a diagram showing a method according to an example embodiment Figure 7 The storage device shown in FIG. Figure 8 , the storage device 10 may include at least one non-volatile memory device NVM (100) and a controller CTRL (200).

[0058] At least one nonvolatile memory device 100 may be implemented to store data. The nonvolatile memory device 100 may be a NAND flash memory, a vertical NAND flash memory, a NOR flash memory, a resistance random access memory (RRAM), a phase change memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM), and a spin transfer torque random access memory (STT-RAM). In addition, the nonvolatile memory device 100 may be implemented in a three-dimensional array structure. In an example embodiment, the charge storage layer may be applied to a flash memory device composed of a conductive floating gate, and may also be applied to a charge trap flash memory CTF in which the charge storage layer is formed as an insulating film. In the following description, for ease of description, the nonvolatile memory device 100 will be referred to as a vertical NAND flash memory device (VNAND).

[0059] In addition, the nonvolatile memory device 100 may be implemented to include a plurality of memory blocks BLK1 to BLKz (z is an integer of 2 or more) and a control logic 150. Each of the plurality of memory blocks BLK1 to BLKz may include a plurality of pages Page 1 to Page m (m is an integer of 2 or more). Each of the plurality of pages Page 1 to Page m may include a plurality of memory cells. Each of the plurality of memory cells may store at least one bit.

[0060] The control logic 150 may be implemented to receive a command and an address from the controller CTRL 200 and may perform an operation (programming operation, reading operation, erasing operation, etc.) corresponding to the received command on the memory cell corresponding to the address. In addition, the control logic 150 may be implemented to control the nonvolatile memory device 100 using control signals CLE, ALE, CE, WE, and RE. For example, during a read operation, the chip enable signal CE may be activated, CLE may be activated in a command transmission section, ALE may be activated in an address transmission section, and RE may be switched in a section in which data is transmitted through a data signal line (DQ). The data strobe signal (DQS) may be switched by a frequency corresponding to a data input / output rate. The read data may be synchronized with the data strobe signal (DQS) and may be transmitted in sequence.

[0061] The controller CTRL ( 200 ) may be implemented to control at least one nonvolatile memory device 100 . The controller 200 may include at least one processor 210 (central processing unit CPU), a buffer memory 220 , and an error correction circuit 230 .

[0062] The processor 210 may be implemented to control the overall operation of the storage device 10. The processor 210 may perform cache / buffer management, firmware management, garbage collection management, wear leveling management, data deduplication management, read refresh / reclaim management, bad block management, multi-stream management, mapping management of host data and non-volatile memory, quality of service (QoS) management, system resource allocation management, non-volatile memory queue management, read level management, erase / program management, hot / cold data management, power loss protection management, dynamic thermal management, initialization management, and inexpensive disk redundant array (RAID) management. In addition, the processor 210 may be implemented as a drive parameter optimizer. The parameter optimizer may derive optimal firmware parameters in response to a firmware parameter setting request from an external device (e.g., a host), and may update the derived parameters as firmware parameters. For example, the parameter optimizer may infer performance equations about firmware parameters by performing machine learning using multiple learning models and may derive optimal firmware parameters using the inferred performance equations.

[0063] The buffer memory 220 may be implemented as a volatile memory (e.g., static random access memory (SRAM), dynamic RAM (DRAM), synchronous RAM (SDRAM)) or a nonvolatile memory (flash memory, phase change RAM (PRAM), magnetoresistive RAM (MRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM)).

[0064] The error correction circuit 230 may be implemented to generate an error correction code (ECC) during a programming operation and to recover data using the error correction code during a read operation. That is, the error correction circuit 230 may generate an error correction code to correct a failed bit or an error bit of data received from the nonvolatile memory device 100. In addition, the error correction circuit 230 may form data with a check bit added by performing error correction coding on the data provided by the nonvolatile memory device 100. The check bit may be stored in the nonvolatile memory device 100. In addition, the error correction circuit 230 may perform error correction decoding on the data output from the nonvolatile memory device 100. The error correction circuit 230 may correct errors using parity checking. The error correction circuit 230 may correct errors using low-density parity check (LDPC) codes, BCH codes, turbo codes, Reed-Solomon codes, convolutional codes, recursive systematic codes (RSC), coded modulation such as trellis coded modulation (TCM) and block coded modulation (BCM). When error correction is not possible in the error correction circuit 230 , a read retry operation may be performed.

[0065] Fig. 9 is a ladder diagram showing a temperature information output operation of a storage device according to an example embodiment. For example, the temperature information may be one of the environmental information. Fig. 9, the temperature information output operation of the storage device SSD can be performed as follows.

[0066] The storage device SSD may periodically / non-periodically detect the temperature of the storage device SSD (S10). The storage device SSD may receive an SMBCLK signal from a host device (S20). The storage device SSD may generate an SMBDAT with an interrupt under predetermined conditions (S30). The storage device SSD may output the SMBDAT with an interrupt to the host device (S40). The host device may determine whether the SMBCLK is synchronized based on the interrupt (S50). When SMBCLK synchronization is not required, the host device may output an ACK signal and may continuously output a periodic SMBCLK. When SMBCLK synchronization is required, the host device may generate a NACK signal, may adjust the SMBCLK, and may output the adjusted SMBCLK to the storage device SSD (S60). Then, the storage device SSD may output temperature information corresponding to the temperature detected under predetermined conditions to the host device using the SMBDAT (S70).

[0067] In an example embodiment, when there is a clock loss of the SMBCLK signal, a negative acknowledgement (NACK) signal may be received from the host device through the data line in response to the interrupt signal. In an example embodiment, the read operation may be terminated in response to the NACK signal. In an example embodiment, when there is no clock loss of the SMBCLK signal, the host device may output an ACK signal through the data line in response to the interrupt signal. In an example embodiment, the number of the plurality of data bits may be 8. In an example embodiment, to generate an interrupt signal, the data line may be switched within a predetermined time period in a section in which the SMBCLK signal is at a low level. In an example embodiment, the predetermined time period may be determined by subtracting the data hold time and the data setup time from the clock low period. In an example embodiment, the predetermined time period may be between 0.12μs and 2.7μs. In an example embodiment, temperature information may be detected from a temperature sensor. The temperature sensor may be included in a storage device SSD. In an example embodiment, when an ACK signal is received from the host device through the data line, the temperature information may be output to the data line. In an example embodiment, the host device may terminate the read operation through a NACK signal under a STOP condition.

[0068] In an example embodiment, to check for errors due to clock loss in the output of temperature information, generating an interrupt may be only an example embodiment. The example embodiment may be applied to the output of any data regarding the Management Component Transport Protocol (MCTP) mentioned in the SMBus specification.

[0069] For example, example embodiments may be used for status flags (in order to check the corresponding SMBus communication status and error reporting), SMART warnings (in order to check the corresponding operation error reporting in the SSD device), and device life (use limit), as well as output of VID (vendor ID), serial number, etc. Therefore, when a clock loss occurs in the serial number area, an incorrect serial number value may be read, and a device loss (the server environment can no longer detect the device) situation may be identified and reported. In addition, when a clock loss occurs under the assumption that a vendor ID (VID) is read, the device may be identified as a non-existent device or a device from another vendor, thereby preventing the server from setting an expected value different from the SSD.

[0070] The above-mentioned device can be implemented by a combination of hardware components, software components and / or hardware components and software components. For example, the device and components described in the example embodiment can be implemented using one or more general or special computers (such as processors, controllers, arithmetic logic units (ALUs), digital signal processors, microcomputers, field programmable gate arrays (FPGAs) and programmable logic units (PLUs), microprocessors or any other devices that can execute instructions and respond). The processing device can execute an operating system (OS) and one or more software applications running on the operating system. In addition, the processing device can access, store, manipulate, process and generate data in response to the execution of the software. For ease of description, a single processing device can be used, but the processing device may include multiple processing elements or multiple types of processing elements. For example, the processing device may include multiple processors or a processor and a controller. In addition, other processing configurations such as parallel processors are also possible.

[0071] Software may include computer programs, codes, instructions, or a combination of one or more of them, and may configure a processing device to operate as desired or to instruct the processing device independently or collectively. The software and / or data may be implemented in any kind of machine, component, physical device, virtual device, computer storage medium, or device interpreted by the processing device or providing instructions or data to the processing device. The software may be distributed over a network of computer systems and may be stored or executed in a distributed manner. The software and data may be stored on one or more computer-readable recording media.

[0072] The present invention can prevent the signal loss phenomenon during SMBus reading. It can improve the data loss that occurs in the case of SMBus reading. The present invention can ensure the reliability of signal denial during communication between the master device and the slave device. The present invention can perform operations to prevent unnecessary occupation of the bus.

[0073] According to the aforementioned example embodiments, the storage device and the method of operating the storage device may generate and output an LBR interrupt under a predetermined condition of a clock signal during a read operation.

[0074] In addition, the storage device and the method of operating the storage device can utilize LBR interruption to avoid bus occupation due to clock omission.

[0075] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the invention as defined by the appended claims.

Claims

1. A method for operating a storage device, the method comprising: receiving a clock signal corresponding to a plurality of data bits and an acknowledge bit from a host device via a clock line during a read operation; outputting a data signal including the plurality of data bits and the confirmation bit from the storage device via a data line during the read operation; Before outputting a last data bit of the plurality of data bits, when the clock signal is at a low level, generating an interrupt signal; sending the interrupt signal to the host device via the data line; as well as When there is a clock loss of the clock signal, a negative acknowledgement signal is received from the host device through the data line in response to the interrupt signal.

2. The method according to claim 1, further comprising: The read operation is terminated in response to the negative acknowledge signal.

3. The method according to claim 1, further comprising: When there is no clock loss of the clock signal, an acknowledgement signal is received from the host device through the data line in response to the interrupt signal.

4. The method according to claim 1, wherein: The number of the plurality of data bits is eight.

5. The method according to claim 1, wherein: The step of generating the interrupt signal includes switching the signal of the data line within a predetermined time period in a section where the clock signal is at a low level.

6. The method according to claim 5, wherein: The predetermined period of time is determined by subtracting a data holding time and a data setting time from the section in which the clock signal is at a low level.

7. The method according to claim 6, wherein: The predetermined time period is between 0.12 μs and 2.7 μs.

8. The method according to claim 1, further comprising: Temperature information is detected from a temperature sensor included in the storage device.

9. The method according to claim 8, further comprising: When a confirmation signal is received from the host device through the data line, the temperature information is output to the data line.

10. The method according to claim 1, further comprising: The read operation is terminated by the host device in a stop condition corresponding to the negative acknowledge signal.

11. A storage device, comprising: at least one non-volatile memory device; as well as a controller configured to control the at least one nonvolatile memory device and receive a clock signal from a host device, The controller is configured to communicate with the host device through a first interface or output the environmental information to the host device through a second interface, and The storage device is configured to: during a read operation for the environmental information, when the clock signal is at a low level, enable the controller to generate an interrupt signal, and output the interrupt signal to the host device through a data line.

12. The storage device according to claim 11, wherein: The first interface comprises a fast non-volatile memory interface, and The second interface includes a system management bus interface supporting a management component transmission protocol.

13. The storage device according to claim 11, wherein: receiving the clock signal corresponding to the data bit and the confirmation bit from the host device through the clock line, and The interrupt signal is generated before the last bit of the data bits is output.

14. The storage device according to claim 11, wherein: When there is a missing clock in the clock signal, the storage device is configured so that the controller receives a negative acknowledgement signal from the host device through the data line in response to the interrupt signal.

15. The storage device according to claim 11, wherein: The environmental information includes temperature information, and Wherein, the storage device further includes at least one temperature sensor configured to generate the temperature information.

16. A host system, comprising: Storage devices; as well as A host device connected to the storage device via a clock line and a data line, Wherein, the host device is configured as: sending a clock signal corresponding to a plurality of data bits and confirmation bits to the storage device via the clock line, receiving a data signal including the plurality of data bits and the confirmation bit from the storage device through the data line, Before receiving the last data bit of the plurality of data bits, receiving an interrupt signal through the data line in a section where the clock signal is at a low level, first determining whether a predetermined data bit position is at an expected time point in response to the interrupt signal, and A second determination is made to generate a negative acknowledgement signal based on a result of the first determination.

17. The host system according to claim 16, wherein: When the predetermined data bit position is at the expected time point in response to the interrupt signal, the host system is configured to cause the host device to output a confirmation signal to the storage device through the data line.

18. The host system according to claim 16, wherein: When the predetermined data bit position is not at the expected time point in response to the interrupt signal, the host system is configured to cause the host device to output the negative acknowledgement signal to the storage device through the data line.

19. The host system according to claim 16, wherein: The host system is configured to cause the host device to terminate a read operation of the storage device in response to the negative acknowledge signal.

20. The host system of claim 16, wherein: The host system is configured so that the host device additionally generates a clock signal according to a standard of the storage device and terminates a read operation in response to the negative acknowledge signal.

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