Adaptive switch implementation method based on universal Serdes

Abstract

The invention discloses an adaptive switch implementation method based on a universal Serdes, and relates to the technical field of chip communication interfaces. According to the invention, the method is realized by adopting a modularly designed switch of the adapter equipment, and the minimum module of the switch of the adapter equipment is an R-NI-Link module, thereby facilitating the realization of routing switching of different port numbers and performances; delay can be adjusted between different R-NI-Link modules through self-definition or self-adaption, so that the delay uniformity between different ports is met; and the R-NI-Link module comprises a Route module which represents a route and an NI-Link module which represents a serdes (Server). According to the invention, an adaptive topological structure switch is adopted to satisfy address routing in different application scenarios; the expansibility of different application scenes is realized by adopting a modular design; and a self-adaptive structure is adopted to meet delay requirements in different scenes.

Description

Technical Field

[0001] The invention belongs to the technical field of chip communication interface, and in particular relates to a method for realizing an adaptive switch based on a general Serdes. Background Art

[0002] At present, information exchange is divided into three layers at the hardware level: (1) Information exchange on circuit boards: interconnection within chips or packages, bus interconnection, chiplet technology; (2) Information exchange within servers: PCIe Switch, NV Switch, network exchange; (3) Information exchange between servers: network exchange;

[0003] Among them, PCI Express Switch is a device for extending PCI Express (PCIe) bus, which allows multiple PCIe devices to share limited PCIe channel resources. The main functions of PCIe Switch include: (1) Expansion: PCIe Switch can expand one PCIe port into multiple ports to connect more devices. This function is particularly important when the PCIe channels provided by the CPU are not sufficient to meet system requirements. (2) Partitioning: Similar to VLAN in a network switch, PCIe Switch can create different partitions to assign certain devices to specific servers or systems, thereby achieving flexible resource allocation and management. (3) Non-transparent bridging: In scenarios where direct communication between multiple systems is required, PCIe Switch can achieve data exchange between different systems through address translation, which is very useful for synchronizing data between multiple controllers in a storage system. (4) Dynamic allocation: Some advanced PCIe Switches support dynamic allocation, allowing device allocation to be dynamically changed during system operation, thereby improving resource utilization efficiency. PCIe Switch must be designed to follow the tree topology of the PCIe bus to maintain backward compatibility with older PCI software and ensure that system software can enumerate and configure PCIe devices in the same way. In addition, PCIe Switch can route data packets to the correct port according to the address information of the data packet, acting as a packet router. In general, PCIe Switch is a key component for achieving efficient and flexible PCIe bus expansion and management, especially for high-end servers, storage systems, and high-density modular server platforms. However, this technology has the following disadvantages: (1) PCIe Switch is based on a CPU-centric architecture design, which does not support the increasing number of GPU servers; (2) PCIe architecture only supports tree topology, which limits the flexibility and redundancy of the network;

[0004] In addition, NV Switch is a high-speed interconnect technology launched by NVIDIA to connect multiple GPUs to meet the computing power requirements of high-performance computing (HPC) and artificial intelligence (AI) applications. It is based on the NVLink protocol and provides higher data transfer rates and bandwidth than traditional PCIe interfaces, thereby reducing the latency of inter-GPU communication and improving the overall throughput of the system; NV Switch technology was first introduced in the Volta architecture and further developed in the subsequent Hopper architecture; in the Volta architecture, the communication rate between GPUs can reach 300GB / s, and in the Hopper architecture, this rate is increased to 900GB / s. The number of NVLink links supported by NV Switch has also been expanded from 6 in Volta to 18 in Hopper, greatly optimizing the efficiency and flexibility of data exchange; the design of NV Switch allows the construction of a completely non-blocking, fully interconnected GPU system, supporting larger-scale GPU interconnection to form a powerful computing cluster. For example, in the DGX-2 server, the use of NVSwitch enables all GPU cards in the server to be fully interconnected, supporting 8 pairs of GPUs to communicate simultaneously without any intermediate GPU hops, achieving direct high-speed communication, thereby significantly improving the efficiency of data transmission and overall computing performance; NVIDIA also launched NVLink-C2C technology, which is a chip-to-chip, die-to-die interconnect technology that supports consistent interconnection between custom dies and NVIDIA GPUs, CPUs, DPUs, NICs, and SoCs. NVLink-C2C's interconnection links have significantly improved energy efficiency and area efficiency compared to PCIe Gen 5 on NVIDIA chips, and can achieve consistent interconnection bandwidth of 900GB per second or even higher; as technology develops, NV Switch and NVLink will continue to promote the communication capabilities and system performance of multi-GPU systems, providing support for the next generation of terabyte supercomputers and large-scale AI training; the third-generation NV Switch is used in the DGX H100 system, and by connecting multiple H100 GPUs and NVSwitch chips, full-bandwidth connections are achieved within the server, further improving the performance of multi-GPU interconnection. However, this technology has the following shortcomings: closedness. NV Switch has high bandwidth and low latency characteristics and can only be used for data sharing between NVIDIA GPUs, but cannot share data with CPUs and other accelerators.

[0005] Both of the above solutions cannot achieve large-scale general node interconnection. As computing power increases, the interconnection bottleneck becomes more and more prominent. Therefore, this technical solution proposes an adaptive switch implementation method based on general Serdes. Summary of the invention

[0006] The present invention provides an adaptive switch implementation method based on universal Serdes, which adopts an adaptive topology switch to meet address routing in different application scenarios; adopts modular design to achieve easy scalability in different application scenarios; adopts an adaptive structure to meet delay requirements in different scenarios; and solves the problems in the background technology in summary.

[0007] In order to solve the above technical problems, the present invention is achieved through the following technical solutions:

[0008] The method for implementing an adaptive switch based on a general Serdes of the present invention comprises the following contents:

[0009] The modular design of the switch is adopted. The smallest module of the switch is the R-NI-Link module, which is convenient for realizing routing and switching of different port numbers and performances. The delay between different R-NI-Link modules can be adjusted by customization or adaptive adjustment to meet the uniformity of delay between different ports.

[0010] The R-NI-Link module includes a Route module representing routing and a NI-Link module representing serdes; wherein NI specifically stands for net interface, representing the interface module of routing and serdes, and Link realizes the efficient transmission function of serdes;

[0011] The Route module uses network on chip to implement routing functions, so as to meet the requirements that the routing topology between different R-NI-Link modules can be adjusted. The adjustment is customized or adaptive, and supports address routing at different levels.

[0012] The Route module and the NI-Link module perform data exchange at the link layer to reduce the overall delay of the adapter device switch;

[0013] The adapter device switch is also provided with an output interface output, which serves as an extended interconnection between multiple adapter devices switches and has the same function as the Route module.

[0014] Furthermore, the application of the switch implementation method includes using the CXL protocol to implement the CXL protocol-supported peripherals in the extended AI server, wherein the peripherals include a CPU, an NPU, a memory, and a hard disk.

[0015] Furthermore, the application of the switch implementation method includes using a custom protocol to implement scalable low-latency related application scenarios.

[0016] Compared with the prior art, the present invention has the following beneficial effects:

[0017] (1) Adopt an adaptive topology switch to meet the address routing requirements in different application scenarios;

[0018] (2) Modular design is adopted to achieve easy scalability for different application scenarios;

[0019] (3) Adopt an adaptive structure to meet the delay requirements in different scenarios.

[0020] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0022] Figure 1 It is a specific application block diagram of the adaptive switch implementation method based on general Serdes of the present invention;

[0023] Figure 2 Design a block diagram for the switch;

[0024] Figure 3 Design a block diagram for R-tile;

[0025] Figure 4 Design a block diagram for Serdes;

[0026] Figure 5 It is a schematic diagram of a switch application scenario in a specific embodiment. DETAILED DESCRIPTION

[0027] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0028] See also Figure 1-5 As shown, the adaptive switch implementation method based on general Serdes of the present invention includes the following contents:

[0029] The modular design of the switch is adopted. The smallest module of the switch is the R-NI-Link module, which is convenient for realizing routing and switching of different port numbers and performances. The delay between different R-NI-Link modules can be adjusted by customization or adaptive adjustment to meet the uniformity of delay between different ports.

[0030] The R-NI-Link module includes the Route module representing routing and the NI-Link module representing serdes. NI stands for net interface, which represents the interface module between routing and serdes. Link implements the efficient transmission function of serdes.

[0031] The Route module uses network on chip to implement routing functions to meet the requirements of adjustable routing topology between different R-NI-Link modules. The adjustment can be customized or adaptive, and supports address routing at different levels.

[0032] The Route module and the NI-Link module exchange data at the link layer to reduce the overall delay of the switch device;

[0033] The adapter device switch also has an output interface output, which serves as an extended interconnection between multiple adapter device switches and has the same function as the Route module;

[0034] like Figure 1 As shown, N0 / N1 in the application box represents a node, representing Figure 2 The R-NI-Link module in the switch design block diagram;

[0035] like Figure 2 The following is a block diagram of the switch design. R stands for Route, which indicates the routing function. Figure 3 R-tile design module; NI-Link module represents serdes function; NI is net interface, which means routing and serdes interface module; Link is to realize serdes efficient transmission function; design reference Figure 4 The serdes design block diagram is shown in the figure. O stands for output, which indicates the output interface of the switch. As a multi-switch expansion interconnection, its function is the same as R, which stands for route. The name is changed to distinguish the interface form.

[0036] like Figure 3 The figure shows the design block diagram of R-tile, including Crossbar, Crossbar arbitration module, routing module, input port, token output, token input, virtual channel control module, etc.

[0037] like Figure 4 The figure shows a schematic diagram of the SerDes structure; SerDes (Serializer / Deserializer) is a technology used for high-speed serial data transmission, which converts parallel data into high-speed serial data and converts it back into parallel data at the receiving end;

[0038] **Parallel Data Input**: Parallel data input, which is data from within the system, usually in the form of multiple bits;

[0039] **Serializer (TX Path)**: Serializer, which is a key component in the transmit path, is responsible for converting parallel data into a higher bit rate serial data stream. This process usually includes data encoding, bit width compression, etc.;

[0040] **High-Speed ​​Serial Link**: A high-speed serial link is a physical transmission medium, such as a cable or optical fiber, used to transmit a serial data stream between a sender and a receiver;

[0041] **Receiver (RX Path)**: Receiver, which is a key component in the receive path, is responsible for receiving the high-speed serial data stream and converting it back to the original parallel data format. This process usually includes data decoding, bit width expansion, etc.;

[0042] **Clock and Data Recovery (CDR)**: Clock and data recovery, a key function in the receiver, is used to recover the clock signal from the received serial data and ensure data synchronization;

[0043] **Equalization**: Equalization is used to adjust the received signal to compensate for attenuation and distortion during transmission;

[0044] **Adaptive Equalization**: Adaptive equalization can dynamically adjust the equalization parameters according to the characteristics of the transmission medium;

[0045] **Decision Feedback Equalization (DFE): Decision feedback equalization, a technique that uses determined bits to improve signal quality;

[0046] SerDes technology is widely used in various high-speed communication interfaces, such as PCI Express, SATA, Ethernet, etc. As data transmission rates increase, SerDes design is also evolving to meet higher performance requirements and longer transmission distances.

[0047] like Figure 5 As shown, it is a schematic diagram of switch application scenario;

[0048] Among them, the application of the switch implementation method includes using the CXL protocol to implement the peripherals supporting the CXL protocol in the extended AI server, and the peripherals include CPU, NPU, memory and hard disk.

[0049] Among them, the application of the switch implementation method includes using a custom protocol to implement scalable low-latency related application scenarios;

[0050] Note: CXL memory extension latency is approximately 150ns, custom protocol latency is approximately 100ns, and DDR memory latency is approximately 100ns.

[0051] The preferred embodiments of the present invention disclosed above are only used to help illustrate the present invention. The preferred embodiments do not describe all the details in detail, nor do they limit the invention to the specific implementation methods described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. The adaptive switch implementation method based on general Serdes is characterized by: It includes the following: The modular design of the switch is adopted. The smallest module of the switch is the R-NI-Link module, which is convenient for realizing routing and switching of different port numbers and performances. The delay between different R-NI-Link modules can be adjusted by customization or adaptive adjustment to meet the uniformity of delay between different ports. The R-NI-Link module includes a Route module representing routing and a NI-Link module representing serdes; wherein NI specifically stands for net interface, representing the interface module of routing and serdes, and Link realizes the efficient transmission function of serdes; The Route module uses network on chip to implement routing functions, so as to meet the requirements that the routing topology between different R-NI-Link modules can be adjusted. The adjustment is customized or adaptive, and supports address routing at different levels. The Route module and the NI-Link module perform data exchange at the link layer to reduce the overall delay of the adapter device switch; The adapter device switch is also provided with an output interface output, which serves as an extended interconnection between multiple adapter devices switches and has the same function as the Route module.

2. The method for implementing an adaptive switch based on general Serdes according to claim 1, characterized in that: The application of the switch implementation method includes using the CXL protocol to implement the CXL protocol-supported peripherals in the extended AI server, wherein the peripherals include a CPU, an NPU, a memory, and a hard disk.

3. The method for implementing an adaptive switch based on general Serdes according to claim 1, characterized in that: The application of the switch implementation method includes using a custom protocol to implement scalable low-latency related application scenarios.

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