A data transmission path suitable for FFT algorithms

Abstract

The present application relates to the technical field of data transmission, and especially relates to a data transmission path suitable for FFT algorithm, and the present application proposes the following scheme: data is acquired from a DDR memory through an AXI bus and is transmitted to an SRAM array through DMA, a data transmission interface is adopted in combination with an fft_port module, 256bit data (four 64bit floating-point numbers) are transmitted per cycle, and the transmission rate is improved by 4 times. The path comprises a conflict-free memory access controller, and data is efficiently stored in the SRAM through an index-address conversion rule. In addition, the system supports multi-batch processing and zero padding operation, ensures that the number of data points meets the requirements of the FFT algorithm, and adapts to the processing requirements of data sets of 2n and non-2n. A handshake signal control unit dynamically manages an ack signal, and data transmission is suspended during zero padding. The path supports FFT operation of up to 4M points, and meets the requirements of efficient and large-scale data processing.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data transmission, and particularly relates to a data transmission path suitable for an FFT algorithm. BACKGROUND

[0002] Under the design structure of a three-dimensional reconfigurable hardware acceleration core, the implementation of the FFT algorithm needs to rely on a butterfly memory access controller to be implemented, and before the butterfly memory access controller starts the calculation work, source data located in the DDR needs to be moved into a storage area (SRAM) through a dma, and this function is implemented by an fft_port module (a data transmission interface), which will transmit the data transmitted by the dma to different positions in the SRAM according to a specific no-memory conflict corresponding rule. Because the data transmission on the axi bus is 256 bits at a time, and the data processed by the butterfly memory access controller is a 64-bit single-precision floating-point number, it is equivalent to that the dma will transmit four data to the butterfly memory access controller in a period. In the past hardware design, because the no-memory conflict corresponding rule and the data zero padding operation are limited, the fft_port can only complete the transmission rate of 256 bits in four periods.

[0003] Meanwhile, it needs to be supplemented that the data transmission of the dma to the SRAM array needs to wait until the fft_port receives the data and normally returns an ack signal to the dma before the next beat data transmission can continue, that is, the data transmission can continue after the handshake.

[0004] The above patents all have the problems proposed in the background, that is, the fft_port can only complete the transmission rate of 256 bits in four periods. In order to solve the above problems, the present application designs a data transmission path suitable for an FFT algorithm. SUMMARY

[0005] The technical problem to be solved by the present application is to provide a data transmission path suitable for an FFT algorithm, which acquires source data from a DDR memory and transmits the source data to an SRAM array through an AXI bus. The data transmission interface adopts a direct memory access (DMA) technology to transmit 256-bit data in each period, and contains a no-conflict memory access controller for mapping each 64-bit floating-point number to an independent storage address in the SRAM through an index-address conversion rule. In order to cope with non-2n power data, a data zero padding module is responsible for zero padding the data to 2n power before transmission, and a handshake signal control unit controls the pause and recovery of data transmission. The system can dynamically adjust the state of the ack signal to adapt to the FFT data set processing requirements of different points, and realizes efficient and conflict-free data transmission and storage.

[0006] To achieve the above object, the present application provides the following technical scheme:

[0007] A data transmission path suitable for FFT algorithm, which acquires source data from DDR memory and transmits to SRAM array through AXI bus, comprising:

[0008] A data transmission interface for acquiring data from external memory through direct memory access technology and transmitting data to SRAM array, the data being 64-bit single-precision floating-point numbers, the data width being 256 bits per cycle;

[0009] An AXI bus for data transmission between external memory and SRAM array;

[0010] A conflict-free access controller, which contains index-address conversion rules for mapping each 64-bit data in the received 256-bit data to an independent memory address of SRAM according to the index conversion rules;

[0011] A data zero padding module for padding the insufficient data to 2^n after zero padding when the amount of data to be transmitted does not meet the requirements of the FFT algorithm, and then transmitting to SRAM.

[0012] The data transmission interface further comprises a handshake signal control unit for pausing or resuming DMA data transmission by controlling the pull-down and pull-up of the ack signal during data transmission, actively pulling down the ack signal to pause data transmission when data zero padding operation is needed, and pulling up the ack signal to resume data transmission after the zero padding operation is completed.

[0013] The data transmission interface can simultaneously complete the data transmission of multiple 64-bit floating-point numbers, and in one data transmission cycle, the 256-bit data transmitted by DMA to SRAM is divided into four groups, each group corresponding to a 64-bit floating-point number, and conflict-free storage of each floating-point number in SRAM is achieved through index-address conversion rules.

[0014] The handshake signal control unit dynamically calculates when to start pulling down the ack signal according to the size of the data transmission amount, so as to pause data transmission for zero padding operation when necessary, and the calculation method is that the quotient of the data transmission amount modulo 4 determines the time point of pulling down the ack signal.

[0015] The zero padding module further comprises a register storage unit for temporarily storing unused data during data zero padding operation, and transmitting to SRAM after combination with subsequent data during the next data transmission.

[0016] When transmitting multiple batches of data that are not 2^n, the register storage unit can store the unused data at the end of the last batch of data transmission cycle.

[0017] The index-address conversion rule generates a unique storage address corresponding to each data in real time according to the batch of data transmission and the storage location in the SRAM.

[0018] The data transmission interface can immediately transmit the data to a specific location in the SRAM according to the index rule after receiving the 256bit data transmitted by the DDR, and ensure that there is no address conflict in the transmission process through the internal address conversion logic.

[0019] The handshake signal control unit dynamically adjusts the pull-up or pull-down of the ack signal according to the amount of data currently transmitted and the zero filling requirement, so as to ensure that the data transmission of the DMA does not affect the data storage in the SRAM when the data zero filling operation is performed.

[0020] The data transmission interface is suitable for processing FFT data sets of different points, including 2n and non-2n data sets, and can automatically perform data zero filling operation according to the size of the data set to adapt to the requirements of the FFT algorithm for specific point number data.

[0021] Compared with the prior art, the beneficial effects of the present application are:

[0022] 1. The present application combines AXI bus and DMA, transmits 256bit data in each cycle, supports parallel transmission of multiple 64-bit floating point numbers at the same time, greatly improves the bandwidth and speed of data transmission, meets the needs of FFT algorithm for efficient data processing, and improves the data transmission rate by four times.

[0023] 2. The present application adopts index-address conversion rule to map each data block to an independent storage address in the SRAM, avoids data storage conflict, ensures reasonable distribution of data in the SRAM, and improves storage utilization and computing efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0024] Other features, objects and advantages of the present application will become more apparent through reading the following detailed description of the non-limiting embodiments made with reference to the accompanying drawings:

[0025] Figure 1 Figure 1 is a module schematic diagram of a data transmission path suitable for an FFT algorithm according to an embodiment of the present application;

[0026] Figure 2 Figure 2 is a data transmission flow diagram according to an embodiment of the present application;

[0027] Figure 3 Figure 3 is a diagram of the storage space division of the butterfly memory access according to an embodiment of the present application;

[0028] Figure 4Workflow diagram for the butterfly access memory controller of embodiment 1 of the present application; DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments.

[0030] Embodiment 1

[0031] Please refer to Figure 1 An embodiment provided by the present application is a data transmission path suitable for FFT algorithm, which obtains source data from DDR memory through AXI bus and transmits the data to DMA, and distributes the data to SRAM array through fft_port, including:

[0032] The AXI bus is used to transmit data between the DDR memory and the DMA.

[0033] The data transmission interface is used to obtain bus data from the DMA through direct memory access technology and transmit the data to the SRAM array, the data being 64-bit single-precision floating-point numbers, the data width being 256 bits per cycle, 4 64-bit single-precision floating-point numbers being transmitted per cycle, the data transmission interface further including multiple parallel channels to ensure the stability and accuracy of data transmission at high speed. The data transmission interface is responsible for managing data scheduling from the DDR to the SRAM and contains a cache mechanism to ensure the continuity and consistency of data flow.

[0034] The conflict-free access memory controller contains index-address conversion rules for mapping each 64-bit data in the received 256-bit data to an independent storage address of the SRAM according to preset index conversion rules. Each 64-bit data is assigned a unique index value, and the controller maps the data to a specific storage unit in the SRAM according to the index value to ensure that no storage address conflict occurs during data transmission. The index-address conversion rules are based on a hash algorithm or a linear mapping algorithm, which can generate the storage address of the data in real time, ensure the conflict-free access, and dynamically adjust the mapping strategy according to the data batch and transmission progress to optimize the data storage efficiency. The conflict-free access memory controller further contains an address mapping table for recording the specific storage location of each data to ensure that the related data can be quickly and accurately accessed when performing FFT calculation.

[0035] Data zero padding module, used for padding the insufficient data to 2^n after the number of the data to be transmitted does not meet the requirement of the FFT algorithm, and then transmitting the data to the SRAM. The FFT algorithm usually requires the number of the input data to be 2^n. If the number of the source data is insufficient, the zero padding operation needs to be performed at the tail of the data. The data zero padding module comprises:

[0036] Zero padding detection unit: used for detecting whether the number of the input data meets the requirement of 2^n. If not, the zero padding operation is automatically started;

[0037] Zero padding control unit: according to the feedback of the zero padding detection unit, the amount of the data needing zero padding is calculated, and the zero padding data is generated. The zero padding data is all zero padding, used for padding the source data;

[0038] Zero padding execution unit: in the data transmission process, the zero padding data is inserted into the transmission queue, and the data after the zero padding is ensured to be transmitted to the SRAM array according to the AXI bus protocol. The execution unit supports the zero padding operation of multiple batches of data, and ensures that each batch of data meets the input requirement of the FFT algorithm;

[0039] Register storage unit: used for temporarily storing the data not processed during the zero padding operation. Especially when the amount of the transmission data is insufficient, the register can record the unfinished data in the last transmission period, and ensure the correctness of the zero padding operation in the next period. The register also supports cross-period data storage management, and can maintain the consistency of the data in multiple transmission periods.

[0040] Please refer to Figure 2 The data transmission flow chart of the embodiment of the application involves components including the AXI bus, the DMA, the FFT_DMA_PORT and multiple groups of storage BANK (a, b, c, d). The data is first obtained from the DDR memory through the AXI bus, and is transmitted to the DMA module. The DMA module divides the 256bit data transmitted into four 64bit floating point numbers, and transmits the data to the FFT_DMA_PORT. The FFT_DMA_PORT maps each 64bit floating point number to different BANK (a, b, c, d) in the SRAM according to the index-address conversion rule. In order to avoid storage conflict, the FFT_DMA_PORT uses a dynamic address generation algorithm to ensure that each data block has a unique storage address. When the amount of the data is less than 2^n, the FFT_DMA_PORT triggers the data zero padding module to automatically pad the data and continue the transmission.

[0041] In the data transmission process, the handshake signal control unit is responsible for controlling the ack signal, and ensuring that the data will not be lost or in disorder during the transmission and the zero padding

[0042] The AXI bus is the core of the entire data transmission path, used to transmit data between the DDR memory and other modules such as DMA and SRAM arrays. The AXI bus is shown as the top-level module, which is responsible for obtaining data from external memory and delivering data through the downstream DMA module. In this embodiment, the AXI bus transmits 256 bits of data each time, ensuring that the bandwidth requirements of the FFT algorithm are met. Through multi-channel parallel processing, the AXI bus can transmit multiple data blocks in a single cycle, ensuring the efficiency and reliability of data transmission;

[0043] The DMA module is used for data transmission between the AXI bus and the FFT_DMA_PORT, which can directly communicate with the AXI bus and transmit data obtained from the DDR to the FFT_DMA_PORT. In the embodiment, the DMA obtains 256 bits of data through the AXI bus and divides it into four 64-bit floating-point numbers. During data transmission, the DMA does not rely on CPU control but directly transmits data, improving the efficiency of data processing. The DMA also cooperates with the handshake signal control unit to dynamically adjust the ack signal, enabling the suspension and resumption of data transmission, especially during the zero-padding operation, ensuring the order and accuracy of data transmission;

[0044] The FFT_DMA_PORT is the module responsible for transmitting data from the DMA to the SRAM. Its main function is to map each 64-bit floating-point number in the 256-bit data to an independent storage address in the SRAM according to the index-address conversion rule. The FFT_DMA_PORT, combined with the conflict-free memory controller, can generate storage addresses in real time after receiving data, ensuring that there is no address conflict when storing data. By using a hash algorithm or linear mapping, the FFT_DMA_PORT can allocate data to different storage units in the SRAM. In addition, the FFT_DMA_PORT is also responsible for the zero-padding operation, which will perform the zero-padding operation during data transmission when the data is not a power of 2;

[0045] In Figure 2 , four independent SRAM storage BANKs (a, b, c, d) are shown. Each BANK represents a storage area in the SRAM, used to store the data required by the FFT algorithm. Under the control of the FFT_DMA_PORT, data is allocated to different storage BANKs according to the index rule, ensuring that data can be stored without conflict. In the embodiment, each BANK is responsible for storing the 64-bit data block transmitted, and the FFT_DMA_PORT evenly distributes data to these storage BANKs according to the index and batch of data. In this way, storage resources can be effectively utilized, ensuring efficient FFT calculation;

[0046] Please refer to Figure 3 The data in each BANK is arranged in a certain order, and these storage areas are used to support data distribution and storage of the butterfly operation. In the butterfly memory access algorithm, data is read or written from different BANKs according to a specific rule to support the parallelism of the FFT calculation. By dispersing data in multiple BANKs, data in multiple storage areas can be accessed simultaneously, avoiding memory access conflicts and improving data transmission efficiency. This division method supports parallel transmission and processing of multiple batches of data. The data in each BANK can be read or written simultaneously, making the entire memory access process more efficient.

[0047] The data transmission interface further comprises a handshake signal control unit for pausing or resuming the data transmission of the DMA by controlling the pull-down and pull-up of the ack signal during the data transmission. When the data zero padding operation needs to be performed, the ack signal is actively pulled down to pause the data transmission. After the zero padding operation is completed, the ack signal is pulled up to resume the data transmission.

[0048] The core function of the handshake signal control unit is to manage the data transmission rhythm of the DMA by controlling the state of the ack signal. In each data transmission period, the unit dynamically adjusts the pull-down and pull-up state of the ack signal according to the current data transmission situation, mainly including the following functions:

[0049] The ack signal is used to identify whether the data can continue to be transmitted. In the normal data transmission process, the ack signal remains high, and the DMA continues to transmit the data block to the SRAM after receiving the high-level signal. When the data transmission needs to be paused, such as data zero padding or memory access adjustment, the ack signal will be pulled down.

[0050] Active pull-down and pull-up of the ack signal need to be considered from two aspects

[0051] a. The size of the data determines when to pull down the ack. Since four 64-bit data are transmitted in the next period under this scheme, the quotient of the data quantity modulo 4 needs to be calculated, which determines when to pull down the ack. For example, 13-point data needs to be zero-padded to 16 points, and the quotient of 13 modulo 4 is 3, which means that the zero padding will be faced in the fourth beat after the data transmission starts. Therefore, the ack signal is pulled down in this period to make the dma stop transmitting data, while the fft_port continues to complete the zero padding operation internally. When it is about to reach 16 points, the ack is pulled up, and the dma continues to transmit the next data after receiving the ack signal.

[0052] When the next batch of unused data needs to be stored in the register, for example, 3 batches of 15 data, the last period of the first batch of data transmission, 13, 14, 15 data need to be normally transmitted into the SRAM array, and the first data of the second batch needs to be stored in the register, and the next wave of data transmission is combined with the 2nd, 3rd and 4th data after the ack is pulled up, and then transmitted into the SRAM array;

[0053] When the number of transmitted data is insufficient to meet the requirement of the FFT algorithm that the number of data points is 2 raised to the power of n, the ack signal is actively pulled down, so that the DMA temporarily stops data transmission. During this period, the data zero padding module completes the zero padding operation, and after the zero padding operation is completed, the ack signal is pulled up again, and the DMA resumes data transmission;

[0054] The handshake signal control unit can adjust the state of the ack signal in real time according to the amount of transmitted data and the zero padding requirement. It determines when to pull down the ack signal for zero padding by monitoring the index and transmission state of the data in each period, and accurately resumes data transmission after the zero padding is completed. In each data transmission, the control unit detects the size of the current batch of data to determine whether zero padding is needed. Assuming that the current batch of transmitted data is 13 points, and the FFT algorithm requires 16 points of input, the zero padding algorithm will be triggered;

[0055] The handshake signal control unit can adjust the index of the data in real time according to the zero padding state. Even if the data stream is paused, the index will still advance according to the predetermined rule, ensuring that the zero padding data can be correctly mapped to the storage address in the SRAM.

[0056] The control unit can manage the zero padding operation of multiple data channels at the same time, ensuring that in the high-bandwidth data transmission scenario, the data streams of all channels can work cooperatively, avoiding the influence of single-channel zero padding operation on the overall data throughput;

[0057] Please refer to Figure 4 The working flow chart of the butterfly memory controller of the embodiment of the application is shown in the figure. The controller first determines whether the number of data points meets the requirement of the FFT algorithm. If not, it performs zero padding operation. After meeting the condition, the controller selects the appropriate BANK to move data from the SRAM to the calculation unit for butterfly operation. After the operation is completed, it checks again whether there is remaining data. If there is, it repeats the BANK selection and moving process until all data processing is completed, ensuring efficient and conflict-free transmission and calculation of data to support the requirements of the FFT algorithm;

[0058] In the hardware implementation of the FFT algorithm, the data quantity often does not meet the requirement of 2 raised to the power of n. The ack signal control mechanism of the handshake signal control unit enables the system to flexibly respond to different batch and data quantity transmission requirements, and completes the zero padding and correct transmission of data without affecting the overall transmission efficiency.

[0059] Through this fine ack signal control mechanism, the handshake signal control unit ensures the smoothness and efficiency of the entire data transmission process, especially in the face of complex zero padding and multi-batch data transmission, the system can maintain efficient and accurate operation;

[0060] The data transmission interface can complete the transmission of multiple 64-bit floating point numbers at the same time. In one data transmission period, the 256-bit data transmitted by the DMA to the SRAM is divided into four groups, each corresponding to a 64-bit floating point number, and the index-address conversion rule is used to realize the conflict-free storage of each floating point number in the SRAM.

[0061] Based on the AXI bus design, data is obtained from the DDR memory through direct memory access (DMA) technology and transmitted to the on-chip memory (SRAM). In each data transmission period, the 256-bit data read from the DDR by the DMA will be divided into four groups, each of which is 64 bits, representing a 64-bit single-precision floating point number. The data transmission interface will package the 256-bit data according to the pre-defined rules, each 64-bit floating point number will be divided into an independent data unit, and will be mapped to different storage addresses in the SRAM through a special index-address conversion rule. This operation ensures that each group of data can be stored in the SRAM without address conflict;

[0062] Each 64-bit floating point number is assigned a unique index value during transmission, and the system maps the index value to the storage address in the SRAM through the index-address conversion rule to ensure that the transmitted data can be stored in different address spaces without conflict. The index rule is generated according to a pre-defined mapping algorithm, such as a hash function or an incremental algorithm to achieve dynamic address allocation;

[0063] By transmitting four 64-bit floating point numbers simultaneously in each data period, the data transmission interface effectively utilizes the bandwidth of the AXI bus, reducing the transmission time. Under the traditional transmission mechanism, only one 64-bit floating point number can be transmitted in one period, while in this embodiment, four floating point numbers can be transmitted in one period, greatly improving the data transmission rate.

[0064] By using the index-address conversion rule, each floating point number has an independent storage address, avoiding the storage conflict problem when multiple data are written to the SRAM at the same time. This rule can ensure that even in a high-concurrency transmission environment, data can be accurately written to different storage units in the SRAM.

[0065] The storage space of SRAM is more effectively utilized. Through the mapping of the index rule, data can be evenly distributed in each storage unit of SRAM, reducing the waste of storage space, especially in the case of processing a large amount of data, this optimized storage strategy can improve the overall efficiency of the system;

[0066] For example, when performing 1024-point FFT calculation, 1024 64-bit floating-point numbers need to be transmitted. Through this parallel data transmission mechanism, the system can complete the transmission of all floating-point numbers in 256 cycles, while the traditional serial transmission mechanism requires 1024 cycles. This substantial cycle shortening directly improves the overall computing efficiency of the FFT algorithm, which is suitable for real-time signal processing and image processing fields with high real-time requirements;

[0067] Each 64-bit floating-point number is assigned a unique index value during transmission, and the system maps the index value to the storage address in SRAM through the index-address conversion rule to ensure that the transmitted data can be stored in different address spaces without conflict. The index rule is generated according to a predefined mapping algorithm, such as a hash function or an incremental algorithm to achieve dynamic address allocation;

[0068] The handshake signal control unit dynamically calculates when to start pulling down the ack signal according to the size of the data transmission amount, so as to pause data transmission for zero padding operation when necessary, and the calculation method is to determine the time point of pulling down the ack signal according to the quotient of the data transmission amount modulo 4;

[0069] The zero padding module further includes a register storage unit for temporarily storing unused data during data zero padding operation, and transmitting the unused data combined with subsequent data to SRAM during the next data transmission;

[0070] The register storage unit is a multi-level register structure, each level of register has a FIFO (First-In-First-Out) mode for storing unused data in the current cycle. During the zero padding operation, if the amount of data to be transmitted is insufficient to fill the 256-bit transmission width (such as transmitting 13 64-bit data, only 3 64-bit data are filled, leaving 1 64-bit space), the multi-level register storage unit will store the remaining unused data in the corresponding register unit;

[0071] Each level of register has a capacity of 64 bits, which can automatically allocate and manage the storage of unused data according to the amount of input data. This structure can support continuous zero padding transmission of multiple batches of data, avoiding data loss caused by zero padding during cross-batch data transmission;

[0072] At the beginning of the zero padding operation, the zero padding detection unit first determines whether the amount of data to be transmitted is a power of 2. If not, the zero padding process is immediately started.

[0073] When the data to be transmitted (e.g., 15 64-bit data) cannot fill a complete transmission cycle (256 bits), the register storage unit temporarily stores the excess data in a FIFO structure.

[0074] In the next cycle of data transmission, the data in the register is combined with the subsequent data to ensure that the transmission width of each cycle is always 256 bits. The untransmitted data is stored in the register for no more than one data transmission cycle to avoid the impact of data retention on the overall transmission process.

[0075] The register storage unit is linked with the handshake signal control unit and the zero padding control unit. When the data is not used, the handshake signal control unit suspends the DMA transmission to prevent data overflow or transmission errors. At this time, the register storage unit receives and stores the data not used in the current cycle. Through the control logic inside the register, these unused data are temporarily stored until the next data transmission cycle.

[0076] In the next data transmission, the register control logic automatically combines the stored data with the new batch of data through index matching, and forms a complete 256-bit data packet for transmission to the SRAM.

[0077] When the transmission batch is a multiple of data that is not a power of 2, the register storage unit can store the unused data at the end of the last batch of data transmission cycle.

[0078] Suppose the amount of data to be transmitted is 13 64-bit data, and the FFT algorithm requires 16 64-bit data, so 3 zeros need to be added after the last 3 data:

[0079] Step 1: When the data is transmitted to the 12th data, the register storage unit enters the active state, ready to transmit the 13th, 14th, and 15th data to the SRAM, but the 16th data has not arrived, so zero padding operation is needed.

[0080] Step 2: The handshake signal control unit actively pulls down the ack signal to suspend data transmission, the zero padding control unit calculates and generates 3 zero padding data, and the register storage unit temporarily stores the unused 13th data.

[0081] Step 3: At the beginning of the next transmission cycle, the ack signal is restored, the register storage unit combines the 13th data with the new data (the subsequent new data may be the first data of the next batch), forms a complete 256-bit data packet, and continues to transmit to the SRAM.

[0082] The index-address conversion rule generates a unique storage address corresponding to each data in real time according to the batch of data transmission and the storage location in the SRAM, and the index-address conversion rule is as follows:

[0083]

[0084] In the data transmission process, the index-address conversion rule is used to convert the index value of each data block into a unique storage address in the SRAM to ensure that the data storage in the SRAM is conflict-free. Specifically, the data transmission interface obtains 256-bit data from the DDR each time, which is divided into 4 64-bit data blocks, and each data block is attached with a unique index value. The index value is composed of the data transmission batch number and the sequence number of the data in the batch;

[0085] The index generator generates the corresponding index value in real time, and converts it into an address in the SRAM through an index mapping algorithm,

[0086] After receiving the 256-bit data transmitted from the DDR, the data transmission interface can immediately transmit the data to a specific location in the SRAM according to the index rule, and through the internal address conversion logic, it ensures that there is no address conflict in the transmission process;

[0087] The data transmission interface is responsible for obtaining data from the DDR and transmitting it to the SRAM through the AXI bus. Each transmission of 256-bit data blocks is divided into 4 64-bit floating-point numbers, which are stored in different locations of the SRAM according to the index rule. The data transmission interface has parallel processing function and can handle multiple data block transmissions simultaneously, improving transmission efficiency. The data transmission interface supports multi-channel parallel transmission and can transmit 4 64-bit data blocks simultaneously in each cycle, shortening the data transmission delay;

[0088] For each transmission cycle, the data in the data queue is taken out and transmitted to the SRAM in index order. Since the amount of data transmitted in each cycle is 256 bits, and the AXI bus supports multi-channel transmission, the scheduler will allocate the data in the data queue to different transmission channels to achieve parallel transmission;

[0089] The handshake signal control unit dynamically adjusts the pull-up or pull-down of the ack signal according to the amount of data currently transmitted and the zero-filling requirement to ensure that the data transmission of the DMA does not affect the data storage in the SRAM when the data zero-filling operation is performed;

[0090] The handshake signal control unit is responsible for controlling the synchronization of data transmission between the DMA and the SRAM. By dynamically adjusting the state (pulling low or pulling high) of the ack signal, the suspension and resumption of data transmission are realized. This unit is mainly used in the data zero-padding process to ensure that data transmission can proceed in an orderly manner after the completion of the zero-padding operation;

[0091] The data transmission interface is suitable for processing FFT data sets of different points, including data sets of 2n and non-2n, and can automatically perform data zero-padding operation according to the size of the data set to adapt to the requirements of the FFT algorithm for specific point number data;

[0092] The FFT algorithm usually requires the input data point number to be 2n, but the actual transmitted data set point number may be non-2n. Therefore, the data transmission interface needs to have the ability to process data sets of different points, especially when the point number is insufficient, it needs to automatically perform zero-padding operation;

[0093] For example, for a 15-point data set, the system will automatically determine that the data point number is insufficient, start the zero-padding module, and pad the data to 16 points. The unused 16th point data is temporarily stored in the register, and after the zero-padding is completed, it is transmitted to the SRAM together with the zero-padding data. The zero-padded data set will meet the input requirements of the FFT algorithm and will not affect the integrity of the original data.

[0094] Although the embodiments of the present application have been shown and described above, it should be understood that the above embodiments are exemplary and should not be construed as limiting the present application, and those skilled in the art can make changes, modifications, replacements and variations to the above embodiments within the scope of the present application.

Claims

1. A data transmission path suitable for use in an FFT algorithm, characterized in that, The data transmission path obtains source data from the DDR memory through the AXI bus and transmits the data to the DMA, and distributes the data to the SRAM array through the fft_port, including: an AXI bus, configured to transmit data between the DDR memory and the DMA; a data transmission interface, configured to obtain bus data from the DMA through a direct memory access technology and transmit the data to the SRAM array, the data being 64-bit single-precision floating-point numbers, and the data width being 256 bits per cycle; a conflict-free access controller, the controller comprising an index-address conversion rule, configured to map each 64-bit data in the received 256-bit data to an independent storage address of the SRAM according to the index conversion rule; a data zero padding module, configured to pad the insufficient data to 2 raised to the power of n when the amount of data to be transmitted does not meet the requirement of the FFT algorithm, and then transmit the data to the SRAM; the data transmission interface further comprises a handshake signal control unit, configured to pause or resume the data transmission of the DMA by controlling the pull-down and pull-up of the ack signal during the data transmission, and actively pull down the ack signal to pause the data transmission when the data zero padding operation needs to be performed, and pull up the ack signal to resume the data transmission after the zero padding operation is completed; the data transmission interface can simultaneously complete data transmission of multiple 64-bit floating-point numbers, and in one data transmission cycle, the 256-bit data transmitted by the DMA to the SRAM is divided into four groups, each group corresponding to a 64-bit floating-point number, and the conflict-free storage of each floating-point number in the SRAM is realized through the index-address conversion rule; the data zero padding module further comprises a register storage unit, configured to temporarily store the unused data during the data zero padding operation, and transmit the data to the SRAM after being combined with subsequent data for the next data transmission.

2. The data transmission path suitable for FFT algorithm according to claim 1, wherein, The handshake signal control unit dynamically calculates when to pull down the ack signal according to the size of the data transmission amount, so as to pause the data transmission for the zero padding operation when necessary, and the calculation method is that the quotient of the data transmission amount modulo 4 determines the time point of pulling down the ack signal.

3. The data transmission path suitable for FFT algorithm as claimed in claim 1 wherein, When the transmission batch is a plurality of batches of data that are not 2 raised to the power of n, the register storage unit can store the unused data at the end of the last batch of data transmission cycle.

4. The data transmission path suitable for FFT algorithm as claimed in claim 1 wherein, The index-address conversion rule generates a unique storage address corresponding to each data in real time according to the batch of data transmission and the storage position in the SRAM.

5. The data transmission path suitable for FFT algorithm as claimed in claim 1 wherein, The data transmission interface can immediately transmit the data to a specific position in the SRAM according to the index rule after receiving the 256-bit data transmitted from the DDR, and ensure that there is no address conflict in the transmission process through the internal address conversion logic.

6. The data transmission path suitable for FFT algorithm as claimed in claim 2 wherein, The handshake signal control unit dynamically adjusts the pull-up or pull-down of the ack signal according to the current data amount and zero padding demand, so as to ensure that the data transmission of the DMA does not affect the data storage in the SRAM when the data zero padding operation is performed.

7. The data path suitable for FFT algorithm as claimed in claim 1 wherein, The data transmission interface is suitable for processing FFT data sets of different point numbers, including 2n and non-2n data sets, and can automatically perform data zero padding operation according to the size of the data set to adapt to the requirement of the FFT algorithm for specific point number data.

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