A fast processing method for super large point number FFT

Abstract

The application discloses a kind of super large point number FFT fast processing method, it is related to digital signal fast processing field, including the following steps: first, zero padding operation is carried out to original sampling signal data to the total length of sequence meets the integer multiple of M1 point;Then, the data after zero padding operation is segmented, and the input super large point number sequence is divided into L length M1 point sub-sequences, then, the sub-sequences are calculated with M1 point FFT, and high-base FFT algorithm architecture is used for iterative calculation;Finally, the phase correction of FFT result is realized by multiplying the specific rotation factor with the FFT calculation result of sub-sequence, the phase-corrected sub-FFT result is combined and spliced according to a specific weighting method, to ensure that the composition of each frequency point is correctly adjusted, and the FFT result of original data sequence is obtained.The application can reduce the algorithm complexity while improving the calculation efficiency of super large point number FFT.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of wireless communication, and particularly relates to a super-large-point FFT fast processing method, which can be used in millimeter wave / terahertz high-speed communication, radar detection, signal processing and the like. BACKGROUND

[0002] FFT (Fast Fourier Transform) is a high-efficiency algorithm for calculating discrete Fourier transform (DFT) and its inverse transform, and is widely used in fields such as signal processing, image processing, communication systems, spectrum analysis and the like. Cooley-Tukey fast Fourier transform algorithm (Cooley-Tukey algorithm) is the most common fast Fourier transform algorithm, which reduces the calculation complexity from O(N 2 ) to O(NlogN), significantly improving the calculation efficiency.

[0003] With the advent of the big data era and the increasing application demand, processing of super-large-point signals becomes more and more common. In order to meet the real-time requirement of information systems, it is necessary to realize fast processing of large-point FFT calculation for high-resolution frequency domain information analysis in millimeter wave / terahertz high-speed communication, radar detection, signal processing and the like. However, the traditional FFT algorithm faces the following challenges in processing super-large-point FFT calculation: 1) high calculation complexity, although FFT reduces the calculation complexity to O(NlogN), but for signals with millions or even billions of points, the calculation amount is still huge, and the traditional algorithm shows obvious deficiency in calculation time; 2) super-large-point FFT calculation needs to occupy a large amount of memory, especially in high-resolution signal processing and large-scale data analysis, memory consumption becomes a key bottleneck, and the traditional FFT implementation is difficult to run efficiently under limited memory resources; 3) in a distributed system or parallel computing environment, super-large-point FFT calculation needs frequent data transmission and synchronization problems, which further increases the complexity of the system and the non-efficiency of the calculation; 4) in terms of hardware limitation, the existing hardware architecture may encounter problems such as insufficient cache and data bus bandwidth limitation when processing super-large-point FFT calculation, resulting in a significant decrease in calculation speed.

[0004] To cope with these challenges, researchers have proposed various improvements and optimization methods. For example, using higher radix decomposition algorithms (such as Radix-4, Radix-8, etc.), reducing the recursion depth; through data rearrangement and storage optimization, improving memory access efficiency; in parallel computing environment, through task decomposition and scheduling strategy optimization data transmission and synchronization. In the selection of radix, the highest radix-32 FFT algorithm architecture can be realized, and the highest 1.32GS / s data throughput is realized on the 4 parallel 1024 point MSC FFT hardware architecture using Radix-32 FFT algorithm. The architecture attempts to use memory computing (IMC) technology to eliminate the need for a dedicated reordering scheme, while enabling ultra-high throughput and low latency FFT computation. In the design scheme using Radix-4 for frequency domain segmentation, researchers ingeniously designed the address transformation of the data sequence of each stage of butterfly transformation, without code bit inversion sorting, to obtain the natural order of the FFT result. After hardware simulation, the scheme takes a total of 40.96μs at a clock speed of 200MHz, with the remaining small amount of time being consumed by butterfly operation multiplication and addition.

[0005] However, the existing optimization methods still have limitations, especially when dealing with ultra-large point number FFT calculation, it is still difficult to balance the calculation efficiency and memory consumption. Therefore, there is an urgent need for a new efficient ultra-large point number FFT calculation method that can significantly reduce memory consumption while ensuring calculation speed and adapt to the characteristics of modern hardware architecture. SUMMARY

[0006] The purpose of the present application is to overcome the shortcomings of the prior art and provide a new ultra-large point number FFT calculation method. By dividing the data of the million-level point number, segmenting the FFT, optimizing the input rearrangement, radix decomposition and recursive calculation, and finally merging the results, the calculation efficiency is significantly improved, the memory consumption is reduced, and the method is suitable for practical applications of large-scale data processing.

[0007] To achieve the above purpose, the technical solutions adopted by the present application are as follows:

[0008] An ultra-large point number FFT fast processing method, comprising the following steps:

[0009] S1, performing zero padding operation on the original sampling signal data to make the total length of the sequence satisfy an integer multiple of M1 points;

[0010] S2, dividing the sampling signal data after zero padding to obtain data segments;

[0011] S3, performing FFT calculation on the obtained data segments with M1 points;

[0012] S4, allocate memory space to store the intermediate results;

[0013] S5, multiply the FFT calculation result of M1 points of each segment by the corresponding rotation factor to correct the phase;

[0014] S6, merge the segmented spectrum for the results after step S5 to obtain the total result after spectrum calculation.

[0015] Overall, the algorithm formula of the large point number FFT fast processing method of the application is as follows:

[0016]

[0017] Wherein,

[0018] The above formula is the M1-point DFT calculation formula, and n and k in the DFT calculation are represented by n1, n2, k1 and k2 in the application, and the rotation factor in the above formula is The rotation factor can be decomposed into a plurality of rotation factors, and the single-level summation calculation can also be decomposed into two-level summation calculation. Specifically, n1 and k1 are used as time domain and frequency domain variables respectively, and since n1, k1 = 0, 1, 2, …, M1, the input data point number of the original digital signal is L×M1, and M1 numbers are used as a group, so there are L groups of M1-point DFT calculations in total; the calculation result after the first layer FFT needs to be multiplied by The rotation factor corresponds to the rotation factor of the intermediate stage in the butterfly calculation, and this step uses the rotation factor generation module to calculate the result generated in the last step in real time, so as to ensure the uninterrupted serial flow of data in hardware.

[0019] Further, in step S1, it is first judged whether the length of the input sampling signal data is a multiple of M1 points, and if this condition is met, step S2 is performed, and if this condition is not met, the sampling signal sequence input into the system is zero-padded to a new sequence whose length is an integer multiple of M1 points.

[0020] Further, in step S2, the data signal sequence from step S1 is first received, and the data signal sequence is represented as L×M1, and specifically, there is: x = {x[0], x[1], x[2], …, x[L×M1-1]}, the input signal x is divided into L segments, each segment has a length of M1, and each segment is defined as x i , and there is:

[0021] x i = {x[i], x[i+L], x[i+2L], …, x[i+(M1-1)L]} i = 0, 1, …, L-1;

[0022] After data segmentation, the length of each sub-sequence is M1.

[0023] Further, in the step S3, L arrays are created to store the rotation factors corresponding to each data segment, and then FFT calculation is performed on each M1-point data sequence. In the FFT calculation, the most reasonable high-radix FFT algorithm architecture is selected. If the step uses a radix-R high-radix algorithm architecture, the M1-point FFT will be divided into multiple levels of calculation, and M1 / R R-point butterfly DFT calculations are performed at each level of calculation.

[0024] The M1-point FFT core calculation module is designed to decompose and recursively calculate the reordered sequence. First, the M1-point sub-sequence input to the module is preprocessed, including R-ary bit reverse permutation to adapt to radix decomposition, and then decomposition and recursive calculation are performed. The input sequence is decomposed according to the predetermined radix. The present application adopts Radix-R FFT algorithm to decompose the input sequence into M1 / R R-point sub-sequences, and performs FFT calculation on each sub-sequence. This calculation can be recursively performed until the length of the sub-sequence reaches the predetermined basic length (R points).

[0025] In a specific implementation, M1-point FFT calculation is performed according to the following formula:

[0026]

[0027] In the formula, a large number of multiplication and accumulation calculations are required for high parallelization in the hardware implementation process. According to actual requirements, the best radix suitable for M1-point sub-sequence FFT calculation is selected, and the parallel degree required in the parallel calculation process is different according to the different radices. If the best radix is R, then M1 is K power of R, and a K-level Radix-R butterfly calculation unit is used to design the sub-module.

[0028] Further, in the step S4, the intermediate results of the M1-point FFT calculation of the data segment are stored in a new memory space.

[0029] Further, in the step S5, the intermediate rotation factors are calculated according to the L segment number Then, the FFT intermediate results calculated in step S4 are multiplied to obtain a new sequence, and the expression of the new sequence is as follows:

[0030]

[0031] Further, in the step S6, the sub-FFT result after phase correction is taken as an intermediate result, and one iteration multiplication addition of FFT of the base L is performed according to the segmentation number L of the original data, and finally the complete high-precision frequency spectrum sequence is obtained. Based on this, a segmented FFT result merging module is designed, and according to the formula Radix-L FFT calculation is performed on X1'(k1, n1), according to the above formula, L*M1 point data continues to perform M1 times L point FFT calculation, and the number of points in each FFT calculation is L points, and this calculation process only needs to perform one stage of iteration to complete the final result calculation.

[0032] In summary, after the large-scale data sequence (the size of the data processed by the application is generally greater than M1 points) is zero-padded, the large-scale data sequence is divided into a plurality of sub-sequences with a length of M1 points, and the sub-sequences are processed by a smaller-scale FFT operation, and then the complete FFT result of the original large-scale data is reconstructed through the innovative merging algorithm.

[0033] Compared with the prior art, the application has the following beneficial effects: through experimental verification, compared with the traditional FFT method, the method can realize significant performance improvement, and in the background of needing to perform super-large point FFT calculation, the algorithm complexity and calculation efficiency of high-precision spectrum calculation are reduced. BRIEF DESCRIPTION OF DRAWINGS

[0034] Other features, objects and advantages of the application will become more apparent from the following detailed description of non-limiting embodiments, made with reference to the accompanying drawings:

[0035] Figure 1 The figure is a flowchart of the whole process of the super-large point FFT fast processing method of the application;

[0036] Figure 2 The figure is a specific implementation architecture diagram of the series structure proposed in the super-large point FFT fast processing method of the application;

[0037] Figure 3 The figure is a 1M point FFT calculation flowchart of the super-large point FFT fast processing method of the application;

[0038] Figure 4 The figure is a multiplication complexity comparison diagram of the super-large point FFT fast processing method of the application for processing 1M point FFT under different bases;

[0039] Figure 5 The figure is an implementation schematic diagram of the super-large point FFT fast processing method of the application after the result merging after the sub-sequence 1M point FFT calculation;

[0040] Figure 6The simulation result picture of the large-point-number FFT fast processing method under different signals. DETAILED DESCRIPTION

[0041] The application will be described in detail below with specific examples. The following examples will help those skilled in the art to further understand the application, but do not limit the application in any form. It should be noted that, in the case of no conflict, the examples in the application and the features in the examples can be combined with each other.

[0042] In some embodiments of the application, Figure 1 is a schematic block diagram showing the overall implementation structure of the algorithm according to one preferred embodiment of the application. Specifically, the method includes the following key steps (the application will 2 20 1M is used to represent, without special instructions, the quantity represented by 1M below is 2 20 ):

[0043] Step 1: data preprocessing, first judge whether the length of the input sampling signal data is a multiple of 1M points (1M points are selected as the multiple in the embodiment in the general case of M1 in actual engineering), if this condition is met, then proceed to step 2, if this condition is not met, then perform zero padding operation on the input system sampling signal sequence to make it an integer multiple of 1M point length. For example, the last end of the original discrete data is padded with 0 data, and the length of the new sequence can be padded up to an integer multiple of 1M points.

[0044] Step 2: data segmentation is performed on the new sequence after zero padding, so that the data length of each sub-segment meets 1M points, and data segments are obtained; the specific method of segmentation is:

[0045] First, receive the zero-padded signal sequence x from step 1, which is represented as LxM1, divide the signal sequence x into L segments, each with a length of 1M points. Define the i-th sub-sequence as x i , then:

[0046] x i = {x[i], x[i+L], x[i+2L],..., x[i+(1M-1)L]} i=0,1,...,L-1;

[0047] Then the elements in each segment can be represented as:

[0048] x i [n] = x[n+L] n=0,1,...,M-1;

[0049] Here n represents the index of the element in the i-th sub-sequence. After data segmentation, the length of each sub-sequence is 1M points. It is worth noting that this step also needs to be initialized and type converted according to the input data type (floating point or fixed point) in actual engineering practice to ensure that the designed precision requirements are met. Specifically: if the input data sequence is in floating point representation, the data sequence is processed by fixed point. First, determine the bit width of the integer and the decimal, for example, 3 bits for the integer, 12 bits for the decimal, and 1 bit for the sign. Then determine the maximum and minimum values of the fixed point, which can be represented by 15 bits and 1 bit of sign. For example, 3.1415926 is fixed-pointed, 3.1415926 / (8 / (32768))=12867.9632896≈12867. Here 12867 after fixed-point processing is the fixed-point data that can be used for subsequent hardware calculation.

[0050] If the fixed-point format of the given data is different from the required fixed-point format, format conversion of the fixed-point data is needed. The specific implementation process of this step is: determine the required fixed-point format, determine the position of the decimal point, the bit width of the integer and the decimal, and then calculate the scaling factor according to the fixed-point format of the input signal. The calculation of the scaling factor depends on the difference in decimal places. For example, the fixed-point format of the input data is Q15 (i.e. 15 bits of decimal part) and the target is Q7 (i.e. 7 bits of decimal part), then the scaling factor is 2 15-7 =256, next divide by the scaling factor. This process from high precision to low precision will round off the decimal. Conversely, if converting from high precision Q15 to low precision Q7, multiplication by the scaling factor is needed. Overflow may occur when multiplying. In this embodiment, a scaling factor of 1 / 32 is used to prevent intermediate result overflow in precision control.

[0051] Especially when dealing with the sign bit, since the fixed-point number can be signed or unsigned. When performing format conversion: for signed numbers, sign extension is needed when increasing the bit width, extending the sign bit to the newly added high bit to maintain the correctness of the value. For unsigned numbers, directly fill 0 in the high bit.

[0052] Step 3: Perform 1M-point FFT calculation on the obtained data segment. Specifically, design Radix-32 as the basic algorithm architecture to perform 5-stage iterative butterfly calculation, improve the Radix-32 butterfly operation, and use specific rotation factors and complex multiplication optimization to improve the calculation efficiency.

[0053] For the specific implementation of Radix-32 FFT, first perform 32-bit reverse sorting to ensure that the elements in the sequence can be correctly matched when performing butterfly calculation, and perform necessary scaling and type conversion on the data. The FFT calculation of the sub-sequence can be represented as:

[0054]

[0055] wherein, L is the number of sub-sequence; according to Radix-32 FFT butterfly operation formula, the above formula can also be expressed as:

[0056]

[0057] wherein, k is the frequency point of FFT, the range of k is 0 to 32767, n represents the index of the element in the i-th sub-sequence, the value of N is 1M in the present application, and W represents a rotation factor. This process adopts a pipeline calculation architecture according to the selection of the hardware platform, and because 1M points are 32 to the power of 5, a 5-level Radix-32 butterfly operation is adopted for the design of the sub-module.

[0058] In the formula, the input discrete sequence (length 1M) is first divided into multiple sub-sequences with a size of 32. In each layer of recursion, the sequence is again divided into 32 sub-blocks, and FFT calculation is performed based on each sub-block. Next, recursive decomposition of the sub-problems is performed, and in each recursive level, the FFT calculation problem is decomposed into 32 smaller FFT sub-problems, and the end of the final algorithm is recursively reduced to each block containing only 32 data points. From the grouping mode of the above formula, 32 parallel multiplication operations are performed in the group, and finally the basic butterfly operation is completed by accumulation. Because 1M points are 32 to the power of 5, a 5-level Radix-32 butterfly operation is adopted for implementation. By recursively processing these smaller problems, the original problem is gradually transformed into a simple DFT calculation.

[0059] After each decomposition, the results of the block are subjected to butterfly operation, and the butterfly structure recombines the calculation results of different sub-blocks to obtain intermediate results. In each level of recursive calculation, the intermediate results are adjusted using the rotation factor, so that the frequency domain information output by each sub-problem can be correctly combined. In the process of hardware implementation of the algorithm, the rotation factor table is calculated in advance, and corresponding memory is created for data storage. An address conflict-free addressing method is designed to query and read the rotation factor table, avoiding the need to recalculate the rotation factor each time.

[0060] Step 4, for the sub-data segment, the intermediate results generated after the 1M-point FFT calculation are stored in a new memory space. Specifically, after the 1M-point FFT calculation, the same amount of intermediate results will be generated, and after L segments of 1M-point FFT calculation, new memory is needed to temporarily store these data, and the size of the memory is: L x 1M x bit width.

[0061] Step 5, calculating the intermediate rotation factor according to the number of L segments k ranges from 0 to 1M-1, and then multiplied with the FFT intermediate result corresponding to the calculation in step S4, the L-segment FFT calculated intermediate result allocates each segment to different complex multiplication calculation core and calculates in parallel. The specific process of calculation is that the expression of the new sequence obtained is as follows:

[0062]

[0063] In the formula, i ranges from 0 to L-1, this step is a transition calculation process for the next stage to perform butterfly merging, after complex multiplication calculation with the intermediate rotation factor according to the corresponding address, the calculated result is stored in the original memory space.

[0064] Step 6, the sub-FFT result after phase correction in step 5 is taken as the input of step 6, and the DFT calculation with the base of L is performed according to the segmentation number L of the original data, the iteration number of DFT is one-time multiplication addition, and finally the complete high-precision frequency spectrum sequence is obtained. The merging formula of DFT is as follows:

[0065]

[0066] The calculation process after splitting the above formula is as follows:

[0067] X(k) = X1'(k) + X2'(k) + L+X L '(k)

[0068]

[0069] In the formula, X1' to X L ' are the data of the 1M-point FFT result of each sub-segment after processing in step 5, and the Lx1M-point FFT processing result is obtained after calculation. According to the form characteristics of the formula, the merging process is highly parallelized by means of the hardware platform, and the calculation process will be realized as a merging calculation with a parallel degree of L on the hardware, and the merging process is processed by means of the pipeline technology, and the data required for X(k+1M) and the merging rotation factor are preloaded at the same time. The step utilizes the rotation factor The frequency components of each frequency point after the FFT calculation of each sub-segment are adjusted and merged, so that the intermediate result of the L-segment 1M-point FFT is in the correct position in the final frequency spectrum.

[0070] In some embodiments of the present application, Figure 2 According to Figure 1 According to the requirements of each step in the specific implementation process, a series form of hardware implementation architecture is proposed, and the specific implementation of the method in the specific hardware platform adopts the pipeline technology, and according to Figure 1After the step decomposition, the engineering requirements are divided into three sub-steps for implementation, and the use of pipeline architecture can provide three times the data throughput rate of the original. In the actual implementation process, fine control is needed for address exchange in the process, so as to ensure that the data in the system can flow correctly between various sub-modules. Specifically, these addresses include the address of the rotation factor stored in the ROM in advance, the address of the intermediate result data stored after each level of FFT iteration calculation, and the address operation of the bit reversal sorting required at the end of the hardware implementation of the algorithm to restore to normal order. In the process of the next level of FFT iteration, the calculation needs to be performed according to these intermediate result data, and the corresponding interface is defined in the sub-module to facilitate the processing of the data. The ping-pong RAM structure is used in cooperation with the pipeline working mode of the butterfly operation unit to ensure continuous operation of the pipeline, and there will be no empty phenomenon in the entire hardware system.

[0071] In some embodiments of the present application, Figure 3 The mutual comparison of the multiplication complexity of different radix calculation 1M-point FFT is shown. According to the simulation calculation, when performing 1M-point FFT calculation, the multiplication complexity of Radix-32 is reduced by 61.25%, 48.33%, 68.37%, 17.3%, and 91.9% compared with Radix-2, Radix-4, Radix-8, Radix-16, and Radix-64, respectively. Through comparison, it is not difficult to see that the selection of Radix-32 is an excellent choice for 1M-point FFT calculation in the process of algorithm hardware implementation. This is because the reduction of algorithm complexity will improve the running efficiency of the algorithm, and ensure that the system can accurately calculate and analyze the spectrum of large-scale data in real time.

[0072] In some embodiments of the present application, Figure 4 The 1M-point FFT algorithm flowchart in the embodiments of the present application is shown. Specifically, after the original data is zero-padded, it is divided into L segments of 1M-point sub-data segments using a specific grouping method. The sub-data segments will complete the 1M-point FFT calculation through this module. The calculation needs to be performed according to the characteristics of the Radix-32 FFT algorithm first, and the data is rearranged in reverse order of 32. According to the formula derivation, 1M-point FFT calculation needs to be iterated for 5 levels. After the reverse arrangement, the related parameters need to be iterated and updated in the process of hardware implementation. Then the parameters are passed to the Radix-32 butterfly calculation submodule. The submodule multiplies the specific elements in x(n) with the corresponding rotation factor and then performs butterfly addition. According to the formula derivation, this butterfly process needs to be performed 32768 times. After one butterfly calculation, the array index and related parameters are immediately prepared for the next stage of calculation.

[0073] In some embodiments of the present application, inFigure 5 In the method, the result of L-time 1M-point FFT is multiplied by the rotation factor of the intermediate stage, and then 1M-time L-point FFT calculation is performed. The base is designed as L by improving the 1M-time L-point FFT calculation, so that only one iteration of the new sequence calculated in the last calculation step is needed to obtain the final result.

[0074] In some embodiments of the present application, in Figure 6 In the method, the result of L-time 1M-point FFT is multiplied by the rotation factor of the intermediate stage, and then 1M-time L-point FFT calculation is performed. The base is designed as L by improving the 1M-time L-point FFT calculation, so that only one iteration of the new sequence calculated in the last calculation step is needed to obtain the final result. Figure 6 In the method, the result of L-time 1M-point FFT is multiplied by the rotation factor of the intermediate stage, and then 1M-time L-point FFT calculation is performed. The base is designed as L by improving the 1M-time L-point FFT calculation, so that only one iteration of the new sequence calculated in the last calculation step is needed to obtain the final result. -15 -15 -15 -15 -15

[0075] The basic principles, main features and advantages of the present application are shown and described above. Those skilled in the art should understand that the present application is not limited by the above embodiments, and the above embodiments and descriptions in the specification are only preferred examples of the present application and are not intended to limit the present application. Without departing from the spirit and scope of the present application, various changes and improvements can be made to the present application, and these changes and improvements all fall within the scope of the present application. The scope of protection of the present application is defined by the appended claims and their equivalents.​​​​​

Claims

1. A fast FFT processing method for ultra-large number of points, characterized in that, Includes the following steps: S1. Pad the original sampled signal data with zeros until the total length of the sequence is an integer multiple of point M1. S2. Perform data segmentation on the sampled signal data after zero-padding to obtain data segments; In step S2, the zero-padded sampled signal sequence x is divided into L segments, each segment having a length of M1 points, and each segment is defined as x. i Then we have: x i ={x[i],x[i+L],x[i+2L],...,x[i+(M1-1)L]}i=0,1,...,L-1; Then the elements in each segment can be represented as: x i [n]=x[n+L]n=0,1,...,M1-1; In the formula, n represents the index of an element in the i-th subsequence; S3. Perform an M1-point FFT on the obtained data segment; S4. Allocate memory space to store intermediate results; In step S4, a new memory space is created to store the intermediate results of the FFT calculation of the data segment with M1 points. S5. Multiply the FFT calculation result of point M1 in each segment by the corresponding rotation factor to perform phase correction; S6. Based on the results processed in step S5, merge the segmented spectra to obtain the total result after spectrum calculation.

2. The fast processing method for ultra-large number of points FFT according to claim 1, characterized in that: In step S1, it is first determined whether the length of the input sampled signal data is a multiple of M1 points. If this condition is met, step S2 is performed. If this condition is not met, zeros are padded to the end of the input system's sampled signal sequence until the length of the new sequence is an integer multiple of M1 points.

3. The fast processing method for ultra-large number of points FFT according to claim 1, characterized in that: In step S3, L arrays are created to store the rotation factor corresponding to each data segment. Then, FFT calculation is performed on each M1-point data sequence. During the calculation, the M1-point number subsequence input by the module is first preprocessed, including the R-ary bit reversal to adapt to radix decomposition. Then, decomposition and recursive calculation are performed to decompose the input sequence according to the predetermined radix.

4. The fast processing method for ultra-large point FFT according to claim 1, characterized in that: In step S3, the Radix-R FFT algorithm is used to decompose the input sequence into M1 / R subsequences with R points, and FFT calculation is performed on each subsequence.

5. The fast processing method for ultra-large point FFT according to claim 1, characterized in that: In step S5, the intermediate rotation factor is calculated based on the number of L segments. Then multiply it with the corresponding intermediate FFT result calculated in step S4.

6. The fast processing method for ultra-large number of points FFT according to claim 1, characterized in that: In step S6, the sub-FFT result after phase correction is used as an intermediate result. Based on the number of segments L of the original data, the FFT of the basis L is iterated and multiplied and added to obtain a complete and high-precision spectrum sequence.

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