A dynamic reconfiguration method of a two-dimensional memory access controller

Abstract

The application discloses a dynamic reconstruction method of a two-dimensional memory access controller and belongs to the technical field of memory access controllers, and specifically comprises the following steps: extracting parallelism and operation characteristics of a matrix algorithm, determining a partition mode of a storage module and partitioning matrix source data according to the parallelism and the operation characteristics; determining the number of activated source data channels based on the parallelism, and realizing efficient transmission of data from storage to calculation; moving the matrix source data from the storage module to a calculation module through the source data channels according to the parallelism and the operation characteristics, and executing matrix operation; determining the number of activated result data channels according to the parallelism and results after the operation is completed, and transmitting the results back to the storage module; and dynamically adjusting configurations of various modules according to algorithms and operation requirements, so that the flexibility and efficiency of matrix operation are improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of memory access controllers, and particularly relates to a dynamic reconstruction method of a two-dimensional memory access controller. BACKGROUND

[0002] With the rapid development of information technology, especially the rise of big data, cloud computing and artificial intelligence, higher and higher requirements are put forward for the performance and flexibility of computing systems. Traditional computing systems often use fixed hardware architectures and algorithm implementations, which are difficult to meet the needs of high performance and flexibility of these emerging applications. Therefore, dynamic reconstruction technology emerges as the times require, which allows dynamic changes in hardware architecture or algorithm implementation during the computing process according to actual needs, thereby improving the flexibility and adaptability of the computing system.

[0003] The memory access controller is responsible for managing and optimizing the transmission of data between the memory and the processor to improve the execution efficiency of the algorithm. However, the traditional memory access controller often uses a fixed design, which is difficult to adapt to the different needs of different matrix algorithms for memory access mode and data transmission speed, resulting in that the memory access controller may become a performance bottleneck when processing complex matrix algorithms, limiting the performance improvement of the entire computing system.

[0004] The patent with the authorized announcement number CN109284231B discloses a memory access request processing method, device and memory controller, which comprises: sequentially obtaining a plurality of memory access requests; extracting the logical channel address in the memory access request; grouping the memory access requests based on the logical channel address to form a plurality of request groups; for each request group, sequentially preprocessing the memory access request to form the instructions required to complete the memory access request; and sequentially reconstructing the instructions corresponding to each memory access request in each request group. The technical solution is based on the fact that the operations of different logical channel addresses of the memory do not affect each other during specific work, and after the pre-charge or activation instruction for the same logical channel address is issued, if another logical channel address is operated, there is no need to wait for the completion of the previous operation, which can avoid the low interface utilization rate caused by the waiting time of each pre-charge and activation, and improve the memory access efficiency.

[0005] The above existing technologies have the following problems: 1) limited dynamic adjustment capability; 2) although the memory access efficiency is improved by avoiding the waiting time of pre-charge and activation, this optimization is not enough to meet the needs of high-performance matrix operations; 3) the application scenarios have limitations. SUMMARY

[0006] In view of the deficiencies of the prior art, the application provides a dynamic reconstruction method of a two-dimensional memory access controller, which is based on the design idea of storage and calculation decoupling, separates the data storage and data processing, extracts the parallelism and operation characteristics of a matrix algorithm, determines the partition mode of a storage module and partitions the matrix source data according to the parallelism and operation characteristics, determines the number of activated source data channels based on the parallelism, realizes the efficient transmission of data from storage to calculation, moves the matrix source data from the storage module to the calculation module through the source data channel according to the parallelism and operation characteristics, executes the matrix operation, determines the number of activated result data channels according to the parallelism and result after the operation is completed, and transmits the result back to the storage module, and dynamically adjusts the configurations of the modules according to the algorithm and operation requirements, thereby improving the flexibility and efficiency of the matrix operation.

[0007] To achieve the above object, the application provides the following technical scheme.

[0008] A dynamic reconstruction method of a two-dimensional memory access controller, comprising:

[0009] Step S1: Extract the parallelism and operation characteristics of a matrix algorithm, determine the partition mode of a storage module according to the parallelism and operation characteristics of the matrix algorithm, and partition and store the matrix source data to the matrix storage module, wherein the parallelism of the matrix algorithm is the proportion or number of the parts that can be executed in parallel in the matrix algorithm, and the matrix source data is stored longitudinally by column / row in the storage module.

[0010] Step S2: Calculate the number of activated matrix source data channels required based on the matrix source data stored in step S1, and configure the corresponding matrix source data channels.

[0011] Step S3: Move the matrix source data from the matrix storage module to the calculation module through the configured matrix source data channels according to the extracted parallelism and operation characteristics of the matrix algorithm, and execute the matrix operation.

[0012] Step S4: After the matrix operation is completed, determine the number of activated matrix operation result data channels based on the extracted parallelism of the matrix algorithm and the matrix operation result, configure the corresponding matrix operation result data channels, and move the matrix operation result data from the calculation module to the matrix storage module through the matrix operation result data channels.

[0013] Step S5: Dynamically evaluate the performance and efficiency of the current system using the throughput index, and adjust the configurations of the storage module, data channels and calculation module according to the evaluation result.

[0014] Specifically, the operation characteristics in step S1 include the number of operands, the in-out number mode and the activation requirement of the intermediate result area.

[0015] The number of operands num, if num=1, is covariance, if num=2, is matrix algorithm, the matrix algorithm includes matrix addition / subtraction, matrix multiplication, weighted method and generalized inner product;

[0016] The input / output number mode includes matrix source data horizontal / vertical broadcast output number mode, matrix source data parallel output number mode, result area sequential input number mode, result area parallel input number mode and intermediate result area input / output number mode;

[0017] The intermediate result area enabling requirement, if it is generalized inner product and covariance algorithm, the intermediate result area needs to be enabled, if it is matrix addition / subtraction, matrix multiplication, matrix algorithm of weighted method, the intermediate result area does not need to be enabled.

[0018] Specifically, the matrix source data partition mode in step S1 includes;

[0019] If num=1, no partition of the matrix source data area is performed, and the matrix source data area is used to store the matrix source data corresponding to a single operand;

[0020] If num=2, the matrix source data area is divided into two partitions, which are respectively used to store the matrix source data corresponding to one operand, and each partition includes m memories, wherein m represents the matrix parallelism degree, and m is a power of 2.

[0021] Specifically, the extraction of the matrix parallelism degree m in step S1 includes:

[0022] According to the peak floating point computing power, the storage bandwidth and the operation density, a ridge performance model is constructed. Under this model, the operation density is the number of floating point operations that can be supported per byte of memory access. The number of floating point operations per byte is determined by the operation characteristics and the parallelism degree. According to the peak floating point computing power and the storage bandwidth, the value of the operation density at the "ridge point" of the model is determined, and then according to the operation characteristics, the matrix algorithm parallelism degree is determined.

[0023] Specifically, the matrix source data channel division in step S2 includes:

[0024] If num=1, no division of the matrix source data channel is performed, and the matrix source data channel is used for transmission of the matrix source data corresponding to a single operand;

[0025] If num=2, the matrix source data channel is divided into two groups of matrix source data channels, which are respectively used to transmit the matrix source data corresponding to one operand, and each group includes m matrix source data channels.

[0026] Specifically, the specific steps of step S3 include:

[0027] S3.1: According to the extracted matrix algorithm parallelism and operation characteristics, determine the required operation unit type and the number of enabled operation units, and according to the operation unit type, determine the output mode of the matrix source data;

[0028] If the matrix algorithm is matrix multiplication or weighted method, the output mode of the matrix source data 1 area and the matrix source data 2 area is parallel output, and m data is transmitted to m addition operation units in a clock cycle Δt for calculation;

[0029] If the matrix algorithm is weighted method, the matrix source data 1 area is reconstructed into a horizontal broadcast output mode, and the matrix source data 2 area is reconstructed into a parallel output mode. In Δt, the matrix source data 1 area provides 1 data broadcast to m multiplication and accumulation calculation units, and the source data 2 area provides m numbers to m multiplication and accumulation calculation units for calculation, wherein the matrix source data 1 area is stored in the storage module in horizontal order by row, and the matrix source data 2 area is stored in the storage module in vertical order by column;

[0030] If the matrix algorithm is generalized inner product, the matrix source data 1 area is reconstructed into a vertical broadcast output mode, and the matrix source data 2 area is reconstructed into a parallel output mode. In Δt, the matrix source data 1 area provides 1 data broadcast to m conjugate multiplication and accumulation calculation units, and the matrix source data 2 area provides m numbers to m conjugate multiplication and accumulation calculation units for calculation, wherein the matrix source data 1 area and the matrix source data 2 area are stored in the storage module in vertical order by column;

[0031] If it is covariance, that is, num = 1, the matrix source data area is reconstructed into a parallel output mode. In Δt, the matrix source data provides m numbers to the multiplication and addition tree calculation unit for calculation, wherein the matrix source data is stored in the storage module in vertical order by column.

[0032] Specifically, the specific steps of the step S3 further include:

[0033] S3.2: Based on the type, number and output mode of the operation unit determined in S3.1, determine the enabling requirement of the intermediate result area;

[0034] If the intermediate result area is not enabled, the n intermediate results generated by the operation module are directly output as the final result, wherein n represents the parallelism of the intermediate result calculation, and n is a power of 2;

[0035] If the intermediate result area is enabled, after the intermediate result operation unit completes the calculation, m intermediate result data is accepted and stored in the intermediate result area in Δt;

[0036] S3.3: Perform matrix operation in the configured calculation module.

[0037] Specifically, the specific steps of the step S4 include:

[0038] S4.1: Obtain the matrix operation result output by the calculation module in step S3.3, and store the matrix operation result data;

[0039] S4.2: Determine the size and structure of the matrix operation result data according to the extracted parallelism of the matrix algorithm, and determine the input mode of the matrix operation result data according to the size and structure of the matrix operation result and the interface capability of the matrix storage module, and determine the number of activated channels of the matrix operation result data at the same time;

[0040] S4.3. If the matrix algorithm adopts a parallel processing mode during operation, and the result data can be output in parallel, the matrix operation result input mode is a parallel input mode;

[0041] If the matrix operation result input mode is a parallel input mode, m result data channels are activated at the same time upon receiving an operation end signal of the calculation module within one Δt, and m result data are stored in the matrix storage module in parallel through the m result data channels;

[0042] S4.4: If the matrix algorithm adopts a sequential processing mode during operation, or the matrix operation result data needs to be output in sequence, the matrix operation result input mode is a sequential input mode;

[0043] If the matrix operation result input mode is a sequential input mode, one result data channel is activated upon receiving an operation end signal of the calculation module for one clock cycle, and one result data is stored in the matrix storage module through the one result data channel.

[0044] An electronic device comprising a memory and a processor, the memory storing a computer program, and the processor implementing the steps of the dynamic reconstruction method of the two-dimensional memory access controller when executing the computer program.

[0045] A computer readable storage medium having computer instructions stored thereon, the computer instructions executing the steps of the dynamic reconstruction method of the two-dimensional memory access controller when executed.

[0046] Compared with the prior art, the beneficial effects of the present application are:

[0047] 1. The present application proposes a dynamic reconstruction method of a two-dimensional memory access controller, and proposes a dynamic reconstruction method of a multi-functional vector algorithm accelerator, which can dynamically reconstruct the hardware circuit according to the actual algorithm operation demand, and flexibly combine and schedule the storage resources, data paths and calculation resources, thereby solving the problems of redundant control logic and data flow paths existing in the multi-functional vector algorithm accelerator.

[0048] 2.The application provides a dynamic reconstruction method of a two-dimensional memory access controller, which realizes flexible configuration of a storage module, a data channel and a calculation module by extracting parallelism and operation characteristics of a matrix algorithm. The customized configuration based on algorithm characteristics not only improves parallel processing efficiency of matrix operation, but also ensures efficiency and accuracy of data in the storage and transmission process. The process realizes full use of hardware resources by storing matrix source data column by column longitudinally and determining the configuration of the storage partition, the data channel and the operation unit according to the algorithm parallelism, thereby improving the overall performance of the system.

[0049] 3.The application provides a dynamic reconstruction method of a two-dimensional memory access controller, which also realizes continuous optimization of system configuration by dynamically evaluating the throughput and efficiency of the system. After the matrix operation is completed, the system automatically adjusts the number of enabled data channels according to the operation result and the algorithm parallelism to optimize the data transmission efficiency. At the same time, by regularly or real-time evaluating the system performance, potential bottleneck problems can be found and solved in time, so as to ensure that the system always maintains an efficient and stable running state, and can adapt to different sizes and complexities of matrix operation. BRIEF DESCRIPTION OF DRAWINGS

[0050] Figure 1 It is a schematic diagram of the dynamic reconstruction method of the two-dimensional memory access controller of the application.

[0051] Figure 2 It is a principle flowchart of the dynamic reconstruction method of the two-dimensional memory access controller of the application.

[0052] Figure 3 It is an implementation flowchart of the dynamic reconstruction method of the two-dimensional memory access controller of the application.

[0053] Figure 4 It is a schematic diagram of matrix source data stored in the storage module in a row transverse manner with a parallelism of 16.

[0054] Figure 5 It is a schematic diagram of matrix source data stored in the storage module in a column longitudinal manner with a parallelism of 16.

[0055] Figure 6 It is a schematic diagram of matrix result data stored in the storage module in a row transverse manner with a parallelism of 16. DETAILED DESCRIPTION

[0056] Embodiment 1

[0057] Please refer to Figure 1 andFigure 3 An embodiment of the present application provides a dynamic reconstruction method of a two-dimensional memory access controller. The core idea is to dynamically adjust and optimize the structure and parameters of the memory access controller according to the operation characteristics and requirements of the matrix algorithm, so as to adapt to different algorithms and data scales, thereby ensuring efficient and accurate execution of the algorithm, and being applicable to hardware circuit implementation of the matrix algorithm accelerator under different parallelism, and improving design efficiency. The method comprises the following steps:

[0058] Step S1: extracting the parallelism and operation characteristics of the matrix algorithm, determining the partition mode of the storage module according to the parallelism and operation characteristics of the matrix algorithm, and storing the matrix source data into the matrix storage module in a partitioned manner, wherein the matrix source data is stored in the storage module in a column / row longitudinal manner;

[0059] It should be noted that when performing matrix multiplication / weighting, E=AB, wherein the A matrix is stored in the storage module in a row transverse manner, and the source data matrix of all other algorithms is stored in the module in a column longitudinal manner.

[0060] The parallelism of the matrix algorithm is the proportion or quantity of the part that can be executed in parallel in the matrix algorithm.

[0061] Further, the specific steps of step S1 comprise:

[0062] (1) analyzing the parallelism of the matrix algorithm to determine the operation parallelism of the matrix algorithm;

[0063] The extraction of the matrix parallelism m comprises:

[0064] A ridge performance model is constructed according to the peak floating point computing power, the storage bandwidth and the operation density. Under this model, the operation density is the number of floating point operations that can be supported per byte of memory access. The number of floating point operations per byte is determined by the operation characteristics and the parallelism. According to the peak floating point computing power and the storage bandwidth, the value of the operation density at the ridge point of the model is determined, and then the matrix algorithm parallelism is determined according to the operation characteristics.

[0065] It should be noted that the determination of the algorithm parallelism usually includes the following aspects in addition to the performance influence.

[0066] 1) calculation step: in the matrix algorithm, some calculation steps are independent and can be executed in parallel. For example, in matrix addition, the addition operation of each element is independent and can be performed in parallel.

[0067] 2) iteration process: for the matrix algorithm involving the iteration process, such as matrix power operation or matrix solution, the iteration process can be divided into multiple stages, and each stage can be executed in parallel.

[0068] Meanwhile, when determining the parts that can be executed in parallel, some limiting factors also need to be considered:

[0069] 1) Data dependency: If there is a data dependency relationship between the calculation steps in the matrix algorithm, these steps cannot be executed in parallel, and the data dependency relationship in the algorithm needs to be carefully analyzed to determine which steps can be executed in parallel;

[0070] 2) Communication overhead: Parallel execution needs to handle data communication problems between multiple processors, and if the communication overhead is too large, it will affect the efficiency of parallel execution, so when selecting the part to be executed in parallel, the balance between the calculation overhead and the communication overhead needs to be considered;

[0071] 3) Load balancing: In order to ensure the efficiency of parallel execution, it is necessary to ensure the load balancing between each processor, if the task of a certain processor is too heavy, and the task of other processors is too light, it will lead to the decline of the overall performance, therefore, when dividing the task, the problem of load balancing needs to be considered.

[0072] (2) Analyze the operation characteristics of the matrix algorithm, such as the size, shape, and number of source data matrices, and determine the data dependency relationship and communication overhead in parallel computation according to the operation characteristics;

[0073] Further, the steps of data dependency relationship include:

[0074] 1) Analyze the operation steps:

[0075] Analyze each operation step in the parallel algorithm to determine which steps need to access or modify shared data, and identify which data is repeatedly used or dependent on each other in multiple steps;

[0076] 2) Build dependency graph:

[0077] Use the dependency graph to intuitively represent the dependency relationship between data, in the dependency graph, the node represents the data item, and the edge represents the dependency relationship between the data items, and by analyzing the dependency graph, determine which data items can be processed in parallel, and which must be processed in order, wherein, the dependency graph analysis method is the prior art content in the art, and is not the inventive scheme of the present application, and will not be repeated here;

[0078] 3) Consider parallel model:

[0079] Further analyze the data dependency relationship according to the parallel computing model used, such as pipeline parallelism, data parallelism, and task parallelism;

[0080] For example, in pipeline parallelism, it is necessary to ensure that the data of each partition can be correctly passed to the next partition after processing is completed.

[0081] Further, the specific steps of determining the communication overhead include:

[0082] 1) Assessing data transfer volume: calculating the amount of data required to be transferred in each step of the parallel algorithm, including data transfer from memory to processor, data transfer between processors;

[0083] 2) Considering communication mode: analyzing the mode of data transfer, such as point-to-point communication, broadcast communication, and collection communication, different communication modes have different effects on communication overhead;

[0084] 3) Assessing communication delay and bandwidth: measuring the delay and bandwidth of the communication network to understand the speed and efficiency of data transfer, where delay represents the time required for data to travel from sender to receiver, and bandwidth represents the amount of data that can be transmitted by the communication network in a unit of time;

[0085] 4) Considering load balancing: ensuring that each processor or computing node in the parallel algorithm is allocated an equal amount of work, where uneven load distribution can cause some processors to wait for other processors to complete data transfer, thereby increasing communication overhead.

[0086] 5) Optimizing communication strategy: using data compression to reduce data transfer volume, and using overlapping communication and computing techniques, i.e., performing data transfer while the processor is performing calculations, to hide communication delay.

[0087] (3) According to the parallel degree and operation characteristics of the matrix algorithm, the partitioning mode of the storage module is designed, and in the present application, the row-column partitioning mode is selected;

[0088] (4) The matrix source data is stored in the matrix storage module according to the designed partitioning mode, to ensure that the storage module can support parallel access and efficient data transfer.

[0089] Step S2: Based on the matrix source data determined in step S1, the number of required matrix source data channels is calculated, and the corresponding matrix source data channels are configured;

[0090] (1) Configure the matrix source data channel, including but not limited to the path, rate, and format of data transfer, and set data handling strategies such as direct memory access or caching strategies to optimize data transfer efficiency;

[0091] (2) Read the matrix source data to be processed from the matrix storage module, and package the read matrix source data according to the requirements of the computing module, where packaging includes data format conversion, data alignment, data blocking, etc. The specific implementation process of data packaging is existing technology in the art, and is not the inventive scheme of the present application, and will not be described here;

[0092] Step S3: According to the extracted matrix algorithm parallelism and operation characteristics, the matrix source data is moved from the matrix storage module to the calculation module through the configured matrix source data channel, and the matrix operation is executed;

[0093] Further, the specific steps of moving the matrix source data from the matrix storage module to the calculation module include:

[0094] (1) Start the data transmission process through the configured data channel, and monitor the transmission state during the data transmission process to ensure that the data is correctly and completely transmitted to the calculation module. If transmission errors or abnormalities are found, error handling or retransmission is performed in a timely manner;

[0095] (2) Access control is performed on the data receiving interface of the calculation module to receive the data transmitted from the matrix storage module. The specific access control is a prior art in the field and is not the inventive scheme of the present application, and will not be described here;

[0096] (3) The calculation module parses the received data to restore it to the original matrix data or the required format for calculation. The parsing includes data format conversion and data reorganization, and the parsing process is a prior art in the field and is not the inventive scheme of the present application, and will not be described here;

[0097] (4) The calculation module processes the parsed data, executes the corresponding matrix algorithm, and transmits the matrix algorithm result back to the matrix storage module for further processing.

[0098] It should be noted that during the process of moving the matrix source data from the matrix storage module to the calculation module, there is a certain relationship between the matrix blocking strategy and the data moving method. The matrix blocking strategy determines how to divide a large matrix into multiple smaller sub-matrices for parallel calculation, while the data moving method focuses on how to efficiently move these sub-matrices from the storage module to the calculation module.

[0099] The relationship between the matrix blocking strategy and the data moving method includes:

[0100] (1) The blocking strategy affects the data moving requirements:

[0101] The size, shape and number of matrix blocks directly affect the scale and frequency of data moving. Larger blocks may reduce the number of data moves, but the amount of data moved each time will increase. Smaller blocks may increase the number of data moves, but the amount of data moved each time is smaller.

[0102] The blocking strategy also affects the complexity of data moving. For example, if the block shape is irregular or the size is inconsistent, it will increase the difficulty and cost of data moving.

[0103] (2) Data transfer method optimization block strategy execution:

[0104] Efficient data transfer methods can accelerate data transmission after matrix blocking, thus supporting more complex blocking strategies. For example, using high-speed data transmission interfaces such as PCIe, Ethernet, or parallel data transmission technologies such as DMA, multi-threading can improve data transfer efficiency;

[0105] Optimization of data transfer methods can also reduce delays and overheads during data transmission, further improving the overall performance of matrix operations.

[0106] On the other hand, the specific steps of determining the data transfer method according to the matrix blocking strategy include:

[0107] (1) Understand the parallelism and operation characteristics of the matrix algorithm, including the computational complexity, memory access pattern, and data dependency relationship. These information are the basis for determining the matrix blocking strategy and data transfer method;

[0108] (2) Determine the matrix blocking strategy based on the parallelism and operation characteristics of the matrix algorithm, including selecting the size, shape, and number of blocks, and determining the partitioning method of the blocks, such as row-wise blocking, column-wise blocking, or sub-matrix blocking;

[0109] (3) Evaluate the feasibility of different data transfer methods, including considering the data transmission rate, delay, overhead, and overall system architecture and communication cost. Common data transfer methods include direct memory access, network transmission, and shared memory;

[0110] (4) Select the data transfer method based on the evaluation results of the matrix blocking strategy and data transfer method, which needs to consider the efficiency, overhead, and overall system performance of data transmission;

[0111] (5) Optimize the data transfer process, including adjusting the data transmission rate, optimizing the data transmission scheduling strategy, reducing the data transmission delay and overhead, etc. At the same time, high-efficiency data transmission protocols and compression algorithms can be used to further improve the efficiency and reliability of data transfer.

[0112] Step S4: After the matrix operation is completed, the number of enabled matrix operation result data channels is determined based on the extracted matrix algorithm parallelism and matrix operation result, and the corresponding matrix operation result data channels are configured. The matrix operation result data is transferred from the calculation module to the matrix storage module through the matrix operation result data channels;

[0113] Step S5: dynamically evaluate the performance and efficiency of the current system using the throughput index, and adjust the configuration of the storage module, data channel and computing module according to the evaluation results, wherein the calculation formula of the throughput index is a prior art content in the field and is not the inventive scheme of the present application, and is not described here.

[0114] In the present application, the analysis of the matrix algorithm and the feature extraction, the partition design of the storage module, the configuration of the data transmission channel, the execution of the matrix operation, the result feedback and storage, and the dynamic configuration adjustment are summarized as matrix calculation and memory access decoupling, which specifically includes:

[0115] (1) Matrix algorithm analysis and feature extraction:

[0116] Parallelism analysis: First, the matrix algorithm is analyzed in depth to determine its parallelism, which refers to the amount of data or operations that can be processed simultaneously by the algorithm. For example, in matrix multiplication, multiple element multiplication and accumulation operations can be processed in parallel.

[0117] Operation feature extraction: In addition to parallelism, the operation features of the algorithm need to be extracted, such as data type, operation mode, and data access mode. The data type includes integer and floating point number, the operation mode includes multiplication and transpose, and the data access mode includes row priority and column priority.

[0118] (2) Storage module partition design:

[0119] Partition mode determination: Based on the extracted parallelism and operation features, the partition mode of the storage module is determined. For example, if the algorithm has high row parallelism, the matrix can be partitioned by rows; if the algorithm needs to frequently access the transpose form of the matrix, it may need to be partitioned by columns or blocks.

[0120] Partitioned storage matrix source data: According to the determined partition mode, the matrix source data is stored in the corresponding storage partition. Each partition can be regarded as an independent data block, which is convenient for subsequent parallel processing.

[0121] (3) Data transmission channel configuration:

[0122] Number of enabled channels determination: Based on the parallelism, the number of enabled channels for source data is determined. These channels are used to transmit data from the storage module to the computing module.

[0123] Efficient transmission implementation: Direct memory access is used to achieve efficient transmission of data from the storage module to the computing module. Direct memory access can transmit data from the source address to the target address without occupying CPU resources, thereby improving the efficiency of data transmission.

[0124] (4) Matrix operation execution:

[0125] Data migration: Move matrix source data from the storage module to the computing module through the configured source data channel.

[0126] Operation execution: In the calculation module, matrix operations are performed according to the algorithm and operation characteristics. This can be achieved through parallel processors or multi-threaded or multi-core processors;

[0127] Intermediate result processing: During the calculation process, if intermediate results need to be processed, they can be stored in the local cache of the computing module or transferred back to the storage module for further processing as needed;

[0128] (5) Result transmission and storage:

[0129] Result data channel configuration: After the operation is completed, the number of result data channels enabled is determined based on the degree of parallelism and the characteristics of the result data.

[0130] Result return: The calculation results are transmitted from the calculation module to the storage module through the configured result data channel;

[0131] Result storage: In the storage module, the operation results are stored and processed as needed. For example, the results can be saved as files, updated to a database, or used for subsequent algorithm processing;

[0132] (6) Dynamic configuration adjustment:

[0133] Module configuration adjustment: Dynamically adjust storage modules, computing modules, and data transmission channels based on changes in algorithms and computing requirements, including adjusting partition sizes, enabling or disabling data channels, and adjusting cache strategies;

[0134] Improved flexibility and efficiency: Through dynamic configuration adjustment, it can adapt to different algorithms and computing requirements, thereby improving the flexibility and efficiency of matrix operations.

[0135] The operation characteristics in step S1 include the number of operands, the input and output data mode, and the requirement to enable the intermediate result area;

[0136] The number of operands num, if num=1, it is covariance, if num=2, it is matrix algorithm, the matrix algorithm includes matrix addition / subtraction, matrix multiplication, weighted method and generalized inner product;

[0137] The input and output modes include horizontal / vertical broadcast output mode of matrix source data, parallel output mode of matrix source data, sequential input mode of result area, parallel input mode of result area and input and output mode of intermediate result area;

[0138] If the intermediate result area is needed, the intermediate result area is enabled if the generalized inner product and covariance algorithm is used, and the intermediate result area is not enabled if the matrix addition / subtraction algorithm, the matrix multiplication algorithm, and the weighted matrix algorithm are used.

[0139] The matrix source data partition mode in step S1 includes:

[0140] If num = 1, the matrix source data area is not partitioned, and the matrix source data area is used to store the matrix source data corresponding to a single operand.

[0141] If num = 2, the matrix source data area is partitioned into two partitions, and each partition is used to store the matrix source data corresponding to one operand. Each partition includes m memories, where m represents the parallelism degree of the matrix algorithm, and m is a power of 2.

[0142] The matrix source data channel division in step S2 includes:

[0143] If num = 1, the matrix source data channels are not divided, and the matrix source data channels are all used to transmit the matrix source data corresponding to a single operand.

[0144] If num = 2, the matrix source data channels are divided into two groups of matrix source data channels, and each group is used to transmit the matrix source data corresponding to one operand. Each group includes m matrix source data channels.

[0145] Embodiment 2

[0146] Please refer to Figures 4-6 , in Figures 4-6In the embodiment, when the large dot matrix source data is stored in the storage module, the matrix is split into a maximum of 16 rows and n columns, instead of being stored row by row. The specific reasons include: 1) The storage module is designed with a parallelism of 16, which means that it can process 16 data channels in parallel at the same time. Splitting the matrix into a maximum of 16 rows and n columns can make full use of the parallel processing capability of the storage module, so that each data access can be performed in parallel, thereby significantly improving the efficiency and throughput of data access; 2) If the matrix is stored row by row, then when processing a large matrix, data needs to be frequently moved between the storage module and the calculation module. By splitting the matrix into 16 rows and n columns, a data block, i.e., 16 rows of data, can be moved to the calculation module for processing at one time, thereby reducing the number and cost of data movement; 3) Matrix operations usually have high data locality, i.e., adjacent data elements are frequently accessed during the operation. By splitting the matrix into 16 rows and n columns, multiple elements within a data block can be continuously accessed during memory access, thereby optimizing the memory access mode and improving the efficiency of memory access; 4) By splitting the matrix into 16 rows and n columns, it is more convenient to perform block processing on the data in the preprocessing stage, and the cache can be used to store and process these data blocks. The specific steps of step S3 in the embodiment include:

[0147] S3.1: Determine the required operation unit type and the number of enabled operation units according to the extracted matrix algorithm parallelism and operation characteristics, and determine the output mode of the matrix source data according to the operation unit type;

[0148] If the matrix algorithm is matrix addition / subtraction, the output mode of the matrix source data 1 region and the matrix source data 2 region is parallel output, and m data are transmitted to m addition operation units for calculation in one clock cycle Δt;

[0149] If the matrix algorithm is matrix multiplication or weighted method, the matrix source data 1 region is reconstructed into a horizontal broadcast output mode, and the matrix source data 2 region is reconstructed into a parallel output mode. In Δt, the matrix source data 1 region provides one data to be broadcast to m multiplication and accumulation calculation units, and the matrix source data 2 region provides m data to m multiplication and accumulation calculation units for calculation, wherein the matrix source data 1 region is stored in the storage module in horizontal order by row, and the matrix source data 2 region is stored in the storage module in vertical order by column;

[0150] If the matrix algorithm is generalized inner product, the matrix source data 1 region is reconstructed into a vertical broadcast output mode, and the matrix source data 2 region is reconstructed into a parallel output mode. In Δt, the matrix source data 1 region provides one data to be broadcast to m conjugate multiplication and accumulation calculation units, and the matrix source data 2 region provides m data to m conjugate multiplication and accumulation calculation units for calculation, wherein the matrix source data 1 region and the matrix source data 2 region are both stored in the storage module in vertical order by column;

[0151] If the covariance, that is, num = 1, the matrix source data area is reconstructed into a parallel output mode, and in Δt, the matrix source data provides m numbers to the multiply-add tree calculation unit to complete the calculation, wherein the matrix source data is stored column by column in the storage module.

[0152] The specific steps of step S3 further include:

[0153] S3.2: Based on the type, enabled number and output mode of the operation unit determined in S3.1, determine the enabled requirement of the intermediate result area;

[0154] If the intermediate result area is not enabled, the n intermediate results generated by the operation module are directly output as the final results, wherein n represents the parallel degree of intermediate result calculation, and n is a power of 2;

[0155] If the intermediate result area is enabled, after the intermediate result operation unit completes the calculation, m intermediate result data is accepted and stored in the intermediate result area in Δt;

[0156] S3.3: Perform matrix operation in the configured calculation module.

[0157] The specific steps of step S4 include:

[0158] S4.1: Obtain the matrix operation result output by the calculation module in step S3.3, and store the matrix operation result data;

[0159] S4.2: Determine the size and structure of the matrix operation result data according to the extracted parallel degree of the matrix algorithm, and determine the input mode of the matrix operation result data according to the size, structure of the matrix operation result and the interface capability of the matrix storage module, and determine the enabled number of the matrix operation result data channel;

[0160] S4.3. If the matrix algorithm adopts parallel processing mode in the operation process, and the result data can be output in parallel, the matrix operation result input mode is parallel input mode;

[0161] If the matrix operation result input mode is parallel input mode, m result data channels are enabled at the same time after receiving the operation end signal of one Δt of the calculation module, and m result data is stored in the matrix storage module through the m result data channels;

[0162] S4.4: If the matrix algorithm adopts sequential processing mode in the operation process, or the matrix operation result data needs to be output in sequence, the matrix operation result input mode is sequential input mode;

[0163] If the matrix operation result is in the sequential number mode, one result data channel is enabled and one result data is stored in the matrix storage module through the result data channel when the operation end signal of one clock cycle of the calculation module is received.

[0164] Embodiment 3

[0165] An electronic device includes a memory and a processor, the memory stores a computer program, and the processor implements the steps of the dynamic reconstruction method of the two-dimensional memory access controller when executing the computer program. For details, refer to the above method embodiments, which will not be repeated here.

[0166] A computer readable storage medium having computer instructions stored thereon, when the computer instructions are executed, the steps of a dynamic reconstruction method of a two-dimensional memory access controller are executed, wherein the storage medium can be a volatile or non-volatile computer readable storage medium.

[0167] The embodiments of the present application are described above in combination with the drawings, but the present application is not limited to the above specific embodiments, and the above specific embodiments are only illustrative and not restrictive. Those skilled in the art can make changes, modifications, replacements and variations to the above embodiments without departing from the purpose of the present application and the scope of protection, which are all within the protection of the present application.

Claims

1. A dynamic reconfiguration method of a two-dimensional memory access controller, characterized in that, The method comprises the following steps: Step S1: Extract the parallelism and operation characteristics of the matrix algorithm, determine the partition mode of the storage module according to the parallelism and operation characteristics of the matrix algorithm, and store the matrix source data into the matrix storage module, wherein the parallelism of the matrix algorithm is the proportion or number of the part that can be executed in parallel in the matrix algorithm, and the matrix source data is stored vertically by column / row in the storage module; Step S2: Based on the stored matrix source data determined in step S1, calculate the number of enabled matrix source data channels required, and configure the corresponding matrix source data channels; Step S3: According to the extracted parallelism and operation characteristics of the matrix algorithm, move the matrix source data from the matrix storage module to the calculation module through the configured matrix source data channels, and execute the matrix operation; Step S4: After the matrix operation is completed, based on the extracted parallelism of the matrix algorithm and the matrix operation result, determine the number of enabled matrix operation result data channels, configure the corresponding matrix operation result data channels, and move the matrix operation result data from the calculation module to the matrix storage module through the matrix operation result data channels; Step S5: Dynamically evaluate the performance and efficiency of the current system using the throughput index, and adjust the configuration of the storage module, data channel and calculation module according to the evaluation result; The operation characteristics in step S1 include the number of operands, the input / output mode and the intermediate result area enablement requirement; The number of operands num, if is a covariance, if is a matrix algorithm, the matrix algorithm including matrix addition / subtraction, matrix multiplication, weighted sum, and generalized inner product; The input / output mode includes the matrix source data horizontal / vertical broadcast output mode, the matrix source data parallel output mode, the result area sequential input mode, the result area parallel input mode and the input / output mode of the intermediate result area; If it is a generalized inner product and covariance algorithm, the intermediate result area needs to be enabled, and if it is a matrix addition / subtraction algorithm, a matrix multiplication algorithm or a weighted matrix algorithm, the intermediate result area does not need to be enabled; The matrix source data partition mode in step S1 includes: If then no partitioning of the matrix source data region is performed and the matrix source data region is used to store the matrix source data corresponding to the single operand; If If m is equal to 2, the matrix source data is divided into two partitions, and each partition is used for storing the matrix source data corresponding to one operand. The extraction of the matrix parallelism m in step S1 includes: A ridge performance model is constructed according to the peak floating point computing power, the storage bandwidth and the operation density; under the ridge performance model, the operation density is the number of floating point operations that can be supported per byte of memory access; the number of floating point operations per byte is determined by the operation characteristics and the parallelism; the operation density at the "ridge point" of the model is determined according to the peak floating point computing power and the storage bandwidth, and then the matrix algorithm parallelism is determined according to the operation characteristics; The matrix source data channel division in step S2 includes: If , no division of the matrix source data lanes is performed and the matrix source data lanes are all used for the transmission of the matrix source data corresponding to a single operand. If then the matrix source data channels are divided into two groups of matrix source data channels, respectively used for transmitting the matrix source data corresponding to one operand, and each group includes m matrix source data channels; The specific steps of step S3 include: S3.1: According to the extracted matrix algorithm parallelism and operation characteristics, determine the required operation unit type and the number of enabled operation units, and determine the output mode of the matrix source data according to the operation unit type; If the matrix algorithm is matrix addition / subtraction, the output modes of the matrix source data 1 area and the matrix source data 2 area are both parallel output, and m data are transmitted to m addition operation units for calculation in one clock cycle If the matrix algorithm is matrix addition / subtraction, the output modes of the matrix source data 1 area and the matrix source data 2 area are both parallel output, and m data are transmitted to m addition operation units for calculation in one clock cycle If the matrix algorithm is matrix multiplication or weighted method, the matrix source data 1 area is reconstructed into a horizontal broadcast number mode, the matrix source data 2 area is reconstructed into a parallel number mode, and within the , the matrix source data 1 area provides 1 data to the m-way multiplication-accumulation calculation unit, and the source data 2 area provides m numbers to the m-way multiplication-accumulation calculation unit for calculation, wherein the matrix source data 1 area is stored in the storage module in horizontal row order, and the matrix source data 2 area is stored in the storage module in vertical column order. If the matrix algorithm is a generalized inner product, the matrix source data 1 area is reconstructed into a longitudinal broadcasting number mode, and the matrix source data 2 area is reconstructed into a parallel number mode, and In the generalized inner product, the matrix source data 1 area provides one data to the m-way conjugate multiplication and accumulation calculation unit, and the matrix source data 2 area provides m numbers to the m-way conjugate multiplication and accumulation calculation unit to complete the calculation, wherein the matrix source data 1 area and the matrix source data 2 area are stored longitudinally by column in the storage module. If the covariance, that is , the matrix source data area is reconstructed into a parallel output mode, and , the matrix source data provides m numbers to the multiply-add tree calculation unit to complete the calculation, wherein the matrix source data is stored column by column in the storage module.

2. The dynamic reconfiguration method of a two-dimensional memory access controller according to claim 1, wherein, The specific steps of step S3 further include: S3.2: Based on the type, number and output mode of the operation unit determined in S3.1, determine the intermediate result area enablement requirement; If the intermediate result area is not enabled, n intermediate results generated by the operation module are directly output as the final result, wherein n represents the parallelism of the intermediate result calculation, and n is a power of 2; If the intermediate result area is enabled, after the intermediate result operation unit finishes calculation, the m intermediate result data are accepted in the intermediate result area ; S3.3: Execute the matrix operation in the configured calculation module.

3. The dynamic reconfiguration method of a two-dimensional memory access controller according to claim 2, wherein, The specific steps of the step S4 include: S4.1: obtaining the matrix operation result output by the calculation module in the step S3.3, and storing the matrix operation result data; S4.2: determining the scale and structure of the matrix operation result data according to the extracted parallelism degree of the matrix algorithm, and judging the input mode of the matrix operation result data according to the scale, structure of the matrix operation result and the interface capability of the matrix storage module, and simultaneously determining the number of activated channels of the matrix operation result data; S4.3: if the matrix algorithm adopts the parallel processing mode in the operation process, and the result data can be output in parallel, the input mode of the matrix operation result is the parallel input mode; If the matrix operation result number mode is a parallel number mode, each time an operation end signal in the calculation module is received, m result data channels are simultaneously enabled, and m result data are stored in the matrix storage module in parallel through the m result data channels. If the matrix operation result number mode is a parallel number mode, each time an operation end signal in the calculation module is received, m result data channels are simultaneously enabled, and m result data are stored in the matrix storage module in parallel through the m result data channels. S4.4: if the matrix algorithm adopts the sequential processing mode in the operation process, or the matrix operation result data needs to be output in sequence, the input mode of the matrix operation result is the sequential input mode; If the input mode of the matrix operation result is the sequential input mode, one result data channel is activated every time a clock cycle of the operation end signal of the calculation module is received, and one result data is stored into the matrix storage module through the one result data channel.

4. An electronic device comprising a memory and a processor, the memory storing a computer program, characterized in that, The processor executes the computer program to implement the steps of the dynamic reconstruction method of the two-dimensional memory access controller according to any one of claims 1-3; A computer-readable storage medium, characterized by The computer program is stored on the computer readable medium, and when the computer program is executed, the steps of the dynamic reconstruction method of the two-dimensional memory access controller according to any one of claims 1-3 are executed.

Images