Correction matrix reset

Abstract

The invention relates to correction matrix reset. A decoding operation is performed by receiving a command to read a correction matrix including a plurality of bit values from a memory of a decoder. The decoding operations also include, in response to receiving the command, generating, using circuitry of a decoder, a predetermined correction matrix including the same bit value. The decoding operation further includes providing the predetermined correction matrix to a decision engine to perform the decoding operation.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to resetting correction matrices, and more specifically, to resetting correction matrices. Background Art

[0002] Various types of electronic devices, such as digital logic circuits and memory systems, can store and process data. A digital logic circuit is an electronic circuit that processes digital signals or binary information that can take two possible values, usually represented as 0 and 1. A digital logic circuit can use logic gates to manipulate and transform digital signals or binary information. Digital logic circuits can be used, for example, in a wide range of electronic devices, including computers, calculators, digital clocks, and many other electronic devices that employ digital processing. Digital logic circuits can be designed to perform specific logic operations on digital inputs to produce digital outputs, and in some examples, can be combined to form more complex circuits to perform more complex operations. A memory device can include one or more memory devices that store data. A memory device can be, for example, a non-volatile memory device and a volatile memory device. In general, a host system can utilize a memory system to store data at a memory device and retrieve data from a memory device. Summary of the invention

[0003] In one aspect, the present disclosure provides a method for resetting a correction matrix, comprising: performing a first iteration of a decoding operation on a bit string by: receiving a command to read a correction matrix including a plurality of bit values ​​from a memory of a decoder; in response to receiving the command, using a circuit system of the decoder to generate a predetermined correction matrix including the same bit values; and providing the predetermined correction matrix to a decision engine to perform the decoding operation.

[0004] In another aspect, the present disclosure provides an apparatus for resetting a correction matrix, comprising: a plurality of registers configured to store a bit mask; an array of memory cells configured to store a correction matrix comprising a first plurality of bits; and a circuit system coupled to the array and configured to: during an iteration of a decoding operation performed to decode a codeword, use the bit mask to change the first plurality of bits of the correction matrix from a second value to a first value to produce a second plurality of bits; provide the second plurality of bits to a decision engine; and the decision engine coupled to the circuit system, the array, and the plurality of registers and configured to: in response to using the second plurality of bits to update the codeword, update the bit mask to reflect that the codeword is updated.

[0005] In another aspect, the present disclosure provides an apparatus for resetting a correction matrix, comprising: a plurality of registers configured to store a bit mask; a memory cell array configured to store a correction matrix comprising a first plurality of bits; and a circuit system coupled to the array and the plurality of registers and configured to: in response to receiving a command to read the correction matrix, read the first plurality of bits of the correction matrix if the bit mask comprises a second value; in response to receiving a command to process a codeword, generate a second plurality of bits using a plurality of AND gates if the bit mask comprises a first value; and provide the first plurality of bits and the second plurality of bits to perform a number of operations using the correction matrix. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the present disclosure.

[0007] Figure 1 An example computing system including a memory subsystem according to some embodiments of the present disclosure is described.

[0008] Figure 2 An example of decoding circuitry according to some embodiments of the present disclosure is described.

[0009] Figure 3 is a flow chart corresponding to a method for resetting a correction matrix according to some embodiments of the present disclosure.

[0010] Figure 4 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0011] Aspects of the present disclosure relate to resetting a correction matrix in a decoder. In some embodiments, the decoder may perform a decoding operation, and in particular, a decoding operation performed within a memory subsystem. The memory subsystem may be a storage system, a storage device, a memory module, or a combination of the like. An example of a memory subsystem is a storage system, such as a solid state drive (SSD). Figure 1 Examples of storage devices and memory modules are described in , etc. In general, a host system may utilize a memory subsystem that includes one or more components, such as a memory device that stores data. The host system may provide data stored at the memory subsystem and may request data retrieved from the memory subsystem.

[0012] Although some non-limiting examples herein are generally described in terms of applicability to memory subsystems and / or to memory devices, the embodiments are not limited thereto, and aspects of the present disclosure may also be applied to systems on a chip, computing subsystems, data collection and processing, storage, networking, communications, power, artificial intelligence, control, telemetry, sensing and monitoring, digital entertainment, and other types of systems / subsystems and / or devices. Thus, aspects of the present disclosure may be applied to these components in order to reset the correction matrix in the decoder, as described herein.

[0013] The data may be written to and stored by one or more digital logic circuits and / or memory systems. The data (e.g., which may correspond to one or more codewords such as user data) may be encoded before being transferred to the memory device and / or before being written to the memory device (e.g., stored by the memory device). When the data is retrieved, the data is typically decoded. There are many techniques for decoding of codewords, some non-limiting examples of which include maximum likelihood decoding, minimum distance decoding (e.g., a decoding technique that seeks to minimize the Hamming distance associated with the codeword), list decoding, linear decoding, bit-flip decoding, and / or information set decoding, among others.

[0014] As will be appreciated, such decoding techniques may be used to detect bit errors in data (e.g., codewords) based on determining that a bit associated with the data has an incorrect state (e.g., a "0" where it should be a "1," and vice versa). Some of the more common decoding techniques employed include Hamming codes, Reed-Solomon (RS) codes, Bose-Chowdhury-Hokkunheim (BCH) codes, cyclic redundancy check (CRC) codes, Gowley codes, Reed-Muller codes, Gopal codes, neighbor cell assisted error correction codes, low density parity check (LDPC) error correction codes, Denniston codes, and syndrome decoding, among others. While each of these decoding techniques has its own advantages, they may also experience various disadvantages. For example, more accurate decoding techniques tend to consume more power and / or time, while less accurate decoding techniques may be performed faster and may consume less power.

[0015] In some methods, decoding of the bit string and / or syndrome is achieved by processing the bit string and / or syndrome with the aid of a series of flip-flops (which may include thousands of flip-flops) and applying a logical operation (e.g., a logical AND, OR, XOR operation, etc.) to the bit string and / or syndrome. In such methods, the number of inputs to the logical operation is typically equal to the number of flip-flops used to process the bit string and / or syndrome. If execution of the logical operation returns a particular value (e.g., a logical value of "1" in the case of a logical AND operation), then the bit string and / or syndrome is considered to be decoded.

[0016] However, before performing a decoding operation, a matrix (e.g., a correction matrix) corresponding to the codeword may be initialized so that the correction matrix includes 0 bits and does not include 1 bits. As used herein, 0 bits and / or 1 bits may refer to logical values ​​"0" and "1", respectively. References to 0 bits or 1 bits may include references to logical values ​​"0" or "1", respectively. The correction matrix may be stored in a correction (CR) memory. The correction matrix may be used to track which bits of the codeword have been corrected or not corrected. For example, a correction matrix having a first bit value in a first bit may indicate that the corresponding bit of the codeword (e.g., the first bit) has not been corrected. A correction matrix having a second bit value in a second bit may indicate that the corresponding bit of the codeword (e.g., the second bit) has been corrected. In various examples, if the correction matrix includes a bit with a second bit value, the codeword may be corrected. In various examples, the first bit value may be 0 bits and the second bit value may be 1 bits. However, other bit values ​​may be selected.

[0017] Initialization of the correction matrix may be performed by initializing a memory (e.g., a CR memory) storing the correction matrix. For example, a memory cell storing the correction matrix may be configured (e.g., initialized) to store a first value (e.g., a 0-bit value) instead of a 1-bit value (e.g., a 1-bit value). The 0-bit may represent a bit of the codeword that has not yet been corrected. However, initialization of the memory consumes time (e.g., write cycles) and power (e.g., 0-bits are sequentially written to the memory cells storing the codewords). In addition, in the first iteration of the decoding operation of the codeword, the correction matrix (e.g., consisting of 0-bit values) may be read out, which may consume time and power.

[0018] To address these and other deficiencies of current methods, embodiments of the present disclosure allow for the generation of a first correction matrix including 0 bits and not including 1 bits without initializing a memory storing a second correction matrix corresponding to the decoding of a previous codeword. The second correction matrix may be left over from the decoding of the previous codeword. Generating a correction matrix (e.g., a first correction matrix) including 0 bits instead of initializing a corresponding correction matrix (e.g., a second correction matrix) and reading the corresponding correction matrix may be referred to as bypassing a memory read. The memory read may be bypassed during or as part of a first iteration of a decoding operation to reduce power used to perform a read operation (e.g., initializing and reading a correction matrix stored in a memory). For example, instead of initializing and reading a correction matrix stored in a memory, a corresponding correction matrix may be generated and may be provided to a decoding engine, thereby bypassing the reading of the correction matrix so that power or time is not utilized to read the correction matrix stored in the memory and bypassing the initialization of the correction matrix, which also consumes time and power.

[0019] In subsequent iterations of the decoding operation, the reading of the memory storing the correction matrix may also be bypassed. For example, if portions of the correction matrix have not been written (e.g., updated) in the current iteration or previous iteration of the decoding operation, the reading of the correction matrix may be bypassed by generating a correction matrix including 0 bits. The execution of the decoding operation may include storing the result of the decoding operation in the memory. For example, as part of performing the decoding operation, the matrix storage may be corrected (e.g., updated) in the memory. Assuming that the correction matrix may have bit values ​​corresponding to the decoding of different codewords, the correction matrix that has not been updated may be referred to as not having been written to the memory. For example, after decoding the first codeword, the correction matrix remains stored in the memory. If the correction matrix has not been updated, then the bits of the correction matrix have not been written for the current iteration of the decoding operation performed to decode a new codeword, and the new codeword associates the correction matrix with the previously decoded codeword instead of the correction matrix currently being decoded.

[0020] The examples described herein avoid initializing the memory storing the correction matrix. The memory is not initialized because the memory is not used in the first iteration of the decoding operation and / or as part of the first iteration. In various examples, the first iteration can be considered complete after the memory is updated. The decoding operation can be performed as part of the first iteration. The decoding operation can be performed before the memory is updated. Compared with initializing the memory as part of the first iteration of the decoding operation, not utilizing the memory in the first iteration of the decoding operation saves power and improves performance. The memory may not be initialized, but may be updated after the first iteration of the decoding operation. In various examples, the memory may be updated as part of the first iteration. For example, the update of the memory may end the first iteration. The decoding operation may be performed without waiting for the memory to be initialized (e.g., set to a 0-bit value). Although the examples described herein are provided to generate a correction matrix with 0 bits and no 1 bits, depending on the type of decoding operation performed, a correction matrix with 1 bit and no 0 bits or any combination of 1 bit and 0 bits may be generated.

[0021] Figure 1 An example computing system 100 is illustrated that includes a memory subsystem 110 in accordance with some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of the like.

[0022] The memory subsystem 110 may be a storage device, a memory module, or a mixture of storage devices and memory modules. Examples of storage devices include solid state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage devices (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0023] Computing system 100 may be a computing device such as a desktop computer, a laptop computer, a server, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, automobile, or other transportation vehicle), a device with Internet of Things (IoT) capabilities, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0024] In other embodiments, the computing system 100 may be deployed on or otherwise included in a computing device, such as a desktop computer, a laptop computer, a server, a network server, a mobile computing device, a vehicle (e.g., an airplane, a drone, a train, a car, or other transportation vehicle), a device with Internet of Things (IoT) capabilities, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such computing devices including a memory and a processing device. As used herein, the term "mobile computing device" generally refers to a handheld computing device having a phablet or tablet form factor. In general, a phablet form factor may include a display screen of between approximately 3 inches and 5.2 inches (measured diagonally), while a tablet form factor may include a display screen of between approximately 5.2 inches and 7 inches (measured diagonally). However, examples of a "mobile computing device" are not limited thereto, and in some embodiments, a "mobile computing device" may refer to an IoT device as well as other types of edge computing devices.

[0025] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1An example of a host system 120 coupled to one memory subsystem 110 is illustrated. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, and the like.

[0026] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an SSD controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110 to, for example, write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0027] Host system 120 includes a processing unit 121. Processing unit 121 may be a central processing unit (CPU) configured to execute an operating system. In some embodiments, processing unit 121 includes a complex instruction set computer architecture, such as x86 or other architecture suitable for use as a CPU of host system 120.

[0028] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel, a Serial Attached SCSI (SAS), a Small Computer System Interface (SCSI), a Double Data Rate (DDR) memory bus, a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM slot interface supporting Double Data Rate (DDR)), an Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a PCIe interface, the host system 120 may further utilize an NVM Express (NVMe) interface to access components (e.g., the memory device 130). The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120 . Figure 1 Memory subsystem 110 is illustrated as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0029] Memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0030] Some examples of non-volatile memory devices (e.g., memory device 130) include non-and (NAND) type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory can perform bit storage based on body resistance changes in combination with a stackable cross-gate data access array. In addition, compared to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without previously erasing the non-volatile memory cells. For example, NAND type flash memory includes two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0031] Each of the memory devices 130, 140 may include one or more memory cell arrays. One type of memory cell, for example a single level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), four-level cells (QLC), and five-level cells (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, or any combination of such. In some embodiments, a particular memory device may include an SLC portion and an MLC portion, a TLC portion, a QLC portion, or a PLC portion of a memory cell. The memory cells of the memory device 130 may be grouped into pages, which may refer to a logical unit of a memory device for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0032] Although nonvolatile memory components such as a three-dimensional cross-point array of nonvolatile memory cells and NAND-type memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of nonvolatile memory or storage device, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), non-OR (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0033] The memory subsystem controller 115 (or, for simplicity, the controller 115) may communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic for performing the operations described herein. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0034] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0035] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 is illustrated as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0036] In general, the memory subsystem controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130 and / or the memory device 140. The memory subsystem controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses, physical media locations, etc.) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuit system to communicate with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions to access the memory device 130 and / or the memory device 140, and convert responses associated with the memory device 130 and / or the memory device 140 into information for the host system 120.

[0037] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoder and column decoder) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130 and / or the memory device 140.

[0038] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may manage memory device 130 externally (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0039] Memory subsystem 110 may include decoding circuitry 113. Although Figure 1Although not shown in order not to obscure the drawings, decoding circuitry 113 may include various circuitry for facilitating aspects of the disclosure described herein. In some embodiments, decoding circuitry 113 may include specialized circuitry in the form of an ASIC, FPGA, state machine, hardware processing device, and / or other logic circuitry that may allow decoding circuitry 113 to program and / or perform decoding operations in accordance with the present disclosure, particularly with respect to systems on a chip. Figure 2 Decoding circuitry 113 is discussed in greater detail.

[0040] In some embodiments, the memory subsystem controller 115 includes at least a portion of the decoding circuitry 113. For example, the memory subsystem controller 115 may include a processor 117 (processing device) configured to execute instructions stored in the local memory 119 for performing the operations described herein. In some embodiments, the decoding circuitry 113 is part of the host system 110, an application, or an operating system. The decoding circuitry 113 may reside on the memory subsystem 110 and / or the memory subsystem controller 115. As used herein, the term "resides on" refers to something that is physically located on a particular component. For example, the decoding circuitry 113 "resides on the memory subsystem 110" refers to the condition that the hardware circuitry including the decoding circuitry 113 is physically located on the memory subsystem 110. Herein, the term "resides on" may be used interchangeably with other terms such as "deployed on" or "located on".

[0041] Figure 2 An example of a decoding circuit system 213 according to some embodiments of the present disclosure is described. The decoding circuit system 213 may include a decision engine 222, a CR memory 223, a register 224 (e.g., a loop valid register), AND gates 225, 232, an XOR gate 226, pipeline circuit systems 227-1, 227-2, and a control circuit system (e.g., CNT) 228. The decoding circuit system 213 also includes OR gates 229, 231. Although Figure 2 Although not explicitly shown in FIG, one or more of the components illustrated may be one of a plurality of such components. Figure 2 A single AND gate is shown in , but AND gate 225 may include multiple AND gates (eg, 16, 32, 128, etc.).

[0042] As used herein, the CR memory 223 may include hardware and / or firmware configured to store a correction matrix. As used herein, the term "codeword" generally refers to a data word of a specified size (e.g., 4KB, etc.) that is encoded so that the codeword can be individually protected by some error encoding and / or decoding schemes. For example, a "codeword" may refer to a set of bits (e.g., a bit string and / or a syndrome) that can be individually encoded and / or decoded. The term "correction matrix" generally refers to a data word of a specific size (e.g., 4KB, etc.) that is used to track which bits of the codeword have been corrected and / or which bits of the codeword have not yet been corrected (e.g., not corrected). The size of the correction matrix may be the same size as the codeword. Each of the bits of the correction matrix may correspond to a different bit of the codeword.

[0043] The CR memory 223 may be an array of memory cells and / or an array of triggers and / or latches, etc. Figure 2 , CR memory 223 is coupled to decision engine 222. CR memory 223 may be coupled to decision engine 222 using AND gate 225. AND gate 225 may receive bits from register 224 and CR memory 223. For example, CR memory 223 may provide a correction matrix, while register 224 provides an activation bit, which may be referred to as a bit mask. The correction matrix and activation bit may be associated with an address. For example, a codeword may be stored in an address. The address of the codeword may be used to associate the correction matrix and activation bit with the codeword.

[0044] The output of AND gate 225 may be provided to decision engine 222 and pipeline 227-1. Decision engine 222 may perform a number of decoding operations on the codeword, and based on whether decision engine 222 corrects any of the bits of the codeword, the bits of the correction matrix provided by AND gate 225 may be flipped. Decision engine 222 may provide a number of outputs to register 224 via OR gate 229 and to CR memory 223 via OR gate 231 and XOR gate 226. Pipeline circuitry 227-2, together with AND gate 232, OR gate 231, and XOR gate 226, may be used to store the entire updated correction matrix to CR memory 223. Pipeline circuitry 227-1, together with OR gate 231 and XOR gate 226, may be used to store portions of the updated correction matrix to CR memory 223 as described below.

[0045] Decision engine 222 includes hardware circuitry configured to correct erroneous bits (e.g., bit flip errors) in bit strings and / or codewords. As used herein, a bit string may refer to a decoded codeword and a codeword may refer to an encoded bit string. The examples described herein may apply to both bit strings and codewords. References to decoding a codeword may include performing error correction on the codeword and / or on the bit string. References to performing a decoding operation on a bit string may include performing a decoding operation on the codeword and / or performing an error correction operation on the bit string.

[0046] In some embodiments, the decision engine 222 may flip one or more bits in the bit string and / or codeword based on the determined probability that such bits are in error. Various linear codes (e.g., syndrome decoding codes, LDPC codes, etc.) may be used to determine the probability that one or more bits in the bit string and / or codeword will be flipped. However, embodiments are not limited to the case where the decision engine 222 flips one or more bits in the bit string and / or codeword based on the determined probability that such bits are in error (e.g., through the use of linear decoding techniques), and in some embodiments, the decision engine 222 may determine which bits of the bit string and / or codeword are in error based on mathematical reasoning algorithms, machine learning algorithms, and / or other suitable techniques for determining which bits of the bit string and / or codeword are in error.

[0047] In a simplified example provided for illustrative purposes, taking a codeword containing the following bit pattern: [1 0 0 1 0 1 1 0], the decision engine 222 may determine that the second bit (starting from the right) may be erroneous, and therefore may process the codeword to flip the second bit, thereby producing the following new codeword [1 0 0 1 0 1 0 0]. However, embodiments are not limited to cases where the decision engine 222 only causes a single bit to be flipped as part of decoding the codeword. For example, using the same initial codeword [1 0 010 1 1 0] given above, the decision engine 222 may determine that the second bit, the third bit, and the eighth bit may be erroneous and therefore may process the codeword to flip the second bit, the third bit, and the eighth bit, thereby producing the following codeword [0 0 0 1 0 0 0 0]. It should be noted that these illustrative, non-limiting examples may be part of an iterative decoding process, where a codeword is processed multiple times by the decision engine 222 in order to decode such codeword. Thus, the illustrative, non-limiting examples given above may represent operations performed by the decision engine 222 at a first iteration of a decoding process (eg, a decoding operation), or at any subsequent iteration of the decoding process.

[0048] The decision engine 222, CR memory 223, and / or other circuitry may use a correction matrix to mask the bits of the bit string and / or codeword once the decision engine 222 has attempted to correct one or more erroneous bits in the bit string and / or codeword, for example, by flipping the value of one or more such bits from a logic value of "1" to a logic value of "0" or vice versa. In various examples, the correction matrix may be used for decoding of each of the bits of the bit string and / or codeword and may be subject to correction during subsequent iterations of the decoding operation and / or may be processed by the decision engine during subsequent iterations of the decoding operation.

[0049] For example, using the initial bit pattern [1 0 0 1 0 1 1 0] given above, the decision engine 222 may determine that the second, fifth, and seventh bits may be erroneous, and therefore may process the received bit string and / or codeword to flip the second, fifth, and seventh bits, thereby producing the following bit pattern [1 1 0 1 1 1 0 0]. Then, a matrix (e.g., a correction matrix) is applied to the second, fifth, and seventh bits as these bits are altered by the decision engine 222. In some embodiments, the bits to which the correction matrix has been applied (and / or the bits to which the correction matrix has not been applied) are written to the CR memory 223 (which may be a register, a cache, or another set of memory cells). In various examples, the correction matrix, syndrome, and / or other bits may be used to decode the codeword.

[0050] During decoding of a codeword, a correction matrix stored in CR memory 223 (referred to as memory 223) may contain bits stored in memory 223 during previous decoding of a different codeword. For example, at the end of a first decoding of a first codeword, the correction matrix may be modified to reflect the corrected and / or uncorrected bits of the first codeword. When a second decoding of a second codeword is initiated, the correction matrix may continue to reflect the corrected and / or uncorrected bits of the first codeword. The correction matrix reflects the corrected and / or uncorrected bits of the first codeword until the correction matrix is ​​initialized. As used herein, initializing a correction matrix includes storing predetermined bit values ​​instead of different bit values ​​in the memory cells storing the correction matrix.

[0051] For example, the correction matrix may be updated by initializing the correction matrix to a predetermined bit pattern. The correction matrix may also be updated after the first iteration of decoding of the second codeword. Initializing the correction matrix and reading the newly initialized correction matrix to provide to the decision engine 222 may utilize resources of the memory subsystem.

[0052] In several examples, AND gate 225 and register 224 may be utilized to generate a predetermined correction matrix rather than initializing the correction matrix (eg, writing a predetermined bit pattern to memory 223). Generating a predetermined correction matrix may utilize fewer resources than initializing the correction matrix and reading the correction matrix.

[0053] In the first iteration of decoding a codeword, instead of reading the correction matrix from memory 223, AND gates 225 may be configured to generate a predetermined correction matrix. In subsequent iterations of decoding a codeword, each of AND gates 225 may receive bits of the correction matrix from memory 223. For example, if the correction matrix includes 128 bits, there may be 128 AND gates 225, each receiving one of the 128 bits.

[0054] In the first iteration of decoding the codeword, each of AND gates 225 may receive the same bit from register 224. The same bit stored in register 224 may be associated with the same address associated with the correction matrix. The same bit may be used to activate the correction matrix or deactivate the correction matrix. For example, if the same bit is a first value (e.g., a 0 bit), the correction matrix may be inactive. If the same bit is a second value (e.g., a 1 bit), the correction matrix is ​​active.

[0055] AND gate 225 may provide the correction matrix if the bit received from register 224 has a second value and may provide a 0 bit if the bit received from register 224 has a first value. For example, if the first AND gate receives a first bit from the correction matrix and a bit having a first value (e.g., a 0 bit) from register 224, the AND gate performs an AND operation using the first bit of the correction matrix and the bit from register 224. Assuming that the bit from register 224 has a first value (e.g., a 0 bit), the AND gate may provide a 0 bit instead of the first bit from the correction matrix. If the bit from register 224 has a second value (e.g., a 1 bit), the AND gate may provide the first bit of the correction matrix regardless of whether the first bit of the correction matrix has the first value or the second value.

[0056] AND gates 225 may generate a predetermined correction matrix. If the bit from register 224 has a first value, AND gates 225 may provide a first value (e.g., a 0 bit). Assuming that each of AND gates 225 receives a bit from register 224, each of AND gates 225 may provide a first value. If each of AND gates 225 provides the same bit, AND gates 225 may provide a predetermined correction matrix. Depending on the decoding scheme utilized, the predetermined value of the predetermined correction matrix may be a 1 bit, a 0 bit, or a combination thereof.

[0057] Register 224 is hardware configured to store one or more bits. Register 224 may be a memory cell array and / or a flip-flop and / or a latch array, etc. At the beginning of each decoding of a codeword, register 224 may be reset to store a first value (0 bit). Control circuit system 228 may provide a signal to register 224 to cause the register to store a first value (e.g., 0 bit). Control circuit system 228 may reset register 224 synchronously or asynchronously. In order to reset register 224 synchronously, control circuit system 228 may provide a signal to register 224 based on a clock signal and / or based on the completion of decoding of a codeword by decision engine 222. In order to reset register 224 asynchronously, a flip-flop in register 224 may be reset without reference to a clock signal. Register 224 may be reset before a new decoding operation begins.

[0058] The decision engine 222 may receive a predetermined correction matrix created by the AND gate 225 during a first iteration of decoding of the codeword. The decision engine 222 may perform a decoding operation. In response to performing the decoding operation, the decision engine 222 may flip one or more bits of the codeword. In response to updating the one or more bits of the codeword, the decision engine 222 may provide a signal to the memory 223. The signal may correspond to the updated one or more bits of the codeword and to the corresponding one or more bits of the predetermined correction matrix.

[0059] The one or more signals provided by the decision engine 222 may be received by the OR gates 229, 231. The OR gate 229 may be an X to 1 OR gate. For example, the decision engine 222 may be coupled to the memory 223 via a plurality of lines. The number of lines (e.g., the width of the bus) coupling the decision engine 222 to the memory 223 may be equal to the number of bits of the correction matrix and / or the predetermined correction matrix. If the first bit of the codeword is updated, the decision engine 222 may provide a bit having a second bit value (e.g., a 1 bit) to the memory 223 using the first line and may provide a number of bits having a first bit value (e.g., a 0 bit) to the memory 223 using the remaining lines. The decision engine 222 may also provide the bit having the second bit value and the number of bits having the first bit value to the OR gates 229 and 231.

[0060] OR gate 229 may perform an OR operation using a bit and a number of bits. Assuming that the bit has a second bit value, OR gate 229 may provide the second bit value (e.g., 1 bit) to register 224. Register 224 may store the second bit value. In subsequent iterations of decoding of the codeword, register 224 may provide the bit to AND gate 225, where the bit has the second bit value. Regardless of whether decision engine 222 updates one or more bits of the codeword, decision engine 222 may activate the correction matrix stored in memory 223 by providing the bit with the second bit value to register 224 via OR gate 229. Register 224 may store the bit with the second bit value.

[0061] OR gate 231 may also receive a signal provided from decision engine 222 to memory 223 and a signal received from AND gate 232. OR gate 231 may include a number of OR gates equal to the number of AND gates 225, the width of a bus of the memory, and / or the number of bits of a predetermined correction matrix generated by AND gate 225. In various examples, memory 223 may store multiple correction matrices per address. The number of OR gates and the number of AND gates 225 may be equal to the width of a bus of memory 223. OR gate 231 may be used to signal memory 223 to store an updated correction matrix and / or a portion of an updated correction matrix in response to updating one or more of the bits of the codeword in an iteration of decoding of a codeword in which the codeword is first updated. In many examples, the codeword is updated for the first time by decision engine 222 during the first iteration of decoding of the codeword. For example, if the codeword is updated, decision engine 222 may provide at least one signal having a second bit value (e.g., 1 bit) to OR gate 231.

[0062] OR gate 231 may also receive one or more bits from AND gate 232, which is coupled to pipeline 227-2 and OR gate 229. Pipeline 227-2 is coupled to register 224 via NOT gate 233. Pipeline 227-2 may be used to delay bits provided by register 224. For example, register 224 may provide bits to AND gate 232 via pipeline 227-2 and NOT gate 233. AND gate 232 may also receive bits from OR gate 229.

[0063] OR gate 231 may be used to cause memory 223 to update the correction matrix. For example, OR gate 231 may update the entire correction matrix in the same iteration (e.g., typically the first iteration) as the correction matrix is ​​to be updated for the first time. For example, if decision engine 222 decides to update the correction matrix for the first time, register 224 may provide a bit mask with 0 bits. NOT gate 233 may output 1 bit. Pipeline 227-2 may delay 1 bit and may provide 1 bit to AND gate 232. If decision engine 222 updates any of the bits of the correction matrix, OR gate 229 may output 1 bit. If it is the first time to update the correction matrix, AND gate 232 may receive two 1 bits. AND gate 232 may output 1 bit to OR gate 231 to cause OR gate 231 to provide a write enable signal (e.g., including 1 bit) to memory 223 to cause the entire correction matrix to be updated, regardless of whether decision engine 222 wishes to update the entire correction matrix or wishes to update only a portion of the correction matrix. In subsequent iterations, register 224 will provide a 1 bit, which after being processed by NOT gate 233 can be provided as a 0 bit to AND gate 232, and if decision engine 222 wishes to update the corresponding bit of the correction matrix (e.g., a partial update of the correction matrix), then the 0 bit will cause OR gate 231 to provide a write enable signal (e.g., including a 1 bit) to memory 223.

[0064] Memory 223 can store the bits provided by XOR gate 226 to update the correction matrix in response to receiving the bit value from OR gate 231. In the first iteration of decoding of the codeword, memory 223 can update each of the bits of the correction matrix. In subsequent iterations of decoding of the codeword, memory 223 can update one or more of the bits of the correction matrix as indicated by the write enable bit provided to memory 223 by decision engine 222. As used herein, the write enable bit is a signal provided from decision engine 222 to memory 223.

[0065] XOR gate 226 may receive a write enable bit from decision engine 222 and a signal from pipeline circuitry 227-1. Pipeline circuitry 227-1, 227-2 may include hardware configured to delay the output of AND gate 225 as provided to XOR gate 226 and a bit mask provided to AND gate 232. In a first iteration of decoding of a codeword, the output of AND gate 225 is a predetermined correction matrix generated by AND gate 225. In subsequent iterations of decoding of a codeword, the output of AND gate 225 is a correction matrix stored in memory 223. Pipeline circuitry 227-1 may delay the output of AND gate 225 to align the output of AND gate 225 with the write enable bit provided to XOR gate 226 by decision engine 222. Any bit provided by decision engine 222 with a second bit value may cause XOR gate 226 to flip a corresponding bit from the output of AND gate 225. For example, if one of the AND gates 225 provides a 0 bit to one of the XOR gates 226 and the decision engine 222 provides a 1 bit to one of the XOR gates 226, then one of the XOR gates 226 may output the 1 bit to the memory 223. The memory 223 may store the bit provided by one of the XOR gates 226 if the corresponding bit provided by the decision engine 222 has the second bit value (e.g., a 1 bit) and may avoid storing the bit provided by one of the XOR gates 226 if the bit provided by the decision engine 222 has the first bit value (e.g., a 0 bit).

[0066] The number of XOR gates 226 may be equal to the number of AND gates 225, the number of OR gates 231, and / or the number of bits of a predetermined correction matrix. Each of the XOR gates 226 may be associated with a bit of the correction matrix and / or a bit of the codeword. For example, the first XOR gate may be associated with the first bit of the correction matrix and the codeword. If the first write enable bit provided by the decision engine 222 has a second bit value, the first XOR gate may provide a bit value that the memory 223 may use to update the first bit of the correction matrix. In various examples, the decision engine 222 may provide multiple write enable bits concurrently. For example, the decision engine 222 may provide a first write enable bit and a tenth write enable bit with a second bit value, while the remaining write enable bits have a first bit value. The XOR gate 226 may flip the first bit and the tenth bit provided by the AND gate 225 and may provide the remaining bits without flipping the remaining bits as provided by the AND gate 225. The memory 223 may store each of the bits as provided by the XOR gate 226 during the first iteration of decoding of the codeword to update the correction matrix. Memory 223 may store the first and tenth bits provided by XOR gate 226 during subsequent iterations of decoding of the codeword to update the correction matrix in response to receiving the first and tenth bits from decision engine 222 instead of the remaining bits provided by XOR gate 226 .

[0067] In subsequent iterations of decoding of the codeword, AND gate 225 may provide a correction matrix updated in the first iteration of decoding of the codeword. Updating the correction matrix in the first iteration of decoding of the codeword may cause register 224 to store bits having a second bit value. The second bit value that may be provided from register 224 to AND gate 225 may cause AND gate 225 to provide a correction matrix instead of generating a predetermined correction matrix. Decision engine 222 may receive the correction matrix and may utilize the correction matrix to continue decoding the codeword. Decoding of the codeword may include correction of errors found in the codeword and / or decoded codeword.

[0068] Decision engine 222 may provide a corresponding write enable bit having a second bit value to memory 223 in response to updating a particular bit of the codeword. After the correction matrix has been updated for the first time (e.g., after the first iteration of decoding of the codeword), decision engine 222 may provide the write enable bit directly to memory 223 without providing the bit to OR gate 229 and / or OR gate 231. Decision engine 222 may also provide the write enable bit to XOR gate 226. XOR gate 226 may flip the corresponding bit from the correction matrix and may provide the flipped bit to memory 223. In various examples, XOR gate 226 may flip each of the bits of the correction matrix and may provide each of the flipped bits to memory 223. Memory 223 writes the received flipped bit and stores the flipped bit, which is write enabled as indicated by the write enable bit having the second bit value as received from decision engine 222. At the end of decoding of the codeword, control circuitry 228 may reset register 224 to deactivate the correction matrix. The correction matrix is ​​not reset and thus the correction matrix may have bits remaining from the decoding of a codeword even when decoding of a subsequent codeword starts.Avoiding resetting (eg, resetting) the correction matrix may save memory subsystem resources and power.

[0069] Although the non-limiting examples herein are generally described in terms of applicability to memory subsystems and / or to memory devices, the embodiments are not limited thereto, and aspects of the present disclosure may also be applied to systems on a chip, computing systems / subsystems, data collection and processing, storage, networking, communications, power, artificial intelligence, control, telemetry, sensing and monitoring, digital entertainment, and other types of systems / subsystems and / or devices. Thus, aspects of the present disclosure may be applied to these components to reset variables, as described herein.

[0070] The examples described herein may be applicable to different algorithms that are not related to decoding. For example, decision engine 222 may be referred to as a processing device. The examples described herein may be applicable to the initialization of any variable utilized by a processing device and / or updated by a processing device. For example, a counter may be initialized before being provided to a processing device. The variables may be initialized as described herein without modifying memory 223. In various examples, a processing device may utilize variables to encode a message. The variables may be initialized before the processing device utilizes the variables to encode a message utilizing the circuitry described herein.

[0071] The examples described herein are applicable to various types of memories and / or storage devices. For example, one or more AND gates may be used to generate predetermined variables (e.g., predetermined correction matrices) and provide them to a processing device, rather than initializing and reading corresponding variables from a memory, register, array, storage device, and / or any type of file. For example, although the examples described herein are given in the context of a hardware circuit system, a computer-readable instruction that generates predetermined variables using one or more AND operations may be used to generate predetermined variables. The predetermined variables may be provided to a processing device. Before reading the updated variables from a file (e.g., a computer file), the processing device may cause the updated variables to be stored in the file. Although the examples described herein are provided in the context of a hardware circuit system including an AND gate, an OR gate, and / or an XOR gate, the examples described herein may be implemented using corresponding operations such as AND operations, OR operations, and / or XOR operations.

[0072] The examples described herein also apply to read-modify-write operations. A read-modify-write operation is one or more operations that cause data to be read from a memory, cause data to be modified, and cause updated data to be written to the memory. The initial reading of data can be bypassed by generating predetermined data. In many examples, generating predetermined data can utilize fewer resources than initializing and reading data. Predetermined data can be generated when data is not utilized. For example, data may not be needed between executing a first plurality of operations and executing a second plurality of operations. Predetermined data can be generated during a transition between executing a first plurality of operations and executing a second plurality of operations. Predetermined data can be used to generate updated data, which can be stored in the memory, thereby canceling the reading and / or initialization of data stored in the memory.

[0073] In various examples, the examples described herein are applicable to generating predetermined data in the areas of decoding, encoding, telemetry, performance counter usage, timing / scheduling counter usage, quality of service (QoS), and / or priority and arbitration counter usage. The examples described herein are also applicable to generating predetermined data in the areas of matrix operations, encryption, decryption, scrambling, and / or interrupt mapping. For example, in the area of ​​QoS, a predetermined QoS definition may be created rather than initializing and reading the QoS definition from a memory using multiple AND gates and / or AND operations as described herein.

[0074] Figure 3 380 is a flow chart corresponding to a method 380 for resetting a correction matrix according to some embodiments of the present disclosure. The method 380 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 380 is performed by Figure 1 The decoding circuit system 113 is executed. Although shown in a specific sequence or order, unless otherwise specified, the order of the process can be modified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be performed in different orders, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0075] Method 380 includes performing a decoding operation. As described above, the decoding operation can be performed by utilizing a correction matrix during the operation of decoding a bit string and / or a codeword. As described above, the decoding operation can be performed to correct one or more bit flip errors within the bit string and / or codeword described herein.

[0076] At operation 381, a command to read a correction matrix including a plurality of bit values ​​from a memory of a decoder may be received. In various examples, the memory may receive the command. The command may originate from a decision engine and / or a control circuit system of a memory subsystem including the decoder. The command may originate from outside the memory subsystem.

[0077] In operation 382, ​​in response to receiving the command, a predetermined correction matrix including the same bit value may be generated using the circuitry of the decoder. For example, the predetermined correction matrix may include bits having a first bit value (e.g., a 0 bit). The predetermined correction matrix may be generated in response to the correction matrix not being previously modified. For example, the correction matrix may not be modified during the decoding of the codeword associated with the correction matrix. In operation 383, the predetermined correction matrix may be provided to the decision engine to perform a decoding operation.

[0078] In various examples, a predetermined correction matrix may be provided instead of providing the correction matrix. For example, if the correction matrix is ​​not modified at the time of decoding of the codeword, the predetermined correction matrix may be provided to the decision engine. If the correction matrix is ​​modified at the time of decoding of the codeword, the correction matrix may be provided to the decision engine instead of generating the predetermined correction matrix.

[0079] A predetermined correction matrix may also be generated instead of resetting the correction matrix. The generation of the predetermined correction matrix may be equal to resetting the correction matrix. For example, the reset correction matrix and the predetermined correction matrix may include bits having a first bit value (e.g., a 0 bit). The reset correction matrix and the predetermined correction matrix may both include the same number of bits. A predetermined correction matrix may also be generated instead of reading the correction matrix. A predetermined correction matrix may be generated instead of resetting and reading the correction matrix from a memory. Generating the predetermined correction matrix may utilize fewer resources than resetting and reading the correction matrix.

[0080] Prior to being updated, a correction matrix stored in a memory may be generated by performing a decoding operation to decode a different bit string. Decoding a different bit string may include updating the correction matrix. At the end of a decoding operation performed to decode a different bit string, the correction matrix is ​​not reset. At the beginning of a decoding operation performed to decode a bit string, the correction matrix is ​​not reset. Even if a bit string is currently being decoded, a correction matrix may be left over from decoding a different bit string. The correction matrix is ​​not provided to the decision engine because the correction matrix is ​​left over from a previous decoding operation. Instead, a predetermined correction matrix may be generated and provided to the decision engine.

[0081] At least one AND gate may be used to generate a predetermined correction matrix. For example, a plurality of AND operations may be used to generate a predetermined correction matrix. The number of AND operations performed by the AND gate may be equal to the number of bits of the correction matrix. The AND gate and a bit mask may be used to generate a predetermined correction matrix. The bit mask stored in the register may be used to activate or deactivate the correction matrix. If the correction matrix is ​​deactivated, a predetermined correction matrix may be generated. If the correction matrix is ​​active, a predetermined correction matrix may not be generated. Each of the AND gates may receive the same bit mask from the register and different bits from the correction matrix. The bit mask may be used to mask the correction matrix using the AND gate.

[0082] In an example where the predetermined correction matrix includes bits having a first value (e.g., a 0 bit), an AND gate may be used to generate the predetermined correction matrix. In an example where the predetermined correction matrix includes bits having a second value (e.g., a 1 bit), an OR gate may be used to generate the predetermined correction matrix. The OR gate may receive the same bit mask and different bits from the correction matrix.

[0083] In various examples, a number of registers may store a bit mask. For example, a register may store bits as a bit mask. A memory cell array may store a correction matrix including a first plurality of bits. Circuitry coupled to the array may include an AND gate. The circuitry may utilize the bit mask to change a first plurality of bits of the correction matrix from a second value to a first value to generate a second plurality of bits during an iteration of a decoding operation performed to decode a codeword. Bits of the correction matrix may have the second value, while bits in the second plurality of bits have the first value.

[0084] The second plurality of bits may be provided to a decision engine. A decision engine coupled to the first circuit system, the array, and the plurality of registers may update the bit mask in response to updating the codeword. In response to updating the codeword using the second plurality of bits, the bit mask may be updated to reflect that the codeword is updated. The change to the bit mask activates the first plurality of bits so that the first plurality of bits are not altered by the circuit system during subsequent iterations of the decoding operation.

[0085] The decision engine is further configured to update a first plurality of bits stored in the memory cell array in response to the update codeword. The bit mask and the first plurality of bits may be updated concurrently. As used herein, concurrently describes actions taken at the same time or at relatively the same time. The decision engine may update the bit mask by updating bits of the bit mask. The bits of the bit mask and / or the bit mask may be associated with an address corresponding to the first plurality of bits.

[0086] The decision engine may utilize an XOR gate to update the first plurality of bits in the array. The XOR gate may be used to flip the bits of the output of the AND gate. For example, in the first iteration, the XOR gate may flip the bits of the predetermined correction matrix. In subsequent iterations, the XOR gate may flip the bits of the correction matrix. The XOR gate may provide the updated correction matrix or the updated predetermined correction matrix to the memory. The memory may store the updated predetermined correction matrix or the updated portion of the codeword based on the identification of the corresponding bits of the codeword that are updated (e.g., flipped) provided by the decision engine. Different circuit systems (e.g., pipeline circuit systems) may align the second plurality of bits with one or more signals indicating that the codeword provided by the decision engine is updated at the XOR gate to update the first plurality of bits. In various examples, a bit mask may be used to open the AND gate to read the updated first plurality of bits in subsequent iterations of the decoding operation. For example, the AND gate may receive and provide the updated first plurality of bits without modifying the updated first plurality of bits in subsequent iterations of the decoding operation.

[0087] In various examples, in response to receiving a command to read the correction matrix, if the bit mask stored in the register includes the second value, then a first plurality of bits of the correction matrix can be read. In response to receiving a command to process the codeword, if the bit mask includes the first value, then a second plurality of bits can be generated using a plurality of AND gates. The first plurality of bits and the second plurality of bits can be provided to perform a number of operations using the correction matrix. The first plurality of bits and the second plurality of bits can be provided to a decision engine, a device external to the decoder but internal to the memory subsystem, and / or a device external to the memory subsystem. For example, the first plurality of bits and the second plurality of bits can be provided to a host.

[0088] The bit mask may be reset in response to providing the first plurality of bits and the second plurality of bits. For example, the bit mask may be reset at the end of decoding of the codeword. The first plurality of bits and the second plurality of bits may be provided to terminate decoding of the codeword. The correction matrix may not be reset in response to initiating decoding of a different codeword or terminating decoding of a codeword. In response to initiating decoding of a different codeword, an AND gate and an updated bit mask may be utilized to generate a third plurality of bits. The third plurality of bits consists of the same bit value.

[0089] Figure 4 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. For example, Figure 4 An example machine illustrating a computer system 490 within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 490 may correspond to a host system (e.g., Figure 1 ) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110 of the controller may be used to execute the operation of the controller (for example, execute the operating system to execute the corresponding Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client user machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client user machine in a cloud computing infrastructure or environment.

[0090] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. In addition, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0091] The example computer system 490 includes a processing device 491, a main memory 493 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 497 (e.g., flash memory, static random access memory (SRAM)), etc.), and a data storage system 498, which communicate with each other via a bus 430.

[0092] The processing device 491 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets or multiple processors implementing a combination of instruction sets. The processing device 491 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 491 is configured to execute instructions 492 for performing the operations and steps discussed herein. The computer system 490 may further include a network interface device 494 to communicate over a network 495.

[0093] The data storage system 498 may include a machine-readable storage medium 499 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 492 or software embodying any one or more of the methodologies or functions described herein. The instructions 492 may also reside, completely or at least partially, within the main memory 493 and / or within the processing device 491 during execution thereof by the computer system 490, the main memory 493 and the processing device 491 also constituting machine-readable storage media. The machine-readable storage medium 499, the data storage system 498, and / or the main memory 493 may correspond to Figure 1 Memory subsystem 110.

[0094] In one embodiment, instructions 492 include implementing circuitry corresponding to syndrome decoding (e.g., Figure 1The functional instructions of the decoding circuit system 113 of the present invention are stored in the storage medium 499. Although the machine-readable storage medium 499 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be taken to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be taken to include any medium capable of storing or encoding a set of instructions for machine execution and causing the machine to perform any one or more of the methodologies of the present disclosure. The term "machine-readable storage medium" should accordingly be taken to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0095] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here and generally conceived to be a self-consistent sequence of operations leading to a desired result. Operations are those requiring physical manipulation of physical quantities. Typically, although not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, primarily for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0096] It should be remembered, however, that all of these and similar terms should be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may involve actions and processes of computer systems or similar electronic computing devices that manipulate and transform data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0097] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0098] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used in conjunction with programs according to the teachings herein, or it may prove convenient to construct more specialized equipment to perform the methods. The structures of a variety of these systems will appear as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It should be appreciated that a variety of programming languages ​​may be used to implement the teachings of the present disclosure as described herein.

[0099] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form that can be read by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory device, etc.

[0100] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be appreciated that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the description and drawings should be viewed in an illustrative rather than a restrictive sense.

Claims

1. A method for resetting a correction matrix, comprising: The first iteration of the decoding operation is performed on the bit string by: receiving a command to read a correction matrix including a plurality of bit values ​​from a memory of a decoder (113, 213); in response to receiving the command, using circuitry of the decoder to generate a predetermined correction matrix including the same bit values; and The predetermined correction matrix is ​​provided to a decision engine (222) to perform the decoding operation. 2 . The method of claim 1 , further comprising providing the predetermined correction matrix instead of providing the correction matrix.

3. The method of claim 1, further comprising generating the predetermined correction matrix instead of resetting the correction matrix. The method of claim 1 , further comprising generating the predetermined correction matrix instead of reading the correction matrix. The method of claim 1 , wherein the correction matrix is ​​generated by performing a decoding operation to decode different bit strings.

6. The method of any one of claims 1 to 5, further comprising generating the predetermined correction matrix using one of: AND gate (225, 232); AND gate (225, 232) and bit mask; OR gate (229, 231); or OR gate (229, 231) and bit mask.

7. A device for resetting a correction matrix, comprising: a plurality of registers (224) configured to store bit masks; a memory cell array (223) configured to store a correction matrix comprising a first plurality of bits; and a circuit system coupled to the array and configured to: changing the first plurality of bits of the correction matrix from a second value to a first value using the bit mask during an iteration of a decoding operation performed to decode a codeword to produce a second plurality of bits; providing the second plurality of bits to a decision engine (222); and The decision engine, coupled to the circuitry, the array, and the plurality of registers and configured to: In response to updating the codeword with the second plurality of bits, the bit mask is updated to reflect that the codeword is updated.

8. The apparatus of claim 7, wherein the decision engine is further configured to update the first plurality of bits stored in the memory cell array in response to updating the codeword.

9. The apparatus of claim 8, wherein the circuitry is further configured to utilize the bit mask to open an AND gate (232) to read the updated first plurality of bits in a subsequent iteration of the decode operation.

10. The apparatus of claim 7, wherein the decision engine is further configured to update bits of the bit mask associated with addresses corresponding to the first plurality of bits.

11. The apparatus of any one of claims 7 to 10, wherein the decision engine is further configured to utilize an XOR gate (226) to update the first plurality of bits in the array.

12. The apparatus of claim 11, further comprising different circuitry (227-1) configured to align the second plurality of bits with one or more signals provided by the decision engine indicating that the codeword is updated at the XOR gate to update the first plurality of bits.

13. A device for resetting a correction matrix, comprising: a plurality of registers (224) configured to store bit masks; a memory cell array (223) configured to store a correction matrix comprising a first plurality of bits; and circuitry coupled to the array and the plurality of registers and configured to: in response to receiving a command to read the correction matrix, if the bit mask includes a second value, reading a first plurality of bits of the correction matrix; In response to receiving a command to process the codeword, if the bit mask includes a first value, generating a second plurality of bits using a plurality of AND gates (225); and The first plurality of bits and the second plurality of bits are provided to perform a number of operations utilizing the correction matrix.

14. The apparatus of claim 13, further comprising control circuitry (228) configured to reset the bit mask in response to providing the first and second pluralities of bits.

15. The apparatus of any one of claims 13-14, wherein the circuitry is further configured to provide the first plurality of bits and the second plurality of bits to terminate decoding of the codeword.

16. The apparatus of claim 15, wherein the circuit system is further configured to: avoiding resetting the correction matrix in response to initiating decoding of a different codeword; and In response to initiating the decoding of the different codeword, a third plurality of bits is generated using the plurality of AND gates and an updated bit mask, wherein the third plurality of bits consists of the same bit value.

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