Information processing apparatus, robot controller, and information processing method

Abstract

The invention provides an information processing apparatus, a robot controller, and an information processing method, capable of suppressing power consumption and realizing high speed of information processing including signature verification of a program. The information processing device is characterized by being provided with: a first CPU core; the working efficiency of the second CPU core is higher than that of the first CPU core; and a program storage unit that stores a first module, a second module, a third module having a larger capacity size than the second module, an electronic signature for the second module, and an electronic signature for the third module. The second CPU core performs a second module verification process for verifying the second module on the basis of the second module electronic signature by executing the second module, and performs a third module verification process for verifying the third module on the basis of the third module electronic signature by executing the second module.

Description

Technical Field

[0001] The present invention relates to an information processing device, a robot controller and an information processing method. Background Art

[0002] An information processing device is being studied that signs a program in advance, stores it, and verifies the signature of the program each time it is started. By verifying the signature, it is possible to detect whether the program has been tampered with.

[0003] For example, Patent Document 1 discloses an information processing device that starts a plurality of modules in sequence after starting a first module, and the information processing device includes a first module, a second module, and a third module that are started in sequence. The first module uses verification information for verifying a signature of a second module to be started next to detect tampering of the second module and tampering of the third module. After being started by the first module, the second module starts the third module to be started next.

[0004] According to such a configuration, when multiple modules are started in sequence, the success of signature verification is a condition, so a mechanism for detecting tampering in the system can be provided. In addition, since the verification information stored in the first module is used to detect tampering of multiple modules, effective use of memory resources can be achieved.

[0005] Patent Document 1: Japanese Patent Application Publication No. 2019-175000

[0006] In the information processing device described in Patent Document 1, there is a technical problem that it takes time to start up because multiple modules are started up in sequence. In addition, although the start-up time can be shortened by increasing the operating speed of the CPU of the information processing device, in this case, there is a technical problem that power consumption increases. Summary of the invention

[0007] An information processing device according to an application example of the present invention includes:

[0008] First CPU core;

[0009] a second CPU core, the operating frequency of the second CPU core being higher than the operating frequency of the first CPU core; and

[0010] a program storage unit storing a first module, a second module, a third module having a capacity larger than that of the second module, an electronic signature for the second module, and an electronic signature for the third module,

[0011] The first CPU core performs a second module verification process of verifying the second module based on the electronic signature of the second module by executing the first module, and the second CPU core performs a third module verification process of verifying the third module based on the electronic signature of the third module by executing the second module.

[0012] The robot controller according to the application example of the present invention is characterized in that it controls the movement of the robot, and the robot controller comprises:

[0013] First CPU core;

[0014] a second CPU core, the operating frequency of the second CPU core being higher than the operating frequency of the first CPU core; and

[0015] a program storage unit storing a first module, a second module, a third module having a capacity larger than that of the second module, an electronic signature for the second module, and an electronic signature for the third module,

[0016] The first CPU core performs a second module verification process of verifying the second module based on the electronic signature of the second module by executing the first module, and the second CPU core performs a third module verification process of verifying the third module based on the electronic signature of the third module by executing the second module.

[0017] The information processing method according to the application example of the invention is characterized in that information processing is performed using a first CPU core, a second CPU core, and a program storage unit, wherein the program storage unit stores a first module, a second module, a third module, an electronic signature for the second module, and an electronic signature for the third module.

[0018] The operating frequency of the second CPU core is higher than the operating frequency of the first CPU core.

[0019] The capacity size of the third module is larger than the capacity size of the second module,

[0020] The first CPU core performs a second module verification process of verifying the second module based on the electronic signature of the second module by executing the first module, and the second CPU core performs a third module verification process of verifying the third module based on the electronic signature of the third module by executing the second module. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a conceptual diagram showing a configuration example of a robot system.

[0022] Figure 2 Yes means Figure 1The block diagram of the robot controller hardware configuration example is shown in FIG.

[0023] Figure 3 Yes means Figure 2 A block diagram of an example of the hardware configuration of a processor shown.

[0024] Figure 4 Yes means Figure 2 A functional block diagram showing the functions of the main substrate.

[0025] Figure 5 yes Figure 2 The memory map of the program storage unit of the main substrate is shown.

[0026] Figure 6 It is used to illustrate Figure 2 Flowchart of a method for starting up a main substrate (information processing method according to an embodiment) shown in FIG.

[0027] Figure 7 It is a conceptual diagram for explaining the signature verification of the IPL (first module) by the boot loader.

[0028] Figure 8 This is a conceptual diagram for explaining the signature verification of the loader program (second module) by IPL.

[0029] Fig. 9 This is a conceptual diagram for explaining the signature verification of a compressed file (third module) by a loader program.

[0030] Description of Reference Numerals

[0031] 1…Robot system, 100…Robot, 120…Base, 130…Robot arm, 132…Arm end, 160…End effector, 200…Robot controller, 220…Main substrate, 222…Processor, 224…External bus, 226…RAM, 228…ROM, 230…Program storage unit, 232…Input / output port, 234…Memory card interface, 240…First sub-substrate, 242…Processor, 244…External bus, 246…RAM, 2 48…ROM, 260…second sub-base, 262…processor, 264…external bus, 266…RAM, 268…ROM, 280…communication interface, 291…first CPU core, 292…second CPU core, 293…RAM, 294…ROM, 295…internal bus, 300…teaching pendant, 312…interface control unit, 314…language analysis unit, 316…input / output control unit, 318…interrupt control unit, 350…computer, 41 0... memory space, 412... boot loader, 416... key for first module, 420... memory space, 422... initial program loader (IPL), 423... hash value, 424... electronic signature for first module, 425... hash value, 426... key for second module, 430... memory space, 432... loader, 433... hash value, 434... electronic signature for second module, 435... hash value, 436... key for third module, 440... memory space Storage space, 442…compressed file, 443…hash value, 444…electronic signature for the third module, 445…hash value, J1…joint, J2…joint, J3…joint, J4…joint, J5…joint, J6…joint, S102…step, S104…step, S106…step, S108…step, S110…step, S112…step, S114…step, S116…step, S118…step, S120…step, S122…step. DETAILED DESCRIPTION

[0032] Hereinafter, the information processing device, the robot controller, and the information processing method of the present invention will be described in detail based on the preferred embodiments shown in the drawings.

[0033] 1. Robotic system

[0034] First, a robot system including a robot controller according to an embodiment will be described.

[0035] Figure 1 : is a conceptual diagram showing a configuration example of the robot system 1 .

[0036] Figure 1The robot system 1 shown includes a robot 100 , a robot controller 200 (robot controller according to the embodiment), a teaching pendant 300 , and a computer 350 .

[0037] 1.1. Robot

[0038] Figure 1 The robot 100 shown includes a base 120 and a robot arm 130. The robot arm 130 includes six arms connected in sequence from the base 120 side and six joints J1 to J6 connecting the base 120 and the arms and between the arms. Figure 1 Among the six joints J1 to J6 shown, three joints J2, J3, and J5 are bending joints, and the other three joints J1, J4, and J6 are torsion joints. In addition, although not shown in the figure, the joints J1 to J6 are respectively equipped with a motor as a driving source and an encoder for detecting the rotation amount of the motor, that is, the position information of the motor. In this specification, the motor and the encoder are collectively referred to as a servo motor.

[0039] An arm end 132 is provided at the front end of the robot arm 130, that is, at the end of the robot arm 130 on the side opposite to the base 120. An end effector 160 is mounted on the arm end 132. The end effector 160 is mounted in a detachable manner. Examples of the end effector 160 include a hand for holding a workpiece, a suction tool for suctioning a workpiece, and the like.

[0040] 1.2. Robot controller

[0041] Figure 1 The robot controller 200 shown includes a main substrate 220 (information processing device according to the embodiment), a first sub-substrate 240 , and a second sub-substrate 260 . These substrates can communicate with each other via a communication interface 280 .

[0042] 1.2.1. Main base board

[0043] Figure 2 Yes means Figure 1 2 is a block diagram of a hardware configuration example of the robot controller 200 shown.

[0044] Figure 2 The main board 220 (information processing device according to the embodiment) shown includes a processor 222, an external bus 224, a RAM 226, a ROM 228, an input / output port 232, and a memory card interface 234. RAM is a random access memory, and ROM is a read-only memory.

[0045] Figure 2The processor 222 shown implements various functions by executing programs loaded in the RAM 226 or programs stored in the ROM 228 .

[0046] Figure 3 Yes means Figure 2 2 is a block diagram of an example of a hardware configuration of the processor 222 shown.

[0047] Figure 3 The processor 222 shown is a SoC (System on a Chip) device. An SoC device is a device in which a CPU core or other devices are mixed and mounted on one chip (die). Figure 3 The processor 222 shown has a first CPU core 291, a second CPU core 292, a RAM 293, a ROM 294, and an internal bus 295. CPU is a central processing unit. By using such a SoC element as the processor 222, the power consumption of the main substrate 220 can be further reduced, and miniaturization and low cost can be achieved. In addition, the RAM 293 and the ROM 294 can be set as needed, or they can be omitted. In addition, it is not necessary for the processor 222 to be a SoC element, for example, it can also be a SiP (System in a Package), and the first CPU core 291 and the second CPU core 292 can also be independent components.

[0048] The operating frequency of the second CPU core 292 is higher than the operating frequency of the first CPU core 291. On the other hand, when the operating frequency is high, there is a tendency that power consumption also becomes high. In view of these circumstances, by mixing CPU cores with different operating frequencies on the main substrate 220, if the program to be executed by each CPU core is appropriately selected, the power consumption of the main substrate 220 can be suppressed, and the information processing on the main substrate 220 can be accelerated.

[0049] The number of CPU cores that a processor 222 has is not limited to Figure 3 The two shown may be three or more.

[0050] In addition, the operating frequency of the second CPU core 292 can be higher than the operating frequency of the first CPU core 291, but it is preferably 1.5 times or more, and more preferably 2.0 times or more. Thus, a sufficiently high speed can be achieved for the module executed by the second CPU core 292. On the other hand, the upper limit of the operating frequency of the second CPU core 292 may not be specifically set, but considering the balance with power consumption, it is preferably 5.0 times or less of the operating frequency of the first CPU core 291, and more preferably 3.0 times or less of the operating frequency of the first CPU core 291.

[0051] In addition, the power consumption of the first CPU core 291 is lower than the power consumption of the second CPU core 292, but the difference often corresponds to the difference in operating frequency. For example, the power consumption of the first CPU core 291 is preferably less than 50% of the power consumption of the second CPU core 292, more preferably less than 30% of the power consumption of the second CPU core 292, and further preferably less than 10% of the power consumption of the second CPU core 292. On the other hand, the lower limit value of the power consumption of the first CPU core 291 may not be specifically set, but in consideration of the balance with the operating frequency, it is preferably more than 1% of the power consumption of the second CPU core 292.

[0052] The RAM 293 temporarily stores programs executed by the processor 222, read data, etc. Examples of the RAM 293 include DRAM (Dynamic Random Access Memory) and the like.

[0053] ROM 294 stores programs and other data for execution by processor 222. Examples of ROM 294 include mask ROM, anti-fuse PROM (Programmable Read-Only Memory), EEPROM (registered trademark) (Electrically Erasable Programmable Read-Only Memory), and Flash ROM (Flash Read-Only Memory).

[0054] The external bus 224 is a transmission path that connects the processor 222 and the RAM 226 and ROM 228 to enable them to communicate with each other.

[0055] The RAM 226 temporarily stores programs executed by the processor 222, read data, etc. As the RAM 226, for example, a DRAM or the like can be cited.

[0056] The ROM 228 stores programs executed by the processor 222, other data, and the like. Examples of the ROM 228 include EEPROM (registered trademark) and Flash ROM. The ROM 228 may be an external storage element.

[0057] The aforementioned ROM 294 and the aforementioned ROM 228 constitute a "program storage unit 230".

[0058] The input / output port 232 is an interface for communicating between each part of the main substrate 220 and other devices. Examples of the input / output port 232 include a digital input / output port such as a USB (Universal Serial Bus), an Ethernet (registered trademark) port, and a video output port. In addition, the input / output port 232 may be configured to download programs and data from the Internet.

[0059] The memory card interface 234 is an interface that can insert and remove a memory card (not shown) and write and read data from the memory card. The memory card interface 234 may be provided as required or may be omitted.

[0060] 1.2.2. First Sub-Substrate

[0061] Figure 2 The first sub-substrate 240 shown includes a processor 242 , an external bus 244 , a RAM 246 , and a ROM 248 .

[0062] The processor 242 implements various functions by executing programs loaded in the RAM 246 or programs stored in the ROM 248. Examples of the processor 242 include a microprocessor and a SoC element. In addition, part or all of the processor 242 may be constituted by a device such as an ASIC or an FPGA.

[0063] The external bus 244 enables communication between the processor 242 and the RAM 246 and the ROM 248. The RAM 246 temporarily stores programs executed by the processor 242, read data, etc. The ROM 248 stores programs executed by the processor 242, other data, etc. For example, the elements mentioned as the RAM 226 and the ROM 228 described above are used for the RAM 246 and the ROM 248.

[0064] 1.2.3. Second Sub-Substrate

[0065] Figure 2 The second sub-substrate 260 shown includes a processor 262 , an external bus 264 , a RAM 266 , and a ROM 268 .

[0066] The processor 262 implements various functions by executing programs loaded in the RAM 266 or programs stored in the ROM 268. Examples of the processor 262 include a microprocessor and a SoC element. In addition, part or all of the processor 262 may be composed of a device such as an ASIC or an FPGA.

[0067] The external bus 264 enables communication between the processor 262 and the RAM 266 and the ROM 268. The RAM 266 temporarily stores programs executed by the processor 262, read data, etc. The ROM 268 stores programs executed by the processor 262, other data, etc. For example, the elements mentioned as the RAM 226 and the ROM 228 described above are used for the RAM 266 and the ROM 268.

[0068] 1.2.4. Communication interface

[0069] The communication interface 280 is a transmission path for transmitting programs, data, etc., and is, for example, a serial communication interface such as PCI or PCI Express (registered trademark).

[0070] The hardware configuration example of the robot controller 200 is described above, but the hardware configuration is not limited thereto. For example, the first sub-substrate 240 and the second sub-substrate 260 may be provided as required, or may be omitted.

[0071] 1.2.5. Functional department

[0072] Figure 4 Yes means Figure 2 A functional block diagram of the functions of the main substrate 220 is shown.

[0073] Figure 4 The main substrate 220 shown has an interface control unit 312, a language analysis unit 314, an input / output control unit 316, and an interrupt control unit 318 as functional units. The functions of each of these functional units are implemented by the processor 222 executing a program loaded in the RAM 226 of the main substrate 220 and a program stored in the ROM 228. In addition, the functional units as described above are examples of the case where the main substrate 220 is used for the robot controller 200. Therefore, the functional units are appropriately selected according to the purpose of the main substrate 220.

[0074] The interface control unit 312 controls, for example, communication among the main substrate 220 , the first sub-substrate 240 , and the second sub-substrate 260 .

[0075] The language analysis unit 314 reads and analyzes the robot language describing the actions of the robot 100. The operation program of the robot 100 is received from the computer 350 via the input / output control unit 316 described later, and the operation program is analyzed to obtain the target position information of the robot arm 130. The target position information is information about the target position as the target point to move the control point of the robot arm 130, for example, data indicating the coordinates of the target position.

[0076] The input / output control unit 316 controls connection with the teaching pendant 300 , the computer 350 , other peripheral devices, and the like connected to the main substrate 220 .

[0077] The interrupt control unit 318 controls a process of branching from a program being executed to another program (interrupt processing).

[0078] Figure 5 yes Figure 2 The memory map of the program storage unit 230 of the main substrate 220 is shown. Figure 5 The memory map shown is an example and is not limited to this.

[0079] like Figure 5 As shown, the program storage unit 230 of the main substrate 220 includes a memory space 410, a memory space 420, a memory space 430, and a memory space 440. These memory spaces 410, 420, 430, and 440 are address spaces that can be accessed by the processor 222. In addition, these memory spaces 410, 420, 430, and 440 can also be divided and allocated to multiple devices, such as ROM 294 and ROM 268. In addition, each memory space 410, 420, 430, and 440 can also be divided into multiple pieces and divided and allocated to multiple devices.

[0080] The memory space 410 stores a boot loader 412 and a first module key 416. The memory space 410 stores the boot loader 412 that is first started after the main board 220 is powered on, so the memory space 410 is preferably allocated to a non-rewritable device.

[0081] The memory space 420 stores an initial program loader 422 (first module), a first module electronic signature 424, and a second module key 426. In the present application, the initial program loader is also referred to as "IPL".

[0082] The memory space 430 stores a loader program 432 (second module), a second module electronic signature 434 , and a third module key 436 .

[0083] A compressed file 442 (third module) and a third module electronic signature 444 are stored in the memory space 440. The third module may include elements other than the compressed file 442.

[0084] The boot loader 412 is executed by the processor 222 immediately after the main substrate 220 is powered on. The boot loader 412 has a function of verifying the signature of the IPL 422.

[0085] After the loader 412 is booted, the processor 222 executes the IPL 422. The IPL 422 has a function of verifying the signature of the loader program 432.

[0086] Following the IPL 422 , the processor 222 executes the loader program 432 . The loader program 432 has a function of verifying the signature of the compressed file 442 , and a function of decompressing the compressed file 442 and loading the compressed file 442 into the RAM 226 .

[0087] The boot loader 412, IPL 422, and loader program 432 described above are all programs necessary for activation of the main substrate 220. By executing these programs by the processor 222, activation (secure activation) of the main substrate 220 is completed.

[0088] The compressed file 442 is a file formed by compressing an OS (operating system), an application program, a root file system, etc. The compressed file 442 is generally a binary file. The programs contained in the compressed file 442 are programs required for information processing, etc. The processor 222 executes these programs loaded in the RAM 226, thereby realizing the functions of the aforementioned functional units of the main substrate 220.

[0089] The capacity size of the compressed file 442 is larger than the capacity size of the loader program 432. In other words, the capacity size of the loader program 432 is smaller than the capacity size of the compressed file 442. The capacity size refers to the capacity occupied in the program storage unit 230 (file size).

[0090] 1.3. How to start the main board

[0091] Next, Figure 2 A method for starting the main substrate 220 shown (an information processing method according to the embodiment) will be described.

[0092] Figure 6 It is used to illustrate Figure 2 The flowchart of the method for starting the main substrate 220 (the information processing method involved in the embodiment) is shown in FIG. Figure 6 In FIG. 1 , a process shared by the first CPU core 291 and a process shared by the second CPU core 292 are separately illustrated.

[0093] Figure 6 The method for starting up the main substrate 220 shown has steps S102 to S122.

[0094] After the main board 220 is powered on, the process proceeds to step S102 . In step S102 , the first CPU core 291 executes the boot loader 412 stored in the memory space 410 .

[0095] In step S104 , the executed boot loader 412 performs a first module verification process. In the first module verification process, the IPL 422 (first module) stored in the memory space 420 is signature-verified based on the first module key 416 stored in the memory space 410 and the first module electronic signature 424 stored in the memory space 420 .

[0096] Figure 7 4 is a conceptual diagram for explaining the signature verification of the IPL 422 (first module) by the boot loader 412.

[0097] When the first CPU core 291 executes the boot loader 412, the executed boot loader 412 applies the IPL 422 to the hash function, thereby obtaining a hash value 423. The hash function is a function that returns output data (hash value) of a fixed length from data of any length, and examples thereof include SHA-256, SHA-384, and SHA-512.

[0098] On the other hand, the boot loader 412 decrypts the first module electronic signature 424 using the first module key 416. This obtains a hash value 425. The first module key 416 may be a public key or a public key.

[0099] Then, the boot loader 412 compares the hash value 423 with the hash value 425. When the two are the same value, the integrity and authenticity of the IPL 422 can be confirmed, and thus the signature verification for the IPL 422 is deemed to be successful. On the other hand, when the two are different values, the signature verification for the IPL 422 is deemed to have failed.

[0100] In addition, the first CPU core 291 can directly read the IPL 422 stored in the program storage unit 230, or can temporarily copy the IPL 422 to the RAM 226 and then read it from the RAM 226. In the latter case, although the time required for copying is unnecessary, due to the good accessibility to the RAM 226, the signature verification for the IPL 422 can sometimes be performed in a shorter time, which is useful.

[0101] In addition, the boot loader 412 may be omitted, but in the present embodiment, the boot loader 412 is configured to perform signature verification on the IPL 422. Thus, the integrity and authenticity of the IPL 422 can be confirmed, and the main substrate 220 can be started while ensuring higher security. In addition, by providing both the boot loader 412 and the IPL 422, the flexibility of the startup program can also be ensured.

[0102] In step S106, if the signature verification in step S104 succeeds, the flow is branched to step S108. On the other hand, if the signature verification in step S104 fails, the flow is branched to step S110. In step S110, the activation of the main board 220 is stopped.

[0103] In step S108 , the first CPU core 291 executes the IPL 422 (first module).

[0104] In step S112 , the executed IPL 422 performs second module verification processing. In the second module verification processing, the loader 432 (second module) stored in the memory space 430 is signature-verified based on the second module key 426 stored in the memory space 420 and the second module electronic signature 434 stored in the memory space 430 .

[0105] Figure 8 This is a conceptual diagram for explaining the signature verification of the loader program 432 (second module) by the IPL 422.

[0106] When the first CPU core 291 executes the IPL 422 , the executed IPL 422 applies the loader 432 to the hash function, thereby obtaining a hash value 433 .

[0107] On the other hand, the IPL 422 decodes the second module electronic signature 434 using the second module key 426. This obtains a hash value 435. The second module key 426 may be a public key or a public key.

[0108] Then, IPL 422 compares hash value 433 with hash value 435. When the two values ​​are the same, the integrity and authenticity of loader 432 can be confirmed, and thus the signature verification for loader 432 is deemed to have succeeded. On the other hand, when the two values ​​are different, the signature verification for loader 432 is deemed to have failed.

[0109] In addition, as described above, the capacity size of the loader 432 is smaller than the capacity size of the compressed file 442. Therefore, in the signature verification for the loader 432, even if the first CPU core 291 with a relatively low operating frequency is used, the required time does not take too long. On the other hand, the power consumption of the first CPU core 291 is lower than the power consumption of the second CPU core 292. Therefore, in the signature verification for the loader 432, the power consumption can be suppressed to a low level.

[0110] In addition, the first CPU core 291 can directly read the loader program 432 stored in the program storage unit 230, or can temporarily copy the loader program 432 to the RAM 226 and then read it from the RAM 226. In the latter case, although the time required for copying is unnecessary, due to the good accessibility to the RAM 226, the signature verification for the loader program 432 can sometimes be performed in a shorter time, which is useful.

[0111] In step S114, if the signature verification in step S112 succeeds, the flow branches to step S116. On the other hand, if the signature verification in step S112 fails, the flow branches to step S110.

[0112] In step S116 , the second CPU core 292 executes the loader program 432 .

[0113] In step S118, the executed loading program 432 performs the third module verification process. In the third module verification process, the compressed file 442 (third module) stored in the memory space 440 is signature-verified based on the third module key 436 stored in the memory space 430 and the third module electronic signature 444 stored in the memory space 440.

[0114] Fig. 9 This is a conceptual diagram for explaining the signature verification of the compressed file 442 (third module) by the loader program 432.

[0115] When the second CPU core 292 executes the loader 432 , the executed loader 432 applies the compressed file 442 to the hash function, thereby obtaining a hash value 443 .

[0116] On the other hand, the loader 432 decrypts the third module electronic signature 444 using the third module key 436. This obtains a hash value 445. The third module key 436 may be a public key or a public key.

[0117] Then, the loader 432 compares the hash value 443 with the hash value 445. If the two values ​​are the same, the integrity and authenticity of the compressed file 442 can be confirmed, and thus the signature verification for the compressed file 442 is deemed to have succeeded. On the other hand, if the two values ​​are different, the signature verification for the compressed file 442 is deemed to have failed.

[0118] In addition, as described above, the capacity size of the compressed file 442 is larger than the capacity size of the loader program 432. However, in the signature verification of the compressed file 442, by using the second CPU core 292 with a relatively high operating frequency, the required time does not take too long. In addition, although the power consumption of the second CPU core 292 is higher than that of the first CPU core 291, since the time required for the signature verification of the compressed file 442 is shorter, the power consumption of the second CPU core 292 is suppressed to be lower accordingly. Therefore, in the main substrate 220, it is possible to achieve high-speed information processing including signature verification while suppressing power consumption.

[0119] In addition, the second CPU core 292 can directly read the compressed file 442 stored in the program storage unit 230, or can temporarily copy the compressed file 442 to the RAM 226 and then read it from the RAM 226. In the latter case, although the time required for copying is unnecessary, due to the good accessibility to the RAM 226, the signature verification for the compressed file 442 can sometimes be performed in a shorter time, which is useful.

[0120] In step S120, if the signature verification in step S118 succeeds, the flow branches to step S122. On the other hand, if the signature verification in step S118 fails, the flow branches to step S110.

[0121] In step S122, the executed loader program 432 decompresses the compressed file 442 and loads it into the RAM 226. Since the loader program 432 is executed by the second CPU core 292, the decompression and loading processes can be performed in a short time and power consumption can be suppressed.

[0122] As described above, the main substrate 220 can be activated.

[0123] According to the above-mentioned information processing method, it is possible to realize high-speed information processing including signature verification of programs while suppressing power consumption. In addition, it is possible to realize a main substrate 220 (information processing device) and a robot controller 200 that can realize high-speed information processing including signature verification of programs while suppressing power consumption. This can help reduce the load of the robot system 1 on the environment. In addition, when the robot system 1 uses power from a battery (storage battery) to operate, it is possible to suppress the reduction of information processing capabilities in the robot controller 200 and help extend the driving time.

[0124] In addition, according to the above information processing method, the boot loader 412, IPL 422 and loader program 432 are configured to sequentially verify the signature of the program to be executed next, thereby preventing the execution of a program whose integrity and authenticity cannot be confirmed, and enabling the main board 220 to be started while ensuring higher security.

[0125] Furthermore, the first module key 416, the second module key 426, and the third module key 436 may be the same key, but in this embodiment, they are prepared separately and thus can be different keys from each other, thereby further improving the security of each signature verification.

[0126] 2. Effects of the above implementation

[0127] As described above, the main substrate 220 as the information processing device according to the above embodiment includes the first CPU core 291, the second CPU core 292, and the program storage unit 230. The operating frequency of the second CPU core 292 is higher than the operating frequency of the first CPU core 291. The program storage unit 230 stores the IPL 422 (first module), the loader program 432 (second module), the compressed file 442 (third module) having a larger capacity than the loader program 432, the second module electronic signature 434, and the third module electronic signature 444.

[0128] Then, the first CPU core 291 executes the IPL 422 to perform a second module verification process for verifying the loader program 432 based on the second module electronic signature 434 .

[0129] Furthermore, the second CPU core 292 executes the loader program 432 to perform a third module verification process of verifying the compressed file 442 based on the third module electronic signature 444 .

[0130] According to such a structure, the capacity size of the loader program 432 is smaller than the capacity size of the compressed file 442. Therefore, in the second module verification process, even if the first CPU core 291 with a relatively low operating frequency is used, the required time will not take too long. On the other hand, the power consumption of the first CPU core 291 is lower than the power consumption of the second CPU core 292. Therefore, in the second module verification process, the power consumption can be suppressed to a low level. In addition, the capacity size of the compressed file 442 is larger than the capacity size of the loader program 432. Therefore, in the third module verification process, by using the second CPU core 292 with a relatively high operating frequency, the required time will not take too long. On the other hand, although the power consumption of the second CPU core 292 is higher than that of the first CPU core 291, since the required time is shorter, the power consumption is suppressed to a lower level accordingly. Therefore, in the main substrate 220, it is possible to achieve high-speed information processing including signature verification while suppressing power consumption.

[0131] Furthermore, in the above-described embodiment, the RAM 226 is provided, and the second CPU core 292 performs a process of loading the compressed file 442 included in the third module into the RAM 226 .

[0132] According to such a configuration, the decompression and loading processes of the compressed file 442 can be performed in a short time, and the power consumption can also be suppressed.

[0133] In the above embodiment, the program storage unit 230 further stores the boot loader 412 and the first module electronic signature 424. Furthermore, the first CPU core 291 performs the first module verification process by executing the boot loader 412 before the second module verification process. In the first module verification process, the IPL 422 (first module) is verified based on the first module electronic signature 424.

[0134] According to such a structure, the integrity and authenticity of IPL422 (first module) can be confirmed, and the main board 220 can be started while ensuring higher security. In addition, by providing both the boot loader 412 and the IPL422, the flexibility of the startup procedure can also be ensured.

[0135] In addition, in the above embodiment, the first module includes the initial program loader 422 (IPL), the second module includes the loader program 432 , and the third module includes the compressed file 442 loaded by the loader program 432 .

[0136] According to such a structure, the IPL 422 and the loader program 432 sequentially verify the signature of the program to be executed next, thereby preventing the execution of a program whose integrity and authenticity cannot be confirmed, and enabling the main board 220 to be started while ensuring higher security.

[0137] In addition, in the above-mentioned embodiment, the first CPU core 291 and the second CPU core 292 are mixed in a SoC device.

[0138] According to such a structure, the power consumption of the main substrate 220 can be further reduced, and miniaturization and cost reduction can be achieved.

[0139] In addition, the robot controller 200 involved in the above-mentioned embodiment is a robot controller for controlling the operation of the robot 100, and includes a first CPU core 291, a second CPU core 292, a RAM 226, and a program storage unit 230. The operating frequency of the second CPU core 292 is higher than the operating frequency of the first CPU core 291. The program storage unit 230 stores an IPL 422 (first module), a loader program 432 (second module), a compressed file 442 (third module) having a larger capacity than the loader program 432, a second module electronic signature 434, and a third module electronic signature 444.

[0140] Furthermore, the first CPU core 291 executes the IPL 422 to perform a second module verification process for verifying the loader program 432 based on the second module electronic signature 434 .

[0141] Furthermore, the second CPU core 292 executes the loader program 432 to perform a third module verification process of verifying the compressed file 442 based on the third module electronic signature 444 .

[0142] According to such a configuration, it is possible to obtain a robot controller 200 that achieves high-speed information processing including signature verification while suppressing power consumption.

[0143] In addition, the information processing method involved in the above-mentioned embodiment is a method for performing information processing using the first CPU core 291, the second CPU core 292, the RAM 226, and the program storage unit 230. The program storage unit 230 stores the IPL 422 (first module), the loader program 432 (second module), the compressed file 442 (third module), the second module electronic signature 434, and the third module electronic signature 444. In addition, the operating frequency of the second CPU core 292 is higher than the operating frequency of the first CPU core 291. Moreover, the capacity size of the compressed file 442 is larger than the capacity size of the loader program 432.

[0144] Furthermore, the first CPU core executes the IPL 422 to perform a second module verification process for verifying the loader program 432 based on the second module electronic signature 434 .

[0145] Furthermore, the second CPU core 292 executes the loader program 432 to perform a third module verification process of verifying the compressed file 442 based on the third module electronic signature 444 .

[0146] According to such a configuration, it is possible to speed up information processing including signature verification while suppressing power consumption.

[0147] As mentioned above, the information processing device, the robot controller, and the information processing method of the present invention have been described based on the illustrated embodiments, but the present invention is not limited thereto.

[0148] For example, the structures of the various parts of the above-mentioned embodiments of the information processing device and robot controller of the present invention may be replaced with any structure having the same function, or any other structure may be added. In addition, the information processing device of the present invention may also be used for purposes other than the purpose of controlling the actions of the robot. For example, the information processing device of the present invention may also be used in a copier, a multifunction machine, etc. In addition, the information processing method of the present invention may also add steps for any purpose to the above-mentioned embodiments.

Claims

1. An information processing device, characterized in that: have: First CPU core; a second CPU core, the operating frequency of the second CPU core being higher than the operating frequency of the first CPU core; and a program storage unit storing a first module, a second module, a third module having a capacity larger than that of the second module, an electronic signature for the second module, and an electronic signature for the third module, The first CPU core performs a second module verification process of verifying the second module based on the electronic signature of the second module by executing the first module, and the second CPU core performs a third module verification process of verifying the third module based on the electronic signature of the third module by executing the second module.

2. The information processing device according to claim 1, characterized in that The information processing device includes a RAM, The second CPU core performs a process of loading the compressed file included in the third module into the RAM.

3. The information processing device according to claim 1 or 2, characterized in that: The program storage unit also stores a boot loader and an electronic signature for the first module. The first CPU core performs a first module verification process for verifying the first module based on the first module electronic signature by executing the boot loader before the second module verification process.

4. The information processing device according to claim 3, characterized in that: The first module includes an initial program loader, The second module includes a loader program, The third module includes a compressed file loaded by the loading program.

5. The information processing device according to claim 1 or 2, characterized in that: The first CPU core and the second CPU core are mixed in a SoC component.

6. A robot controller, characterized in that: Controlling the actions of the robot, the robot controller comprises: First CPU core; a second CPU core, the operating frequency of the second CPU core being higher than the operating frequency of the first CPU core; and a program storage unit storing a first module, a second module, a third module having a capacity larger than that of the second module, an electronic signature for the second module, and an electronic signature for the third module, The first CPU core performs a second module verification process of verifying the second module based on the electronic signature of the second module by executing the first module, and the second CPU core performs a third module verification process of verifying the third module based on the electronic signature of the third module by executing the second module.

7. An information processing method, characterized in that: information processing using a first CPU core, a second CPU core, and a program storage unit, wherein the program storage unit stores a first module, a second module, a third module, an electronic signature for the second module, and an electronic signature for the third module, The operating frequency of the second CPU core is higher than the operating frequency of the first CPU core. The capacity size of the third module is larger than the capacity size of the second module, The first CPU core performs a second module verification process of verifying the second module based on the electronic signature of the second module by executing the first module, and the second CPU core performs a third module verification process of verifying the third module based on the electronic signature of the third module by executing the second module.

Images