Verification method and device of data transmission module, storage medium and computer equipment
Through the method of direct backdoor access and data comparison, the problem of poor complexity and accuracy of verification data transmission modules in the prior art is solved, and the verification environment is simplified and verification efficiency is improved.
Patent Information
- Application Number
- CN202411397365.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-09
- Publication Date
- 2025-02-14
AI Technical Summary
In the prior art, verification of data transmission modules requires consideration of a variety of complex factors, which leads to high verification difficulty and poor accuracy.
Through direct backdoor access to data comparison, simplifies the setup and maintenance of the verification environment and improves verification efficiency and accuracy.
It greatly simplifies the setup and maintenance of the verification environment, improves the efficiency and accuracy of verification, reduces the complexity and cost of verification, and improves the reliability and stability of the verified data transmission module.
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Figure CN119442983A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of IC verification, and in particular to a verification method, device, storage medium and computer equipment for a data transmission module. Background Art
[0002] In the SOC (System-on-Chip) architecture, data transfer modules such as DMA (Direct Memory Access) modules play a vital role, responsible for efficiently moving data between source addresses and destination addresses, and in this process may involve complex protocol and transmission type conversions, such as AHB (Advanced High-performance Bus) to APB (Advanced Peripheral Bus) protocol conversion, and adjustment of transmission granularity (such as AHB's word increase 4 mode conversion to a single transmission of 8 halfwords). To ensure that these data transfer operations are accurate, verification of DMA modules has become an indispensable part of the SOC development and design process.
[0003] The verification process is usually divided into multiple strategies according to the level and requirements of verification, mainly including system-level simulation verification (using C language simulation), FPGA-based prototype verification, and module-level simulation verification using UVM (Universal Verification Methodology) combined with EDA tools. Among them, UVM occupies a dominant position in module-level simulation verification due to its high efficiency, scalability and reusability.
[0004] See also Figure 1 As shown, it is a verification system structure diagram of the data transmission module in the prior art. When UVM is used for module-level simulation verification, the construction of the verification environment revolves around core components, which are carefully designed to simulate real working scenarios and capture the data required for verification. Specifically, the verification process involves two key Monitor components, which are deployed at the bus interface of the source VIP (Verification Intellectual Property) and the destination VIP, respectively, responsible for capturing data transmission activities on the bus and encapsulating them into Transaction objects. These transactions are then passed to the Scoreboard through the TLM (Transaction-Level Modeling) mechanism. The latter, as the core of data comparison and analysis, is responsible for comparing the data content in the source and destination transactions, thereby verifying the integrity and correctness of data transmission.
[0005] In the implementation details of the TLM mechanism and Scoreboard, a variety of complex factors need to be fully considered to ensure the comprehensiveness and accuracy of the verification. First, it is necessary to evaluate whether there is a data cache mechanism inside the DMA module being verified, which directly affects the delay and consistency check strategy of data transmission. Secondly, the possible protocol conversion and transmission type conversion between the source and destination VIPs require the verification environment to have flexible parsing and adaptation capabilities to accurately capture and handle these differences. Furthermore, due to the asynchronous nature of bus transmission and the complex and numerous sequence scenarios of the completion time of a single transmission at the source or destination caused by the data transmission module "splitting-reorganizing-splitting" the data during the transmission process, the timing issues must be carefully considered during the verification process to ensure that the integrity and accuracy of the data transmission can be verified under all possible timing conditions. In summary, the verification of the data transmission module in the SOC is a complex and meticulous process. Summary of the invention
[0006] The embodiments of the present application provide a data transmission module verification method, device, storage medium and computer equipment, which can solve the problem that the verification of the data transmission module in the prior art needs to consider multiple complex factors, resulting in high verification difficulty and poor accuracy. The technical solution is as follows:
[0007] In a first aspect, an embodiment of the present application provides a method for verifying a data transmission module, the method comprising:
[0008] Calculating the amount of data of the test sequence to be transmitted;
[0009] Start the data transmission module, the source VIP and the destination VIP, and instruct the source VIP to send the test sequence to the destination VIP through the data transmission module;
[0010] When it is detected that the test sequence transmission is completed, the first data is read from the sequence generator of the source VIP through the preset backdoor read-write function, and the second data is read from the sequence generator of the destination VIP through the preset backdoor read-write function, and the comparison function in the Virtual Sequencer is called to compare the first data and the second data.
[0011] In a second aspect, an embodiment of the present application provides a verification device for a data transmission module, the device comprising:
[0012] A calculation unit, used for calculating the data volume of the test sequence to be transmitted;
[0013] A starting unit, used to start the data transmission module, the source VIP and the destination VIP, and to instruct the source VIP to send the test sequence to the destination VIP through the data transmission module;
[0014] A verification unit is used to read the first data in the sequence generator of the source VIP through a preset backdoor read-write function when detecting that the test sequence transmission is completed, and to read the second data in the sequence generator of the destination VIP through a preset backdoor read-write function, and to call a comparison function in a Virtual Sequencer to compare the first data with the second data.
[0015] In a third aspect, an embodiment of the present application provides a computer storage medium, wherein the computer storage medium stores a plurality of instructions, wherein the instructions are suitable for being loaded by a processor and executing the above-mentioned method steps.
[0016] In a fourth aspect, an embodiment of the present application provides a computer device, which may include: a processor and a memory; wherein the memory stores a computer program, and the computer program is suitable for being loaded by the processor and executing the above-mentioned method steps.
[0017] The beneficial effects brought about by the technical solutions provided by some embodiments of the present application include at least:
[0018] Through direct backdoor access and data comparison, reducing the reliance on internal mechanisms and timing processing, etc., the setup and maintenance of the verification environment is greatly simplified, and the efficiency and accuracy of verification are improved. These technical effects not only reduce the complexity and cost of verification, but also improve the reliability and stability of the verified data transmission module. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0020] Figure 1 It is a schematic diagram of the network architecture of the verification system in the prior art;
[0021] Figure 2 is a schematic diagram of the network architecture of the verification system provided in an embodiment of the present application;
[0022] Figure 3 It is a flowchart of a verification method of a data transmission module provided in an embodiment of the present application;
[0023] Figure 4 It is a structural schematic diagram of a verification device for a data transmission module provided by the present application;
[0024] Figure 5 It is a structural schematic diagram of a computer device provided by this application. DETAILED DESCRIPTION
[0025] In order to make the objectives, technical solutions and advantages of the present application more clear, the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.
[0026] It should be noted that the verification method of the data transmission module provided in the present application is generally executed by a computer device, and accordingly, the verification device of the data transmission module is generally set in the computer device.
[0027] Figure 2 An exemplary system architecture that can be applied to the data transmission module verification method or data transmission module verification device of the present application is shown.
[0028] like Figure 2 As shown, the schematic diagram of the architecture of the verification system based on UVM includes: a source VIP, a destination VIP, a data transmission module to be verified, a virtual sequencer, and a virtual sequence library. The source VIP and the destination VIP both include a sequence library, a sequence generator, and a protocol driver. The source VIP and the destination VIP both communicate with the data transmission module. The data transmission module is a multi-channel DMA (Direct Memory Access) or a NoC (Network-on-Chip).
[0029] In a system for verifying data transmission modules based on UVM (Universal Verification Methodology), various components work together to ensure the accuracy and reliability of data transmission. The following is a detailed description of the system and its key components:
[0030] Source VIP (Verification IP): responsible for generating and sending test data to the data transmission module to be verified.
[0031] Destination VIP: Receives data from the data transmission module and performs verification.
[0032] The data transmission module to be verified: DUT (Device Under Test) is the core object of system verification.
[0033] Virtual Sequencer: It is used to manage and schedule the execution order of different sequences to ensure the orderly progress of the test process.
[0034] Virtual Sequence library: stores a series of sequences used for testing, which define the specific content and behavior of the test.
[0035] Detailed structure of source VIP and destination VIP
[0036] Sequence Library: Contains multiple sequences, each of which defines specific test scenarios and data.
[0037] Sequence Generator: Selects and generates sequences from a sequence library and then passes these sequences to the protocol driver.
[0038] Protocol Driver: It is responsible for converting the test data in the sequence into a format that complies with the protocol specification and sending it to the data transmission module through the interface. At the same time, it is also responsible for receiving data from the data transmission module and passing it to the corresponding monitor or comparator.
[0039] System workflow:
[0040] The Virtual Sequencer selects appropriate sequences from the Virtual Sequence library and arranges their execution order.
[0041] The sequence generator of the source VIP obtains the sequence from the sequence library according to the instructions of the Virtual Sequencer and prepares to generate test data. The protocol driver of the source VIP converts the test data into a format that complies with the protocol specification and sends it to the data transmission module to be verified through the interface. The data transmission module receives and processes the data and then sends the processed data to the destination VIP. The protocol driver of the destination VIP receives the data from the data transmission module and passes it to the monitor or comparator for verification.
[0042] The method of this application uses the backdoor read and write functions to read data from the source VIP and the destination VIP for comparison to verify whether the function and performance of the data transmission module meet the requirements. If differences or errors are found, corresponding error reports or logs will be generated for engineers to analyze and debug.
[0043] The following will be combined with the attached Figure 3 , the verification method of the data transmission module provided in the embodiment of the present application is described in detail. Among them, the verification device of the data transmission module in the embodiment of the present application can be Figure 2 Computer equipment shown.
[0044] See also Figure 2, is a flow chart of a verification method for a data transmission module provided in an embodiment of the present application. Figure 2 As shown, the method of the embodiment of the present application may include the following steps:
[0045] S301: Calculate the data volume of the test sequence to be transmitted.
[0046] Among them, in UVM, the test sequence (Test Sequence) is responsible for generating and sending data or instructions to be verified. First of all, it is necessary to clarify the specific content of the data to be transmitted (test sequence) in the test sequence. According to the data packet size, quantity or other relevant parameters defined in the test sequence, the total data volume is calculated through the built-in function or custom function of UVM. For example, if each data packet is of a fixed size, the total data volume = data packet size * number of data packets. After the calculation is completed, the data volume can be recorded in the UVM log system, or output as part of the test report for subsequent verification and debugging
[0047] S302 , start the data transmission module, the source VIP and the destination VIP, and instruct the source VIP to send the test sequence to the destination VIP through the data transmission module.
[0048] Among them, during the construction phase of the test environment, the data transmission module (such as one or more UVM agents, representing the source and destination respectively), as well as the VIP (Verification IP) model are instantiated. Call the startup function or method of the VIP to ensure that the VIP model is in a ready state and can receive and send data. Configure the source VIP, including setting the test sequence it sends, the target address (if applicable), etc. Through the test sequence or test environment control, trigger the source VIP to start sending data. This usually involves calling the VIP's send function and passing the test sequence as a parameter.
[0049] S303. When it is detected that the test sequence transmission is completed, the first data is read in the sequence generator of the source VIP through the preset backdoor read and write function, and the second data is read in the sequence generator of the destination VIP through the preset backdoor read and write function, and the comparison function in the Virtual Sequencer is called to compare the first data with the second data.
[0050] Among them, the end of the transmission is detected by the internal state of the VIP. This can be done by checking whether a specific end signal is received or confirming that all data packets have been sent and received. The backdoor access interface provided by the VIP is used to read data directly from the sequence generators at the source and destination ends. Backdoor access usually bypasses the normal interface and protocol and directly accesses the internal state or register. In the Virtual Sequencer (or any other suitable UVM component), the comparison function is called to compare the data from the source and destination ends. The comparison function should be able to handle different types of data (such as integers, arrays, structures, etc.) and return comparison results (such as complete equality, partial match, mismatch, etc.). The comparison results are recorded in the UVM log system or test report. If the data does not match, the differences should be recorded in detail to facilitate debugging and problem location. Based on the comparison results, the UVM assertion mechanism is used to verify whether the data meets expectations. If the data does not match, the corresponding error handling mechanism should be triggered, such as recording error logs, stopping the test, or performing other recovery operations.
[0051] In some embodiments of the present application, the sequence generator of the source VIP and the sequence generator of the destination VIP are both provided with an associative array, a write data amount pointer array, a read data amount pointer array, a reference data amount pointer array, a read end flag, a write end flag, and a backdoor read and write function;
[0052] The associative array is used to store data written or read during the test;
[0053] The reference data amount pointer array is used to store the data amount of the data packet to be transmitted;
[0054] The write data amount pointer data is used to store the amount of data written into the associative array;
[0055] The read data amount pointer data is used to store the amount of data read from the associative array;
[0056] When the amount of data written in the associative array is equal to the amount of data stored in the reference data amount pointer array, the write end flag is equal to a preset value;
[0057] When the amount of data read from the associative array is equal to the amount of data stored in the reference data amount array, the read end flag is equal to a preset value;
[0058] The backdoor read / write function is used to read data from or write data to the associative array.
[0059] Among them, the associated array is used to store all the data involved in the test process, including the written data and (possibly) the read data. The associative array allows quick access to specific data items by index (such as packet address, ID, timestamp, etc.). In UVM, SystemVerilog's associative array or similar data structures can be used to implement it.
[0060] The Reference Data Size Pointer Array stores the data size information of each packet to be transmitted. This helps determine when the transmission of a packet is complete. It can be a one-dimensional array, with each element corresponding to the expected data size of a packet.
[0061] The Write Data Size Pointer Array records the amount of data actually written into the associated array. When this value reaches the corresponding value in the Reference Data Size Pointer Array, it indicates that the data packet has been completely written. Similar to the Reference Data Size Pointer Array, but used to track the actual amount of data written.
[0062] The Read Data Size Pointer Array records the amount of data read from the associative array. When this value reaches the corresponding value in the Reference Data Size Pointer Array, it indicates that the data packet has been completely read. Corresponding to the Write Data Size Pointer Array, but used to track the amount of data read.
[0063] The Write End Flag and Read End Flag indicate whether the write and read operations are completed. When the amount of data written or read reaches the reference amount, the corresponding flag is set to a preset value (such as 1), indicating that the operation is completed. It can be a Boolean variable or a bit field in a status register.
[0064] Backdoor Read / Write Functions provide the ability to bypass the normal interface and directly access the associative array to read or write data during testing. This is particularly useful for debugging and verifying internal states. These functions are usually defined in VIP or test environments to allow access to associative arrays from the outside through specific API calls.
[0065] Before the test starts, initialize all state variables and arrays, including associative arrays, pointer arrays, and flags. The source VIP generates data through the normal interface or internal mechanism, and uses the backdoor write function to write the data to the associative array. At the same time, update the write data pointer array and set the write end flag if necessary. The data is sent to the destination VIP through the data transmission module. The destination VIP reads data from the associative array through the backdoor read function and updates the read data pointer array. When the read data reaches the reference data, set the read end flag. In the test sequence or test environment, check the write end flag and the read end flag to ensure that all data packets have been correctly transmitted and received. Use the comparison function to verify whether the data in the source and destination associative arrays are consistent. Result recording: Record the verification results in the log or test report for subsequent analysis and debugging.
[0066] In some embodiments of the present application, the Virtual Sequencer plays a role in coordinating and managing multiple Sequencers in a UVM (Universal Verification Methodology) verification environment, especially in systems involving complex systems or systems with multiple communication channels.
[0067] The role of Virtual Sequencer.
[0068] Coordinating multiple sequencers: In scenarios involving multiple independent sequencers (such as multi-channel DMA or NoC), the Virtual Sequencer can serve as a central control point to coordinate the activities of these sequencers.
[0069] Simplified environment configuration: With Virtual Sequencer, you can centrally configure and start multiple sequencers, thereby simplifying the test environment configuration process.
[0070] Data Collection and Comparison: Because the Virtual Sequencer has access to the state and data of all related Sequencers, it is an ideal location for data collection, comparison, and validation.
[0071] Implementing a comparison function (such as backdoor_cmp) in the Virtual Sequencer can bring the following benefits:
[0072] Centralized processing: All data comparison logic is centralized in one place, helping to reduce code duplication and improve maintainability.
[0073] Easy to extend: As the system complexity increases, new comparison logic can be easily added or existing logic can be modified in the Virtual Sequencer without changing the implementation of individual Sequencers.
[0074] Efficient execution: Because the Virtual Sequencer is at a higher level in the test environment, it can perform data comparison operations without interfering with low-level transaction processing.
[0075] First, you need to define a Virtual Sequencer class, which inherits from uvm_sequencer. In the Virtual Sequencer, you need to add handles (pointers) to each actual Sequencer, as well as other interface or configuration information that may be required. In the Virtual Sequencer, implement the backdoor_cmp function. This function will use backdoor access technology to read the data in the simulated memory of the source and destination VIPs, and compare them as needed. In the test sequence or test environment, when the read and write operations of a channel are detected to be completed (that is, the corresponding read and write end flag is set to 1), the execution of the backdoor_cmp function is triggered through some mechanism (such as interrupt, polling or callback). The backdoor_cmp function will return the comparison result, which can be further processed in the test environment, such as recording test results, generating reports, or triggering assertions.
[0076] The embodiments of the present application specifically include the following beneficial effects:
[0077] In this technical solution, the Virtual sequence directly accesses the internal data of the sequencer of the source VIP and the destination VIP through pointers. This backdoor access mechanism greatly shortens the data path and reduces the intermediate links of data transmission. Compared with the traditional TLM (Transaction-Level Modeling) mechanism, this solution does not need to use complex transmission transactions for data transmission, thus avoiding the additional overhead and complexity that the TLM mechanism may bring.
[0078] Based on direct access to data, Virtual sequence can perform data comparison and verify the correctness of data transmission. This backdoor data comparison method not only improves verification efficiency, but also reduces the risk of errors or loss of data during transmission. At the same time, since there is no need to use Soreboard (scoreboard) for data storage and comparison, the verification environment can completely ignore the control flow initiative and structure of TLM transmission, so that the verification environment can adapt to different data transmission modules, further simplifying the setting and maintenance of the verification environment and improving the reusability of the environment.
[0079] During the verification process, this solution does not need to care whether there is a cache mechanism inside the data transmission module being verified. This feature makes the verification environment more flexible and can adapt to the verification requirements of different designs, while also reducing the verification complexity and uncertainty caused by the cache mechanism.
[0080] This solution is also very applicable to data transmission modules with multiple transmission channels (such as multi-channel DMA). Since there is no need to consider the TLM transmission mechanism and the use of backdoor access, this solution does not need to consider the problem of back-labeling / mapping the destination information back to the source information during multi-channel transmission in the prior art, so that this solution can solve the comparison and verification of transmission data from a higher level of abstraction.
[0081] This solution does not need to consider whether there is protocol conversion or transmission type conversion between the source VIP and the destination VIP. This feature allows the verification environment to focus on the correctness verification of data transmission without having to deeply understand or deal with complex protocols and type conversion logic. This not only reduces the complexity of verification, but also improves the accuracy and reliability of verification.
[0082] In the verification of data transmission, the timing problem is often a complex and difficult problem to deal with. This solution effectively simplifies the logic of timing processing through direct backdoor access and real-time data comparison. Verifiers do not need to worry about the complex timing problems of the completion time of a single transmission at the source or destination due to asynchrony and "split-reassemble-split" when transmitting between the source VIP and the destination VIP, so they can focus more on the essential verification of data transmission.
[0083] The following is an embodiment of the device of the present application, which can be used to execute the embodiment of the method of the present application. For details not disclosed in the embodiment of the device of the present application, please refer to the embodiment of the method of the present application.
[0084] See also Figure 4, which shows a schematic diagram of the structure of a verification device for a data transmission module provided by an exemplary embodiment of the present application, hereinafter referred to as device 4. The device 4 can be implemented as all or part of a computer device through software, hardware, or a combination of both. The device 4 includes: a computing unit 401, a startup unit 402, and a verification unit 403.
[0085] A calculation unit 401, used to calculate the data volume of the test sequence to be transmitted;
[0086] A starting unit 402 is used to start the data transmission module, the source VIP and the destination VIP, and instruct the source VIP to send the test sequence to the destination VIP through the data transmission module;
[0087] The verification unit 403 is used to read the first data in the sequence generator of the source VIP through a preset backdoor read-write function when it is detected that the test sequence transmission is completed, and read the second data in the sequence generator of the destination VIP through a preset backdoor read-write function, and call the comparison function in the Virtual Sequencer to compare the first data with the second data.
[0088] In one or more possible embodiments, the sequence generator of the source VIP and the sequence generator of the destination VIP are both provided with an associative array, a write data amount pointer array, a read data amount pointer array, a reference data amount pointer array, a read end flag, a write end flag, and a backdoor read and write function;
[0089] The associative array is used to store data written or read during the test;
[0090] The reference data amount pointer array is used to store the data amount of the data packet to be transmitted;
[0091] The write data amount pointer data is used to store the amount of data written into the associative array;
[0092] The read data amount pointer data is used to store the amount of data read from the associative array;
[0093] When the amount of data written in the associative array is equal to the amount of data stored in the reference data amount pointer array, the write end flag is equal to a preset value;
[0094] When the amount of data read from the associative array is equal to the amount of data stored in the reference data amount array, the read end flag is equal to a preset value;
[0095] The backdoor read / write function is used to read data from or write data to the associative array.
[0096] In one or more possible embodiments, when it is detected that the read end flag bit in the sequence generator of the source VIP or the destination VIP is equal to a preset value or the write end flag bit is equal to a preset value, it is determined that the test sequence transmission is completed.
[0097] In one or more possible embodiments, the data transmission module is a DMA or a NOC, etc.
[0098] In one or more possible embodiments, the comparison function is set in a Virtual Sequencer.
[0099] It should be noted that, when the device 4 provided in the above embodiment executes the verification method of the data transmission module, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the above functions. In addition, the verification device of the data transmission module provided in the above embodiment and the verification method embodiment of the data transmission module belong to the same concept, and the implementation process thereof is detailed in the method embodiment, which will not be repeated here.
[0100] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.
[0101] The present application also provides a computer storage medium, which can store multiple instructions, and the instructions are suitable for being loaded and executed by a processor as described above. Figure 2 The method steps of the embodiment shown in the figure can be found in the specific execution process. Figure 2 The specific description of the illustrated embodiment will not be repeated here.
[0102] The present application also provides a computer program product, which stores at least one instruction, and the at least one instruction is loaded and executed by the processor to implement the verification method of the data transmission module described in the above embodiments.
[0103] See also Figure 5 , which is a schematic diagram of the structure of a computer device according to an embodiment of the present application. Figure 5 As shown, the computer device 500 may include: at least one processor 501 , at least one network interface 504 , a user interface 503 , a memory 505 , and at least one communication bus 502 .
[0104] The communication bus 502 is used to realize the connection and communication between these components.
[0105] The user interface 503 may include a display screen (Display), and the optional user interface 503 may also include a standard wired interface and a wireless interface.
[0106] The network interface 504 may optionally include a standard wired interface or a wireless interface (such as a WI-FI interface).
[0107] Among them, the processor 501 may include one or more processing cores. The processor 501 uses various interfaces and lines to connect various parts within the entire computer device 500, and executes various functions and processes data of the computer device 500 by running or executing instructions, programs, code sets or instruction sets stored in the memory 505, and calling data stored in the memory 505. Optionally, the processor 501 can be implemented in at least one hardware form of digital signal processing (Digital Signal Processing, DSP), field programmable gate array (Field-Programmable Gate Array, FPGA), and programmable logic array (Programmable Logic Array, PLA). The processor 501 can integrate one or a combination of a central processing unit (Central Processing Unit, CPU), a graphics processing unit (Graphics Processing Unit, GPU) and a modem. Among them, the CPU mainly processes the operating system, user interface and application programs; the GPU is responsible for rendering and drawing the content to be displayed on the display screen; the modem is used to process wireless communications. It can be understood that the above-mentioned modem may not be integrated into the processor 501, and it can be implemented separately through a chip.
[0108] Among them, the memory 505 may include a random access memory (Random Access Memory, RAM) and may also include a read-only memory (Read-Only Memory). Optionally, the memory 505 includes a non-transitory computer-readable storage medium. The memory 505 can be used to store instructions, programs, codes, code sets or instruction sets. The memory 505 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playback function, an image playback function, etc.), instructions for implementing the above-mentioned various method embodiments, etc.; the data storage area may store data involved in the above-mentioned various method embodiments, etc. The memory 505 may also be optionally at least one storage device located away from the aforementioned processor 501. As Figure 5As shown, the memory 505 as a computer storage medium may include an operating system, a network communication module, a user interface module and an application program.
[0109] exist Figure 5 In the computer device 500 shown in FIG. 1 , the user interface 503 is mainly used to provide an input interface for the user and obtain the data input by the user; and the processor 501 can be used to call the application program stored in the memory 505 and specifically execute the following steps: Figure 2 The specific process can be referred to Figure 2 As shown, no further description is given here.
[0110] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. The storage medium can be a disk, an optical disk, a read-only storage memory, or a random access memory, etc.
[0111] The above disclosure is only the preferred embodiment of the present application, which certainly cannot be used to limit the scope of rights of the present application. Therefore, equivalent changes made according to the claims of the present application are still within the scope covered by the present application.
Claims
1. A method for verifying a data transmission module, characterized in that: include: Calculating the amount of data of the test sequence to be transmitted; Start the data transmission module, the source VIP and the destination VIP, and instruct the source VIP to send the test sequence to the destination VIP through the data transmission module; When it is detected that the test sequence transmission is completed, the first data is read from the sequence generator of the source VIP through the preset backdoor read-write function, and the second data is read from the sequence generator of the destination VIP through the preset backdoor read-write function, and the comparison function in the Virtual Sequencer is called to compare the first data and the second data.
2. The method according to claim 1, characterized in that The sequence generator of the source VIP and the sequence generator of the destination VIP are both provided with an associative array, a write data amount pointer array, a read data amount pointer array, a reference data amount pointer array, a read end flag, a write end flag, and a backdoor read and write function; The associative array is used to simulate storage space to store data written or read during the test; The reference data amount pointer array is used to store the data amount of the data packet to be transmitted; The write data amount pointer data is used to store the amount of data written into the associative array; The read data amount pointer data is used to store the amount of data read from the associative array; When the amount of data written in the associative array is equal to the amount of data stored in the reference data amount pointer array, the write end flag is equal to a preset value; When the amount of data read from the associative array is equal to the amount of data stored in the reference data amount array, the read end flag is equal to a preset value; The backdoor read / write function is used to read data from or write data to the associative array.
3. The method according to claim 2, characterized in that When it is detected that the read end flag bit in the sequence generator of the source end VIP or the destination end VIP is equal to a preset value or the write end flag bit is equal to a preset value, it is determined that the test sequence transmission is completed.
4. The method according to claim 1, 2 or 3, characterized in that: The data transmission module is DMA or NOC.
5. The method according to claim 1, characterized in that The comparison function is set in the Virtual Sequencer virtual sequence generator.
6. A verification device for a data transmission module, characterized in that: include: A calculation unit, used for calculating the data volume of the test sequence to be transmitted; A starting unit, used to start the data transmission module, the source VIP and the destination VIP, and to instruct the source VIP to send the test sequence to the destination VIP through the data transmission module; A verification unit is used to read the first data in the sequence generator of the source VIP through a preset backdoor read-write function when detecting that the test sequence transmission is completed, and to read the second data in the sequence generator of the destination VIP through a preset backdoor read-write function, and to call a comparison function in a Virtual Sequencer to compare the first data with the second data.
7. A computer storage medium, characterized in that: The computer storage medium stores a plurality of instructions, and the instructions are suitable for being loaded by a processor and executing the method steps according to any one of claims 1 to 7.
8. A computer device, characterized in that: include: A processor and a memory; wherein the memory stores a computer program, and the computer program is suitable for being loaded by the processor and executing the method steps as claimed in any one of claims 1 to 7.