Simulation waveform capturing method, device and equipment and storage medium
By setting preset script files in the verification platform, the run time is automatically obtained, and the problem of inability to accurately capture the simulated waveforms is solved, and more accurate debugging and positioning is achieved.
Patent Information
- Application Number
- CN202411487900.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-23
- Publication Date
- 2025-02-14
AI Technical Summary
During the verification process of the platform simulation SoC, it is impossible to accurately determine the exact time required for the triggering condition, resulting in the inability to accurately capture the simulation waveform.
By setting a preset script file, including trigger conditions and crawling parameters, the verification platform can automatically obtain the first run time and the second run time to accurately capture the simulation waveform.
It realizes that the simulation waveform is started to be captured before the trigger condition is met, and more information related to the trigger condition is obtained, so as to more accurately locate the reasons affecting the trigger condition and perform precise debugging of the SoC.
Smart Images
Figure CN119442984A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of chip technology, and in particular to a method, device, equipment and storage medium for capturing simulation waveforms. Background Art
[0002] Due to the increasing complexity of large-scale integrated circuit design, simulation speed has become a major obstacle to verification progress. In addition, due to the limitation of simulation speed, some actual use cases cannot quickly display results in RTL (Register Transfer Level) level simulation, so the verification platform based on FPGA (Field Programmable Gate Array) solution came into being. The main purpose of emulating and debugging chips is to simulate the operation of the chip in a software or hardware environment so as to verify and debug the functions and performance of the system without the need for actual hardware. This helps to discover and solve potential problems in the early stages of development, reducing development costs and time.
[0003] However, when the verification platform simulates the operation of SoC (System on Chip) and performs debugging of SoC, the verification platform cannot determine the exact time required to run until the trigger condition is met, and thus cannot accurately capture the simulation waveform. Summary of the invention
[0004] The embodiment of the present application provides a method, device, equipment and storage medium for capturing simulation waveforms, which can determine the exact time when the verification platform runs to meet the trigger condition, and then accurately capture the simulation waveform. The technical solution is as follows:
[0005] According to a first aspect of an embodiment of the present application, a method for capturing a simulation waveform is provided, the method comprising:
[0006] Obtain a preset script file; the preset script file indicates the process of the verification platform simulating the SoC; the preset script file includes a trigger condition and a capture parameter; the capture parameter includes a first duration and a second duration; the first duration indicates the duration of capturing the simulation waveform; the second duration indicates the duration before the verification platform runs to meet the trigger condition; the simulation waveform is generated during the process of the verification platform simulating the SoC; the trigger condition indicates that the process of the verification platform simulating the SoC reaches a preset state; the first duration is greater than the second duration;
[0007] Acquire a first running time; the first running time is the time during which the verification platform runs until the trigger condition is met;
[0008] Obtain a second running time; the second running time is the time from when the verification platform runs to when the simulation waveform starts to be captured; the second running time is determined based on the second time and the first running time;
[0009] Acquire a target waveform; the target waveform is obtained by capturing the simulation waveform for the first duration after the verification platform has run for the second running duration.
[0010] In a possible implementation, the method further includes: the verification platform runs a clock test parameter to test a clock; the clock instructs the verification platform to simulate the process of the SoC;
[0011] The verification platform runs a reset parameter to reset the verification platform, and the clock test parameter indicates a clock test process; the reset parameter indicates the reset of the verification platform;
[0012] Wherein, the clock test parameter and the reset parameter are set in the preset script file.
[0013] In a possible implementation, the trigger condition includes a trigger signal and a trigger value; the trigger signal is equal to the trigger value; and the trigger signal indicates a preset register of the SoC.
[0014] In a possible implementation, obtaining the first running time includes:
[0015] The verification platform runs a first enabling parameter to simulate the SoC;
[0016] The verification platform runs for the time duration until the trigger condition is satisfied as the first running time duration;
[0017] Wherein, the first enabling parameter is set in the preset script file.
[0018] In a possible implementation, obtaining the second running time includes:
[0019] The verification platform automatically writes the first running time into the preset script file;
[0020] The verification platform calculates the difference between the first running time and the second running time to obtain the second running time;
[0021] The verification platform writes the second running time into the preset script file to obtain an updated script file.
[0022] In a possible implementation, the method further includes: the verification platform runs a second enabling parameter to simulate the SoC running the second running time; and the second enabling parameter is set in the update script file.
[0023] In a possible implementation, the method further includes: the verification platform runs a judgment parameter to determine whether the clock is stopped;
[0024] Wherein, when the verification platform determines that the clock stops, the simulation of the SoC is stopped;
[0025] Or when the verification platform determines that the clock is not stopped, the SoC is continuously simulated.
[0026] In a possible implementation, the acquiring the target waveform includes:
[0027] The verification platform runs the startup parameters to start the crawler; the startup parameters are set in the update script file;
[0028] After running for the second running time, the verification platform starts to capture the simulation waveform based on the capture tool and continues to capture the first time to obtain the target waveform.
[0029] In a possible implementation, the method further includes:
[0030] The verification platform runs a shutdown parameter to close the crawler; the shutdown parameter is set in the update script file.
[0031] In a possible implementation, the verification platform is a Zebu verification platform.
[0032] According to a second aspect of an embodiment of the present application, a device for capturing a simulation waveform is provided, the device comprising:
[0033] A first acquisition module is used to acquire a preset script file; the preset script file indicates the process of the verification platform simulating the SoC; the preset script file includes a trigger condition and a capture parameter; the capture parameter includes a first duration and a second duration; the first duration indicates the duration of capturing the simulation waveform; the second duration indicates the duration before the verification platform runs to meet the trigger condition; the simulation waveform is generated during the process of the verification platform simulating the SoC; the trigger condition indicates that the process of the verification platform simulating the SoC reaches a preset state;
[0034] A second acquisition module is used to acquire a first running time; the first running time is the time during which the verification platform runs until the trigger condition is met;
[0035] A third acquisition module is used to acquire a second running time; the second running time is the time from when the verification platform runs to when the simulation waveform starts to be captured; the second running time is determined based on the second time and the first running time;
[0036] The fourth acquisition module is used to acquire a target waveform; the target waveform is obtained by capturing the simulation waveform for the first duration after the verification platform has run for the second running duration.
[0037] According to a third aspect of an embodiment of the present application, a computer device is provided, characterized in that the computer device includes a processor and a memory, the memory is used to store at least one program, and the at least one program is loaded by the processor and executes the method for capturing simulation waveforms as described above.
[0038] According to a fourth aspect of an embodiment of the present application, a computer-readable storage medium is provided, in which at least one program is stored. The at least one program is loaded and executed by a processor to implement the method for capturing a simulation waveform as described above.
[0039] In an embodiment of the present application, an embodiment of the present application provides a method for capturing simulation waveforms, a preset script including a trigger condition and a capture parameter is set, and a verification platform runs the preset script. When the verification platform runs to meet the trigger condition, the verification platform automatically obtains the first running time. The verification platform obtains the second running time based on the first running time and the second running time. The second running time indicates the time when the verification platform starts to capture the simulation waveform. In the above technical solution, the verification platform determines the exact time when the trigger condition takes effect through the first running time. In addition, through the second running time, the verification platform starts to capture the simulation waveform before running to meet the trigger condition. In this way, not only the simulation waveform after the trigger condition occurs can be captured, but also the simulation waveform before the trigger condition occurs can be captured, so that more information related to the trigger condition can be obtained, and then the cause affecting the occurrence of the trigger condition can be more accurately located, and the SoC can be accurately debugged. BRIEF DESCRIPTION OF THE DRAWINGS
[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0041] Figure 1 is a schematic diagram of an implementation environment provided according to an embodiment of the present application;
[0042] Figure 2 A flowchart of using a GUI operation verification platform in the related art;
[0043] Figure 3 It is a flowchart of a method for capturing a simulation waveform provided in an embodiment of the present application;
[0044] Figure 4 is a flow chart of step 302 provided according to an embodiment of the present application;
[0045] Figure 5 is a flow chart of step 303 provided according to an embodiment of the present application;
[0046] Figure 6 is a flow chart of step 304 provided according to an embodiment of the present application;
[0047] Figure 7 It is a structural schematic diagram of a device for capturing simulation waveforms provided according to an embodiment of the present application;
[0048] Figure 8 is a schematic diagram of the structure of a terminal provided according to an embodiment of the present application;
[0049] Fig. 9 It is a structural diagram of a server provided according to an embodiment of the present application. DETAILED DESCRIPTION
[0050] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.
[0051] Here, exemplary embodiments will be described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.
[0052] In this application, the terms "first", "second", etc. are used to distinguish between identical or similar items with substantially the same effects and functions. It should be understood that there is no logical or temporal dependency between "first", "second", and "nth", nor is there a limitation on the quantity and execution order. It should also be understood that although the following description uses the terms first, second, etc. to describe various elements, these elements should not be limited by the terms.
[0053] These terms are only used to distinguish one element from another element. For example, without departing from the scope of various examples, a first action can be referred to as a second action, and similarly, a second action can also be referred to as a first action. Both the first action and the second action can be actions, and in some cases, can be separate and different actions.
[0054] Here, at least one means one or more than one, for example, at least one action can be one action, two actions, three actions, or any other action that is an integer greater than or equal to one. And multiple means two or more than two, for example, multiple actions can be two actions, three actions, or any other action that is an integer greater than or equal to two.
[0055] Figure 1 It is a schematic diagram of an implementation environment provided according to an embodiment of the present application, and the implementation environment may include a terminal 101 and a server 102.
[0056] In the terminal 101, a Zebu verification platform is provided; the Zebu verification platform is a high-performance hardware-assisted verification (HAV) platform. The Zebu verification platform is mainly used to accelerate the verification of large-scale digital systems. It provides performance improvements of several orders of magnitude higher than traditional software simulation by running design prototypes on specialized hardware, thereby significantly shortening the verification cycle. Specifically, ZeBu achieves rapid verification by running the design prototype of SoC on FPGA (Field-Programmable Gate Array). This method enables the hardware to execute instructions much faster than software simulation, thereby greatly improving the verification speed.
[0057] The terminal 101 may be a smart phone with a Zebu authentication platform, a wearable device, a personal computer, a laptop, a tablet computer, a smart TV, a car terminal, etc.
[0058] The server 102 may be a single server, a server cluster consisting of multiple servers, or a cloud processing center.
[0059] The terminal 101 is connected to the server 102 via a wired or wireless network.
[0060] In some embodiments, the wireless network or wired network uses standard communication technology and / or protocol. The network is usually the Internet, but it can also be any network, including but not limited to any combination of local area network (LAN), metropolitan area network (MAN), wide area network (WAN), mobile, wired or wireless network, private network or virtual private network. In some embodiments, the data exchanged through the network is represented by technology and / or format including HyperText Mark-up Language (HTML), Extensible Markup Language (XML), etc. In addition, conventional encryption technologies such as Secure Socket Layer (SSL), Transport Layer Security (TLS), Virtual Private Network (VPN), Internet Protocol Security (IPsec) can also be used to encrypt all or some links. In other embodiments, customized and / or dedicated data communication technology can also be used to replace or supplement the above data communication technology.
[0061] At present, due to the increasing complexity of large-scale integrated circuit design, simulation speed has become a major obstacle to verification progress. In addition, due to the limitation of simulation speed, some actual use cases cannot quickly display results in RTL (Register Transfer Level) level simulation, so the verification platform based on FPGA (Field Programmable Gate Array) solution has emerged.
[0062] In the related art, a GUI (Graphical User Interface) operation method is used in the process of simulating the operation of the SoC and executing debug using a verification platform.
[0063] Figure 2 A flowchart of using a GUI operation verification platform in the related art;
[0064] Combine the following Figure 2 , an exemplary description is given of using GUI to operate the verification platform.
[0065] In step 201, the verification platform sets debug-related trigger signals and trigger values according to specific requirements.
[0066] In step 202, the verification platform simulates the SoC environment. After the verification platform starts simulating, it waits for the trigger value to take effect.
[0067] In step 203, the verification platform pauses the simulation of the SoC after being triggered, and starts the function of capturing the simulation waveform.
[0068] In step 204, the verification platform sets the duration of the simulation waveform capture, continues to simulate the SoC, and waits for the simulation waveform capture process to end.
[0069] Among them, simulation waveform is an indispensable part of the hardware design and verification process. It is used to show the signal changes after hardware description language (HDL) simulation. In hardware design and verification, simulation waveforms are usually generated by simulation tools. These simulation tools read HDL code, simulate the operation of hardware circuits, and record the signal changes in the form of simulation waveforms, so as to locate problems based on simulation waveforms and realize SoC debugging.
[0070] However, using GUI to complete debugging work has the following disadvantages:
[0071] The first disadvantage is that when setting the relevant trigger signal and trigger value, the time of the trigger signal is not known in advance, so it is not known when the trigger signal is most suitable to take effect. That is, during the first simulation of the verification platform, the exact time when the SOC system is running at the trigger moment cannot be known. That is, the trigger signal and trigger value are set blindly.
[0072] The second disadvantage is that since the trigger signal and trigger value are set blindly, when the trigger signal takes effect, part of the simulation waveform captured is not actually needed.
[0073] The third disadvantage: Since the waveform capture task can only be started after the trigger, the waveform information before the trigger cannot be obtained. Therefore, the operating status of the SoC before the trigger cannot be determined, which is not conducive to determining the cause of the trigger.
[0074] The fourth disadvantage: After each step of the entire process is completed, engineers need to perform manual operations before proceeding to the next step, which is time-consuming and cumbersome.
[0075] Figure 3 is a flow chart of a method for capturing a simulation waveform provided in an embodiment of the present application; Figure 3 As shown, in the embodiment of the present application, the application is described by taking the application on a terminal with a Zebu verification platform as an example. The method comprises the following steps:
[0076] In step 301, the terminal obtains a preset script file.
[0077] The preset script file is used to instruct the verification platform how to simulate the SoC and capture the simulation waveform.
[0078] In some embodiments, before step 301, an initial script file is obtained, and information such as trigger conditions and capture parameters are written into the initial script file to obtain a preset script file.
[0079] In some embodiments, a verification platform is selected according to actual needs. For example, the verification platform is the Zebu verification platform. The Zebu verification platform can carry out verification for SoC design, and can also quickly develop and verify software on the SoC. The compilation efficiency of the Zebu verification platform is quite high, and users can achieve rapid iteration. In addition, it also has a powerful error location capability, which can assist users to quickly locate hardware and software problems. The preset script file is a tcl (tool command language) / tk (tcl toolkit) script file. Among them, tcl is a simple scripting language used to provide scalability, a short learning curve and easy embedding features. Tcl is used in rapid prototyping, script programming and testing.
[0080] In the related art, registers are a crucial part in the process of simulating and debugging SoCs. They are used to store and control the status and behavior of various hardware components in SoCs. Optionally, registers can store various types of data, such as status information, configuration parameters, etc. Registers can also participate in data processing operations, such as arithmetic operations, logical operations, etc.
[0081] It is important to understand that register debugging is one of the key steps to ensure the functional correctness and stability of the SoC. By reading and writing registers, you can verify that the hardware components in the SoC are working as expected. For example, write specific data to the control register and then read the status register to check whether the hardware component has responded correctly. When the SoC fails, the register status can provide important clues. By detecting the value of the register, you can determine the cause and location of the failure. Understanding the status and behavior of the register helps optimize the performance of the SoC. For example, you can optimize the operating mode of the peripheral by adjusting the value of the control register, thereby improving the overall performance.
[0082] The embodiment of the present application takes the Zebu verification platform as an example to exemplify the method of capturing waveforms.
[0083] In some embodiments, the preset script file instructs the verification platform to simulate the process of the SoC; the preset script file includes trigger conditions and capture parameters.
[0084] In one example, the trigger condition includes a trigger signal and a trigger value; the trigger signal is equal to the trigger value; the trigger signal indicates a preset register of the SoC. Optionally, the trigger signal indicates any preset register of the SoC.
[0085] In some embodiments, the Zebu verification platform capture parameters include a first duration and a second duration; the first duration indicates the duration of capturing the simulation waveform.
[0086] The first duration includes multiple clock cycles; the second duration includes multiple clock cycles.
[0087] In one example, the Zebu verification platform uses a certain state of various hardware components in the SoC as a preset state and uses the data stored in a register in the preset state as a trigger value. That is, when the trigger signal is equal to the trigger value, it indicates that the various hardware components in the SoC are in the preset state, and the simulation waveform before and after the preset state are captured, so as to analyze the factors affecting the preset state by analyzing the simulation waveform before and after, thereby debugging the SoC. For example: the preset state is that the various hardware components in the SoC are executing a preset function or algorithm, etc.
[0088] In some embodiments, the second duration indicates the length of time before the verification platform runs to meet the trigger condition; the simulation waveform is generated during the process of the Zebu verification platform simulating the SoC; the trigger condition indicates that the process of the Zebu verification platform simulating the SoC reaches a preset state; the first duration is greater than the second duration.
[0089] In some embodiments, the Zebu verification platform runs clock test parameters to test the clock; the clock indicates the process of the verification platform simulating the SoC; the verification platform runs reset parameters to reset the verification platform, and the clock test parameters indicate the test process of the clock; the reset parameters indicate the reset of the verification platform; wherein, the clock test parameters and reset parameters are set in a preset script file.
[0090] In some embodiments, after step 301, the process further includes: initializing the Zebu verification platform, wherein initializing the Zebu verification platform may include clock testing and resetting the Zebu verification platform.
[0091] In one example, the Zebu verification platform runs a clock test parameter of a preset script file, and the clock test parameter instructs the Zebu verification platform to run several clock cycles to determine whether the clock is normal. Optionally, when a clock error signal of the Zebu verification platform is received, the clock is abnormal; or when a clock error signal of the Zebu verification platform is not received, the clock is normal.
[0092] It is understandable that the specific value of the clock cycle can be set according to actual needs.
[0093] For example: the clock test parameter is ZEBU_Clock_enable zebu_top. <clk>x, the clock test parameter instructs the Zebu verification platform to run x clock cycles. x is an integer greater than or equal to 1.
[0094] In some embodiments, if the clock is normal, the Zebu verification platform continues to run the reset parameters, releases the reset signal, and the Zebu verification platform resets based on the reset signal. Then, the Zebu verification platform starts to simulate the SoC. During the process of the Zebu verification platform simulating the SoC, the clock is used to control the timing of the process of the Zebu verification platform simulating the SoC.
[0095] In one example, before simulating the SoC, the Zebu verification platform obtains the code file of the SoC and simulates the SoC by running the code file.
[0096] It should be noted that the code file of SoC can be directly obtained from the relevant technology, and the embodiments of this application will not be described in detail.
[0097] For example: the reset parameter is ZEBU_Signal_force zebu_top. <rst>1% h.
[0098] Through the analysis of step 301, it can be known that the embodiment of the present application writes the trigger condition, the first duration and the second duration in the preset script file. Among them, when the Zebu verification platform detects that the process of simulating the SoC by the Zebu verification platform has reached the preset state, that is, the value of the preset register is equal to the trigger value, the operation of the Zebu verification platform meets the trigger condition. The Zebu verification platform determines the duration of capturing the simulation waveform through the first duration. The Zebu verification platform can capture the simulation waveform before the trigger condition is met through the second duration. That is, the embodiment of the present application, the Zebu verification platform, runs to a period of time (second duration) before the trigger condition is met and starts to capture the simulation waveform. Compared with the related art, which can only capture the simulation waveform when the trigger condition is met, and thus can only obtain the information of the operation of the simulation SoCd after the trigger condition is met, the embodiment of the present application can obtain more relevant information that affects the satisfaction of the trigger condition, and thus can debug the SoC more accurately.
[0099] In addition, by writing the trigger condition, the first duration and the second duration in the preset script file, the Zebu verification platform can automatically record the first running time that runs to meet the trigger condition after startup. Then, according to the first running time, the first duration and the second duration, it automatically starts to capture the simulation waveform, and after continuously capturing the simulation waveform of the first duration, it automatically stops capturing the simulation waveform. Therefore, the embodiment of the present application solves the problem of using a GUI to operate the Zebu verification platform in the related art through a preset script file, and each step of the whole process requires manual operation by an engineer before continuing to execute the next step, which is time-consuming and cumbersome.
[0100] In step 302, the terminal obtains a first operating time; the first operating time is the time it takes for the verification platform to run until a trigger condition is met.
[0101] The first running time is the time taken by the Zebu verification platform from the start of SoC simulation to the satisfaction of the trigger condition.
[0102] Figure 4 It is a flowchart of step 302 provided according to an embodiment of the present application.
[0103] Combine the following Figure 4 Step 302 is exemplarily described.
[0104] In some embodiments, the above step 302 includes the following steps 3021 and 3022:
[0105] In step 3021: the Zebu verification platform runs the first enabling parameter to simulate the SoC.
[0106] In step 3022: the Zebu verification platform takes the time required to run until the trigger condition is met as the first running time; wherein the first enabling parameter is set in a preset script file.
[0107] In one example, when the Zebu verification platform detects that the trigger signal is equal to the trigger value based on the detection parameters in the preset script file, the trigger condition is met. At this time, the Zebu verification platform records the time it takes to run until the trigger condition is met, and the time is the first running time. Optionally, the Zebu verification platform automatically records the first running time.
[0108] In one example, after the Zebu verification platform starts simulating the SoC, the Zebu verification platform runs the first enabling parameter, continuously enables the clock, and continuously simulates the SoC based on the clock. Optionally, when the Zebu verification platform simulation detects that the SoC has reached a preset state. That is, when the Zebu verification platform detects that the trigger signal is equal to the trigger value, the Zebu verification platform automatically records the first running time. Optionally, the Zebu verification platform detects the state and behavior of the registers in the simulation environment by running the detection parameters in the preset script file. When the Zebu verification platform detects that the trigger signal is equal to the trigger value, the Zebu verification platform automatically records the length of time the verification platform runs to the trigger condition. That is, the Zebu verification platform obtains the first running time. Optionally, when the Zebu verification platform detects that the trigger signal is equal to the trigger value, the clock is on the rising edge. That is, the rising edge of the clock is used as the trigger clock.
[0109] For example: the first enable parameter is ZEBU_Clock_enable zebu_top. <clk>forever.
[0110] For example: T2 represents the first duration. For example: The trigger signal is:
[0111] ZEBU_Trigger_setExprtrig"zebu_top.<tri_sig> ==$ <value>",Will<tri_sig> .
[0112] in,<tri_sig> Indicates preset triggers; <value>Indicates the trigger value. The trigger value is 0 or 1.
[0113] Since the exact time when the trigger condition is met cannot be determined in the related art, the duration of capturing the simulation waveform is set very long in the related art to avoid missing relevant information. However, both capturing the simulation waveform and converting the format are very time-consuming. Therefore, capturing more simulation waveforms will result in a long capture time, which greatly affects the operation of the Zebu verification platform and reduces the simulation speed. Moreover, more simulation waveforms will also result in a long format conversion time.
[0114] In the embodiment of the present application, since the trigger condition is set in the preset script file, when the Zebu verification platform simulates the SoC for the first time, the time from the start of the Zebu verification platform to the satisfaction of the trigger condition is used as the first running time, and the first running time is automatically written into the preset script file, and then the simulation waveform is captured according to the first time, and the first time is much shorter than the time for capturing the simulation waveform in the related art. Optionally, the preset script file also includes a recording parameter, which instructs the Zebu verification platform to automatically write the first running time.
[0115] Through the analysis of step 302, it can be known that, since the trigger condition is set in the preset script file, when the Zebu verification platform detects that the process of simulating the SoC by the Zebu verification platform reaches the preset state during the first simulation of the SoC, that is, the data stored in the preset register is equal to the trigger value, the operation of the Zebu verification platform satisfies the trigger condition, and the Zebu verification platform automatically records the time from the start of the operation of the Zebu verification platform to the satisfaction of the trigger condition. That is, in the embodiment of the present application, when the Zebu verification platform simulates the SoC for the first time, the exact time when the Zebu verification platform runs to the satisfaction of the trigger condition can be obtained, thereby solving the problem in the related art that the exact time when the trigger condition is satisfied cannot be determined when the SoC is simulated for the first time. And because the first time length is much shorter than the time length of capturing the simulation waveform in the related art, therefore, the embodiment of the present application greatly shortens the time length of capturing the simulation waveform and the time length of converting the format of the simulation waveform, thereby greatly improving the simulation speed, and then greatly improving the simulation efficiency.
[0116] In step 303, the terminal obtains the second running time.
[0117] In some embodiments, the second running time is the time from when the verification platform runs to when the simulation waveform is captured; the second running time is determined based on the second time and the first running time. The sum of the second running time and the first time is greater than the first running time.
[0118] Figure 5 It is a flowchart of step 303 provided according to an embodiment of the present application.
[0119] Combine the following Figure 5 Step 303 is exemplarily described.
[0120] In some embodiments, the above step 303 includes the following steps 3031 to 3033:
[0121] In step 3031, the Zebu verification platform automatically writes the first running time into a preset script file.
[0122] In step 3032, the Zebu verification platform calculates the difference between the first running time and the second running time to obtain the second running time.
[0123] In step 3033, the Zebu verification platform writes the second running time into the preset script file to obtain an updated script file.
[0124] In one example, the second running time=the first running time-the second time.
[0125] In the above embodiment, after the Zebu verification platform simulates the SoC for the first time, it obtains the first running time, automatically writes the first running time into a preset script file, runs the calculation parameter, calculates the difference between the first running time and the second running time, obtains the second running time, writes the second running time into the preset script file, and obtains an updated script file. The calculation parameter is set in the preset script file.
[0126] For example, T1 is used to represent the second operation time, T3 is used to represent the second operation time, and T4 is used to represent the second operation time, that is, T4 = T1 - T3.
[0127] In some embodiments, the Zebu verification platform runs a second enabling parameter and simulates the SoC running for a second running time; the second enabling parameter is set in the update script file.
[0128] For example: the second enable parameter is ZEBU_Clock_enable zebu_top. <clk>T1-T3.
[0129] In step 304, the terminal obtains a target waveform; the target waveform is obtained by capturing a simulation waveform for a first duration after the verification platform has run for a second duration.
[0130] In some embodiments, after the first running time is determined, the simulation waveform is not captured starting from the moment corresponding to the first running time. Instead, based on actual needs, a first running time that is more conducive to debugging is determined to avoid capturing unnecessary simulation waveforms. Simulation waveforms that need to be captured but cannot be captured in related technologies are also captured. Compared with related technologies, not only the time for capturing simulation waveforms is greatly shortened, but also the time for format conversion of simulation waveforms is greatly shortened, thereby improving the simulation speed and debugging accuracy.
[0131] For example: after determining the first running time, the simulation waveform is not captured from the moment corresponding to the first running time, but the time to start capturing the simulation waveform is set to a certain moment before T1, that is, the moment corresponding to after the Zebu verification platform runs the second running time (T4). Therefore, in the embodiment of the present application, the time to capture the simulation waveform is a period of time earlier than the time when the trigger condition is met. Therefore, the embodiment of the present application not only captures the simulation waveform after the trigger condition is met, but also captures the simulation waveform before the trigger condition is met.
[0132] Since the reasons that affect the trigger conditions may not only occur at the moment when the trigger conditions are met or after the trigger conditions are met, it is also possible that the reasons have already occurred at a certain period of time before the trigger conditions are met. Therefore, by capturing the simulation waveform before the trigger conditions are met, more information can be obtained, so that the reasons can be located more accurately, and the SoC can be better debugged. For example: During the period (T3) between the moment corresponding to T4 and the moment corresponding to T1, the Zebu verification platform continues to simulate the SoC. Therefore, between the moment corresponding to T4 and the moment corresponding to T1, the Zebu verification platform continues to generate simulation waveforms. By analyzing the simulation waveforms generated between the moment corresponding to T4 and the moment corresponding to T1, more factors that affect the satisfaction of the trigger conditions can be obtained, so that the factors that affect the operation of the SoC to the preset state can be located more accurately, and the SoC can be better debugged.
[0133] Figure 6 It is a flowchart of step 304 provided according to an embodiment of the present application.
[0134] Combine the following Figure 6 Step 304 is exemplarily described.
[0135] In some embodiments, the above step 304 includes the following steps:
[0136] In step 3041, the Zebu verification platform runs the startup parameters and starts the crawler. The startup parameters are set in the update script file.
[0137] In step 3042, after running for the second running time, the Zebu verification platform starts to capture the simulation waveform based on the capture tool, and continues to capture for the first time period to obtain the target waveform.
[0138] In some embodiments, the Zebu verification platform runs the update script file and simulates the SoC a second time.
[0139] In one example, the zebu verification platform is also provided with a capture tool, and the zebu verification platform runs the startup parameters to automatically start the capture tool. Optionally, after the zebu verification platform starts the capture tool, the capture tool is automatically initialized, the simulation waveform is captured based on the capture signal list, and the captured simulation waveform is stored in a folder under a preset directory. Among them, the capture signal list indicates the type of the captured simulation waveform; the startup parameters are set in the update script file.
[0140] In one example, during the process of continuously capturing the first duration, the zebu verification platform runs the third enabling parameter and continuously simulates the SoC for the first duration. The third enabling parameter is set in the update script file. For example: the captured signal list indicates to capture all types of simulation waveforms. The types of simulation waveforms include sine waves, square waves, triangle waves, trapezoidal waves, and sawtooth waves. For example: the startup parameter is while{[ZEBU_getStatus]=="open". For example: the relevant parameters for automatically initializing the capture tool, setting the capture signal list, and creating a folder under the preset directory are:
[0141] ZEBU_Fwc_isDefined, ZEBU_Fwc_init, ZEBU_Fwc_addValueSet<QIWC_TOP> , ZEBU_Fwc_setOutputDir. / fwc.ztdb, ZEBU_Fwc_dumpOnOff "on". in,<QIWC_TOP> Indicates the capture signal list. fwc.ztdb indicates the folder. For example: the third enable parameter is: ZEBU_Clock_enable zebu_top. <clk>T2.
[0142] In some embodiments, the verification platform runs a shutdown parameter to close the crawler; the shutdown parameter is set in the update script file. For example, the shutdown parameter is: ZEBU_Fwc_dumpOnOff "off", ZEBU_Fwc_flush, ZEBU_Fwc_close.
[0143] In some embodiments, the verification platform runs a judgment parameter to determine whether the clock has stopped; wherein, when it is determined that the clock has stopped, the verification platform stops simulating the SoC; or when it is determined that the clock has not stopped, the verification platform continues to simulate the SoC.
[0144] In the first example, when the Zebu verification platform detects that the trigger signal is equal to the trigger value, the judgment parameter is run. If the Zebu verification platform determines that the clock is stopped based on the judgment parameter, it is determined that the trigger condition has been triggered, that is, the trigger condition has taken effect. Or if the Zebu verification platform determines that the clock is not stopped based on the judgment parameter, it is determined that the trigger condition has not been triggered. For example: the judgment parameter is: while{[ZEBU_getStatus]=="open"&&[ZEBU_Clock_getStatus zebu_top. <clk>]=="running"}Judgement <clk>Status. <clk>=="running" is true, it means the clock is running, that is, the Zebu verification platform is simulating the SoC at this time; when <clk>=="running" is not true, it means that the clock stops running, that is, the Zebu verification platform stops simulating the SoC at this time.
[0145] In the second example, after the Zebu verification platform has run for the second running time, the judgment parameter is run again. If the Zebu verification platform determines that the clock is stopped based on the judgment parameter, it is determined that the Zebu verification platform has run for the second running time and the simulation waveform can be captured. Or if the Zebu verification platform determines that the clock is not stopped based on the judgment parameter, it is determined that the Zebu verification platform has not run for the second running time.
[0146] In the third example, after the capture tool has run for the first time, the Zebu verification platform runs the judgment parameter again. If the Zebu verification platform determines that the clock has stopped based on the judgment parameter, it is determined that the capture tool has run for the first time, and the simulation waveform can be stopped at this time. Or if the Zebu verification platform determines that the clock has not stopped based on the judgment parameter, it is determined that the capture tool has not run for the first time.
[0147] In some embodiments, after the Zebu verification platform closes the crawler, it runs an exit parameter to stop simulating the SoC. The exit parameter is set in the update script file. For example, the exit parameter is: ZEBU_close.
[0148] In some embodiments, after obtaining the target waveform, the Zebu verification platform runs the waveform conversion parameters and opens the waveform conversion tool of the Zebu verification platform. The Zebu verification platform uses the waveform conversion tool to convert the target waveform, obtains the converted waveform, and outputs the converted waveform. Optionally, the Zebu verification platform stops running after outputting the converted waveform. Optionally, the waveform conversion parameters are set in the update script file. For example: the waveform conversion parameters are zSimzilla. The format of the target waveform is ztdb; the format of the converted waveform is zwd. The format of the converted waveform is a format that can be recognized by the preset recognition tool.
[0149] In some embodiments, the conversion waveform is output to a preset recognition tool. The preset recognition tool opens the conversion waveform and performs debugging analysis based on the conversion waveform. For example, the preset recognition tool is verdi (verdi Advanced Debug Solution). verdi is mainly used for hardware description language (HDL) simulation waveform viewing and debugging, and supports multiple simulators and simulation waveform formats. It provides rich debugging functions, such as signal search, waveform zoom, signal grouping, custom signal, base and symbol settings, etc.
[0150] In an embodiment of the present application, a preset script including a trigger condition and capture parameters is set, and the verification platform runs the preset script. When the verification platform runs to meet the trigger condition, the verification platform automatically obtains the first running time. The verification platform obtains the second running time based on the first running time and the second running time. The second running time indicates the time when the verification platform starts to capture the simulation waveform. In the above technical solution, the verification platform determines the exact time when the trigger condition takes effect through the first running time. In addition, through the second running time, the verification platform starts to capture the simulation waveform before running to meet the trigger condition. In this way, not only the simulation waveform after the trigger condition occurs can be captured, but also the simulation waveform before the trigger condition occurs can be captured, so that more information related to the trigger condition can be obtained, and then the cause that affects the occurrence of the trigger condition can be more accurately located, and the SoC can be accurately debugged.
[0151] Figure 7 1 is a schematic diagram of a structure of a device for capturing a simulation waveform according to an embodiment of the present application, the device is used for:
[0152] The first acquisition module 701 is used to acquire a preset script file; the preset script file indicates the process of simulating SoC by the verification platform; the preset script file is used for trigger conditions and capture parameters; the capture parameters are used for the first duration and the second duration; the first duration indicates the duration of capturing the simulation waveform; the second duration indicates the duration before the verification platform runs to meet the trigger condition; the simulation waveform is generated during the process of simulating SoC by the verification platform; the trigger condition indicates that the process of simulating SoC by the verification platform reaches a preset state; the first duration is greater than the second duration;
[0153] The second acquisition module 702 is used to acquire a first running time; the first running time is the time it takes for the verification platform to run until the trigger condition is met;
[0154] The third acquisition module 703 is used to obtain the second running time; the second running time is the time from when the verification platform runs to when the simulation waveform is captured; the second running time is determined based on the second time and the first running time; the sum of the second running time and the first time is greater than the first running time.
[0155] The fourth acquisition module 704 is used to acquire a target waveform; the target waveform is obtained by capturing a simulation waveform after the verification platform has run for a second running time and continues for a first time period.
[0156] In some embodiments, the apparatus is further used to: verify the platform operation clock test parameters, test the clock; the clock indicates the process of verifying the platform simulation SoC;
[0157] The verification platform runs the reset parameter, resets the verification platform, and the clock test parameter indicates the clock test process; the reset parameter indicates the reset of the verification platform;
[0158] Among them, the clock test parameters and reset parameters are set in the preset script file.
[0159] In some embodiments, the trigger condition is for a trigger signal and a trigger value; the trigger signal is equal to the trigger value; and the trigger signal indicates a preset register of the SoC.
[0160] In some embodiments, the apparatus is further configured to:
[0161] The verification platform runs the first enabling parameter and simulates the SoC;
[0162] The verification platform will run until the trigger condition is met as the first running time;
[0163] Among them, the first enabling parameter is set in a preset script file.
[0164] In a possible implementation, the device is further configured to:
[0165] The verification platform automatically writes the first running time into a preset script file;
[0166] The verification platform calculates the difference between the first running time and the second running time to obtain the second running time; the verification platform writes the second running time into a preset script file to obtain an updated script file.
[0167] In a possible implementation, the device is further used to: verify that the platform runs a second enabling parameter and simulate that the SoC runs a second running time; the second enabling parameter is set in the update script file.
[0168] In a possible implementation, the device is further used to: verify the platform operation judgment parameter to determine whether the clock is stopped;
[0169] Wherein, when the verification platform determines that the clock stops, the verification platform stops simulating the SoC;
[0170] Or when the verification platform determines that the clock is not stopped, the verification platform continues to simulate the SoC.
[0171] In a possible implementation, the device is further configured to:
[0172] Verify the platform running startup parameters and start the crawler; the startup parameters are set in the update script file;
[0173] After running for the second running time, the verification platform starts to capture the simulation waveform based on the capture tool, and continues to capture for the first time to obtain the target waveform.
[0174] In a possible implementation, the device is further configured to:
[0175] Verify that the platform runs with shutdown parameters and closes the crawler; the shutdown parameters are set in the update script file.
[0176] In a possible implementation, the verification platform is a Zebu verification platform.
[0177] It should be noted that: when the device for capturing simulation waveforms provided in the above-mentioned embodiments executes the corresponding steps, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the device for capturing simulation waveforms provided in the above-mentioned embodiments and the method embodiment for capturing simulation waveforms belong to the same concept. The specific implementation process is detailed in the method embodiment and will not be repeated here.
[0178] In an embodiment of the present application, a preset script including a trigger condition and capture parameters is set, and the verification platform runs the preset script. When the verification platform runs to meet the trigger condition, the verification platform automatically obtains the first running time. The verification platform obtains the second running time based on the first running time and the second running time. The second running time indicates the time when the verification platform starts to capture the simulation waveform. In the above technical solution, the verification platform determines the exact time when the trigger condition takes effect through the first running time. In addition, through the second running time, the verification platform starts to capture the simulation waveform before running to meet the trigger condition. In this way, not only the simulation waveform after the trigger condition occurs can be captured, but also the simulation waveform before the trigger condition occurs can be captured, so that more information related to the trigger condition can be obtained, and then the cause that affects the occurrence of the trigger condition can be more accurately located, and the SoC can be accurately debugged.
[0179] An embodiment of the present application further provides a computer device, including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, and the processor implements the above method when executing the computer program.
[0180] Taking computer equipment as the terminal as an example, Figure 8 is a schematic diagram of the structure of a terminal provided in an embodiment of the present application. Figure 8 The terminal 800 may be a smart phone, a tablet computer, an MP3 player (Moving Picture Experts Group Audio Layer III), an MP4 player (Moving Picture Experts Group Audio Layer IV), a laptop computer or a desktop computer. The terminal 800 may also be called a user device, a portable terminal, a laptop terminal, a desktop terminal or other names.
[0181] Typically, the terminal 800 includes a processor 801 and a memory 802 .
[0182] The processor 801 may include one or more processing cores, such as a 4-core processor, a 5-core processor, etc. The processor 801 may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor 801 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 801 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 801 may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.
[0183] The memory 802 may include one or more computer-readable storage media, which may be non-transitory. The memory 802 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In some embodiments, the non-transitory computer-readable storage medium in the memory 802 is used to store at least one program code, which is used to be executed by the processor 801 to implement the process provided by the method embodiment of the present application for the terminal execution in the above method.
[0184] In some embodiments, the terminal 800 may further optionally include: a peripheral device interface 803 and at least one peripheral device. The processor 801, the memory 802 and the peripheral device interface 803 may be connected via a bus or a signal line. Each peripheral device may be connected to the peripheral device interface 803 via a bus, a signal line or a circuit board. Specifically, the peripheral device includes: at least one of a display screen 804, a camera assembly 805, an audio circuit 806 and a power supply 807.
[0185] The peripheral device interface 803 can be used to connect at least one peripheral device related to I / O (Input / Output) to the processor 801 and the memory 802. In some embodiments, the processor 801, the memory 802, and the peripheral device interface 803 are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor 801, the memory 802, and the peripheral device interface 803 can be implemented on a separate chip or circuit board, which is not limited in the embodiments of the present application.
[0186] The display screen 804 is used to display the UI (User Interface). The UI may include graphics, text, icons, videos, and any combination thereof. When the display screen 804 is a touch display screen, the display screen 804 also has the ability to collect touch signals on the surface or above the surface of the display screen 804. The touch signal can be input to the processor 801 as a control signal for processing. At this time, the display screen 804 can also be used to provide virtual buttons and / or virtual keyboards, also known as soft buttons and / or soft keyboards. In some embodiments, the display screen 804 can be one, set on the front panel of the terminal 800; in other embodiments, the display screen 804 can be at least two, respectively set on different surfaces of the terminal 800 or in a folding design; in other embodiments, the display screen 804 can be a flexible display screen, set on the curved surface or folding surface of the terminal 800. Even, the display screen 804 can also be set to a non-rectangular irregular shape, that is, a special-shaped screen. The display screen 804 can be made of materials such as LCD (Liquid Crystal Display), OLED (Organic Light-Emitting Diode, organic light-emitting diode).
[0187] The camera assembly 805 is used to capture images or videos. In some embodiments, the camera assembly 805 includes a front camera and a rear camera. Typically, the front camera is disposed on the front panel of the terminal, and the rear camera is disposed on the back of the terminal. In some embodiments, there are at least two rear cameras, which are any one of a main camera, a depth of field camera, a wide-angle camera, and a telephoto camera, so as to realize the fusion of the main camera and the depth of field camera to realize the background blur function, the fusion of the main camera and the wide-angle camera to realize panoramic shooting and VR (Virtual Reality) shooting function or other fusion shooting functions. In some embodiments, the camera assembly 805 may also include a flash. The flash can be a monochrome temperature flash or a dual-color temperature flash. A dual-color temperature flash refers to a combination of a warm light flash and a cold light flash, which can be used for light compensation at different color temperatures.
[0188] The audio circuit 806 may include a microphone and a speaker. The microphone is used to collect sound waves from the user and the environment, and convert the sound waves into electrical signals and input them into the processor 801 for processing. For the purpose of stereo acquisition or noise reduction, there may be multiple microphones, which are respectively arranged at different parts of the terminal 800. The microphone may also be an array microphone or an omnidirectional acquisition microphone. The speaker is used to convert the electrical signal from the processor 801 into sound waves. The speaker may be a traditional film speaker or a piezoelectric ceramic speaker. When the speaker is a piezoelectric ceramic speaker, it can not only convert the electrical signal into sound waves audible to humans, but also convert the electrical signal into sound waves inaudible to humans for purposes such as ranging. In some embodiments, the audio circuit 806 may also include a headphone jack.
[0189] The power supply 807 is used to power various components in the terminal 800. The power supply 807 can be an alternating current, a direct current, a disposable battery, or a rechargeable battery. When the power supply 807 includes a rechargeable battery, the rechargeable battery can support wired charging or wireless charging. The rechargeable battery can also be used to support fast charging technology.
[0190] Those skilled in the art will understand that Figure 8 The structure shown in the figure does not constitute a limitation on the terminal 800, and the terminal 800 may include more or less components than those shown in the figure, or combine some components, or adopt a different component arrangement.
[0191] Take the computer device as a server as an example. Fig. 9 It is a structural diagram of a server provided in an embodiment of the present application. The server 900 may have relatively large differences due to different configurations or performances, and may include one or more processors (Central Processing Units, CPU) 901 and one or more memories 902, wherein the one or more memories 902 store at least one computer program, and the at least one computer program is loaded and executed by the one or more processors 901 to implement the above-mentioned method of capturing simulation waveforms. Of course, the server 900 may also have components such as a wired or wireless network interface, a keyboard, and an input and output interface for input and output. The server 900 may also include other components for implementing device functions, which will not be repeated here.
[0192] The embodiment of the present application also provides a computer-readable storage medium, the computer-readable storage medium includes a stored computer program, wherein when the computer program is running, the device where the computer-readable storage medium is located is controlled to execute the above generation method. Optionally, the computer-readable storage medium can be a read-only memory (ROM), a random access memory (RAM), a compact disc (CD-ROM), a magnetic tape, a floppy disk, an optical data storage device, etc.
[0193] A person skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware or by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.
[0194] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.< / clk> < / clk> < / clk> < / clk> < / clk> < / clk> < / value> < / value> < / clk> < / rst> < / clk>
Claims
1. A method for capturing a simulation waveform, characterized in that: include: Get the preset script file; The preset script file indicates the process of verifying the platform simulating SoC; The preset script file includes trigger conditions and capture parameters; The capture parameters include a first duration and a second duration; The first duration indicates the duration of capturing the simulation waveform; the second duration indicates the duration before the verification platform runs to meet the trigger condition; The simulation waveform is generated during the process of simulating the SoC on the verification platform; The trigger condition indicates that the verification platform simulates the process of the SoC to reach a preset state; The first duration is greater than the second duration; Acquire a first running time; the first running time is the time during which the verification platform runs until the trigger condition is met; Obtaining a second running time; the second running time is the time from when the verification platform runs to when the simulation waveform starts to be captured; The second running time is determined based on the second time and the first running time; Get the target waveform; The target waveform is obtained by capturing the simulation waveform after the verification platform has run for the second running time and continues for the first time period.
2. The method according to claim 1, characterized in that The method further includes: the verification platform runs a clock test parameter to test a clock; the clock instructs the verification platform to simulate the process of the SoC; The verification platform runs a reset parameter to reset the verification platform, and the clock test parameter indicates a clock test process; the reset parameter indicates the reset of the verification platform; Wherein, the clock test parameter and the reset parameter are set in the preset script file.
3. The method according to claim 2, characterized in that The trigger condition includes a trigger signal and a trigger value; the trigger signal is equal to the trigger value; and the trigger signal indicates a preset register of the SoC.
4. The method according to claim 3, characterized in that The obtaining of the first running time comprises: The verification platform runs a first enabling parameter to simulate the SoC; The verification platform runs until the trigger condition is met as the first running time; Wherein, the first enabling parameter is set in the preset script file.
5. The method according to claim 3, characterized in that: The obtaining of the second running time comprises: The verification platform automatically writes the first running time into the preset script file; The verification platform calculates the difference between the first running time and the second running time to obtain the second running time; The verification platform writes the second running time into the preset script file to obtain an updated script file.
6. The method according to claim 5, characterized in that The method further includes: the verification platform runs a second enabling parameter to simulate the SoC running the second running time; and the second enabling parameter is set in the update script file.
7. The method according to claim 6, characterized in that The method further includes: the verification platform runs a judgment parameter to determine whether the clock is stopped; Wherein, when the verification platform determines that the clock stops, the simulation of the SoC is stopped; Or when the verification platform determines that the clock is not stopped, the SoC is continuously simulated.
8. The method according to claim 6, characterized in that The step of obtaining a target waveform comprises: The verification platform runs the startup parameters to start the crawler; the startup parameters are set in the update script file; After running for the second running time, the verification platform starts to capture the simulation waveform based on the capture tool and continues to capture the first time to obtain the target waveform.
9. The method according to claim 8, characterized in that The method further comprises: The verification platform runs a shutdown parameter to close the crawler; the shutdown parameter is set in the update script file.
10. The method according to claim 1, characterized in that The verification platform is the Zebu verification platform.
11. A device for capturing a simulation waveform, characterized in that: include: A first acquisition module is used to acquire a preset script file; The preset script file indicates the process of verifying the platform simulating SoC; The preset script file includes a trigger condition and a capture parameter; the capture parameter includes a first duration and a second duration; The first duration indicates the duration of capturing the simulation waveform; the second duration indicates the duration before the verification platform runs to meet the trigger condition; The simulation waveform is generated during the process of simulating the SoC on the verification platform; The trigger condition indicates that the verification platform simulates the process of the SoC to reach a preset state; The first duration is greater than the second duration; A second acquisition module is used to acquire a first running time; the first running time is the time during which the verification platform runs until the trigger condition is met; A third acquisition module is used to acquire a second running time; the second running time is the time from when the verification platform runs to when the simulation waveform starts to be captured; The second running time is determined based on the second time and the first running time; A fourth acquisition module, used to acquire a target waveform; The target waveform is obtained by capturing the simulation waveform after the verification platform has run for the second running time and continues for the first time period.
12. A computer device, characterized in that: The computer device comprises a processor and a memory, wherein the memory is used to store at least one program, and the at least one program is loaded by the processor and executes the method for capturing a simulation waveform according to any one of claims 1 to 10.
13. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores at least one program, and the at least one program is loaded and executed by a processor to implement the method for capturing a simulation waveform according to any one of claims 1 to 10.