Wiring method and device, electronic equipment and computer readable medium

Abstract

The invention discloses a wiring method and device, electronic equipment and a computer readable medium, and belongs to the technical field of integrated circuits, and the method comprises the steps: obtaining a reference path and expected total delay; dividing the reference path into a corresponding fixed sub-path and an aligned sub-path; performing wiring design on the fixed sub-path to obtain a first sub-path corresponding to the reference path; determining a target delay corresponding to the reference path based on a difference value between the path delay of the first sub-path and an expected total delay; based on the target delay, performing wiring design on the aligned sub-path of the reference path corresponding to the target delay to obtain a second sub-path corresponding to the reference path; and combining the first sub-path and the second sub-path corresponding to the reference path to obtain a target path. Through the wiring design of the reference path, the target path with the time delay being the expected total time delay is obtained, the target signal can reach the chip receiving end at the same time, the application requirement of target signal synchronization is met, and the cost of target signal synchronization is low.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and more specifically, to a wiring method, device, electronic device and computer-readable medium. Background Art

[0002] In certain specific scenarios in the FPGA field, it is necessary to synchronously transmit a specified signal to the chip receiving end to achieve synchronous processing of subsequent data. The existing technology performs synchronous processing on the received specified signal to achieve synchronization of subsequent processing of the specified signal. This method is relatively complex and consumes more resources. Summary of the invention

[0003] The present application proposes a wiring method, device, electronic device and computer-readable medium to improve the above-mentioned defects.

[0004] In a first aspect, the present application provides a wiring method, which is applied to a programmable logic device, including: obtaining a reference path and an expected total delay, the reference path being the initial transmission path of a target signal from a corresponding starting point logic device to an end point logic device; dividing the reference path into corresponding fixed sub-paths and alignment sub-paths; performing wiring design on the fixed sub-path to obtain a first sub-path corresponding to the reference path; determining a target delay corresponding to the reference path based on a difference between a path delay of the first sub-path and an expected total delay; performing wiring design on the alignment sub-path of the corresponding reference path based on the target delay to obtain a second sub-path corresponding to the reference path, the delay of the second sub-path being the same as the corresponding target delay; and combining the first sub-path and the second sub-path both corresponding to the reference path to obtain the target path.

[0005] Optionally, for a possible implementation, the reference path is divided into corresponding fixed sub-paths and aligned sub-paths, including: obtaining multiple logic devices distributed on the reference path and the arrangement order of each logic device; based on the arrangement order, the logic device adjacent to the endpoint logic device is used as a critical logic device; based on the critical logic device, the reference path is divided into corresponding fixed sub-paths and aligned sub-paths, the fixed sub-path being a transmission path of the target signal from the starting point logic device to the output end of the critical logic device, and the aligned sub-path being a transmission path of the target signal from the output end of the critical logic device to the endpoint logic device.

[0006] Optionally, for a possible implementation, based on the target delay, a wiring design is performed on the alignment sub-path of the corresponding reference path to obtain a second sub-path corresponding to the reference path, including: determining an alternative path based on the alignment sub-path of the reference path; judging whether the path delay of the alternative path is equal to the target delay; if it is equal to the target delay, taking the alternative path as the second sub-path corresponding to the reference path; if it is not equal to the target delay, performing a wiring design on the alternative path to obtain a new alternative path, and returning to execute judging whether the path delay of the alternative path is equal to the target delay and subsequent steps.

[0007] Optionally, for a possible implementation, the first sub-path is the shortest delay path of the corresponding fixed sub-path.

[0008] Optionally, for a possible implementation, obtaining a reference path and an expected total delay includes: obtaining at least two reference paths; obtaining a path delay of each reference path; and taking the maximum value of the path delay of each reference path as the expected total delay.

[0009] Optionally, for a possible implementation, obtaining reference paths and expected total delay includes: obtaining at least two reference paths; obtaining the shortest path delay of each reference path; and taking the maximum value of the shortest path delay of each reference path as the expected total delay.

[0010] Optionally, for a possible implementation, after combining the first sub-path and the second sub-path both corresponding to the reference path to obtain the target path, the method further includes: storing the logic device corresponding to the target path and the wiring parameters between adjacent logic devices.

[0011] In a second aspect, the present application also provides a wiring device, which is applied to a programmable logic device, including: an acquisition unit, used to acquire a reference path and an expected total delay, the reference path being the initial transmission path of the target signal from the corresponding starting point logic device to the end point logic device; a division unit, used to divide the reference path into corresponding fixed sub-paths and aligned sub-paths; a first wiring unit, used to perform wiring design on the fixed sub-path to obtain a first sub-path corresponding to the reference path; a calculation unit, used to determine the target delay corresponding to the reference path based on the difference between the path delay of the first sub-path and the expected total delay; a second wiring unit, used to perform wiring design on the aligned sub-path of the corresponding reference path based on the target delay to obtain a second sub-path corresponding to the reference path, the delay of the second sub-path being the same as the corresponding target delay; a combination unit, used to combine the first sub-path and the second sub-path, both corresponding to the reference path, to obtain the target path.

[0012] In a third aspect, the present application also provides an electronic device comprising: one or more processors; a memory; and one or more applications, wherein the one or more applications are stored in the memory, the one or more applications are configured to be executed by the one or more processors, and the one or more applications are configured to execute the above method.

[0013] In a fourth aspect, the present application also provides a computer-readable storage medium, which stores a program code executable by a processor, and when the program code is executed by the processor, the processor executes the above method.

[0014] The solution provided by the present application is as follows: first, a reference path and an expected total delay are obtained, where the reference path is the initial transmission path of the target signal from the corresponding starting point logic device to the end point logic device; then, the reference path is divided into corresponding fixed sub-paths and alignment sub-paths; the fixed sub-paths are designed for wiring to obtain a first sub-path corresponding to the reference path; secondly, based on the difference between the path delay of the first sub-path and the expected total delay, the target delay corresponding to the reference path is determined; based on the target delay, the alignment sub-path of the corresponding reference path is designed for wiring to obtain a second sub-path corresponding to the reference path, and the delay of the second sub-path is the same as the corresponding target delay; finally, the first sub-path and the second sub-path, both corresponding to the reference path, are combined to obtain the target path.

[0015] The present application obtains a target path with a delay equal to the expected total delay only by adjusting the wiring design of the reference path. When the target signals start to be transmitted at the same time, the target signals can reach the chip receiving end at the same time, meeting the application requirements of target signal synchronization without the need for an additional synchronization processing unit, and the cost of achieving target signal synchronization is low.

[0016] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by practicing the present application. The purpose and other advantages of the present application can be realized and obtained by the structures specifically pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 A method flow chart of a wiring method provided by an embodiment of the present application is shown;

[0019] Figure 2A method flow chart of a wiring method provided by another embodiment of the present application is shown;

[0020] Figure 3 A method flow chart of a wiring method provided by another embodiment of the present application is shown;

[0021] Figure 4 A method flow chart of a wiring method provided by another embodiment of the present application is shown;

[0022] Figure 5 A method flow chart of a wiring method provided by another embodiment of the present application is shown;

[0023] Figure 6 A method flow chart of a wiring method provided by another embodiment of the present application is shown;

[0024] Figure 7 A method flow chart of a wiring method provided by another embodiment of the present application is shown;

[0025] Figure 8 A schematic diagram showing a reference path provided by an embodiment of the present application is shown;

[0026] Fig. 9 A structural block diagram of a wiring method and device provided in an embodiment of the present application is shown;

[0027] Fig.10 A structural block diagram of an electronic device provided in an embodiment of the present application is shown;

[0028] Fig.11 A structural block diagram of a computer-readable storage medium provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0029] In order to make those skilled in the art better understand the present application scheme, the technical scheme in the present application embodiment will be clearly and completely described below in conjunction with the drawings in the present application embodiment. Obviously, the described embodiment is only a part of the present application embodiment, rather than all the embodiments. The components of the present application embodiment usually described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the present application for protection, but merely represents the selected embodiment of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0030] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0031] In certain specific scenarios in the FPGA field, it is necessary to synchronously transmit a specified signal to the chip receiving end to achieve synchronous processing of subsequent data. The existing technology performs synchronous processing on the received specified signal to achieve synchronization of subsequent processing of the specified signal. This method is relatively complex and consumes more resources.

[0032] Therefore, in the embodiments of the present application, a wiring method, an apparatus, an electronic device and a computer-readable medium are provided to solve or partially solve the above-mentioned problems.

[0033] See also Figure 1 , which shows a method flow chart of a wiring method provided in an embodiment of the present application. The method is applied to a programmable logic device, and the method specifically includes steps S110 to S160.

[0034] Step S110: obtaining a reference path and an expected total delay, where the reference path is an initial transmission path of a target signal from a corresponding starting point logic device to a destination logic device.

[0035] It should be noted that the target signal is a designated signal whose delay duration needs to be adjusted, and the reference path is the initial transmission path of the target signal from the corresponding starting logic device to the key logic device, and the initial transmission path is a randomly wired path.

[0036] The expected total delay is used to characterize the total delay that the target signal needs to reach from the corresponding starting logic device to the end logic device. The expected total delay can be preset data, which is set by the staff according to actual needs. The expected total delay can also be determined based on the path delay of at least two reference paths. For details, please refer to the subsequent embodiments.

[0037] Step S120: Divide the reference path into corresponding fixed sub-paths and alignment sub-paths.

[0038] The reference path is divided into two sub-paths, namely a fixed sub-path and an aligned sub-path connected end to end. The fixed sub-path and the aligned sub-path can be obtained by dividing based on the logic devices on the reference path. For details, please refer to the subsequent embodiments.

[0039] Step S130: performing wiring design on the fixed sub-path to obtain a first sub-path corresponding to the reference path.

[0040] The fixed sub-path is re-wired to obtain a first sub-path. It should be noted that the logic devices in the fixed sub-path are the same as those in the first sub-path.

[0041] Step S140: Determine a target delay corresponding to the reference path based on the difference between the path delay of the first sub-path and the expected total delay.

[0042] Since the expected total delay represents the total delay that the target signal needs to reach from the corresponding starting point logic device to the end point logic device, and the reference path is divided into a fixed sub-path and an aligned sub-path, the fixed sub-path is routed to obtain the first path, the expected total delay can be subtracted from the path delay of the first path to obtain the target delay corresponding to the reference path.

[0043] It should be noted that in the field of programmable logic devices, there are a variety of software tools that can implement routing and obtain routing delays. These tools are generally called synthesis and placement and routing tools, and the path delay of the first subpath can be obtained based on the placement and routing tools.

[0044] Step S150: Based on the target delay, a routing design is performed on the alignment sub-path of the corresponding reference path to obtain a second sub-path corresponding to the reference path, and the delay of the second sub-path is the same as the corresponding target delay.

[0045] It should be noted that the target delay is the path delay that the alignment sub-path needs to achieve. For this purpose, based on the target delay, the alignment sub-path of the corresponding reference path is designed for routing, and a second sub-path corresponding to the reference path is obtained. The second sub-path is the path after the alignment sub-path routing is adjusted.

[0046] It should be noted that the delay of the second sub-path can be the same or approximately the same as the corresponding target delay. First, during the wiring design process, the delay adjustment of the path has a minimum adjustable accuracy. For this reason, there is a situation where the delay of the second sub-path is not equal to the corresponding target delay. Secondly, there is also a certain allowable time difference when the target signal arrives at the chip receiving end at the same time. When the difference between the delay of the second sub-path and the corresponding target delay is within the allowable time difference range, it can be understood that the delay of the second sub-path is approximately the same as the corresponding target delay.

[0047] Step S160: combining the first sub-path and the second sub-path both corresponding to the reference path to obtain a target path.

[0048] The first subpath and the second subpath corresponding to the same reference path are combined to obtain a target path, that is, the reference path is adjusted to obtain the target path, and the total delay of the target path is the expected total delay.

[0049] In one embodiment, a reference path and an expected total delay are first obtained, and then the reference path is divided into corresponding fixed sub-paths and alignment sub-paths, and the fixed sub-paths are designed for wiring to obtain a first sub-path corresponding to the reference path. Secondly, based on the difference between the path delay of the first sub-path and the expected total delay, the target delay corresponding to the reference path is determined, and based on the target delay, the alignment sub-path of the corresponding reference path is designed for wiring to obtain a second sub-path corresponding to the reference path, and the delay of the second sub-path is the same as the corresponding target delay. Finally, the first sub-path and the second sub-path, both corresponding to the reference path, are combined to obtain the target path.

[0050] Based on this method, the transmission path of the target signal can be designed for wiring to obtain the target path, so that the delay of the target path is the expected total delay. Based on this method, the transmission paths of multiple target signals can be designed for wiring respectively, so that the delays of multiple target paths are all the expected total delay, so that multiple target signals can arrive at the chip receiving end synchronously. It should be noted that multiple target signals are transmitted to the chip receiving end from their corresponding starting logic devices at the same time.

[0051] In the prior art, synchronization of subsequent processing of the designated signal is achieved by performing synchronization processing on the received designated signal. This method is relatively complex and consumes a lot of resources.

[0052] However, the present application obtains the target path with a delay equal to the expected total delay by only adjusting the wiring design of the reference path, so that the target signals can reach the chip receiving end at the same time, meeting the application requirements of target signal synchronization without the need for an additional synchronization processing unit, and the cost of achieving target signal synchronization is low.

[0053] See also Figure 2 , which shows a method flow chart of a wiring method provided in an embodiment of the present application. The method is applied to a programmable logic device, and the method specifically includes steps S210 to S280.

[0054] Step S210: obtaining a reference path and an expected total delay, where the reference path is an initial transmission path of a target signal from a corresponding starting point logic device to a destination logic device.

[0055] Among them, step S210 has been introduced in detail in the above embodiment and will not be repeated here.

[0056] Step S220: Acquire multiple logic devices distributed on the reference path and the arrangement order of each logic device.

[0057] It should be noted that the reference path is the initial transmission path of the target signal from the corresponding starting logic device to the key logic device. There are multiple logic devices distributed on the reference path, including the starting logic device and the end logic device. The logic devices are sorted based on the order in which the target signal passes through the logic devices, and the arrangement order of each logic device can be obtained.

[0058] Step S230: taking logic devices adjacent to the endpoint logic device as critical logic devices based on the arrangement order.

[0059] Based on the arrangement order of each logic device, the logic device adjacent to the endpoint logic device is used as the critical logic device, that is, the second to last logic device is used as the critical logic device.

[0060] Step S240: Based on the critical logic device, the reference path is divided into corresponding fixed sub-paths and aligned sub-paths, the fixed sub-path is the transmission path of the target signal from the starting logic device to the output end of the critical logic device, and the aligned sub-path is the transmission path of the target signal from the output end of the critical logic device to the end logic device.

[0061] For a schematic diagram of the reference path, see Figure 8 , based on the critical logic device, the reference path is divided into a fixed sub-path and an aligned sub-path. The transmission path of the target signal from the starting logic device to the output end of the critical logic device is the fixed sub-path, and the transmission path of the target signal from the output end of the critical logic device to the end logic device is the aligned sub-path.

[0062] Step S250: performing wiring design on the fixed sub-path to obtain a first sub-path corresponding to the reference path.

[0063] Step S260: Determine a target delay corresponding to the reference path based on the difference between the path delay of the first sub-path and the expected total delay.

[0064] Step S270: Based on the target delay, a routing design is performed on the alignment sub-path of the corresponding reference path to obtain a second sub-path corresponding to the reference path, and the delay of the second sub-path is the same as the corresponding target delay.

[0065] Step S280: Combine the first sub-path and the second sub-path that both correspond to the reference path to obtain a target path.

[0066] Among them, step S250 and step S280 have been introduced in detail in the above embodiments and will not be repeated here.

[0067] Furthermore, the first subpath is the shortest delay path of the corresponding fixed subpath. The second subpath can be obtained by adjusting the wiring of the corresponding aligned subpath through the target delay, so that the path delay of the target path is the same as the expected total delay, thereby achieving the delay of the target signal to be the expected total delay.

[0068] See also Figure 3 , which shows a method flow chart of a wiring method provided in an embodiment of the present application. The method is applied to a programmable logic device, and the method specifically includes steps S310 to S390.

[0069] Step S310: obtaining a reference path and an expected total delay, where the reference path is an initial transmission path of a target signal from a corresponding starting point logic device to a destination logic device.

[0070] Step S320: Divide the reference path into corresponding fixed sub-paths and alignment sub-paths.

[0071] Step S330: performing wiring design on the fixed sub-path to obtain a first sub-path corresponding to the reference path.

[0072] Step S340: Determine a target delay corresponding to the reference path based on the difference between the path delay of the first sub-path and the expected total delay.

[0073] Among them, step S310 and step S340 have been introduced in detail in the above embodiments and will not be repeated here.

[0074] Step S350: determining an alternative path based on the aligned sub-paths of the reference path.

[0075] It should be noted that the alignment sub-path of the reference path is designed for routing to obtain an alternative path. Specifically, since there are multiple routing methods between adjacent logic devices, multiple legal transmission paths can be obtained by searching the transmission path of the alignment sub-path through existing routing software, and a legal path is selected from the multiple searched transmission paths as an alternative path. Among them, the legal path means that the timing constraints, path delays, power and ground line limitations, crosstalk and interference, routing resources, etc. of the path meet the requirements.

[0076] Step S360: Determine whether the path delay of the candidate path is equal to the target delay.

[0077] It is necessary to determine whether the candidate path meets the requirements through the delay of the candidate path. To this end, it is necessary to determine whether the delay of the candidate path is equal to the target delay.

[0078] Furthermore, since the delay adjustment of the path has a minimum adjustable accuracy during the wiring design process, it is possible to determine whether the difference between the path delay of the alternative path and the target delay is less than the allowed time difference. If the difference between the path delay of the alternative path and the target delay is less than the allowed time difference, it can be understood whether the path delay of the alternative path is equal to the target delay, otherwise it is not equal to the target delay.

[0079] Step S370: If the delay is equal to the target delay, the alternative path is used as the second sub-path corresponding to the reference path.

[0080] If the path delay of the candidate path is equal to the target delay, it means that the candidate path meets the requirement, and the candidate path is used as the second sub-path corresponding to the reference path.

[0081] Step S380: If the delay is not equal to the target delay, a routing design is performed on the candidate path to obtain a new candidate path, and the process returns to execute the determination of whether the path delay of the candidate path is equal to the target delay and subsequent steps.

[0082] If the path delay of the alternative path is not equal to the target delay, it means that the alternative path does not meet the requirements. The alternative path is wired and designed to obtain a new alternative path. The execution is returned to determine whether the path delay of the alternative path is equal to the target delay and subsequent steps.

[0083] Step S390: Combine the first sub-path and the second sub-path that both correspond to the reference path to obtain a target path.

[0084] Among them, step S390 has been introduced in detail in the above embodiment and will not be repeated here.

[0085] See also Figure 4 , which shows a method flow chart of a wiring method provided in an embodiment of the present application. The method is applied to a programmable logic device, and the method specifically includes steps S410 to S480.

[0086] Step S410: Obtain at least two reference paths.

[0087] That is, initial transmission paths of at least two target signals from corresponding starting point logic devices to end point logic devices are obtained.

[0088] Step S420: Obtain the path delay of each reference path.

[0089] It should be noted that the reference path can be routed based on existing software tools, and delay analysis can be performed on the routed reference path to obtain the path delay of the reference path. To this end, the path delay of the reference path can be obtained by this method.

[0090] Step S430: taking the maximum value of the path delays of each reference path as the expected total delay.

[0091] It should be noted that the reference path is the initial transmission path of the target signal from the corresponding starting logic device to the end logic device. The path delay of each reference path may be different. The maximum value of the path delay of each reference path is taken as the expected total delay. The expected total delay is the delay that needs to be achieved, that is, the path delay of each reference path needs to be adjusted to the expected total delay.

[0092] Step S440: Divide the reference path into corresponding fixed sub-paths and alignment sub-paths.

[0093] Step S450: performing wiring design on the fixed sub-path to obtain a first sub-path corresponding to the reference path.

[0094] Step S460: Determine a target delay corresponding to the reference path based on the difference between the path delay of the first sub-path and the expected total delay.

[0095] Step S470: Based on the target delay, a routing design is performed on the alignment sub-path of the corresponding reference path to obtain a second sub-path corresponding to the reference path, and the delay of the second sub-path is the same as the corresponding target delay.

[0096] Step S480: Combine the first sub-path and the second sub-path that both correspond to the reference path to obtain a target path.

[0097] Among them, step S440 and step S480 have been introduced in detail in the above embodiments and will not be repeated here.

[0098] See also Figure 5 , which shows a method flow chart of a wiring method provided in an embodiment of the present application. The method is applied to a programmable logic device, and the method specifically includes steps S510 to S580.

[0099] Step S510: Obtain at least two reference paths.

[0100] Among them, step S510 has been introduced in detail in the above embodiment and will not be repeated here.

[0101] Step S520: Obtain the shortest path delay of each reference path.

[0102] It should be noted that the reference path can be routed based on existing software tools, and the reference path can be delayed and analyzed to obtain the reference path delay. There may be multiple reference path routing methods, and the path delay corresponding to each reference path routing method can be obtained to determine the shortest path delay of the reference path. The shortest path delay of each reference path is obtained in this way.

[0103] Step S530: taking the maximum value of the shortest path delays of each reference path as the expected total delay.

[0104] It should be noted that the reference path is the initial transmission path of the target signal from the corresponding starting point logic device to the end point logic device. The path delay of each reference path may be different. The maximum value of the shortest path delay of each reference path is taken as the expected total delay. The expected total delay is the delay that needs to be achieved, that is, the path delay of each reference path needs to be adjusted to the expected total delay.

[0105] The present application determines the expected total delay through the shortest delay path of each reference path, which can make the expected total delay as short as possible, and make the transmission delay of the target signal from the starting logic device to the end logic device as short as possible, thereby making the timing of the target signal better.

[0106] Step S540: Divide the reference path into corresponding fixed sub-paths and alignment sub-paths.

[0107] Step S550: performing wiring design on the fixed sub-path to obtain a first sub-path corresponding to the reference path.

[0108] Step S560: Determine a target delay corresponding to the reference path based on the difference between the path delay of the first sub-path and the expected total delay.

[0109] Step S570: Based on the target delay, a routing design is performed on the alignment sub-path of the corresponding reference path to obtain a second sub-path corresponding to the reference path, and the delay of the second sub-path is the same as the corresponding target delay.

[0110] Step S580: Combine the first sub-path and the second sub-path that both correspond to the reference path to obtain a target path.

[0111] Among them, step S540 and step S580 have been introduced in detail in the above embodiments and will not be repeated here.

[0112] See also Figure 6 , which shows a method flow chart of a wiring method provided in an embodiment of the present application. The method is applied to a programmable logic device, and the method specifically includes steps S610 to S670.

[0113] Step S610: Obtain a reference path and an expected total delay, where the reference path is an initial transmission path of a target signal from a corresponding starting point logic device to a destination logic device.

[0114] Step S620: Divide the reference path into corresponding fixed sub-paths and alignment sub-paths.

[0115] Step S630: performing wiring design on the fixed sub-path to obtain a first sub-path corresponding to the reference path.

[0116] Step S640: Determine a target delay corresponding to the reference path based on the difference between the path delay of the first sub-path and the expected total delay.

[0117] Step S650: Based on the target delay, a routing design is performed on the alignment sub-path of the corresponding reference path to obtain a second sub-path corresponding to the reference path, and the delay of the second sub-path is the same as the corresponding target delay.

[0118] Step S660: Combine the first sub-path and the second sub-path that both correspond to the reference path to obtain a target path.

[0119] Among them, step S610 and step S660 have been introduced in detail in the above embodiments and will not be repeated here.

[0120] Step S670: storing the logic devices corresponding to the target path and the wiring parameters between adjacent logic devices.

[0121] It should be noted that in the wiring design, it is necessary not only to wire the reference path, but also to wire the transmission paths of other signals. To this end, it is necessary to wire the reference path corresponding to the target signal first to obtain the target path, so that the delay of the target path is the expected total delay, and then wire the transmission paths of other signals. After obtaining the target path, it is necessary to save the wiring parameters of the logic device corresponding to the target path and the adjacent logic devices. When wiring the transmission paths of other reference signals, the wiring is performed based on the saved target path, that is, the non-reference path is kept unchanged.

[0122] See also Figure 7 , which shows a method flow chart of a wiring method provided in an embodiment of the present application. The method is applied to a programmable logic device, and the method specifically includes steps S710 to S780.

[0123] Step S710: Acquire multiple reference paths, where the reference paths are initial transmission paths of target signals from corresponding starting point logic devices to end point logic devices.

[0124] Among them, step S710 has been introduced in detail in the above embodiment and will not be repeated here.

[0125] Step S720: Divide each reference path into corresponding fixed sub-paths and alignment sub-paths.

[0126] Each reference path is divided into corresponding fixed sub-paths and alignment sub-paths. For details, please refer to the aforementioned embodiment.

[0127] Step S730: performing routing design on the fixed sub-path corresponding to each reference path to obtain a first sub-path with the shortest delay.

[0128] Based on the existing layout and routing tools, after the transmission path of the reference path is designed, the reference path can be subjected to delay analysis based on the layout and routing tools, and the fixed sub-path corresponding to each reference path can be subjected to routing design based on the layout and routing tools to obtain the first sub-path with the shortest delay.

[0129] Step S740: Obtain the total path delay corresponding to each reference path.

[0130] Continuing with the above-mentioned embodiment, based on the existing placement and routing tools, the total path delay corresponding to each reference path can be obtained.

[0131] Step S750: taking the maximum value of the total path delays corresponding to each reference path as the expected total delay.

[0132] The maximum value of the total path delay corresponding to each reference path is taken as the expected total delay.

[0133] Step S760: Determine a target delay corresponding to the reference path based on the difference between the path delay of the first sub-path and the expected total delay.

[0134] Step S770: Based on the target delay, a routing design is performed on the alignment sub-path of the corresponding reference path to obtain a second sub-path corresponding to the reference path, and the delay of the second sub-path is the same as the corresponding target delay.

[0135] Among them, step S760 and step S770 have been introduced in detail in the above embodiments and will not be repeated here.

[0136] Step S780: Combine the first sub-path and the second sub-path that both correspond to the reference path to obtain a target path.

[0137] The first sub-path and the second sub-path, both corresponding to the reference path, are combined to obtain a target path, so that the path delay of the target path is equal to or approximately equal to the expected total delay. When the difference between the path delay of the target path and the expected total delay is within the allowable time difference range, the path delay of the target path is considered to be equal to the expected total delay.

[0138] See also Fig. 9 , which shows a structural block diagram of a test device 600 provided in an embodiment of the present application, wherein the test device 600 includes: an acquisition unit 610, a division unit 620, a first wiring unit 630, a calculation unit 640, a second wiring unit 650 and a combination unit 660.

[0139] The acquisition unit 610 is used to acquire a reference path and an expected total delay, where the reference path is an initial transmission path of a target signal from a corresponding starting point logic device to a destination logic device.

[0140] Further, the acquisition unit 610 may also be configured to acquire at least two reference paths; acquire the path delay of each reference path; and take the maximum value of the path delay of each reference path as the expected total delay.

[0141] Further, the acquisition unit 610 may also be configured to acquire at least two reference paths; acquire the shortest path delay of each reference path; and take the maximum value of the shortest path delay of each reference path as the expected total delay.

[0142] Furthermore, the first sub-path is the shortest delay path of the corresponding fixed sub-path.

[0143] The division unit 620 is used to divide the reference path into corresponding fixed sub-paths and alignment sub-paths.

[0144] Furthermore, the division unit 620 can also be used to obtain multiple logic devices distributed on the reference path and the arrangement order of each logic device; based on the arrangement order, the logic device adjacent to the endpoint logic device is used as a critical logic device; the reference path is divided into corresponding fixed sub-paths and alignment sub-paths, the fixed sub-path is the transmission path of the target signal from the starting point logic device to the output end of the critical logic device, and the alignment sub-path is the transmission path of the target signal from the output end of the critical logic device to the endpoint logic device.

[0145] The first wiring unit 630 is used to perform wiring design on the fixed sub-path to obtain a first sub-path corresponding to the reference path.

[0146] The calculation unit 640 is configured to determine a target delay corresponding to the reference path based on a difference between the path delay of the first sub-path and the expected total delay.

[0147] The second wiring unit 650 is used to perform wiring design on the alignment sub-path of the corresponding reference path based on the target delay to obtain a second sub-path corresponding to the reference path, and the delay of the second sub-path is the same as the corresponding target delay.

[0148] Furthermore, the second wiring unit 650 can also be used to determine an alternative path based on the aligned sub-path of the reference path; determine whether the path delay of the alternative path is equal to the target delay; if it is equal to the target delay, use the alternative path as the second sub-path corresponding to the reference path; if it is not equal to the target delay, perform wiring design on the alternative path to obtain a new alternative path, and return to execute whether the path delay of the alternative path is equal to the target delay and subsequent steps.

[0149] The combining unit 660 is configured to combine the first sub-path and the second sub-path, both corresponding to the reference path, to obtain a target path.

[0150] Furthermore, the combination unit 660 may also be used to store the logic devices corresponding to the target path and the wiring parameters between adjacent logic devices.

[0151] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described devices and modules can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here.

[0152] In several embodiments provided in the present application, the coupling between modules may be electrical, mechanical or other forms of coupling.

[0153] In addition, each functional module in each embodiment of the present application can be integrated into a processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The above integrated modules can be implemented in the form of hardware or software functional modules.

[0154] Please refer to Fig.10 , which shows a structural block diagram of an electronic device 700 provided in an embodiment of the present application. The electronic device 700 may be a vehicle system, which may be arranged in a vehicle. The electronic device 700 in the present application may include one or more of the following components: a processor 711, a memory 712, and one or more application programs, wherein the processor 711 is electrically connected to the memory 712, and the one or more program configurations are used to execute the methods described in the various embodiments of the aforementioned test method.

[0155] The processor 711 may include one or more processing cores. The processor 711 uses various interfaces and lines to connect various parts of the entire electronic device 700, and executes various functions and processes data of the electronic device 700 by running or executing instructions, programs, code sets or instruction sets stored in the memory 712, and calling data stored in the memory 712. Optionally, the processor 711 can be implemented in at least one hardware form of digital signal processing (DSP), field programmable gate array (FPGA), and programmable logic array (PLA). The processor 711 can integrate one or a combination of a central processing unit (CPU), a graphics processor (GPU), and a modem. Among them, the CPU mainly processes the operating system, user interface, and computer programs; the GPU is responsible for rendering and drawing display content; and the modem is used to process wireless communications. It can be understood that the above-mentioned modem may not be integrated into the processor 711, but may be implemented separately through a communication chip. Specifically, the method described in the above embodiments may be executed by one or more processors 711 .

[0156] For some embodiments, the memory 712 may include a random access memory (RAM) or a read-only memory (ROM). The memory 712 may be used to store instructions, programs, codes, code sets, or instruction sets. The memory 712 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for implementing at least one function, instructions for implementing the following various method embodiments, etc. The data storage area may also store data created by the electronic device 700 during use, etc.

[0157] Please refer to Fig.11 , which shows a structural block diagram of a computer-readable medium provided in an embodiment of the present application. The computer-readable medium 800 stores program codes, which can be called by a processor to execute the method described in the above method embodiment.

[0158] The computer readable medium 800 can be an electronic memory such as a flash memory, an EEPROM (electrically erasable programmable read-only memory), an EPROM, a hard disk, or a ROM. Optionally, the computer readable medium 800 includes a non-transitory computer-readable storage medium. The computer readable medium 800 has storage space for program code 810 that performs any method step in the above method. These program codes can be read from or written to one or more computer program products. The program code 810 can be compressed, for example, in an appropriate form.

[0159] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A wiring method, characterized in that: The method is applied to a programmable logic device, including: Obtain a reference path and an expected total delay, where the reference path is an initial transmission path of a target signal from a corresponding starting point logic device to a destination logic device; Divide the reference path into corresponding fixed sub-paths and alignment sub-paths; Performing wiring design on the fixed sub-path to obtain a first sub-path corresponding to the reference path; Determine a target delay corresponding to the reference path based on a difference between the path delay of the first subpath and the expected total delay; Based on the target delay, a routing design is performed on the alignment sub-path of the corresponding reference path to obtain a second sub-path corresponding to the reference path, and the delay of the second sub-path is the same as the corresponding target delay; The first sub-path and the second sub-path, both corresponding to the reference path, are combined to obtain a target path.

2. The method according to claim 1, characterized in that The reference path is divided into corresponding fixed sub-paths and alignment sub-paths, including: Acquire multiple logic devices distributed on a reference path and an arrangement order of each logic device; Based on the arrangement order, a logic device adjacent to the endpoint logic device is used as a critical logic device; Based on the critical logic device, the reference path is divided into corresponding fixed sub-paths and alignment sub-paths. The fixed sub-path is the transmission path of the target signal from the starting logic device to the output end of the critical logic device, and the alignment sub-path is the transmission path of the target signal from the output end of the critical logic device to the end logic device.

3. The method according to claim 1, characterized in that Based on the target delay, a routing design is performed on the alignment sub-path of the corresponding reference path to obtain a second sub-path corresponding to the reference path, including: determining an alternative pathway based on the aligned sub-pathways of the reference pathway; Determine whether the path delay of the alternative path is equal to the target delay; If the delay is equal to the target, the alternative path is used as the second subpath corresponding to the reference path; If the delay is not equal to the target delay, the alternative path is routed and designed to obtain a new alternative path, and the process returns to determine whether the path delay of the alternative path is equal to the target delay and the subsequent steps.

4. The method according to claim 1, characterized in that The first sub-path is the shortest delay path of the corresponding fixed sub-path.

5. The method according to claim 1, characterized in that Get the reference path and expected total latency, including: Obtain at least two reference paths; Obtain the path delay of each reference path; The maximum value of the path delays of each reference path is taken as the expected total delay.

6. The method according to claim 1, characterized in that Get the reference path and expected total latency, including: Obtain at least two reference paths; Obtain the shortest path delay of each reference path; The maximum value of the shortest path delays of each reference path is taken as the expected total delay.

7. The method according to claim 1, characterized in that After combining the first sub-path and the second sub-path corresponding to the reference path to obtain the target path, the method further includes: The logic devices corresponding to the target path and the wiring parameters between adjacent logic devices are stored.

8. A wiring device, characterized in that: The device is applied to programmable logic devices, including: An acquisition unit, used to acquire a reference path and an expected total delay, the reference path being an initial transmission path of a target signal from a corresponding starting point logic device to an end point logic device; A division unit, used for dividing the reference path into corresponding fixed sub-paths and alignment sub-paths; A first wiring unit, used for performing wiring design on the fixed sub-path to obtain a first sub-path corresponding to the reference path; A calculation unit, configured to determine a target delay corresponding to the reference path based on a difference between a path delay of the first subpath and an expected total delay; A second wiring unit is used to perform wiring design on an alignment sub-path of a corresponding reference path based on a target delay, so as to obtain a second sub-path corresponding to the reference path, wherein the delay of the second sub-path is the same as the corresponding target delay; The combining unit is used to combine the first sub-path and the second sub-path both corresponding to the reference path to obtain a target path.

9. An electronic device, characterized in that: include: one or more processors; Memory; One or more applications, wherein the one or more applications are stored in a memory, the one or more applications are configured to be executed by one or more processors, and the one or more applications are configured to execute the method according to any one of claims 1-7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores program codes, which can be called by a processor to execute the method according to any one of claims 1 to 7.

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