Wiring method, device, electronic equipment and computer readable medium

Abstract

The application discloses a wiring method and device, electronic equipment and computer readable medium, and belongs to the technical field of integrated circuits. The method comprises the following steps: obtaining a reference path and an expected total delay; dividing the reference path into corresponding fixed sub-paths and alignment sub-paths; performing wiring design on the fixed sub-paths to obtain first sub-paths corresponding to the reference path; determining a target delay corresponding to the reference path based on the difference between the path delay of the first sub-paths and the expected total delay; performing wiring design on the alignment sub-paths corresponding to the reference path based on the target delay to obtain second sub-paths corresponding to the reference path; and combining the first sub-paths and the second sub-paths corresponding to the reference path to obtain a target path. Through the wiring design on the reference path, the target path with the expected total delay is obtained, the target signal can reach the chip receiving end at the same time, the application demand of target signal synchronization is met, and the cost of realizing target signal synchronization is low.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and more particularly, to a wiring method and device, electronic equipment and computer readable medium. BACKGROUND

[0002] In some specific scenarios in the field of FPGA, it is necessary to synchronously transmit a specified signal to a chip receiving end to realize subsequent synchronous processing of data. The prior art realizes the synchronization of subsequent processing of the specified signal by synchronously processing the received specified signal. This method is relatively complex and consumes more resources. SUMMARY

[0003] The present application provides a wiring method, device, electronic equipment and computer readable medium to improve the above-mentioned defects.

[0004] In a first aspect, the present application provides a wiring method, which is applied to a programmable logic device and includes: obtaining a reference path and an expected total delay, the reference path being an initial transmission path of a target signal from a corresponding starting logic device to an ending logic device; dividing the reference path into a corresponding fixed sub-path and an alignment sub-path; performing wiring design on the fixed sub-path to obtain a first sub-path corresponding to the reference path; determining a target delay corresponding to the reference path based on a difference between a path delay of the first sub-path and the expected total delay; performing wiring design on the alignment sub-path corresponding to the reference path based on the target delay to obtain a second sub-path corresponding to the reference path, the delay of the second sub-path being the same as the corresponding target delay; and combining the first sub-path and the second sub-path corresponding to the reference path to obtain a target path.

[0005] Optionally, for a possible implementation, the dividing of the reference path into the corresponding fixed sub-path and the alignment sub-path includes: obtaining a plurality of logic devices distributed in the reference path and an arrangement order of each logic device; taking a logic device adjacent to the ending logic device as a critical logic device based on the arrangement order; and dividing the reference path into the corresponding fixed sub-path and the alignment sub-path based on the critical logic device, the fixed sub-path being a transmission path of the target signal from the starting logic device to an output end of the critical logic device, and the alignment sub-path being a transmission path of the target signal from the output end of the critical logic device to the ending logic device.

[0006] Optionally, for one possible implementation, the aligning sub-path of the reference path corresponding to the target delay is routed to obtain a second sub-path corresponding to the reference path, including: determining an alternative path based on the aligning sub-path of the reference path; judging whether the path delay of the alternative path is equal to the target delay; if yes, taking the alternative path as the second sub-path corresponding to the reference path; if no, routing the alternative path to obtain a new alternative path, and returning to execute the judgment of whether the path delay of the alternative path is equal to the target delay and the subsequent steps.

[0007] Optionally, for one possible implementation, the first sub-path is the shortest delay path of the corresponding fixed sub-path.

[0008] Optionally, for one possible implementation, the reference path and the expected total delay are obtained, including: obtaining at least two reference paths; obtaining the path delay of each reference path; and taking the maximum value in the path delay of each reference path as the expected total delay.

[0009] Optionally, for one possible implementation, the reference path and the expected total delay are obtained, including: obtaining at least two reference paths; obtaining the shortest path delay of each reference path; and taking the maximum value in the shortest path delay of each reference path as the expected total delay.

[0010] Optionally, for one possible implementation, after the first sub-path and the second sub-path corresponding to the reference path are combined to obtain the target path, the method further includes: storing the wiring parameters between the logic devices corresponding to the target path and the adjacent logic devices.

[0011] In a second aspect, the present application further provides a wiring device, which is applied to a programmable logic device and includes: an obtaining unit, configured to obtain a reference path and an expected total delay, the reference path being an initial transmission path of a target signal from a corresponding starting logic device to a terminal logic device; a dividing unit, configured to divide the reference path into a corresponding fixed sub-path and an aligning sub-path; a first routing unit, configured to route the fixed sub-path to obtain a first sub-path corresponding to the reference path; a calculating unit, configured to determine a target delay corresponding to the reference path based on the difference between the path delay of the first sub-path and the expected total delay; a second routing unit, configured to route the aligning sub-path of the reference path corresponding to the target delay to obtain a second sub-path corresponding to the reference path, the delay of the second sub-path being the same as the corresponding target delay; and a combining unit, configured to combine the first sub-path and the second sub-path corresponding to the reference path to obtain a target path.

[0012] In a third aspect, the present application also provides an electronic device, comprising: one or more processors; a memory; and one or more application programs, wherein the one or more application programs are stored in the memory, the one or more application programs are configured to be executed by the one or more processors, and the one or more application programs are configured to execute the method described above.

[0013] In a fourth aspect, the present application also provides a computer readable medium, wherein the readable storage medium stores a program code executable by a processor, and the program code, when executed by the processor, causes the processor to execute the method described above.

[0014] The scheme provided by the present application first acquires a reference path and an expected total delay, the reference path being an initial transmission path of a target signal from a corresponding starting logic device to a terminal logic device; then, the reference path is divided into a corresponding fixed sub-path and an alignment sub-path; the fixed sub-path is subjected to wiring design to obtain a first sub-path corresponding to the reference path; secondly, based on a difference between a path delay of the first sub-path and the expected total delay, a target delay corresponding to the reference path is determined; based on the target delay, the alignment sub-path corresponding to the reference path is subjected to wiring design to obtain a second sub-path corresponding to the reference path, the delay of the second sub-path being the same as the corresponding target delay; finally, the first sub-path and the second sub-path, both corresponding to the reference path, are combined to obtain a target path.

[0015] The present application only adjusts the wiring design of the reference path to obtain the target path with the expected total delay, and when the target signals start to transmit at the same time, the target signals can reach the chip receiving end at the same time, meeting the application requirement of target signal synchronization, without the need of additional setting of a synchronization processing unit, and the cost of realizing target signal synchronization is low.

[0016] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent to those skilled in the art from the description, or can be learned by practice of the present application. The objects and other advantages of the present application will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0018] Figure 1 A method flowchart of the wiring method provided by the embodiments of the present application is shown;

[0019] Figure 2A method flow chart of a wiring method provided by another embodiment of the present application is shown;

[0020] Figure 3 A method flow chart of a wiring method provided by another embodiment of the present application is shown;

[0021] Figure 4 A method flow chart of a wiring method provided by another embodiment of the present application is shown;

[0022] Figure 5 A method flow chart of a wiring method provided by another embodiment of the present application is shown;

[0023] Figure 6 A method flow chart of a wiring method provided by another embodiment of the present application is shown;

[0024] Figure 7 A method flow chart of a wiring method provided by another embodiment of the present application is shown;

[0025] Figure 8 A schematic diagram of a reference path provided by an embodiment of the present application is shown;

[0026] Figure 9 A structural block diagram of a wiring method device provided by an embodiment of the present application is shown;

[0027] Figure 10 A structural block diagram of an electronic device provided by an embodiment of the present application is shown;

[0028] Figure 11 A structural block diagram of a computer readable storage medium provided by an embodiment of the present application is shown. DETAILED DESCRIPTION

[0029] In order to enable persons skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. The components of the embodiments of the present application described and shown in the accompanying drawings can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0030] It should be noted that similar reference numerals and letters refer to like items throughout the accompanying drawings, and once an item is defined in one drawing, it should not require further defining and explaining in subsequent drawings. Meanwhile, in the description of the present application, the terms "first", "second", and the like are merely used to distinguish descriptions, and cannot be understood as indicating or implying relative importance.

[0031] In some specific scenarios in the field of FPGA, it is required to synchronously transmit a specified signal to a chip receiving end to realize synchronous processing of subsequent data. The prior art realizes the synchronization of subsequent processing of the specified signal by performing synchronous processing on the received specified signal. This method is relatively complex and consumes more resources.

[0032] Therefore, in the embodiments of the present application, a wiring method, device, electronic equipment and computer readable medium are provided to solve or partially solve the above problems.

[0033] Please refer to Figure 1 which shows a method flowchart of a wiring method provided by an embodiment of the present application. The method is applied to a programmable logic device, and specifically includes steps S110 to S160.

[0034] Step S110: Obtain a reference path and an expected total delay. The reference path is an initial transmission path of a target signal from a corresponding starting logic device to an ending logic device.

[0035] It should be noted that the target signal is a specified signal that needs to be regulated in terms of delay duration, the reference path is an initial transmission path of the target signal from the corresponding starting logic device to the ending logic device, and the initial transmission path is a randomly wired path.

[0036] The expected total delay is used to represent the total delay that the target signal needs to reach from the corresponding starting logic device to the ending logic device. The expected total delay can be preset data set by the staff according to actual needs. Alternatively, the expected total delay can be determined based on the path delays of at least two reference paths. For details, please refer to subsequent embodiments.

[0037] Step S120: Divide the reference path into corresponding fixed sub-paths and alignment sub-paths.

[0038] The reference path is divided into two sub-paths, i.e., a fixed sub-path and an alignment sub-path connected at both ends. The fixed sub-path and the alignment sub-path can be obtained based on the logic devices on the reference path. For details, please refer to subsequent embodiments.

[0039] Step S130: Perform wiring design on the fixed sub-path to obtain a first sub-path corresponding to the reference path.

[0040] The fixed sub-path is rewired to obtain a first sub-path. It should be noted that the logic device in the fixed sub-path is the same as the logic device in the first sub-path.

[0041] In step S140, a target delay corresponding to the reference path is determined based on a difference between the path delay of the first sub-path and the expected total delay.

[0042] The expected total delay represents the total delay that the target signal needs to reach from the corresponding start logic device to the end logic device. Since the reference path is divided into a fixed sub-path and an aligned sub-path, and the fixed sub-path is wired to obtain a first path, the expected total delay can be subtracted from the path delay of the first path to obtain the target delay corresponding to the reference path.

[0043] It should be noted that in the field of programmable logic devices, there are various software tools that can implement wiring and obtain the delay of wiring. These tools are commonly referred to as synthesis and placement and routing tools, and the path delay of the first sub-path can be obtained based on the placement and routing tool.

[0044] In step S150, the aligned sub-path of the reference path corresponding to the target delay is wired based on the target delay to obtain a second sub-path corresponding to the reference path, and the delay of the second sub-path is the same as the corresponding target delay.

[0045] It should be noted that the target delay is the path delay that the aligned sub-path needs to reach. Therefore, based on the target delay, the aligned sub-path of the reference path corresponding to the target delay is wired to obtain a second sub-path corresponding to the reference path, and the second sub-path is the path after the wiring adjustment of the aligned sub-path.

[0046] It should be noted that the delay of the second sub-path can be the same or approximately the same as the corresponding target delay. First, in the process of wiring design, the delay adjustment of the path has a minimum adjustable precision. Therefore, there are cases where the delay of the second sub-path is not equal to the corresponding target delay. Second, there is a certain allowed time difference when the target signal simultaneously reaches the chip receiving end. When the difference between the delay of the second sub-path and the corresponding target delay is within the allowed time difference range, it can be understood that the delay of the second sub-path is approximately the same as the corresponding target delay.

[0047] In step S160, the first sub-path and the second sub-path corresponding to the reference path are combined to obtain a target path.

[0048] The first sub-path and the second sub-path corresponding to the same reference path are combined to obtain a target path, i.e., the reference path is adjusted to obtain a target path, and the total delay of the target path is the expected total delay.

[0049] In an embodiment, a reference path and an expected total delay are first obtained, and then the reference path is divided into corresponding fixed sub-paths and alignment sub-paths, the fixed sub-paths are routed to obtain first sub-paths corresponding to the reference path. Next, based on the path delay of the first sub-paths and the difference between the expected total delay, a target delay corresponding to the reference path is determined, and based on the target delay, the alignment sub-paths corresponding to the reference path are routed to obtain second sub-paths corresponding to the reference path, and the delay of the second sub-paths is the same as the corresponding target delay. Finally, the first sub-paths and the second sub-paths corresponding to the reference path are combined to obtain a target path.

[0050] The transmission path of the target signal can be routed based on this method to obtain a target path, so that the delay of the target path is the expected total delay. The transmission paths of multiple target signals can also be routed based on this method, so that the delays of the multiple target paths are the expected total delay. In this way, the multiple target signals can be synchronized to arrive at the chip receiving end. It should be noted that the multiple target signals are transmitted from their corresponding starting logic devices to the chip receiving end at the same time.

[0051] In the prior art, the received specified signal is processed synchronously to realize the synchronization of subsequent processing of the specified signal. This method is relatively complex and consumes more resources.

[0052] The present application only adjusts the routing design of the reference path to obtain a target path with a delay of the expected total delay, which can achieve the simultaneous arrival of the target signal at the chip receiving end and meet the application requirement of target signal synchronization without the need for additional synchronization processing unit, thereby realizing the synchronization of the target signal at a low cost.

[0053] Please refer to Figure 2 which shows a method flowchart of a routing method provided by an embodiment of the present application. The method is applied to a programmable logic device, and specifically includes steps S210 to S280.

[0054] Step S210: obtaining a reference path and an expected total delay. The reference path is an initial transmission path of a target signal from a corresponding starting logic device to a terminal logic device.

[0055] In the foregoing embodiment, step S210 has been described in detail, and thus will not be described here.

[0056] Step S220: obtaining multiple logic devices distributed in the reference path and the arrangement order of each logic device.

[0057] It should be noted that the reference path is an initial transmission path of the target signal from the corresponding starting point logic device to the key logic device, and a plurality of logic devices are distributed on the reference path, wherein, the starting point logic device and the terminal logic device are also included, and the logic devices are sorted based on the order of the target signal passing through the logic devices, so as to obtain the arrangement order of each logic device.

[0058] Step S230: based on the arrangement order, the logic device adjacent to the terminal logic device is taken as the critical logic device.

[0059] Based on the arrangement order of each logic device, the logic device adjacent to the terminal logic device is taken as the critical logic device, that is, the second last logic device is taken as the critical logic device.

[0060] Step S240: based on the critical logic device, the reference path is divided into a corresponding fixed sub-path and an alignment sub-path, the fixed sub-path is a transmission path of the target signal from the starting point logic device to the output end of the critical logic device, and the alignment sub-path is a transmission path of the target signal from the output end of the critical logic device to the terminal logic device.

[0061] The schematic diagram of the reference path is shown in Figure 8 Based on the critical logic device, the reference path is divided into a fixed sub-path and an alignment sub-path, the transmission path of the target signal from the starting point logic device to the output end of the critical logic device is the fixed sub-path, and the transmission path of the target signal from the output end of the critical logic device to the terminal logic device is the alignment sub-path.

[0062] Step S250: the fixed sub-path is designed, and a first sub-path corresponding to the reference path is obtained.

[0063] Step S260: based on the difference between the path delay of the first sub-path and the expected total delay, a target delay corresponding to the reference path is determined.

[0064] Step S270: based on the target delay, the alignment sub-path of the reference path corresponding thereto is designed, and a second sub-path corresponding to the reference path is obtained, and the delay of the second sub-path is the same as the corresponding target delay.

[0065] Step S280: the first sub-path and the second sub-path corresponding to the reference path are combined to obtain a target path.

[0066] Among them, step S250 and step S280 have been described in detail in the foregoing embodiment, and will not be repeated here.

[0067] Further, the first sub-path is the shortest delay path of the corresponding fixed sub-path. The second sub-path can be obtained by adjusting the wiring of the alignment sub-path corresponding to the target delay, so that the path delay of the target path is the same as the expected total delay, thereby realizing that the delay of the target signal is the expected total delay.

[0068] Please refer to Figure 3 which shows a method flowchart of a wiring method provided by an embodiment of the present application, and the method is applied to a programmable logic device, and the method specifically includes steps S310 to S390.

[0069] Step S310: obtaining a reference path and an expected total delay, the reference path being an initial transmission path of a target signal from a corresponding starting logic device to a terminal logic device.

[0070] Step S320: dividing the reference path into a corresponding fixed sub-path and an alignment sub-path.

[0071] Step S330: performing wiring design on the fixed sub-path to obtain a first sub-path corresponding to the reference path.

[0072] Step S340: determining a target delay corresponding to the reference path based on the difference between the path delay of the first sub-path and the expected total delay.

[0073] Among them, step S310 and step S340 have been described in detail in the foregoing embodiments, and will not be repeated here.

[0074] Step S350: determining a candidate path based on the alignment sub-path of the reference path.

[0075] It should be noted that the wiring design on the alignment sub-path of the reference path obtains a candidate path. Specifically, since there are various wiring modes between adjacent logic devices, a plurality of legal transmission paths can be obtained by searching the transmission path of the alignment sub-path through existing wiring software, and a legal path is selected from the plurality of transmission paths as a candidate path. Among them, the legal path means that the timing constraints, path delay, power and ground line restrictions, crosstalk and interference, wiring resources, etc. of the path meet the requirements.

[0076] Step S360: judging whether the path delay of the candidate path is equal to the target delay.

[0077] The delay of the candidate path needs to be judged to determine whether the candidate path meets the requirements, and therefore, it is necessary to judge whether the delay of the candidate path is equal to the target delay.

[0078] Further, since there is minimum adjustable precision in the path delay adjustment in the process of routing design, it can be determined whether the difference between the path delay of the candidate path and the target delay is less than the allowable time difference. If the difference between the path delay of the candidate path and the target delay is less than the allowable time difference, it can be understood that the path delay of the candidate path is equal to the target delay, otherwise, the path delay of the candidate path is not equal to the target delay.

[0079] Step S370: If the path delay of the candidate path is equal to the target delay, the candidate path is taken as the second sub-path corresponding to the reference path.

[0080] If the path delay of the candidate path is equal to the target delay, it means that the candidate path meets the requirement, and the candidate path is taken as the second sub-path corresponding to the reference path.

[0081] Step S380: If the path delay of the candidate path is not equal to the target delay, the candidate path is routed to obtain a new candidate path, and the subsequent steps of determining whether the path delay of the candidate path is equal to the target delay are executed.

[0082] If the path delay of the candidate path is not equal to the target delay, it means that the candidate path does not meet the requirement, and the candidate path is routed to obtain a new candidate path, and the subsequent steps of determining whether the path delay of the candidate path is equal to the target delay are executed.

[0083] Step S390: The first sub-path and the second sub-path corresponding to the reference path are combined to obtain the target path.

[0084] Wherein, step S390 has been described in detail in the foregoing embodiments, and will not be described here.

[0085] Please refer to Figure 4 which shows a method flowchart of a routing method provided by the embodiment of the application, and the method is applied to a programmable logic device, and the method specifically includes steps S410 to S480.

[0086] Step S410: Obtain at least two reference paths.

[0087] That is, obtain the initial transmission paths of at least two target signals from the corresponding starting logic device to the ending logic device.

[0088] Step S420: Obtain the path delay of each reference path.

[0089] It should be noted that the routing of the reference path and the delay analysis of the routed reference path can be realized based on the existing software tool, and the path delay of the reference path can be obtained. Therefore, the path delay of the reference path can be obtained through the method.

[0090] Step S430: taking the maximum value in the path delay of each reference path as the expected total delay.

[0091] It should be noted that the reference path is the initial transmission path of the target signal from the corresponding starting point logic device to the terminal logic device. The path delays of each reference path can be different. The maximum value in the path delay of each reference path is taken as the expected total delay, which is the delay that needs to be reached, i.e., the path delay of each reference path needs to be adjusted to the expected total delay.

[0092] Step S440: dividing the reference path into a corresponding fixed sub-path and an alignment sub-path.

[0093] Step S450: performing wiring design on the fixed sub-path to obtain a first sub-path corresponding to the reference path.

[0094] Step S460: determining a target delay corresponding to the reference path based on the difference between the path delay of the first sub-path and the expected total delay.

[0095] Step S470: based on the target delay, performing wiring design on the alignment sub-path corresponding to the reference path to obtain a second sub-path corresponding to the reference path, the delay of the second sub-path being the same as the corresponding target delay.

[0096] Step S480: combining the first sub-path and the second sub-path corresponding to the reference path to obtain a target path.

[0097] Among them, step S440 and step S480 have been described in detail in the foregoing embodiments, which will not be repeated here.

[0098] Please refer to Figure 5 which shows a method flowchart of a wiring method provided by an embodiment of the present application, the method being applied to a programmable logic device, and the method specifically comprising steps S510 to S580.

[0099] Step S510: obtaining at least two reference paths.

[0100] Among them, step S510 has been described in detail in the foregoing embodiments, which will not be repeated here.

[0101] Step S520: obtaining the shortest path delay of each reference path.

[0102] It should be noted that the wiring of the reference path and the delay analysis of the wired reference path can be realized based on existing software tools, and the delay of the reference path can be obtained. There can be multiple wiring modes of the reference path, and the path delay corresponding to each wiring mode of the reference path can be obtained, so as to determine the shortest path delay of the reference path. The shortest path delay of each reference path is obtained in this way.

[0103] Step S530: taking the maximum value in the shortest path delay of each reference path as the expected total delay.

[0104] It should be noted that the reference path is the initial transmission path of the target signal from the corresponding start point logic device to the end point logic device. The path delay of each reference path can be different, and the maximum value in the shortest path delay of each reference path is taken as the expected total delay, which is the delay that needs to be reached, i.e., the path delay of each reference path needs to be adjusted to the expected total delay.

[0105] The present application determines the expected total delay through the shortest delay path of each reference path, so that the expected total delay is as short as possible, the transmission delay of the target signal from the start point logic device to the end point logic device is as short as possible, and the timing of the target signal is more optimal.

[0106] Step S540: dividing the reference path into the corresponding fixed sub-path and the alignment sub-path.

[0107] Step S550: performing the wiring design on the fixed sub-path to obtain the first sub-path corresponding to the reference path.

[0108] Step S560: determining the target delay corresponding to the reference path based on the difference between the path delay of the first sub-path and the expected total delay.

[0109] Step S570: performing the wiring design on the alignment sub-path corresponding to the reference path based on the target delay to obtain the second sub-path corresponding to the reference path, and the delay of the second sub-path is the same as the corresponding target delay.

[0110] Step S580: combining the first sub-path and the second sub-path corresponding to the reference path to obtain the target path.

[0111] Among them, step S540 and step S580 have been described in detail in the foregoing embodiments, and will not be repeated here.

[0112] Please refer to Figure 6 which shows a method flowchart of a wiring method provided by an embodiment of the present application, and the method is applied to a programmable logic device, and the method specifically includes steps S610 to S670.

[0113] Step S610: obtaining the reference path and the expected total delay, and the reference path is the initial transmission path of the target signal from the corresponding start point logic device to the end point logic device.

[0114] Step S620: dividing the reference path into the corresponding fixed sub-path and the alignment sub-path.

[0115] Step S630: routing design is performed on the fixed sub-path, to obtain a first sub-path corresponding to the reference path.

[0116] Step S640: based on a difference between the path delay of the first sub-path and the expected total delay, a target delay corresponding to the reference path is determined.

[0117] Step S650: based on the target delay, routing design is performed on the aligned sub-path of the reference path corresponding to the target delay, to obtain a second sub-path corresponding to the reference path, and the delay of the second sub-path is the same as the corresponding target delay.

[0118] Step S660: the first sub-path and the second sub-path corresponding to the reference path are combined to obtain a target path.

[0119] It should be noted that the steps S610 and S660 have been described in detail in the foregoing embodiments, and thus will not be described herein.

[0120] Step S670: the logic device corresponding to the target path and the routing parameters between adjacent logic devices are stored.

[0121] It should be noted that in the routing design, not only the reference path needs to be routed, but also the transmission path of other signals needs to be routed. Therefore, the reference path corresponding to the target signal needs to be routed first to obtain a target path, so that the delay of the target path is the expected total delay, and then the transmission path of other signals is routed. When the target path is obtained, the logic device corresponding to the target path and the routing parameters between adjacent logic devices are stored, and the target path is used as a basis for routing when the transmission path of other reference signals is routed, that is, the target path is kept unchanged.

[0122] Please refer to Figure 7 which shows a method flowchart of a routing method provided by an embodiment of the present application. The method is applied to a programmable logic device, and specifically includes steps S710 to S780.

[0123] Step S710: a plurality of reference paths are obtained, and the reference path is an initial transmission path of a target signal from a corresponding starting logic device to a terminal logic device.

[0124] The step S710 has been described in detail in the foregoing embodiments, and thus will not be described herein.

[0125] Step S720: each reference path is divided into a corresponding fixed sub-path and an aligned sub-path.

[0126] Each reference path is divided into a corresponding fixed sub-path and an aligned sub-path, and the detailed content can be referred to the foregoing embodiments.

[0127] Step S730: performing routing design on the fixed sub-path corresponding to each reference path to obtain a first sub-path with the shortest delay.

[0128] The existing layout routing tool can be used. After the transmission path of the reference path is designed, the layout routing tool can be used to analyze the delay of the reference path, and the layout routing tool can be used to perform routing design on the fixed sub-path corresponding to each reference path to obtain a first sub-path with the shortest delay.

[0129] Step S740: obtaining the total path delay of each reference path.

[0130] The existing layout routing tool can be used. After the transmission path of the reference path is designed, the layout routing tool can be used to analyze the delay of the reference path, and the layout routing tool can be used to perform routing design on the fixed sub-path corresponding to each reference path to obtain a first sub-path with the shortest delay.

[0131] Step S750: taking the maximum value in the total path delay of each reference path as the expected total delay.

[0132] The maximum value in the total path delay of each reference path is taken as the expected total delay.

[0133] Step S760: determining the target delay of the reference path based on the difference between the path delay of the first sub-path and the expected total delay.

[0134] Step S770: performing routing design on the aligned sub-path of the reference path based on the target delay to obtain a second sub-path corresponding to the reference path, and the delay of the second sub-path is the same as the target delay.

[0135] Steps S760 and S770 have been described in detail in the foregoing embodiments, and will not be described here.

[0136] Step S780: combining the first sub-path and the second sub-path corresponding to the reference path to obtain a target path.

[0137] The first sub-path and the second sub-path corresponding to the reference path are combined to obtain a target path, so that the path delay of the target path is equal to or approximately equal to the expected total delay. When the difference between the path delay of the target path and the expected total delay is within the allowable difference range, it is considered that the path delay of the target path is equal to the expected total delay.

[0138] Please refer to Figure 9 which shows a structural block diagram of a test device 600 provided by an embodiment of the present application. The test device 600 includes an obtaining unit 610, a dividing unit 620, a first routing unit 630, a calculating unit 640, a second routing unit 650, and a combining unit 660.

[0139] The acquisition unit 610 is configured to acquire a reference path and an expected total delay, the reference path being an initial transmission path of a target signal from a corresponding starting logic device to a terminal logic device.

[0140] Further, the acquisition unit 610 can also be configured to acquire at least two reference paths, acquire a path delay of each reference path, and take a maximum value in the path delays of each reference path as the expected total delay.

[0141] Further, the acquisition unit 610 can also be configured to acquire at least two reference paths, acquire a shortest path delay of each reference path, and take a maximum value in the shortest path delays of each reference path as the expected total delay.

[0142] Further, the first sub-path is a shortest delay path of the corresponding fixed sub-path.

[0143] The division unit 620 is configured to divide the reference path into a corresponding fixed sub-path and an alignment sub-path.

[0144] Further, the division unit 620 can also be configured to acquire a plurality of logic devices distributed in the reference path and an arrangement order of each logic device, take a logic device adjacent to the terminal logic device as a critical logic device based on the arrangement order, and divide the reference path into a corresponding fixed sub-path and an alignment sub-path, the fixed sub-path being a transmission path of the target signal from the starting logic device to an output end of the critical logic device, and the alignment sub-path being a transmission path of the target signal from the output end of the critical logic device to the terminal logic device.

[0145] The first wiring unit 630 is configured to perform wiring design on the fixed sub-path to obtain a first sub-path corresponding to the reference path.

[0146] The calculation unit 640 is configured to determine a target delay corresponding to the reference path based on a difference between a path delay of the first sub-path and the expected total delay.

[0147] The second wiring unit 650 is configured to perform wiring design on the alignment sub-path of the reference path corresponding to the target delay based on the target delay to obtain a second sub-path corresponding to the reference path, the delay of the second sub-path being the same as the corresponding target delay.

[0148] Further, the second wiring unit 650 can also be configured to determine an alternative path based on the alignment sub-path of the reference path, judge whether a path delay of the alternative path is equal to the target delay, take the alternative path as the second sub-path corresponding to the reference path if the path delay of the alternative path is equal to the target delay, perform wiring design on the alternative path to obtain a new alternative path if the path delay of the alternative path is not equal to the target delay, and return to execute the judgment of whether the path delay of the alternative path is equal to the target delay and the subsequent steps.

[0149] The combination unit 660 is configured to combine the first sub-path and the second sub-path corresponding to the reference path to obtain the target path.

[0150] Further, the combination unit 660 can also be configured to store the wiring parameters between the logic device corresponding to the target path and adjacent logic devices.

[0151] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the above-described device and module can refer to the corresponding process in the foregoing method embodiments, which will not be described here.

[0152] In several embodiments provided in the present application, the coupling between the modules can be electrical, mechanical or other forms of coupling.

[0153] In addition, each functional module in each embodiment of the present application can be integrated in one processing module, or each module can exist physically independently, or two or more modules can be integrated in one module. The integrated module can be realized in the form of hardware or in the form of a software functional module.

[0154] Please refer to Figure 10 which shows a structural block diagram of an electronic device 700 provided by an embodiment of the present application. The electronic device 700 can be a car machine system which can be arranged in a vehicle. The electronic device 700 in the present application can include one or more of the following components: a processor 711, a memory 712, and one or more application programs, wherein the processor 711 is electrically connected to the memory 712, and the one or more programs are configured to perform the method described in the foregoing method embodiments.

[0155] The processor 711 can include one or more processing cores. The processor 711 connects various parts within the entire electronic device 700 by running or executing instructions, programs, code sets or instruction sets stored in the memory 712, and calling data stored in the memory 712, to perform various functions and process data of the electronic device 700. Optionally, the processor 711 can be implemented in at least one of a hardware form of a digital signal processing (DSP), a field-programmable gate array (FPGA), a programmable logic array (PLA). The processor 711 can integrate a combination of one or several of a central processing unit (CPU), a graphics processing unit (GPU), and a modem. Among them, the CPU is mainly responsible for processing operating systems, user interfaces, and computer programs; the GPU is responsible for rendering and drawing display content; and the modem is responsible for processing wireless communication. It can be understood that the above-mentioned modem can also not be integrated into the processor 711, but can be implemented by a separate communication chip. Specifically, one or more processors 711 can execute the methods described in the foregoing embodiments.

[0156] For some embodiments, the memory 712 can include a random access memory (RAM) and can also include a read-only memory (ROM). The memory 712 can be used to store instructions, programs, codes, code sets or instruction sets. The memory 712 can include a program storage area and a data storage area, wherein the program storage area can store instructions for implementing an operating system, instructions for implementing at least one function, instructions for implementing each of the methods described below, etc. The data storage area can also store data created by the electronic device 700 in use, etc.

[0157] Please refer to Figure 11 which shows a structural block diagram of a computer readable medium provided by an embodiment of the present application. The computer readable medium 800 stores program codes therein, and the program codes can be called and executed by a processor to perform the methods described in the above method embodiments.

[0158] The computer readable medium 800 can be an electronic storage, such as a flash memory, EEPROM (electrically erasable programmable read-only memory), EPROM, hard disk or ROM. Alternatively, the computer readable medium 800 comprises a non-transitory computer-readable storage medium. The computer readable medium 800 has a storage space for the program code 810 to execute any of the method steps described above. These program codes can be read from or written to one or more computer program products. The program code 810 can be compressed, for example, in an appropriate form.

[0159] Finally, it should be noted that the above embodiments are merely used to illustrate the technical solutions of the present application, rather than limit the technical solutions of the present application; even though the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent replacements can be made to some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A wiring method, characterized in that, The method is applied to programmable logic devices, including: Obtain the reference path and the expected total delay. The reference path is the initial transmission path of the target signal from the corresponding starting logic device to the ending logic device. The reference path is divided into corresponding fixed sub-paths and aligned sub-paths; The routing design of the fixed sub-path is performed to obtain the first sub-path corresponding to the reference path; Based on the difference between the path delay of the first sub-path and the expected total delay, the target delay corresponding to the reference path is determined. Based on the target delay, routing design is performed on the aligned sub-path of the reference path corresponding to the target delay to obtain the second sub-path corresponding to the reference path. The delay of the second sub-path is the same as the corresponding target delay. The target path is obtained by combining the first sub-path and the second sub-path, which are both corresponding to the reference path. The step of dividing the reference path into corresponding fixed sub-paths and aligned sub-paths includes: Obtain the multiple logic devices distributed along the reference path and the arrangement order of each logic device; Based on the arrangement order, the logic devices adjacent to the terminal logic device are regarded as critical logic devices; Based on the critical logic device, the reference path is divided into corresponding fixed sub-paths and aligned sub-paths. The fixed sub-path is the transmission path of the target signal from the starting logic device to the output of the critical logic device, and the aligned sub-path is the transmission path of the target signal from the output of the critical logic device to the ending logic device. The step of designing a routing scheme for the aligned sub-path of the reference path corresponding to the target delay, based on the target delay, to obtain a second sub-path corresponding to the reference path, includes: Alignment of sub-paths with reference path to determine alternative paths; Determine whether the path delay of the alternative path is equal to the target delay; If the delay is equal to the target delay, the alternative path will be used as the second sub-path corresponding to the reference path. If the delay is not equal to the target delay, the routing design of the alternative path is performed to obtain a new alternative path. Then, the process returns to determine whether the path delay of the alternative path is equal to the target delay and proceed with subsequent steps.

2. The method according to claim 1, characterized in that, The first sub-path is the shortest delay path of the corresponding fixed sub-path.

3. The method according to claim 1, characterized in that, Obtain the reference path and expected total latency, including: Obtain at least two reference paths; Obtain the path delay for each reference path; The maximum value of the path delay for each reference path is used as the expected total delay.

4. The method according to claim 1, characterized in that, Obtain the reference path and expected total latency, including: Obtain at least two reference paths; Obtain the shortest path delay for each reference path; The maximum value among the shortest path delays of each reference path is used as the expected total delay.

5. The method according to claim 1, characterized in that, After combining the first and second sub-paths, which both correspond to the reference path, to obtain the target path, the following is also included: Store the logic devices corresponding to the target path and the wiring parameters between adjacent logic devices.

6. A wiring device, characterized in that, The device is used in programmable logic devices, including: The acquisition unit is used to acquire the reference path and the expected total delay. The reference path is the initial transmission path of the target signal from the corresponding starting logic device to the ending logic device. A partitioning unit is used to divide a reference path into corresponding fixed sub-paths and aligned sub-paths. Dividing the reference path into corresponding fixed sub-paths and aligned sub-paths includes: acquiring multiple logic devices distributed along the reference path and the arrangement order of each logic device; identifying logic devices adjacent to the endpoint logic device as critical logic devices based on the arrangement order; and dividing the reference path into corresponding fixed sub-paths and aligned sub-paths based on the critical logic devices. The fixed sub-path is the transmission path of the target signal from the starting logic device to the output of the critical logic device, and the aligned sub-path is the transmission path of the target signal from the output of the critical logic device to the endpoint logic device. The first wiring unit is used to design the wiring of the fixed sub-path to obtain the first sub-path corresponding to the reference path. The calculation unit is used to determine the target delay corresponding to the reference path based on the difference between the path delay of the first sub-path and the expected total delay. The second routing unit is used to design routing for the aligned sub-paths of the reference path corresponding to the target delay based on the target delay, to obtain a second sub-path corresponding to the reference path, wherein the delay of the second sub-path is the same as the corresponding target delay; the step of designing routing for the aligned sub-paths of the reference path corresponding to the target delay based on the target delay to obtain a second sub-path corresponding to the reference path includes: determining candidate paths based on the aligned sub-paths of the reference path; determining whether the path delay of the candidate path is equal to the target delay; if it is equal to the target delay, then the candidate path is used as the second sub-path corresponding to the reference path; if it is not equal to the target delay, then the routing for the candidate path is designed to obtain a new candidate path, and the process returns to the step of determining whether the path delay of the candidate path is equal to the target delay and subsequent steps. The combination unit is used to combine the first sub-path and the second sub-path, both of which correspond to the reference path, to obtain the target path.

7. An electronic device, characterized in that, include: One or more processors; Memory; One or more applications, wherein the one or more applications are stored in memory, the one or more applications are configured to be executed by one or more processors, and the one or more applications are configured to perform the method as claimed in any one of claims 1-5.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium contains program code that can be called by a processor to execute the method as described in any one of claims 1-5.

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