Signal Integrity Analysis and Optimization Methods Considering Electrothermal Coupling and Parasitic Effects in Artificial Intelligence Chips

Abstract

This invention discloses a signal integrity analysis and optimization method for artificial intelligence chips considering electrothermal coupling and parasitic effects. This method focuses on random access resistive memory (RRAM) cross-arrays in artificial intelligence chips, combining a compact RRAM model to study the impact of device electrothermal coupling and parasitic effects on signal integrity in the cross-array, conducting evaluation analysis, and proposing optimization schemes. The method includes: (1) establishing an equivalent thermal circuit network based on the compact model of the RRAM device to characterize the electrothermal coupling effect of the devices in the cross-array; (2) establishing an equivalent circuit model of interconnects containing parasitic resistance, capacitance, and inductance, and extracting parasitic parameters from the model using the Partial Component Equivalent Circuit (PEEC) method; (3) analyzing simulation results to achieve signal integrity evaluation considering electrothermal coupling and parasitic effects; and (4) proposing optimization schemes to address parasitic voltage drop and leakage path issues. This method has significant application value in random access resistive memory and neuromorphic brain-like chips.

Description

Technical Field

[0001] This invention relates to the fields of random resistive memory cross arrays and signal integrity modeling and simulation, and to a signal integrity analysis and optimization method for artificial intelligence chips that considers electrothermal coupling and parasitic effects. Background Technology

[0002] Theoretically, as the integration density of RRAM cross-connect arrays increases, the reduction in device size and spacing introduces two key problems: thermal crosstalk and parasitic effects. Due to electrothermal effects, the heat generated in the cells negatively impacts the stability and reliability of adjacent cells. Furthermore, parasitic effects between interconnects in the cross-connect array can lead to various signal integrity issues, including parasitic voltage drops, inter-neighbor crosstalk, and creeping paths. These problems directly affect the system's computational accuracy when the RRAM cross-connect array is used as a computing unit. Therefore, it is essential to model the electrothermal coupling and parasitic effects in RRAM cross-connect arrays to study the integrity issues within the array.

[0003] Currently, modeling and simulation based on the electrothermal coupling effect of devices mainly rely on commercial software or the finite element method for electrothermal simulation modeling. This approach suffers from low simulation efficiency when solving large-scale cross-arrays, and many compact models only consider internal self-heating effects while neglecting thermal crosstalk between devices in the array. Furthermore, current parasitic circuit models based on cross-arrays mostly utilize commercial software such as ANSYS Q3D and ANSYS HFSS, which also exhibit low simulation efficiency for parasitic effects in large-scale cross-arrays. Therefore, modeling and analyzing the electrothermal coupling and parasitic effects in random access resistive memory cross-arrays from a circuit perspective is essential. Currently, there are almost no circuit models that comprehensively consider both electrothermal and parasitic effects in random access resistive memory cross-arrays.

[0004] In recent years, numerous studies and reports have been published on the optimization of parasitic voltage drop and leakage paths. For example, for neural network computation, voltage compensation is achieved during offline learning by changing weight values ​​to map the resistance values ​​in the memory, or by stimulating both ends separately to mitigate the voltage drop effect of intermediate cells; resistance state reading under leakage paths can be achieved through a three-write scheme, grounding, or complex circuit connection schemes. However, currently available solutions to the parasitic voltage drop problem are limited to complex algorithm corrections and specific application scenarios, while read schemes to solve the creeping path problem in cross-arrays are limited by power consumption, number of writes, and circuit connection complexity. Therefore, more efficient solutions are needed to alleviate the parasitic voltage drop and creeping path problems. This invention is based on a general compact model of the device, constructs an equivalent thermal circuit network through thermal resistance and thermal capacitance, then establishes an interconnect parasitic model including parasitic resistance, capacitance, and inductance, and uses a partial component equivalent circuit method to achieve efficient extraction of parasitic parameters. Furthermore, it presents a signal integrity analysis considering electrothermal coupling and parasitic effects for random resistive memory cross-arrays in artificial intelligence chips, and an optimization scheme for parasitic voltage drop and leakage paths. This method is applicable to random resistive memory cross-array structures of any size. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a signal integrity analysis and optimization method for artificial intelligence chips that considers electrothermal coupling and parasitic effects.

[0006] The technical solution adopted in this invention is as follows:

[0007] A signal integrity analysis and optimization method for artificial intelligence chips considering electrothermal coupling and parasitic effects mainly includes:

[0008] Based on a compact model of random resistive RAM (RRAM), an equivalent thermal circuit network was established using thermal resistance and thermal capacitance to characterize the electrothermal effects of devices in the cross array.

[0009] A parasitic equivalent circuit model between interconnects in a cross array is established using parasitic resistance, capacitance, and inductance components, and the values ​​of parasitic components are solved using the partial component equivalent circuit method.

[0010] Based on the comprehensive circuit model that considers electrothermal coupling and parasitic effects, signal integrity analysis is further performed on a 1MB (1024×1024) cross-array memory using circuit simulation software such as SPICE. This allows for the evaluation of performance factors such as thermal crosstalk, parasitic voltage drop, parasitic crosstalk, and leakage current, which can then guide optimization.

[0011] In the above technical solution, a compact memory model is further established based on the changes in conductive filaments. The electrical power of the RRAM and control elements is calculated as a heat source based on the compact model. The thermal resistance and thermal capacity of the device are calculated to obtain an equivalent thermal circuit model. The heat source is coupled to the equivalent thermal circuit network to calculate the temperature distribution of the device. The temperature is coupled to the compact memory model to update the electrical characteristics and obtain the updated electrical power. The above process is iterated until convergence is achieved.

[0012] Furthermore, an RLC parasitic circuit model of the interconnects in the cross array is established, including the parasitic resistance of the interconnects, the capacitance to ground and mutual capacitance of the interconnects, and the self-inductance and mutual inductance between the interconnects. The parasitic resistance, parasitic capacitance and parasitic inductance parameter values ​​are calculated using the partial component equivalent circuit method.

[0013] Furthermore, when calculating parasitic capacitance and parasitic inductance parameters using the partial component equivalent circuit method, the discrete interconnects are divided into several rectangular blocks, i.e., block units. In the capacitance and inductance calculations, only the four outer surfaces of the interconnects of each rectangular block are considered.

[0014] Furthermore, based on the above integrity analysis, optimizations can be made for parasitic voltage drop and leakage path issues. For parasitic voltage drop, the relationship between the voltage drop and the storage location of the device can be analyzed to further correct and compensate for the parasitic voltage drop in the array. For leakage path issues, a new current reading method under leakage path can be set, and the correct identification of the resistance state of the storage device can be achieved by combining the setting of reference cells with grounding.

[0015] Compared with the prior art, the present invention has the following beneficial effects:

[0016] 1. This invention provides a signal integrity analysis and optimization method for artificial intelligence chips that considers electrothermal coupling and parasitic effects. Compared with the traditional finite element method, this method can simultaneously simulate temperature distribution in the device, thermal crosstalk between devices, parasitic voltage drop and inter-neighbor crosstalk, leakage path current, etc., to evaluate the comprehensive impact of signal integrity problems on computing performance. It has guiding significance for further improving the computing performance of the system and has important application value in random access resistive memory and neuromorphic computing chips.

[0017] 2. In this invention, an equivalent thermal circuit network is used to characterize the electrothermal coupling effect of the device, and a partial component equivalent circuit method is used to solve the parasitic parameters. By modeling at the circuit level, the modeling efficiency and simulation speed can be greatly improved.

[0018] 3. The present invention uses a combination of fitting and testing to achieve effective correction and compensation of parasitic voltage drop, and optimizes the leakage path problem by combining the setting of reference units and grounding, so as to achieve accurate storage state identification. Attached Figure Description

[0019] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0020] Figure 1 This invention provides a typical random resistive memory cross-array structure. The array size in the figure is 3×3. The non-ideal effects in the array include random noise, thermal crosstalk, IR voltage drop, crosstalk, and creep path.

[0021] Figure 2 A flowchart illustrating the signal integrity modeling, simulation, and optimization scheme for a random resistive memory cross-array considering electrothermal and parasitic effects provided by this invention.

[0022] Figure 3 The equivalent thermal circuit model diagram of the resistor-diode series structure (1D1R) unit containing thermal resistance and thermal capacitance provided by the present invention is shown in the figure. The red part represents the vertical thermal resistance, and the black part corresponds to the horizontal thermal resistance and capacitance on the right side of the 1D1R battery. The horizontal thermal resistance and capacitance in the front-back and left directions are the same as those in the right direction.

[0023] Figure 4 The present invention provides a parasitic equivalent circuit model containing parasitic resistance, capacitance, and inductance. Among them, (a) is the parasitic equivalent circuit of interconnects in the array, and (b) is a schematic diagram of discrete interconnects as three rectangular blocks when using the partial component equivalent circuit method. In the capacitance and inductance calculation, only the four surfaces of each rectangular block are considered.

[0024] Figure 5 The temperature distribution of the 1D1R unit during operation in this embodiment of the invention is shown in (a), where (a) is the temperature distribution of the 1D1R unit in COMSOL, and (b) is the relationship between the equivalent thermal circuit and the temperature of the memory center in COMSOL as a function of power consumption.

[0025] Figure 6 This is a diagram showing the thermal crosstalk of the array under worst-case conditions in an embodiment of the present invention, wherein (a) is a schematic diagram of the array operating under worst-case conditions, and (b) is the relationship between thermal crosstalk and device spacing and device size.

[0026] Figure 7The following are examples of the voltage variation with device position under different numbers and values ​​of low-resistance state units in the embodiments of the present invention, where (a) is the voltage variation with device position under different resistance values, and (b) is the voltage variation with device position under different numbers of low-resistance state units.

[0027] Figure 8 The parasitic inter-neighbor crosstalk changes with the input pulse in this embodiment of the invention, wherein (a) is the change relationship of crosstalk in different columns in adjacent rows with time, and (b) is the change relationship of parasitic crosstalk in the last column of the three adjacent rows closest to the input row with time.

[0028] Figure 9 This illustrates the relationship between array leakage current and array size in an embodiment of the present invention.

[0029] Figure 10 This refers to the error in voltage correction based on the exponential relationship between voltage drop and device position fitting under different numbers of low-resistivity units in the embodiments of the present invention.

[0030] Figure 11 This is a schematic diagram of a current reading scheme that combines a reference column with grounding in an embodiment of the present invention. Detailed Implementation

[0031] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.

[0032] This paper selects a typical random resistive memory cross-array structure, taking the 1D1R cell as an example, and comprehensively and in detail describes the signal integrity modeling and analysis method considering electrothermal coupling and parasitic effects in this array. It also introduces the optimization scheme for parasitic voltage drop and leakage path, which is applicable to neural computing systems or artificial intelligence chips such as memory and neuromorphic chips composed of random resistive memory cross-array structures.

[0033] According to a specific example of the present invention, the signal integrity modeling and analysis method for random resistive memory cross-arrays considering electrothermal coupling and parasitic effects includes the following steps:

[0034] Step 1: Calculate the electrical power of the RRAM and diode based on the 1D1R compact model, and couple it as a heat source to the equivalent thermal circuit network to calculate the temperature distribution of the device; couple the temperature into the compact model of the 1D1R unit to update the electrical characteristics, and these iterative processes continue until convergence is achieved, where the boundary conditions of the equivalent thermal circuit network are set to room temperature (300K). The governing equations for this solution process are listed in Table 1.

[0035] Step 2: Establish an equivalent circuit model of the interconnects in the array containing parasitic resistance, capacitance, and inductance, including the self-parasitic resistance of the interconnects, the capacitance to ground and inter-line mutual capacitance of the interconnects, and the self-inductance and inter-line mutual inductance of the interconnects. Calculate the parasitic parameter values ​​using the partial component equivalent circuit method. The governing equations for this solution process are listed in Table 1. The model based on the thermal circuit network and parasitic circuit model can simultaneously analyze the overall impact of signal integrity issues such as electrothermal coupling and parasitic effects on the computational accuracy of the neuromorphic chip during device operation.

[0036] Step 3: Signal Integrity Analysis. Steps 1 and 2 are implemented and simulated in the circuit simulation software SPICE. The simulation results yield the array's thermal crosstalk, parasitic voltage drop, parasitic inter-neighbor crosstalk, and leakage current.

[0037] Step 4: Based on the analysis in Step 3, the relationship between voltage drop and device location in the simulation results is studied, and an exponential relationship is fitted. The fitted parameters are then accurately solved using testing, thereby enabling accurate correction of voltage drop at different device locations. Furthermore, by combining a reference cell with grounding, the correct identification of resistance status under leakage paths can be achieved. The governing equations for this model are listed in Table 1.

[0038] Table 1. Governing equations in the model

[0039]

[0040]

[0041] The symbols and terms used in the text are shown in Table 2.

[0042] Table 2. Symbols and terms appearing in the text

[0043]

[0044]

[0045]

[0046] like Figure 2As shown, a flowchart for signal integrity modeling and simulation of a random access resistive memory (RRAM) cross-array in an artificial intelligence chip is provided. First, the electrical power of the RRAM and diodes is calculated as heat sources based on the 1D1R compact model (Equation 1-5). All fitting parameters in the compact model are determined by fitting experimental voltage-current curves.

[0047] Step 2: Calculate the thermal resistance and thermal capacity of the device (Equation 6-8), couple the heat source to the equivalent thermal circuit network to calculate the temperature distribution of the device; couple the temperature to the compact model of the 1D1R element to update the electrical characteristics, and these iterative processes continue until convergence is achieved, where the boundary conditions of the equivalent thermal circuit network are set to room temperature (300K). The governing equations for this solution process are listed in Table 1.

[0048] Step 3: Establish the RLC parasitic circuit model of the interconnects in the array, including the parasitic resistance of the interconnects, the capacitance to ground and mutual capacitance of the interconnects, and the self-inductance and mutual inductance between the interconnects. Calculate the parasitic resistance (Equation 9), parasitic capacitance (Equations 10-13), and parasitic inductance (Equation 14) parameters using the partial component equivalent circuit method. The governing equations for this solution process are listed in Table 1.

[0049] Step 4: Signal Integrity Analysis. Steps 1 and 2 are implemented and simulated in the circuit simulation software SPICE. The simulation results yield the array's thermal crosstalk, parasitic voltage drop, parasitic inter-neighbor crosstalk, and leakage path. Furthermore, based on the voltage drop variation with device location in the circuit simulation, an exponential fit is performed (Equations 15-16). Combining this with test results to solve the fitting parameters allows for accurate correction of the voltage drop at different device locations. Additionally, by setting a reference cell combined with grounding (Equations 17-18), the correct identification of the resistance state under the leakage path can be achieved. The governing equations for this model are listed in Table 1.

[0050] like Figure 3 As shown, the equivalent thermal circuit network of the 1D1R unit, composed of thermal resistance and thermal capacitance, in step two is provided in the vertical and right horizontal directions. The red part represents the vertical thermal resistance, and the black part corresponds to the horizontal thermal resistance and capacitance on the right side of the 1D1R unit. The horizontal thermal resistance and capacitance in the front-back and left directions are the same as above.

[0051] for Figure 3 The relevant parameters used in the simulation of the example are listed in Table 3.

[0052] Table 3. Relevant parameters for thermal resistance calculation

[0053] Parameters (units) value <![CDATA[d CF (nm)]]> 80 <![CDATA[d diode (nm)]]> 50 <![CDATA[r CF (nm)]]> 8 <![CDATA[r diode (nm)]]> 40 <![CDATA[k CF (w / (m·k))]]> 0.5 <![CDATA[k diode (w / (m·k))]]> 22 <![CDATA[c CF (J / (kg·k))]]> 445 <![CDATA[c diode (J / (kg·k))]]> 710 <![CDATA[ρ CF (kg / m 3 )]]> <![CDATA[8.9×10 3 ]]> <![CDATA[ρ diode (kg / m 3 )]]> <![CDATA[4.17×10 3 ]]>

[0054] like Figure 4The figure shows the equivalent parasitic circuit model in a crossbar switch array. The parasitic elements in the model include the parasitic resistance (R) and self-inductance (L) of the word lines and bit lines. sw L sb ) and self-capacitance (C sw C sb Mutual inductance between adjacent word lines and adjacent bit lines (L) mw L mb ) and mutual capacitance (C mw C mb The mutual capacitance (C) between the word line and the bit line. mwb ).

[0055] for Figure 4 The relevant parameters are listed in Table 4.

[0056] Table 4 Interconnect Size and Parasitic Parameter Values

[0057]

[0058]

[0059] Figure 5 The temperature at the center of the hot node n1 calculated by COMSOL and the thermal network is almost identical to the change in CF power consumption, which verifies the accuracy of the device's equivalent thermal circuit. Figure 6 This shows the relationship between thermal crosstalk of a 1D1R cell under worst-case operation and the device spacing and size. As the device spacing decreases, thermal crosstalk becomes more severe, and the change in thermal crosstalk is even more drastic within a 50nm device spacing. Furthermore, due to differences in thermal resistance, the diode size also has a significant impact on thermal crosstalk. Figure 7 This diagram shows the voltage variation with device position under different numbers and values ​​of low-resistance cells. It reveals that the resistance of high-resistance cells has little impact on parasitic voltage drop, while the resistance of low-resistance cells has a significant impact. Furthermore, when all cells are in high-resistance states, the voltage drop is relatively slow, with the bias voltage of the 1024th cell decreasing by only 32%. However, as the number of low-resistance cells increases, the trend of parasitic voltage drop deteriorates sharply. Figure 8 This represents the relationship between parasitic inter-row crosstalk in the array and the input pulse. The larger the array size, the more severe the crosstalk between adjacent rows or columns becomes due to the series and parallel relationship of parasitic capacitance and inductance. For Figure 5-8 The relevant parameters used in the simulation of the example are listed in Table 4.

[0060] Figure 9As the leakage current varies with array size, the creeping current increases with increasing array size, making it increasingly difficult to identify the resistance state of the selected cells. Furthermore, the creeping path current is significantly higher when all cells are in a low-resistance state than when all cells are in a high-resistance state. Figure 10 For different numbers of low-resistivity cells, the error in voltage correction based on the exponential relationship between voltage drop and device position is calculated at V. read At 350mV, the voltage correction error is within 10mV for different numbers of low-resistivity cells. For Figure 10 The relevant parameters used in the simulation of the example are listed in Table 5. Figure 11 This is a schematic diagram of a current reading scheme that combines a reference column with grounding.

[0061] Table 5. Exponential Fit Relationship between Parasitic Voltage Drop and Device Location (Parameters)

[0062]

[0063] Simulation results on signal integrity show that thermal crosstalk and parasitic effects between devices can significantly interfere with signal transmission and detection. There is still considerable room for optimization in device structure and circuit design, and more efficient signal integrity optimization and calibration schemes deserve further exploration. The signal integrity analysis and optimization method considering electrothermal coupling and parasitic effects provided in this invention has significant application value in random access resistive memories and neuromorphic brain-like chips.

[0064] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A signal integrity analysis and optimization method for artificial intelligence chips considering electrothermal coupling and parasitic effects, characterized in that, include: For random resistive memory cross-arrays in artificial intelligence chips, an equivalent thermal circuit network is established based on a compact model of random resistive memory devices (RRAM) to characterize the electrothermal coupling effect of devices in the cross-array. A parasitic equivalent circuit model between interconnects in a cross array is established using parasitic resistance, capacitance, and inductance components, and the values ​​of parasitic components are solved using the partial component equivalent circuit method. Taking into account electrothermal coupling and parasitic effects, based on the equivalent thermal circuit network and parasitic equivalent circuit model, signal integrity analysis is performed on the cross-array memory using circuit simulation software to evaluate the influencing factors and variation patterns of thermal crosstalk, parasitic voltage drop, parasitic inter-neighbor crosstalk, and leakage current, so as to guide optimization.

2. The signal integrity analysis and optimization method for artificial intelligence chips considering electrothermal coupling and parasitic effects according to claim 1, characterized in that, A compact model of the memory is established based on the changes in the conductive filaments. The electrical power of the RRAM and control elements is calculated based on the compact model as a heat source. The thermal resistance and thermal capacity of the device are calculated to obtain an equivalent thermal circuit model. The heat source is coupled to the equivalent thermal circuit network to calculate the temperature distribution of the device. The temperature is coupled to the compact model of the memory to update the electrical characteristics and obtain the updated electrical power. The above process is iterated until convergence is achieved. The boundary condition of the equivalent thermal circuit network is set to room temperature, i.e., 300K.

3. The signal integrity analysis and optimization method for artificial intelligence chips considering electrothermal coupling and parasitic effects according to claim 2, characterized in that, The change of the conductive filament over time in the compact memory model is as follows: Where g is the distance between the conductive filament and the electrode, v0 is the fitting parameter, and E a The activation energy is T, where k is the Boltzmann constant. CF T is the temperature of the conductive filament. CF = T0 + ΔT, where T0 is room temperature, ΔT is the temperature change, and γ is the field enhancement factor, γ = γ0 - β·g 3 γ0 and β are both fitting parameters, a0 is the effective jump distance, and t ox Where q is the oxide layer thickness, q is the elementary charge, and V is the electric potential; The current equation of the device: I0, g0, and V0 are all fitting parameters.

4. The signal integrity analysis and optimization method for artificial intelligence chips considering electrothermal coupling and parasitic effects according to claim 1, characterized in that, An RLC parasitic circuit model of interconnects in a cross array is established, including the parasitic resistance of interconnects, the capacitance to ground and mutual capacitance of interconnects, and the self-inductance and mutual inductance between interconnects. The parasitic resistance, parasitic capacitance and parasitic inductance parameter values ​​are calculated using the partial component equivalent circuit method.

5. The signal integrity analysis and optimization method for artificial intelligence chips considering electrothermal coupling and parasitic effects according to claim 4, characterized in that, The parasitic resistance R of the interconnect is: ρ is the mass density of the interconnect, l is the length of the interconnect, and s is the cross-sectional area of ​​the interconnect. Parasitic capacitance and inductance parameters are calculated using the partial component equivalent circuit method. When using this method, the discrete interconnects are represented as several rectangular blocks, or modular units. In the capacitance and inductance calculations, only the four outer surfaces of the interconnects within each rectangular block are considered. Specifically, these include: [Cs]=[P] -1 Among them, C s Let P be the short-circuit capacitance matrix of the interconnects, and let P be the potential coefficient matrix. The elements of the matrix are: ε is the dielectric constant, S i S j Let r be the planar area in the block unit of the interconnect, g(r,r′) be the scalar Green's function, r be the coordinates of the source point, and r′ be the coordinates of the target point. For any three adjacent rectangular blocks a, b, and c obtained after discretizing word lines or bit lines, the outer surfaces of the four interconnects in rectangular block a are defined as surfaces 1 to 4, the outer surfaces of the four interconnects in rectangular block b are defined as surfaces 5 to 8, and the outer surfaces of the four interconnects in rectangular block c are defined as surfaces 9 to 12. The capacitance matrix formula is as follows: Among them, Cs aa Cs bb Cs cc Cs represents the self-capacitance between the block cell surfaces of the interconnect. ab Cs bc Cs ac Cs ba Cs cb Cs ca Cs represents the mutual capacitance between the block cell surfaces of the interconnect. ij The interplane capacitance of the block unit of the interconnect; The self-capacitance and mutual capacitance of each of the three rectangular blocks are as follows: For any two rectangular blocks: Among them, L ij Let μ be the parasitic inductance between two rectangular blocks i and j, μ0 be the free permeability, and a be the inductance between them. i and a j These are the cross-sectional areas of the two rectangular blocks perpendicular to the signal transmission direction, l i and l j These are the lengths of the two rectangular blocks along the signal transmission direction, V and V. i and V j Let be the volumes of the two rectangular blocks respectively.

6. The signal integrity analysis and optimization method for artificial intelligence chips considering electrothermal coupling and parasitic effects according to claim 1, characterized in that, To address the parasitic voltage drop problem, a fitting relationship analysis is performed between the voltage drop and the storage location of the devices, thereby further correcting and compensating for the parasitic voltage drop in the array; the fitting relationship can be any of the following: V d =V read yes -pn Among them, V d For parasitic voltage drop, p1, p2, p3, and p are all fitting parameters, V read The voltage to be read is given, and n is the device location.

7. The signal integrity analysis and optimization method for artificial intelligence chips considering electrothermal coupling and parasitic effects according to claim 1, characterized in that, To address the leakage path issue, a method combining reference cell setting and grounding is employed to correctly identify the resistance state of storage devices. The current reading method under leakage path conditions is as follows: I j =Is j +Ir j Among them, I j Let Is be the output current of the j-th column cell. j Let Ir be the leakage current of the j-th column cell. j To read the current of the j-th column cell, I sum The total leakage current is the sum of the first n-2 columns.

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