Circuit structure of self-starting bit cell SRAM write assist, storage array and SRAM

Abstract

The present application relates to a circuit structure, a storage array and an SRAM for self-starting bit unit SRAM write assistance, wherein the circuit structure includes: a first inverter and a second inverter, the input end of the first inverter is connected to the first bit line, and the input end of the second inverter is connected to the second bit line; a first NMOS tube and a second NMOS tube, the gate of the first NMOS tube is connected to the output end of the first inverter, the drain of the first NMOS tube is connected to the first bit line, the source of the first NMOS tube is grounded, the gate of the second NMOS tube is connected to the output end of the second inverter, the drain of the second NMOS tube is connected to the second bit line, and the source of the second NMOS tube is grounded. The problem that the write-assist circuit on the periphery of the current storage array will increase the difficulty of SRAM circuit layout and greatly increase the circuit area occupied is solved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular to a circuit structure, a storage array and an SRAM for self-starting bit cell SRAM write assistance. Background Art

[0002] The demand for low-power and high-performance system-on-chips (SoCs) continues to increase to cope with the recent exponentially growing computational load of machine learning and improve the battery life of mobile devices. In SoCs, the area occupied by embedded static random access memory (SRAM) is a large part, and therefore, SRAM has a dominant impact on the total power, performance, and area. For applications that process a large amount of data in a limited area, such as mobile and graphics applications, the need for high-density SRAM becomes more obvious. The SRAM cell area has gradually decreased with the expansion of technology to achieve the goal of high density. However, there are new problems in SRAM design due to interconnect resistance. In technology nodes below 5nm, the interconnect cross-sectional area is reduced due to grain boundary scattering and surface scattering, and the electron mobility is reduced, resulting in an exponential increase in interconnect resistance. This is despite the reduction in bit line length driven by scaling. The exponential increase in interconnect resistance leads to an increase in the bit line resistance of each memory array, making it impossible for the bit line to be fully discharged, that is, the potential still exists at the position of the bit line far away from the ground terminal, resulting in a decrease in the writability of the memory array, which greatly affects the performance of SRAM.

[0003] In response to the above technical problems, currently, independent write assist circuits are mainly set outside the memory array to assist the discharge of the bit lines of the memory array. These write assist circuits cannot be directly applied to the memory array. Therefore, the current write assist circuits outside the memory array will increase the difficulty of SRAM circuit layout and significantly increase the circuit area occupied.

[0004] Currently, no effective solution has been proposed to the problem that the write assist circuit on the periphery of the current storage array will increase the difficulty of SRAM circuit layout and significantly increase the circuit area occupied. Summary of the invention

[0005] The present invention provides a circuit structure of a self-starting bit cell SRAM write assist, a storage array and an SRAM to solve the problem that the current write assist circuit around the storage array increases the difficulty of SRAM circuit layout and greatly increases the circuit area occupied.

[0006] In a first aspect, the present invention provides a circuit structure of a self-starting bit cell SRAM write assist, which is applied to a memory array of an SRAM, wherein the memory array comprises a first bit line, a second bit line, and a plurality of memory cells, wherein the memory cells implement data writing through the first bit line and the second bit line, and the circuit structure is used to discharge the first bit line and the second bit line and comprises:

[0007] A first inverter and a second inverter, wherein an input terminal of the first inverter is connected to the first bit line, and an input terminal of the second inverter is connected to the second bit line;

[0008] A first NMOS tube and a second NMOS tube, wherein the gate of the first NMOS tube is connected to the output end of the first inverter, the drain of the first NMOS tube is connected to the first bit line, the source of the first NMOS tube is grounded, the gate of the second NMOS tube is connected to the output end of the second inverter, the drain of the second NMOS tube is connected to the second bit line, and the source of the second NMOS tube is grounded.

[0009] In a second aspect, the present invention provides a storage array of an SRAM, comprising:

[0010] A first bit line and a second bit line;

[0011] A plurality of storage units, wherein data is written into the storage units through the first bit line and the second bit line;

[0012] At least one circuit structure of the self-starting bit cell SRAM write assist according to the first aspect, the circuit structure is used to discharge the first bit line and the second bit line;

[0013] Wherein, an input end of the first inverter in the circuit structure is connected to the first bit line, and an input end of the second inverter in the circuit structure is connected to the second bit line.

[0014] Compared with the related art, the circuit structure of the self-starting bit unit SRAM write assist provided by the present invention can be directly arranged in the storage array of the SRAM due to its simple structure and relatively matching storage array, that is, the circuit structure is directly arranged between the first bit line and the second bit line, and provides an additional discharge path for the first bit line and the second bit line, thereby improving the writability of the storage array and the performance of the SRAM. Moreover, the circuit structure automatically adjusts the opening and closing state of the corresponding discharge path according to the potential state of the bit line. Therefore, the write assist circuit structure provided by the present invention, on the basis of providing an additional discharge path, does not significantly increase the circuit layout difficulty and circuit area occupied by the SRAM, thereby solving the problem that the write assist circuit outside the current storage array will increase the circuit layout difficulty of the SRAM and significantly increase the circuit area occupied.

[0015] Details of one or more embodiments of the present application are set forth in the following drawings and description to make other features, objects, and advantages of the present application more readily apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic diagram of the circuit structure of a self-starting bit unit SRAM write assist in one embodiment of the present invention;

[0017] Figure 2 It is a schematic diagram of a circuit structure of a self-starting bit cell SRAM write assist for assisting discharge of a first bit line in one embodiment of the present invention;

[0018] Figure 3 It is a schematic diagram of a circuit structure of a self-starting bit unit SRAM write assist in performing assistive discharge on a second bit line in one embodiment of the present invention;

[0019] Figure 4 It is a schematic diagram of a circuit structure module of a self-starting bit unit SRAM write assist in one embodiment of the present invention. DETAILED DESCRIPTION

[0020] In order to more clearly understand the purpose, technical solutions and advantages of the present application, the present application is described and illustrated below in conjunction with the accompanying drawings and embodiments.

[0021] Unless otherwise defined, the technical terms or scientific terms involved in this application shall have the general meaning understood by people with ordinary skills in the technical field to which this application belongs. The words "one", "a", "a", "the", "these" and the like in this application do not indicate a quantitative limitation, and they may be singular or plural. The terms "include", "comprise", "have" and any variants thereof involved in this application are intended to cover non-exclusive inclusions; for example, a process, method and system, product or device comprising a series of steps or modules (units) is not limited to the listed steps or modules (units), but may include unlisted steps or modules (units), or may include other steps or modules (units) inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether short-circuited or indirect. The "multiple" involved in this application refers to two or more. "And / or" describes the association relationship of associated objects, indicating that there may be three relationships, for example, "A and / or B" may mean: A exists alone, A and B exist at the same time, and B exists alone. Generally, the character " / " indicates that the objects associated with each other are in an "or" relationship. The terms "first", "second", "third", etc. in this application are only used to distinguish similar objects and do not represent a specific ordering of the objects.

[0022] The present invention provides a self-starting bit cell SRAM write assist circuit structure, which is applied to the storage array of SRAM. Figure 2 and Figure 3 , the storage array includes a first bit line BL, a second bit line BLB and a plurality of storage cells, and the storage cell implements data writing through the first bit line BL and the second bit line BLB. The storage cell has a first storage node and a second storage node. In a single storage array, the first storage nodes of the plurality of storage cells are respectively connected to the same first bit line BL through a switching device, and the second storage nodes of the plurality of storage cells are respectively connected to the same second bit line BLB through a switching device. The potential relationship between the first storage node and the second storage node can be adjusted through the first bit line BL and the second bit line BLB, thereby causing the data stored in the storage cell to change. This part is an existing mature storage array structure, and this article will not explain it further.

[0023] Reference Figure 1The circuit structure is used to discharge the first bit line BL and the second bit line BLB and includes a first inverter and a second inverter, a first NMOS tube N1 and a second NMOS tube N2. The input end of the first inverter is connected to the first bit line BL, and the input end of the second inverter is connected to the second bit line BLB; the gate of the first NMOS tube N1 is connected to the output end of the first inverter, the drain of the first NMOS tube N1 is connected to the first bit line, the source of the first NMOS tube N1 is grounded, the gate of the second NMOS tube N2 is connected to the output end of the second inverter, the drain of the second NMOS tube N2 is connected to the second bit line BLB, and the source of the second NMOS tube N2 is grounded.

[0024] For the above circuit structure, the first NMOS tube N1 and the second NMOS tube N2 respectively constitute the discharge path of the first bit line BL and the second bit line BLB. When the storage unit performs a write operation, the first bit line BL and the second bit line BLB need to be charged and discharged respectively. For example, the first bit line BL is charged to be at a high potential and the second bit line BLB is discharged to be at a low potential, so that the first storage node in the selected storage unit is at a high potential and the second storage node is at a low potential.

[0025] When the first bit line BL is connected to the input terminal of the first inverter and the drain of the first NMOS transistor N1 respectively, if the first bit line BL is charged at a high potential (the first bit line does not need to be discharged at this time), the first inverter outputs a low potential, thereby turning off the first NMOS transistor N1. At this time, the first NMOS transistor N1 does not provide a discharge path for the first bit line BL. Figure 2 When the first bit line BL is discharged and is at a low potential (the first bit line is discharging at this time), the first inverter outputs a high potential, thereby turning on the first NMOS tube N1. At this time, the first NMOS tube N1 provides a discharge path for the first bit line BL. The discharge path is an additional discharge path for the first bit line BL (in conventional designs, one end of the bit line is grounded through a switch), thereby making the discharge of the first bit line BL more thorough, that is, the potential is closer to 0, thereby greatly improving the probability of successful writing of "1".

[0026] When the second bit line BLB is connected to the input end of the second inverter and the drain of the second NMOS transistor N2 respectively, if the second bit line BLB is charged at a high potential (the second bit line does not need to be discharged at this time), the second inverter outputs a low potential, thereby turning off the second NMOS transistor N2. At this time, the second NMOS transistor N2 does not provide a discharge path for the second bit line BLB. Figure 3When the second bit line BLB is discharged and is at a low potential (the second bit line is discharging at this time), the second inverter outputs a high potential, thereby turning on the second NMOS tube N2. At this time, the second NMOS tube N2 provides a discharge path for the second bit line BLB, which is an additional discharge path for the second bit line BLB (in conventional designs, one end of the bit line is grounded through a switch), thereby making the discharge of the second bit line BLB more thorough, that is, the potential is closer to 0, thereby greatly improving the probability of successful writing of "0".

[0027] In summary, the circuit structure of the self-starting bit unit SRAM write assist provided by the present invention can be directly arranged in the storage array of the SRAM due to its simple structure and relatively matching storage array, that is, the circuit structure is directly arranged between the first bit line and the second bit line, and provides an additional discharge path for the first bit line and the second bit line, thereby improving the writability of the storage array and the performance of the SRAM. Moreover, the circuit structure automatically adjusts the opening and closing state of the corresponding discharge path according to the potential state of the bit line. Therefore, the write assist circuit structure provided by the present invention, on the basis of providing an additional discharge path, does not significantly increase the circuit layout difficulty and circuit area occupied by the SRAM, thereby solving the problem that the current write assist circuit outside the storage array will increase the circuit layout difficulty of the SRAM and significantly increase the circuit area occupied.

[0028] In some embodiments, the first inverter includes a first PMOS tube P1 and a third NMOS tube N3, the source of the first PMOS tube P1 is connected to the control word line WEN, the source of the third NMOS tube N3 is grounded, the gate of the first PMOS tube P1 is connected to the gate of the third NMOS tube N3 and constitutes the input end of the first inverter, and the drain of the first PMOS tube P1 is connected to the drain of the third NMOS tube N3 and constitutes the output end of the first inverter; the second inverter includes a second PMOS tube P2 and a fourth NMOS tube N4, the source of the second PMOS tube P2 is connected to the control word line WEN, the source of the fourth NMOS tube N4 is grounded, the gate of the second PMOS tube P2 is connected to the gate of the fourth NMOS tube N4 and constitutes the input end of the second inverter, and the drain of the second PMOS tube P2 is connected to the drain of the fourth NMOS tube N4 and constitutes the output end of the second inverter. When the control word line is at a high level, the two inverters are in working state.

[0029] Considering that MOS devices may have leakage current, the first NMOS tube N1 and the second NMOS tube N2 may not be completely turned off. When the first bit line BL is short-circuited with the first NMOS tube N1 and the second bit line BLB is short-circuited with the second NMOS tube N2, when the first bit line BL or the second bit line BLB is charged at a high potential, the corresponding NMOS tube will produce a slight discharge, thereby reducing the charging rate of the first bit line BL or the second bit line BLB or failing to be fully charged to the ideal potential. Although the above phenomenon basically does not affect the use during actual use, in order to minimize the charging impact on the first bit line BL and the second bit line BLB, additional switching devices can be set on the discharge path.

[0030] Correspondingly, in some of the embodiments, the circuit structure further includes a first switch device and a second switch device; the drain of the first NMOS tube N1 is connected to the first bit line BL through the first switch device, and the drain of the second NMOS tube N2 is connected to the second bit line BLB through the second switch device. In this embodiment, by additionally setting a switch device, the leakage current on the discharge path can be further reduced. For example, when the first bit line BL does not need to be discharged, the first NMOS tube N1 is automatically in an off state, and by controlling the first switch device to be in an off state, the two switch devices are in an off state at the same time, which can further reduce the generation of leakage current. Similarly, when the second bit line BLB does not need to be discharged, the second NMOS tube N2 is automatically in an off state, and by controlling the second switch device to be in an off state, the two switch devices are in an off state at the same time, which can further reduce the generation of leakage current.

[0031] The input end of the first inverter and the drain of the first NMOS tube may be the same node or may not be the same node. When the two are not the same node, the two nodes are connected to the first bit line through two independent paths respectively.

[0032] In an embodiment where the circuit structure further includes a first switch device and a second switch device, whether the input end of the first inverter and the drain of the first NMOS tube are the same node will produce different usage effects.

[0033] When the input end of the first inverter and the drain of the first NMOS tube N1 are not the same node, the input end of the first inverter is short-circuited with the first bit line BL, and at this time, the potential of the first bit line is the potential of the input end of the first inverter, which is not affected by the first switch device. Then, when the first bit line BL is charged at a high level, the first inverter outputs a low potential, so that the first NMOS tube N1 is in an off state. Similarly, when the input end of the second inverter and the drain of the second NMOS tube N2 are not the same node, the input end of the second inverter is short-circuited with the second bit line BLB, and at this time, the potential of the second bit line is the potential of the input end of the second inverter, which is not affected by the second switch device. Then, when the second bit line BLB is charged at a high level, the second inverter outputs a low potential, so that the second NMOS tube N2 is in an off state.

[0034] When the input end of the first inverter and the drain of the first NMOS tube are at the same node, the input end of the first inverter is also connected to the first bit line through the first switch device. Then, when the first bit line BL is charged at a high level (no auxiliary discharge is required at this time), since the first switch device is turned off, the input of the first inverter is low potential, and the first inverter outputs a high potential, so that the first NMOS tube is in a conducting state, and then the first switch device and the first NMOS tube cannot be in a turned-off state at the same time. Similarly, when the input end of the second inverter and the drain of the second NMOS tube are at the same node, the input end of the second inverter is also connected to the second bit line through the second switch device. Then, when the second bit line is charged at a high level (no auxiliary discharge is required at this time), since the second switch device needs to be turned off, the input of the second inverter is low potential, and the second inverter outputs a high potential, so that the second NMOS tube is in a conducting state, and then the second switch device and the second NMOS tube cannot be in a turned-off state at the same time. The above problem can be overcome by adjusting the level of the control word line WEN, that is, when auxiliary discharge is not required, the control word line WEN outputs a low level so that the inverter does not work. When the two switching devices are turned off, the first NMOS tube and the second NMOS tube are also in the off state.

[0035] Correspondingly, in the embodiment where the input terminal of the inverter is short-circuited with the corresponding bit line, the control word line WEN can be kept at a high level, thereby simplifying the control difficulty.

[0036] Specifically, the first switch device is the fifth NMOS tube N5, the source of the fifth NMOS tube N5 is connected to the first bit line BL, the drain of the fifth NMOS tube N5 is connected to the drain of the first NMOS tube N1, the second switch device is the sixth NMOS tube N6, the source of the sixth NMOS tube N6 is connected to the second bit line BLB, the drain of the sixth NMOS tube N6 is connected to the drain of the second NMOS tube N2, and the gates of the fifth NMOS tube N5 and the sixth NMOS tube N6 are both connected to the control word line WEN. In this embodiment, two NMOS tubes are respectively used as the first switch device and the second switch device, and the gate potential of the NMOS tube can be controlled by the control word line WEN, thereby controlling the conduction state of the NMOS tube.

[0037] In the above embodiment, the control of the switch device and the inverter is unified, and both are controlled by the control word line WEN. When the control word line WEN is at a low level, the switch device is turned off, and the inverter does not work, so that the first NMOS tube and the second NMOS tube are also in the off state. On the contrary, when the control word line WEN is at a high level, the switch device is turned on, and the inverter works, so that the first NMOS tube and the second NMOS tube are turned off or turned on according to the bit line potential adaptively.

[0038] As described above, this is the circuit structure of the self-starting bit cell SRAM write assist provided by the present invention. As follows, the effectiveness of the above circuit structure of the self-starting bit cell SRAM write assist is explained through a simulation experiment result.

[0039] In a simulation experiment, the simulation object is a memory array with 128 memory cells. Taking the longitudinal direction as the reference direction, the lower ends of the first bit line and the second bit line of the memory array are grounded through switches (existing structure). This simulation experiment specifically simulates the write data speed of the first memory cell at the top of the memory array.

[0040] First, the circuit structure of the self-starting bit unit SRAM write assist provided by the present invention is not added.

[0041] When writing 0, the first bit line is discharged and the second bit line is charged. The simulation results show that after about 0.35ns, the first bit line is converted to a low level and the second bit line is converted to a high level, and the data is written successfully.

[0042] When writing 1, the first bit line is charged and the second bit line is discharged. The simulation results show that after about 0.35ns, the first bit line is converted to a high level and the second bit line is converted to a low level, and the data is written successfully.

[0043] Next, a self-starting bit unit SRAM write-assisting circuit structure provided by the present invention is connected between the first storage unit and the second storage unit above.

[0044] When writing 0, the first bit line is discharged and the second bit line is charged. The simulation results show that after about 0.25ns, the first bit line is converted to a low level and the second bit line is converted to a high level, and the data is written successfully.

[0045] When writing 1, the first bit line is charged and the second bit line is discharged. The simulation results show that after about 0.25ns, the first bit line is converted to a high level and the second bit line is converted to a low level, and the data is written successfully.

[0046] By comparing the above two simulation results, for the first storage cell at the top of the storage array, after the circuit structure of the self-starting bit cell SRAM write assist provided by the present invention is set below it, its data write time is improved by about 0.1ns (shortened by 40%). It should be noted that although different storage cells are subject to different write assist effects, or the circuit structure of the self-starting bit cell SRAM write assist is set at different positions, it will have different write assist effects. However, it can be seen from the above simulation experiments that the circuit structure of the self-starting bit cell SRAM write assist provided by the present invention is at least effective, and the write assist effect is significant at least in some cases.

[0047] Reference Figure 2 and Figure 3 The present invention also provides a SRAM storage array, including: a first bit line, a second bit line and a plurality of storage cells and at least one self-starting bit cell SRAM write-assist circuit structure provided by the present invention, the storage cell implements data writing through the first bit line and the second bit line, and the circuit structure is used to discharge the first bit line and the second bit line; wherein the input end of the first inverter in the circuit structure is connected to the first bit line, and the input end of the second inverter in the circuit structure is connected to the second bit line.

[0048] Compared with the existing conventional SRAM storage array, the SRAM storage array provided by the present invention is provided with the circuit structure of the self-starting bit unit SRAM write assist provided by the present invention, through which an additional discharge path can be provided for the first bit line and the second bit line, so that the storage array has better feasibility and improves the performance of the SRAM. Furthermore, there is no need to set up an additional write assist circuit, which greatly reduces the circuit area occupied by itself.

[0049] Typically, one end of the bit line is grounded through a switch, and resistance accumulation is related to the length of the bit line, that is, the potential of a position farther from the ground end in the bit line is more difficult to be released to 0, and thus additional discharge of the position farther from the ground end in the bit line has a better discharge effect.

[0050] In a preferred embodiment, the first ends of the first bit line and the second bit line are both grounded, and the input ends of the first inverter and the second inverter in at least one circuit structure are respectively connected to the second ends of the first bit line and the second bit line.

[0051] Reference Figure 4 The present invention also provides a SRAM storage module, which encapsulates the SRAM storage array provided by the present invention. The storage module at least has: a first bit line pin, a second bit line pin, a control word line pin, a ground pin and a control word line pin.

[0052] The present invention also provides a static random access memory, and data storage is achieved through the storage array of the SRAM provided by the present invention.

[0053] The present invention also provides an electronic device, which implements data access through the static random access memory provided by the present invention.

[0054] It should be understood that the specific embodiments described herein are only used to explain the application, rather than to limit it. Based on the embodiments provided in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the protection scope of this application.

[0055] Obviously, the drawings are only some examples or embodiments of the present application. For ordinary technicians in the field, the present application can also be applied to other similar situations based on these drawings without creative work. In addition, it is understandable that although the work done in this development process may be complicated and lengthy, for ordinary technicians in the field, certain changes in design, manufacturing or production based on the technical content disclosed in this application are only conventional technical means and should not be regarded as insufficient content disclosed in this application.

Claims

1. A circuit structure of a self-starting bit cell SRAM write assist, applied to a memory array of an SRAM, wherein the memory array comprises a first bit line, a second bit line and a plurality of memory cells, and the memory cells implement data writing via the first bit line and the second bit line, characterized in that: The circuit structure is used to discharge the first bit line and the second bit line and includes: A first inverter and a second inverter, an input end of the first inverter is connected to the first bit line, and an input end of the second inverter is connected to the second bit line; A first NMOS tube and a second NMOS tube, wherein the gate of the first NMOS tube is connected to the output end of the first inverter, the drain of the first NMOS tube is connected to the first bit line, the source of the first NMOS tube is grounded, the gate of the second NMOS tube is connected to the output end of the second inverter, the drain of the second NMOS tube is connected to the second bit line, and the source of the second NMOS tube is grounded; The first inverter comprises a first PMOS tube and a third NMOS tube, the source of the first PMOS tube is connected to the control word line, the source of the third NMOS tube is grounded, the gate of the first PMOS tube is connected to the gate of the third NMOS tube and constitutes an input end of the first inverter, and the drain of the first PMOS tube is connected to the drain of the third NMOS tube and constitutes an output end of the first inverter; The second inverter includes a second PMOS tube and a fourth NMOS tube, the source of the second PMOS tube is connected to the control word line, the source of the fourth NMOS tube is grounded, the gate of the second PMOS tube is connected to the gate of the fourth NMOS tube and constitutes the input end of the second inverter, and the drain of the second PMOS tube is connected to the drain of the fourth NMOS tube and constitutes the output end of the second inverter.

2. The circuit structure of the self-starting bit cell SRAM write assist according to claim 1, characterized in that: The circuit structure also includes a first switching device and a second switching device; The drain of the first NMOS tube is connected to the first bit line through the first switch device, and the drain of the second NMOS tube is connected to the second bit line through the second switch device.

3. The circuit structure of the self-starting bit cell SRAM write assist according to claim 2, characterized in that: An input terminal of the first inverter is short-circuited with the first bit line, and an input terminal of the second inverter is short-circuited with the second bit line.

4. The circuit structure of the self-starting bit cell SRAM write assist according to claim 2, characterized in that: The input terminal of the first inverter is also connected to the first bit line through the first switch device, and the input terminal of the second inverter is also connected to the second bit line through the second switch device.

5. The circuit structure of the self-starting bit cell SRAM write assist according to claim 2, characterized in that: The first switching device is a fifth NMOS tube, a source of the fifth NMOS tube is connected to the first bit line, a drain of the fifth NMOS tube is connected to the drain of the first NMOS tube, the second switching device is a sixth NMOS tube, a source of the sixth NMOS tube is connected to the second bit line, a drain of the sixth NMOS tube is connected to the drain of the second NMOS tube, and gates of the fifth NMOS tube and the sixth NMOS tube are both connected to a control word line.

6. A SRAM storage array, characterized in that: include: A first bit line and a second bit line; A plurality of storage units, wherein data is written into the storage units through the first bit line and the second bit line; At least one circuit structure of a self-starting bit cell SRAM write assist according to any one of claims 1 to 5, wherein the circuit structure is used to discharge the first bit line and the second bit line.

7. The SRAM memory array according to claim 6, characterized in that: The first ends of the first bit line and the second bit line are both grounded, and the input ends of the first inverter and the second inverter in at least one of the circuit structures are connected to the second ends of the first bit line and the second bit line respectively.

8. A static random access memory, characterized in that: Data storage is achieved by using the SRAM storage array according to claim 6 or 7.

9. An electronic device, characterized in that: Data access is achieved through the static random access memory described in claim 8.

Images