Controlling use-based interference mitigation

Abstract

Devices and techniques for controlling use-based interference mitigation are described. In an example aspect, usage-based interference mitigation is performed between activation and pre-charging of a row. More specifically, an array counter update process is performed while the row is active based on the use of disturbing circuitry. The technique for controlling usage-based interference mitigation controls timing of the array counter update process at a multi-bank level or a local bank level. In addition, the technique for controlling usage-based interference mitigation controls timing of pre-charge operations to ensure completion of the array counter update process. The techniques for controlling use-based interference mitigation are not limited to the array counter update process and are typically applicable to other aspects of use-based interference mitigation, such as bit error detection and / or correction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 517,293, filed on August 2, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present application relates to controlling usage-based interference mitigation. Background Art

[0004] Computers, smartphones, and other electronic devices rely on processors and memory. The processor executes code based on data to run applications and provide features to users. The processor obtains the code and data from the memory. The memory in an electronic device may include volatile memory (e.g., random access memory (RAM)) and non-volatile memory (e.g., flash memory). Like the power of the processor, the power of the memory may affect the performance of the electronic device. This performance impact may increase as processors that execute code faster are developed and as applications require even more memory to operate on larger and larger data sets. Summary of the invention

[0005] One aspect of the present application relates to an apparatus comprising: a memory device comprising: at least one memory body comprising a plurality of rows of memory cells, each of the plurality of rows being configured to store activation counts within a subset of the memory cells; a circuit system configured to perform an array counter update process to update the activation counts corresponding to activated rows within the at least one memory body; and a control circuit system configured to: receive an external precharge command from a memory controller; and initiate precharging of the activated rows after a time interval has elapsed since the receipt of the external precharge command, the time interval being sufficient to enable the array counter update process to be completed before initiating the precharge of the activated rows.

[0006] Another aspect of the present application relates to a method performed by a memory device, the method comprising: storing an activation count in a subset of memory cells of a row of a memory bank; activating the row of the memory bank; initiating an array counter update process based on an external precharge command received from a memory controller; and initiating a precharge of the activated row after a time interval has passed since the initiation of the array counter update process, the time interval enabling the array counter update process to be completed before precharging the activated row.

[0007] Another aspect of the present application relates to an apparatus comprising: a memory device comprising: a plurality of memory banks, each of the plurality of memory banks comprising a plurality of rows of memory cells, each of the plurality of rows being configured to store activation counts within a subset of the memory cells; a circuit system configured to perform an array counter update process to update the activation counts corresponding to activated rows within a memory bank among the plurality of memory banks; and a control circuit system comprising a multi-memory bank control circuit coupled to the plurality of memory banks and comprising a timing circuit configured to delay precharging of the activated rows for a period of time to enable completion of the array counter update process.

[0008] Another aspect of the present application relates to an apparatus comprising: a memory device comprising: a plurality of memory bodies, each of the plurality of memory bodies comprising a plurality of rows of memory cells, each of the plurality of rows being configured to store activation counts in a subset of the memory cells; a circuit system configured to perform an array counter update process to update the activation counts corresponding to the activated rows; and a control circuit system comprising a plurality of local memory body control circuits respectively coupled to the plurality of memory bodies, each of the plurality of local memory body control circuits comprising a timing circuit configured to delay precharging of the activated rows in the corresponding memory body for a period of time to enable completion of the array counter update process.

[0009] Another aspect of the present application relates to a method performed by a memory device, the method comprising: storing an activation count in a subset of memory cells corresponding to a row within a memory body; performing an array counter update process to update the activation count based on the row being activated; and delaying precharging of the row for a period of time to enable the array counter update process to be completed.

[0010] Yet another aspect of the present application relates to a method performed by a memory device, the method comprising: storing timing parameters in a mode register of the memory device; determining, by control circuitry of the memory device, a time interval associated with performing an array counter update process based on the timing parameters; and delaying, by the control circuitry, precharging of an activated row by the time interval to enable completion of the array counter update process. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Devices and techniques for controlling usage-based interference mitigation are described with reference to the following drawings. The same numbers are used throughout the drawings to refer to similar features and components:

[0012] Figure 1 Describing example devices that may implement aspects of controlling usage-based interference mitigation;

[0013] Figure 2 An example computing system is described in which aspects of controlling usage-based interference mitigation may be implemented;

[0014] Figure 3 describing example memory devices in which aspects of controlling usage-based interference mitigation may be implemented;

[0015] Figure 4 Describing example arrangements of multi-bank control circuitry and local bank control circuitry on a die;

[0016] Figure 5 Describing example components of control circuitry capable of controlling usage-based interference mitigation;

[0017] Figure 6 illustrating example operands of a mode register for controlling timing associated with usage-based interference mitigation;

[0018] Figure 7-1 An example multi-bank control circuit capable of controlling usage-based interference mitigation is described;

[0019] Figure 7-2 illustrates an example timing diagram for controlling usage-based interference mitigation using a multi-bank control circuit;

[0020] Figure 8-1 An example local bank control circuit capable of controlling usage-based interference mitigation is described;

[0021] Figure 8-2 illustrates an example timing diagram for controlling usage-based interference mitigation using local bank control circuitry;

[0022] Fig. 9 A first example method of a memory device performing aspects of controlling usage-based interference mitigation is described;

[0023] Fig.10 A second example method of illustrating a memory device performing aspects of controlling usage-based interference mitigation; and

[0024] Fig.11 A third example method in which a memory device performs aspects of controlling usage-based interference mitigation is described. DETAILED DESCRIPTION

[0025] Overview

[0026] Processors and memory work together to provide features to users of computers and other electronic devices. As processors and memory operate together faster in a complementary manner, electronic devices can provide enhanced features, such as high-resolution graphics and artificial intelligence (AI) analysis. Some applications, such as applications for financial services, medical devices, and advanced driver assistance systems (ADAS), may also require more reliable memory. These applications use increasingly reliable memory to limit errors in financial transactions, medical decisions, and object recognition. However, in some implementations, more reliable memory may sacrifice bit density, power efficiency, and simplicity.

[0027] In order to meet the demand for physically smaller memories, memory devices with higher chip density can be designed. However, increasing chip density may increase electromagnetic coupling (e.g., capacitive coupling) between adjacent or proximate rows of memory cells, which is at least partially due to the reduced distance between these rows. Due to this undesirable coupling, the activation (or charging) of the first row of memory cells may sometimes adversely affect the second nearby row of memory cells. In particular, the activation of the first row may produce interference or crosstalk, which causes the second row to experience voltage fluctuations. In some examples, such voltage fluctuations may cause the state (or value) of the memory cell in the second row to be incorrectly determined by the sense amplifier. Consider an example in which the state of the memory cell in the second row is "1". In this example, the voltage fluctuation may cause the sense amplifier to incorrectly determine the state of the memory cell as "0" instead of "1". If not checked, such interference may cause memory errors or data loss within the memory device.

[0028] In some cases, a particular row of memory cells is repeatedly activated, either inadvertently or intentionally (sometimes maliciously). For example, consider that the memory cells in row R are subjected to repeated activation, which causes one or more memory cells in neighboring rows (e.g., within row R+1, row R+2, row R-1, and / or row R-2) to change state. This effect is known as usage-based interference. The occurrence of usage-based interference may result in corruption or alteration of the contents within the affected row of memory.

[0029] To address this and other issues regarding usage-based interference, this document describes techniques for controlling usage-based interference mitigation. One aspect of usage-based interference mitigation involves tracking how often a row has been activated since the last refresh. More specifically, usage-based interference circuitry performs an array counter update process that updates activation counts associated with an activated row. The activation counts are stored in a subset of memory cells within the activated row. To limit the impact on overall system timing, execution of the array counter update process is constrained to a time frame in which the row is active for normal memory operations (e.g., normal read operations or normal write operations). In other words, usage-based interference mitigation is performed between activation and precharge of the row.

[0030] The techniques for controlling usage-based interference mitigation control the timing of the array counter update process at a multi-bank level or a local bank level. Additionally, the techniques for controlling usage-based interference mitigation control the timing of precharge operations to ensure completion of the array counter update process. The techniques for controlling usage-based interference mitigation are not limited to the array counter update process and can be generally applied to other aspects of usage-based interference mitigation, such as bit error detection and / or correction.

[0031] Instance operating environment

[0032] Figure 1 An example operating environment including an apparatus 102 in which aspects of controlling usage-based interference mitigation may be implemented is generally illustrated at 100. The apparatus 102 may include various types of electronic devices that may be part of a cloud computing infrastructure, a data center, or a portion thereof (e.g., a printed circuit board (PCB)), including an Internet of Things (IoT) device 102-1, a tablet device 102-2, a smartphone 102-3, a notebook computer 102-4, a bus 102-5, a server computer 102-6, and a server cluster 102-7. Other examples of the apparatus 102 include a wearable device (e.g., a smart watch or smart glasses), an entertainment device (e.g., a set-top box, a video dongle, a smart TV, a gaming device), a desktop computer, a motherboard, a blade server, a consumer appliance, a vehicle, a drone, industrial equipment, a security device, a sensor, or an electronic component thereof. Each type of apparatus may include one or more components to provide computing functionality or features.

[0033] In an example implementation, the apparatus 102 may include at least one host device 104, at least one interconnect 106, and at least one memory device 108. The host device 104 may include at least one processor 110, at least one cache memory 112, and a memory controller 114. The memory device 108 (which may also be implemented using a memory module) may include, for example, a dynamic random access memory (DRAM) die or module (e.g., a low power double data rate synchronous DRAM (LPDDR SDRAM)). The DRAM die or module may include a three-dimensional (3D) stacked DRAM device, which may be a high bandwidth memory (HBM) device or a hybrid memory cube (HMC) device. The memory device 108 may operate as a main memory of the apparatus 102. Although not illustrated, the apparatus 102 may also include a storage memory. The storage memory may include, for example, a storage class memory device (e.g., a flash memory, a hard disk drive, a solid state drive, a phase change memory (PCM), or a 3D XPoint TM of memory).

[0034] The processor 110 is operably coupled to a cache memory 112, which is operably coupled to a memory controller 114. The processor 110 is also directly or indirectly coupled to the memory controller 114. The host device 104 may include other components to form, for example, a system on a chip (SoC). The processor 110 may include a general purpose processor, a central processing unit, a graphics processing unit (GPU), a neural network engine or accelerator, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) integrated circuit (IC), or a communication processor (e.g., a modem or baseband processor).

[0035] In operation, the memory controller 114 may provide a high-level or logical interface between the processor 110 and at least one memory (e.g., an external memory). The memory controller 114 may be implemented using any of a variety of suitable memory controllers (e.g., a double data rate (DDR) memory controller that can process requests for data stored on the memory device 108). Although not shown, the host device 104 may include a physical interface (PHY) that transmits data between the memory controller 114 and the memory device 108 through the interconnect 106. For example, the physical interface may be an interface compatible with the DDR PHY interface (DFI) group interface protocol. For example, the memory controller 114 may receive a memory request from the processor 110 and provide the memory request with appropriate format, timing, and reordering to the external memory. The memory controller 114 may also forward a response to a memory request received from the external memory to the processor 110.

[0036] Host device 104 is operably coupled to memory device 108 via interconnect 106. In some examples, memory device 108 is connected to host device 104 via interconnect 106 with an intervening buffer or cache. Memory device 108 is operably coupled to storage memory (not shown). Host device 104 may also be coupled directly or indirectly to memory device 108 and storage memory via interconnect 106. Interconnect 106 and other interconnects ( Figure 1 The interconnect 106 may transmit data between two or more components of the apparatus 102 (not illustrated). Examples of the interconnect 106 include a bus (e.g., a unidirectional or bidirectional bus), a switch fabric, or one or more wires carrying voltage or current signals. The interconnect 106 may propagate one or more communications 116 between the host device 104 and the memory device 108. For example, the host device 104 may transmit a memory request to the memory device 108 via the interconnect 106. Also, the memory device 108 may transmit a corresponding memory response to the host device 104 via the interconnect 106.

[0037] The illustrated components of the apparatus 102 represent an example architecture having a hierarchical memory system. The hierarchical memory system may include memory at different levels, where each level has memory with different speeds or capacities. As illustrated, cache memory 112 logically couples the processor 110 to the memory device 108. In the illustrated implementation, the cache memory 112 is at a higher level than the memory device 108. The storage memory, in turn, may be at a lower level than the main memory (e.g., the memory device 108). Memory at a lower level of the hierarchy may have a reduced speed but an increased capacity relative to memory at a higher level of the hierarchy.

[0038] Device 102 may be implemented in various ways using more, fewer, or different components. For example, host device 104 may include multiple cache memories (e.g., multiple levels of cache memories) or no cache memories. In other embodiments, host device 104 may omit processor 110 or memory controller 114. Memory (e.g., memory device 108) may have "internal" or "local" cache memories. As another example, device 102 may include cache memories between interconnect 106 and memory device 108. Computer engineers may also include any of the illustrated components in a distributed or shared memory system.

[0039] Computer engineers can implement host device 104 and various memories in a variety of ways. In some cases, host device 104 and memory device 108 can be placed on or physically supported by a printed circuit board (e.g., a rigid or flexible motherboard). Host device 104 and memory device 108 can also be integrated together on an integrated circuit or fabricated on separate integrated circuits and packaged together. Memory device 108 can also be coupled to multiple host devices 104 via one or more interconnects 106 and can respond to memory requests from two or more host devices 104. Each host device 104 can include a respective memory controller 114, or multiple host devices 104 can share a memory controller 114. This document references Figure 1 An example computing system architecture is described having at least one host device 104 coupled to a memory device 108 .

[0040] Two or more memory components (e.g., modules, dies, banks, or groups of banks) may share an electrical path or coupling of the interconnect 106. The interconnect 106 may include at least one command and address bus (CA bus) and at least one data bus (DQ bus). The command and address bus may transmit addresses and commands from the memory controller 114 of the host device 104 to the memory device 108, which may not include the propagation of data. The data bus may propagate data between the memory controller 114 and the memory device 108. The memory device 108 may also be implemented as any suitable memory, including but not limited to DRAM, SDRAM, three-dimensional (3D) stacked DRAM, DDR memory, or LPDDR memory (e.g., LPDDR DRAM or LPDDR SDRAM).

[0041] Memory device 108 may form at least part of a main memory of apparatus 102. However, memory device 108 may form at least part of a cache memory, storage memory, or a system on a chip of apparatus 102. Memory device 108 includes at least one instance of usage-based interference circuitry 120 and at least one instance of control circuitry 122.

[0042] The usage-based interference circuitry 120 mitigates usage-based interference on one or more memory banks associated with the memory device 108. The usage-based interference circuitry 120 may be implemented using software, firmware, hardware, fixed circuit circuitry, or a combination thereof. The usage-based interference circuitry 120 may also include at least one counter circuit for updating an activation count, and / or at least one error correction code (ECC) circuit for detecting and / or correcting bit errors.

[0043] The control circuitry 122 may include various components that the memory device 108 may use to perform various operations, such as communicating with other devices, managing memory performance, performing refresh operations (e.g., self-refresh operations or auto-refresh operations), and supporting usage-based interference mitigation. The control circuitry 122 includes at least one mode register 124, at least one multi-bank control circuit 126 (e.g., bank group control circuit), and local bank control circuits 128-1 to 128-B, where B represents a positive integer.

[0044] Mode register 124 stores timing parameters 130. Control circuit system 122 references timing parameters 130 to determine when to initiate operations associated with usage-based interference mitigation and / or when to initiate precharging of activated rows. Information associated with timing parameters 130 may be represented in a variety of different ways, such as with respect to Figure 6 Further description.

[0045] The multi-bank control circuit 126 generates internal commands for multiple banks (e.g., multiple banks of a bank group) based on external commands received from the memory controller 114 via the interconnect 106. In this manner, the multi-bank control circuit 126 can control the operation of multiple banks within the memory device 108. The multi-bank control circuit 126 can be implemented using software, firmware, hardware, fixed circuit circuitry, or a combination thereof.

[0046] Each local bank control circuit 128-1 to 128-B controls the operation of its corresponding bank based on internal commands received from the multi-bank control circuit 126. The local bank control circuits 128-1 to 128-B may be implemented using software, firmware, hardware, fixed circuit circuitry, or a combination thereof. Figure 4 and 5 An example layout and example components of multi-bank control circuitry 126 and local bank control circuitry 128-1 through 128-B are further described.

[0047] In general, techniques for controlling usage-based interference mitigation may be performed at least in part by control circuitry 122. More specifically, these techniques may be implemented at a multi-bank level using multi-bank control circuitry 126 or at a local bank level using local bank control circuitry 128-1 through 128-B.

[0048] One controllable aspect of usage-based interference mitigation involves an array counter update process 132 (ACU process 132). The usage-based interference circuitry 120 performs the array counter update process 132 to update activation counts associated with activated rows. To update the activation counts, the usage-based interference circuitry 120 reads the activation counts stored within the activated rows, increments the activation counts, and writes the updated activation counts to the activated rows. By maintaining the activation counts, the usage-based interference circuitry 120 can determine when to perform refresh operations to reduce the risk of usage-based interference.

[0049] In a first example implementation, the multi-bank control circuit 126 generates internal commands to initiate and execute one or more operations associated with the array counter update process 132. In addition, the multi-bank control circuit 126 may control the timing of the precharge operation to ensure completion of the array counter update process 132. Figure 7-1 An example implementation of the multi-bank control circuit 126 that controls usage-based interference mitigation is further described.

[0050] In a second example implementation, the local bank control circuits 128-1 to 128-B generate signals to initiate and perform one or more operations associated with the array counter update process 132. The local bank control circuits 128-1 to 128-B may initiate the array counter update process 132 based on an internal command (e.g., an internal precharge command) generated by the multi-bank control circuit 126. Additionally, the local bank control circuits 128-1 to 128-B may control the timing of the precharge operation to ensure completion of the array counter update process 132. Figure 8-1 An example implementation of the local bank control circuit 128 that controls usage-based interference mitigation is further described.

[0051] In general, the execution of the array counter update process 132 requires time and the rows must be active during the array counter update process 132. This means that precharging of activated rows is delayed based on the duration of the array counter update process 132. Therefore, it is desirable for the control circuitry 122 to control the timing of the array counter update process 132 in a reliable and efficient manner and to control the timing of the precharge operation to constrain the amount of time required by the memory device 108 between receiving an external precharge command and the next external activate command.

[0052] Although techniques for controlling usage-based interference mitigation are described with respect to array counter update process 132, these techniques may generally be applied to initiate and perform any type of operation that enables usage-based interference circuitry 120 to mitigate usage-based interference. Other operations may include bit error detection and / or correction using usage-based interference circuitry 120. Figure 2 The control circuitry 122 is further described.

[0053] Figure 2 An example computing system 200 is illustrated in which aspects of controlling usage-based interference mitigation may be implemented. In some implementations, the computing system 200 includes at least one memory device 108, at least one interconnect 106, and at least one processor 202. The memory device 108 may include or be associated with at least one memory array 204, at least one interface 206, and a control circuit system 122 (or peripheral circuit system) operably coupled to the memory array 204. The memory array 204 may include an array of memory cells, including but not limited to memory cells of DRAM, SDRAM, three-dimensional (3D) stacked DRAM, DDR memory, LPDDR SDRAM, etc. The memory array 204 and the control circuit system 122 may be components on a single semiconductor die or on separate semiconductor dies. The memory array 204 or the control circuit system 122 may also be distributed across multiple dies. This control circuit system 122 may manage traffic on a bus separate from the interconnect 106.

[0054] In the depicted configuration, control circuitry 208 includes mode registers 124, multi-bank control circuitry 126, local bank control circuitry 128-1 through 128-B, at least one instance of array control circuitry 210, and at least one instance of clock circuitry 212. Array control circuitry 210 may include circuitry that provides command decoding, address decoding, input / output functions, amplification circuitry, power supply management, power control modes, and other functions. Clock circuitry 212 may synchronize various memory components with one or more external clock signals provided through interconnect 106, including command and address clocks or data clocks. Clock circuitry 212 may also synchronize memory components using internal clock signals and may provide timer functionality.

[0055] The memory device 108 also includes usage-based interference circuitry 120. In some aspects, the usage-based interference circuitry 120 may be considered part of the control circuitry 122. For example, the usage-based interference circuitry 120 may represent another portion of the control circuitry 122. The usage-based interference circuitry 120 may be coupled to a set of memory cells within the memory array 204 that store usage-based interference data 214. The usage-based interference data 214 may include information such as activation counts that represent the number of times one or more rows within the memory array 204 have been activated (or accessed) by the memory device 108.

[0056] In an example embodiment, each row of the memory array 204 includes a subset of memory cells associated with that row that store usage-based interference data 214. For example, a first row includes a subset of memory cells that store a first activation count representing the number of times the first row has been activated. Additionally, a second row includes another subset of memory cells that store a second activation count representing the number of times the second row has been activated. Other embodiments are also possible in which the activation count represents the number of activations associated with more than one row.

[0057] The interface 206 may couple the control circuitry 122 or the memory array 204 directly or indirectly to the interconnect 106. In some implementations, the use-based interference circuitry 120, the mode registers 124, the multi-bank control circuitry 126, the local bank control circuitry 128-1 to 128-B, the array control circuitry 210, and the clock circuitry 212 may be parts of a single component (e.g., the control circuitry 122). In other implementations, one or more of the use-based interference circuitry 120, the mode registers 124, the multi-bank control circuitry 126, the local bank control circuitry 128-1 to 128-B, the array control circuitry 210, or the clock circuitry 212 may be implemented as separate components that may be provided on a single semiconductor die or disposed across multiple semiconductor dies. These components may be coupled to the interconnect 106 individually or jointly via the interface 206.

[0058] The interconnect 106 may use one or more of a variety of interconnects that communicatively couple various components together and enable commands, addresses, or other information and data to be transferred between two or more components (e.g., between the memory device 108 and the processor 202). Figure 2 106 is illustrated as a single line, but the interconnect 106 may include at least one bus, at least one switch fabric, one or more wires or traces carrying voltage or current signals, at least one switch, one or more buffers, etc. In addition, the interconnect 106 may be divided into at least a command and address bus and a data bus.

[0059] In some aspects, the memory device 108 may be relative to ( Figure 1The "separate" components of either the host device 104 or the processor 202 are "separate" components. The separate components may include a printed circuit board, a memory card, a memory stick, and a memory module (e.g., a single in-line memory module (SIMM) or a dual in-line memory module (DIMM)). Thus, the separate physical components may be located together in the same housing of an electronic device or may be distributed across a server rack, a data center, and the like. Alternatively, the memory device 108 may be integrated with other physical components (including the host device 104 or the processor 202) by being combined on a printed circuit board or in a single package or system on a chip.

[0060] like Figure 2 , processor 202 may include a computer processor 202-1, a baseband processor 202-2, and an application processor 202-3 coupled to a memory device 108 via an interconnect 106. Processor 202 may include or form part of a central processing unit, a graphics processing unit, a system on a chip, an application specific integrated circuit, or a field programmable gate array. In some cases, a single processor may include multiple processing resources each dedicated to a different function (e.g., modem management, applications, graphics, central processing). In some implementations, baseband processor 202-2 may include or be coupled to a modem ( Figure 2 Modem or baseband processor 202-2 may be implemented via, for example, cellular, Near field or another technology or protocol for wireless communication wirelessly couples to the network.

[0061] In some implementations, processors 202 may be directly connected to memory device 108 (e.g., via interconnect 106). In other implementations, one or more of processors 202 may be indirectly connected to memory device 108 (e.g., through a network connection or through one or more other devices).

[0062] Example Technology and Hardware

[0063] Figure 3 An example memory device 108 is illustrated in which aspects of controlling usage-based interference mitigation may be implemented. The memory device 108 includes a memory module 302, which may include a plurality of dies 304. As illustrated, the memory module 302 includes a first die 304-1, a second die 304-2, a third die 304-3, and a D-th die 304-D, where D represents a positive integer. The memory module 302 may be a SIMM or a DIMM. As another example, the memory module 302 may be interconnected via a bus (e.g., a peripheral component interconnect fast Bus) to interface with other components. For example, Figure 1 and 2The memory device 108 illustrated in FIG. 1 may correspond to a plurality of dies (or dices) 304-1 through 304-D or a memory module 302 having two or more dies 304. As shown, the memory module 302 may include one or more electrical contacts 306 (e.g., pins) to interface the memory module 302 to other components.

[0064] The memory module 302 can be implemented in various ways. For example, the memory module 302 can include a printed circuit board, and the plurality of dies 304-1 to 304-D can be mounted or otherwise attached to the printed circuit board. The dies 304 (e.g., memory dies) can be arranged in rows or arranged along two or more dimensions (e.g., forming a grid or array). The dies 304 can have similar sizes or can have different sizes. Each die 304 can be similar to another die 304 or different in size, shape, data capacity, or control circuitry. The die 304 can also be positioned on a single side or multiple sides of the memory module 302.

[0065] One or more of the dies 304-1 to 304-D include a usage-based interference circuit system 120, a control circuit system 122, and memory groups 308-1 to 308-G, where G represents a positive integer. Each memory group 308 includes at least two memory banks 310, such as memory banks 310-1 to 310-B. In some embodiments, the die 304 includes multiple instances of the usage-based interference circuit system 120, and the usage-based interference circuit system 120 mitigates the usage-based interference across at least one of the memory banks 310. For example, multiple instances of the usage-based interference circuit system 120 can respectively mitigate the usage-based interference across the memory bank groups 308-1 to 308-G. In this example, one instance of the usage-based interference circuit system 120 mitigates the usage-based interference across multiple memory banks 310-1 to 310-B of the memory bank group 308. In another example, multiple instances of the usage-based interference circuit system 120 can respectively mitigate the usage-based interference to the corresponding memory banks 310. In this case, each usage-based interference circuitry 120 mitigates usage-based interference on a single memory bank 310 within one of the memory bank groups 308-1 to 306-B. In yet another example, each usage-based interference circuitry 120 mitigates usage-based interference on a subset of memory banks 310 associated with one of the memory bank groups 308-1 to 308-G, where the subset of memory banks 310 includes at least two memory banks 310. Figure 4 The relationship between memory banks 310 - 1 through 310 -B and control circuitry 122 is further described.

[0066] Figure 4An example arrangement of multi-bank control circuitry 126 and local bank control circuitry 128-1 to 128-B (LBCCs 128-1 to 128-B) on a die 304 is illustrated. The die 304 includes bank-specific circuitry 402 and bank-shared circuitry 404. The bank-specific circuitry 402 includes components associated with a particular bank 310. For example, the bank-specific circuitry 402 includes banks 310-1, 310-2 ... 310-(B / 2), 310-(B / 2+1), 310-(B / 2+2) ... 310-B and local bank control circuitry 128-1, 128-2 ... 128-(B / 2), 128-(B / 2+1), 128-(B / 2+2) ... 128-B. The local memory bank control circuits 128-1 to 128-B are coupled to the memory banks 310-1 to 310-B, respectively. In some cases, subsets of the memory banks 310-1 to 310-B are associated with different memory bank groups 308. In an example embodiment, the die 304 includes 32 memory banks 310 (e.g., B equals 32). The 32 memory banks 310 form eight memory bank groups 308 (e.g., G equals 8), where each memory bank group 308 includes four memory banks 310. In other cases, the memory banks 310-1 to 310-B are associated with a single memory bank group 308.

[0067] The bank-shared circuitry 404 includes components associated with the plurality of memory banks 310. These components perform operations associated with the plurality of memory banks 310. Example components of the bank-shared circuitry 404 include the multi-bank control circuitry 126, the command decoder 406 of the array control circuitry 210, and the clock circuitry 212. In this example, the usage-based interference circuitry 120 is shown as part of the bank-shared circuitry 404. Alternatively, multiple instances of the usage-based interference circuitry 120 may be implemented as part of the bank-specific circuitry 402.

[0068] In an example embodiment, the multi-bank control circuit 126 is positioned near (or integrated within) the command decoder 406. In some cases, the distance between the multi-bank control circuit 126 and the command decoder 406 is shorter than the distance between the multi-bank control circuit 126 and one of the memory banks 310.

[0069] On the die 304, the bank-specific circuitry 402 is positioned on two opposing sides of the bank-shared circuitry 404. In other words, the bank-shared circuitry 404 may be centrally positioned on the die 304. Thus, the multi-bank control circuitry 126 may be positioned closer to the center of the die 304 than to the edge of the die 304. Positioning the bank-shared circuitry 404 in the center enables the wiring between the bank-shared circuitry 404 and the bank-specific circuitry 402 to be simplified.

[0070] Considering a first axis 408-1 (eg, X-axis 408-1) and a second axis 408-2 (eg, Y-axis 408-2), the second axis 408-2 is perpendicular to the first axis 408-1. Figure 4 , the first axis 408-1 is depicted as a "horizontal" axis and the second axis 408-2 is depicted as a "vertical" axis. The components of the memory bank sharing circuit system 404 are distributed across the second axis 408-2. The first group of memory banks (e.g., memory banks 310-1 to 310-B / 2) are arranged on the "left" side of the memory bank sharing circuit system 404 along the second axis 408-2, and the second group of memory banks (e.g., memory banks 310-(B / 2+1) to 310-B) are arranged on the "right" side of the memory bank sharing circuit system 404 along the second axis 408-2. The local memory bank control circuits 128-1 to 128-B are positioned between the corresponding memory banks 310-1 to 310-B and the memory bank sharing circuit system 404. By locating the multi-bank control circuitry 126 in a central location between the local bank control circuits 128-1 through 128-B, signals may be more easily routed between the multi-bank control circuitry 126 and the local bank control circuits 128-1 through 128-B.

[0071] As about Figure 5Described in more detail, the multi-storage control circuit 126 or the local storage control circuit 128-1 to 128-B can perform aspects of controlling the use-based interference mitigation. In a first embodiment, the multi-storage control circuit 126 provides such control without significantly increasing the die size. Additional routing is required to pass the control signal from the multi-storage control circuit 126 to the local storage control circuit 128-1 to 128-B. In a second embodiment, the local storage control circuit 128-1 to 128-B provides such control without changing the signal routing between the multi-storage control circuit 126 and the local storage control circuit 128-1 to 128-B. This is because the local storage control circuit 128-1 to 128-B can perform aspects of controlling the use-based interference mitigation based on the signal provided by the multi-storage control circuit 126. However, implementing aspects of controlling the use-based interference mitigation using the local storage control circuit 128-1 to 128-B may require additional space. Thus, the die 304 may have a larger footprint in this second embodiment compared to the first embodiment.

[0072] In some cases, techniques for controlling usage-based interference mitigation may be performed based on a clock signal generated by the clock circuitry 212. In this case, because the multi-memory control circuitry 126 is positioned near the clock circuitry 212, it may be easier for the multi-memory control circuitry 126 to control usage-based interference mitigation. This close proximity may mitigate delays associated with passing the clock signal from the clock circuitry 212 to the multi-memory control circuitry 126. In contrast, performing aspects of controlling usage-based interference mitigation based on clock signals using the local memory control circuitry 128-1 through 128-B may be more challenging due to additional signal routing between the clock circuitry 212 and the local memory control circuitry 128-1 through 128-B. In this case, variations in delay may require additional timing margins, which may make it challenging to perform aspects of usage-based interference mitigation within available time intervals. About Figure 5 The control circuitry 122 is further described.

[0073] Figure 5Example components of the control circuitry 122 for controlling usage-based interference mitigation are illustrated. In the depicted configuration, the control circuitry 122 includes a mode register 124, a multi-bank control circuit 126, local bank control circuits 128-1 to 128-B, and a clock circuitry 212. The multi-bank control circuit 126 is coupled to the local bank control circuits 128-1 to 128-B. The multi-bank control circuit 126 includes a column circuit 502 (or column logic) and a normal control circuit 504. The column circuit 502 generates commands for initiating and / or performing various operations of the memory device 108. The normal control circuit 504 controls the timing of these commands for initiating and performing normal read operations or normal write operations. The multi-bank control circuit 126 controls the operation of the local bank control circuits 128-1 to 128-B.

[0074] The local bank control circuits 128-1 to 128-B are respectively coupled to the banks 310-1 to 310-B (not shown) and respectively control the operation of the banks 310-1 to 310-B. Each of the local bank control circuits 128-1 to 128-B includes a column address strobe (CAS) circuit 506 (CAS circuit 506) (or column address strobe logic) and a row address strobe (RAS) circuit 508 (RAS circuit 508) (or row address strobe logic). Figure 8-1 The operation of column address strobe circuit 506 and row address strobe circuit 508 is further described.

[0075] The control circuit system 122 further includes a usage-based interference control circuit 510 (UBD control circuit 510), which can be configured to control the multi-bank control circuit 126 (eg, Figure 7-1 ) or local memory bank control circuits 128-1 to 128-B (as shown in Figure 8-1 132 ) are implemented within each of the normal control circuits 504 and the multi-bank control circuits 126. If the usage-based interference control circuit 510 is implemented as part of the multi-bank control circuit 126, the normal control circuit 504 and the usage-based interference control circuit 510 may utilize at least some of the same components. The usage-based interference control circuit 510 controls the timing associated with the array counter update process 132 and the precharge operation. In particular, the usage-based interference control circuit 510 initiates the array counter update process 132 and initiates the precharge after an appropriate amount of time has passed to ensure that the array counter update process 132 is completed.

[0076] Implementing the usage-based interference control circuit 510 within the multi-bank control circuit 126 (e.g., at a multi-bank level) may have less impact on the footprint of the memory device 108, but increases the cost and complexity associated with routing signals between the multi-bank control circuit 126 and the local bank control circuits 128-1 to 128-B. Alternatively, implementing the usage-based interference control circuit 510 within the local bank control circuits 128-1 to 128-B (e.g., at a local bank level) may have less impact on signal routing between the multi-bank control circuit 126 and the local bank control circuits 128-1 to 128-B, but at the expense of increasing the footprint of the memory device 108.

[0077] The usage-based interference control circuit 510 is coupled to the mode register 124. The mode register 124 stores at least one timing parameter 130. The usage-based interference control circuit 510 reads or accesses the timing parameter 130 from the mode register 124 to determine an amount of time associated with performing one or more aspects of the array counter update process 132. In an example implementation, the timing parameter 130 includes a time interval that specifies the time between reading the activation count and a precharge operation as part of the array counter update process 132. In general, the usage-based interference control circuit 510 can initiate (or trigger) a precharge operation based on the timing parameter 130.

[0078] The usage-based interference control circuit 510 may be implemented using a clock-based timing circuit 512 or a non-clock-based timing circuit 514. The clock-based timing circuit 512 is coupled to the clock circuitry 212 and evaluates the passage of time based on a clock signal 516. The non-clock-based timing circuit 514 evaluates the passage of time based on another timing aspect or mechanism that is independent of the clock signal 516. The non-clock-based timing circuit 514 may be implemented using analog delays, such as gate delay circuits or resistor-capacitor delay circuits.

[0079] During operation, the multi-bank control circuit 126 receives an external command 518 from the memory controller 114 (not shown). In some implementations, the command decoder 406 (not shown) decodes and passes the decoded external command 518 to the multi-bank control circuit 126. The column circuit 502 generates an internal command 520 based on the external command 518. For normal operation (e.g., a normal read operation or a normal write operation), the normal control circuit 504 controls the timing of the internal command 520. For the case where the external command 518 is an external activate command, an external read command, or an external write command, the normal control circuit 504 can control the timing of the internal command 520. For usage-based interference, the usage-based interference control circuit 510 controls the timing of the internal command 520. For the case where the external command 518 is an external precharge command 522, the usage-based interference control circuit 510 can control the timing of the internal command 520.

[0080] The local bank control circuits 128-1 to 128-B generate control signals 524 based on the internal commands 520. The control signals 524 cause the bank 310 to perform operations associated with the internal commands 520. If the usage-based interference control circuits 510 are implemented within the local bank control circuits 128-1 to 128-B, the usage-based interference control circuits 510 may control the timing of the control signals 524 for the case where the internal commands 520 include the internal precharge commands 526. Figure 6 The mode register 124 is further described.

[0081] Figure 6 An example mode register 124 for controlling timing associated with usage-based interference mitigation is illustrated. The mode register 124 stores timing parameters 130 within at least one operand 602. The operand 602 may represent a shared operand 604, a usage-based interference-specific operand 606 (UBD-specific operand 606), or a non-usage-based interference operand 608 (non-UBD operand 608). For the shared operand 604 and the usage-based interference-specific operand 606, the timing parameters 130 may represent a time interval during which the array counter update process 132 is performed. The time interval may be specified in terms of a number of clock cycles or in time units (e.g., in nanoseconds). For the non-usage-based interference operand 608, the timing parameters 130 may represent parameters that may be used to determine a time interval during which the array counter update process 132 is performed. In some examples, the time interval for performing the array counter update process 132 is equal to 20 nanoseconds (ns). Other values ​​for the time interval are also possible.

[0082] The shared operand 604 specifies both the timing parameter 130 and another parameter associated with the memory operation. In other words, the shared operand 604 has multiple functions or multiple meanings, one of which is associated with the timing parameter 130. In this case, the value of the operand 602 can be a code representing a specific value of the timing parameter 130 and a specific value of the other parameter. Consider an example in which the mode register 124 represents the mode register 6 (MR6) and the shared operand 604 represents OP[3:0]. In this case, the shared operand 604 specifies both the timing parameter 130 and the write recovery time (nWR or tWR).

[0083] In this example, the value of the timing parameter 130 may be equal to the write recovery time multiplied by the value of the factor. Consider the case where the factor is equal to two-thirds. In this case, a first value of the shared operand 604 representing a write recovery time of 48 clock cycles also represents a timing parameter 130 of 32 clock cycles. A second value of the shared operand 604 representing a write recovery time of 90 clock cycles also represents a timing parameter 130 of 60 clock cycles. The shared operand 604 enables more efficient use of the mode register 124, but at the expense of limiting the control of the timing parameter 130.

[0084] In contrast to the shared operand 604, the usage-based interference-specific operand 606 specifies the timing parameter 130 and does not specify another parameter associated with the memory operation. In other words, the usage-based interference-specific operand 606 has a single function or a single meaning associated with the timing parameter 130. The value of the usage-based interference-specific operand 606 may be encoded to represent different values ​​of the timing parameter 130. For example, a first value of the usage-based interference-specific operand 606 may represent a timing parameter 130 of 32 clock cycles. A second value of the usage-based interference-specific operand 606 may represent a timing parameter 130 of 60 clock cycles. Compared to the shared operand 604, the usage-based interference-specific operand 606 provides greater flexibility for setting the timing parameter 130, but at the expense of making the operand dedicated to usage-based interference mitigation.

[0085] Alternatively, operand 602 may be implemented as a non-usage-based interference operand 608. In this case, timing parameter 130 may represent a speed (e.g., clock frequency) utilized by host device 104. For example, mode register 124 may be mode register 13 (MR13), and non-usage-based interference operand 608 may be OP[3:0]. Based on the clock speed indicated by MR13OP[3:0], usage-based interference control circuit 510 determines the number of clock cycles used to perform array counter update process 132 within a predetermined amount of time (e.g., 20 ns). Figure 7-1An example implementation of usage-based disturb control circuit 510 at the multi-bank level is further described.

[0086] Figure 7-1 An example multi-bank control circuit 126 capable of controlling usage-based interference mitigation is illustrated. In the depicted configuration, the multi-bank control circuit 126 is shown to include column circuits 502 and usage-based interference control circuits 510. Although not explicitly shown, the column circuits 502 are coupled to the column address strobe circuits 506 of the local bank control circuits 128-1 to 128-B. The usage-based interference control circuit 510 includes a read control circuit 702 (or read control logic), a write control circuit 704 (or write control logic), and an activate / precharge circuit 706 (ACT / PRE circuit 706). The activate / precharge circuit 706 is coupled to the row address strobe circuit 508 of the local bank control circuits 128-1 to 128-B. The usage-based interference control circuit 510 also includes delay circuits 708-1 and 708-2. The first delay circuit 708-1 is coupled between the read control circuit 702 and the write control circuit 704. The second delay circuit 708-2 is coupled between the write control circuit 704 and the activation / precharge circuit 706. For simplicity, Figure 7-1 The normal control circuit 504 is not shown in FIG. In some implementations, the read control circuit 702, the write control circuit 704, and the activate / precharge circuit 706 can be shared between the normal control circuit 504 and the usage-based disturb control circuit 510.

[0087] In this example, the use-based interference control circuit 510 has a single signal path in which the read control circuit 702, the first delay circuit 708-1, the write control circuit 704, the delay circuit 708-2, and the activation / precharge circuit 706 are coupled together in series. Other implementations are also possible. For example, the second delay circuit 708-2 can be coupled between the read control circuit 702 and the activation / precharge circuit 706.

[0088] For the array counter update process 132, the read control circuit 702 initiates the reading of the activation count. The write control circuit 704 initiates the writing of the updated activation count. The activation / precharge circuit 706 controls the timing associated with the precharge operation. The delay circuit 708-1 ensures that a sufficient amount of time has passed for the reading of the activation count to complete before the writing of the updated activation count. The delay circuit 708-2 ensures that a sufficient amount of time has passed for the writing of the updated activation count to complete before the precharge operation is initiated.

[0089] In some implementations, the first delay 710-1 is substantially less than the second delay 710-2. Consider a case where the time interval for performing the array counter update process 132 is 20ns. In this case, the first delay 710-1 may be approximately 5ns, and the second delay 710-2 may be approximately 15ns.

[0090] The activation / precharge circuit 706 controls the activation and precharge of the row. In this example, for simplicity, the activation / precharge circuit 706 is shown as a single entity. Alternatively, the activation / precharge circuit 706 can be implemented using multiple entities. In this case, one of the entities can control the activation of the row and another of the entities can control the precharge of the row.

[0091] During operation, the usage-based interference control circuit 510 reads the timing parameters 130 from the mode register 124. In one aspect, the usage-based interference control circuit 510 determines the first delay 710-1 and the second delay 710-2 based on the timing parameters 130. In another aspect, the timing parameters 130 directly specify the first delay 710-1 and the second delay 710-2. The usage-based interference control circuit 510 receives an external precharge command 522 from the memory controller 114. The external precharge command 522 causes the read control circuit 702 to generate a read strobe 712, which is passed to the column circuit 502. The read control circuit 702 also activates the delay circuit 708-1. After a first amount of time has elapsed according to the first delay 710-1, the first delay circuit 708-1 triggers the write control circuit 704. The write control circuit 704 generates a write strobe 714, which is passed to the column circuit 502. The write control circuit 704 also enables the second delay circuit 708 - 2 .

[0092] During this time, the column circuit 502 generates a read / write flag 718 and an array counter update flag 720 based on the read strobe 712 and the write strobe 714. The read / write flag 718 causes the local memory bank control circuit 128 to perform a read operation or a write operation. The array counter update flag 720 causes the read / write flag 718 to be used in the array counter update process 132. In particular, the array counter update flag 720 causes the column address strobe circuit 506 to activate the column storing the activation count of the activated row. Moreover, the array counter update flag 720 and the read / write flag 718 cause the local memory bank control circuit 128 to initiate reading the activation count from the activated row and / or initiate writing the updated activation count to the activated row.

[0093] After the second amount of time has elapsed according to the second delay 710-2, the second delay circuit 708-2 triggers the activate / precharge circuit 706. The activate / precharge circuit 706 generates an activate / precharge signal 722. The activate / precharge signal 722 initiates an activate operation and / or a precharge operation.

[0094] Implementing the usage-based interference control circuit 510 within the multi-bank control circuit 126 means that at least three signals are passed from the multi-bank control circuit 126 to each of the local bank control circuits 128-1 to 128-B. These signals include a read / write flag 718, an array counter update flag 720, and an activate / precharge signal 722. Figure 7-2 The timing associated with these signals is further described.

[0095] Figure 7-2 An example timing diagram 724 is illustrated for controlling usage-based interference mitigation using the multi-bank control circuit 126. For simplicity, the rising or falling edges of the signals are shown as appearing on the dashed lines. It should be understood that there may be Figure 7-2 Additional delays associated with one or more of these edges that are not explicitly shown in .

[0096] In the timing diagram 724, the signals represent binary or logic signals. In particular, these signals may have a high voltage that may be approximately equal to the supply voltage or a low voltage that may be approximately equal to the reference voltage. In the examples described below, the activate / precharge signal 722 has a low voltage to enable precharge or a high voltage to enable activate. The read / write flag 718 may have a low voltage to enable a read operation or a high voltage to enable a write operation. The array counter update flag 720 may have a low voltage to disable the array counter update process 132 or a high voltage to enable the array counter update process 132.

[0097] In this example, the memory device 108 performs a normal read operation 726 or a normal write operation 728. Aspects of the normal read operation 726 are represented using dashed lines. Aspects of the normal write operation 728 are represented using dashed lines.

[0098] After the normal read operation 726 or the normal write operation 728, the memory device 108 performs the array counter update process 132. The array counter update process 132 includes a usage-based disturb read operation 730 and a usage-based disturb write operation 732. The duration of the array counter update process 132 is represented by a time interval 736. The time interval 736 represents the sum of the delays 710-1 and 710-2. In some examples, the read / write flag 718 and the array counter update flag 720 cause the column address strobe circuit 506 to generate a column address strobe, such as the column address strobe 804 in FIG. 8, for the usage-based disturb read operation 730 and / or the usage-based disturb write operation 732. After the array counter update process 132, the memory device 108 performs a precharge operation 734.

[0099] Prior to a normal read operation 726 or a normal write operation 728, the multi-bank control circuit 126 initiates activation of the row by driving the activation / precharge signal 722 from low to high. The activation / precharge circuit 706 maintains driving the activation / precharge signal 722 high during the duration of the normal read operation 726, the normal write operation 728, and the array counter update process 132. In a first example, the normal control circuit 504 initiates a normal read operation 726 by driving the read strobe 712 high and the write strobe 714 low. This causes the column circuit 502 to drive the read / write flag 718 low and the array counter update flag 720 low. In a second example, the normal control circuit 504 initiates a normal write operation 728 by driving the read strobe 712 low and the write strobe 714 high. This causes the column circuit 502 to drive the read / write flag 718 high and the array counter update flag 720 low.

[0100] The multi-bank control circuit 126 initiates the array counter update process 132 based on the external precharge command 522. Specifically, the usage-based disturb control circuit 510 initiates the usage-based disturb read operation 730 by driving the read strobe 712 high and the write strobe 714 low. This causes the column circuit 502 to drive the read / write flag 718 low and the array counter update flag 720 high. After the first delay 710-1, the usage-based disturb control circuit 510 initiates the usage-based disturb write operation 732 by driving the read strobe 712 low and the write strobe 714 high. This causes the column circuit 502 to drive the read / write flag 718 high and the array counter update flag 720 high. After the second delay 710-2, the activate / precharge circuit 706 initiates the precharge operation 734 by driving the activate / precharge signal 722 low. Figure 8-1An example implementation of usage-based interference control circuit 510 at the local bank level is further described.

[0101] Figure 8-1 An example local bank control circuit 128 capable of controlling usage-based interference mitigation is illustrated. In the depicted configuration, the local bank control circuit 128 is shown to include a column address strobe circuit 506 (CAS circuit 506), a row address strobe circuit 508 (RAS circuit 508), and a usage-based interference control circuit 510. The usage-based interference control circuit 510 includes a read control circuit 702, a write control circuit 704, and a word line shut down circuit 802. The usage-based interference control circuit 510 also includes delay circuits 708-1 and 708-2. The first delay circuit 708-1 is coupled between the read control circuit 702 and the write control circuit 704. The second delay circuit 708-2 is coupled between the write control circuit 704 and the word line shut down circuit 802.

[0102] In this example, the use-based interference control circuit 510 has a single signal path in which the read control circuit 702, the first delay circuit 708-1, the write control circuit 704, the delay circuit 708-2, and the word line shut-down circuit 802 are coupled together in series. Other implementations are also possible. For example, the second delay circuit 708-2 can be coupled between the read control circuit 702 and the word line shut-down circuit 802.

[0103] The operations of the read control circuit 702, the write control circuit 704, and the delay circuits 708-1 and 708-2 are similar to those described above with respect to Figure 7-1 The operations described are similar. Column address strobe circuit 506 generates column address strobe 804 (CAS 804) based on read strobe 712 and / or write strobe 714. After time interval 736 associated with delays 710-1 and 710-2 has elapsed, word line shut-down circuit 802 generates word line shut-down flag 806 (WL shut-down flag 806) to start precharging of the activated row. Row address strobe circuit 508 generates row address strobe 808 (RAS 808) based on word line shut-down flag 806.

[0104] Figure 7-1 and 8-1The delay circuits 708-1 and 708-2 in may evaluate the elapsed time based on the clock signal 516, based on another timing mechanism that is independent of the clock signal 516, or some combination thereof. In some cases, the first delay circuit 708-1 is implemented using a non-clock-based timing circuit 514 and uses a timing mechanism that is independent of the clock signal 516, and the second delay circuit 708-2 is implemented using a clock-based timing circuit 512 and uses the clock signal 516. The delays 710-1 and 710-2 and the time interval 736 may be determined in a manner that provides sufficient margin to account for variations. Figure 8-2 The timing associated with the signals is further described.

[0105] Figure 8-2 An example timing diagram 810 illustrating the use of local bank control circuitry 128 to control usage-based interference mitigation. For simplicity, the rising or falling edges of some signals are shown as appearing on dashed lines. It should be understood that there may be Figure 8-2 108 is associated with one or more of these edges. Figure 7-2 The operations described are similar to the operations described above.

[0106] In the timing diagram 810, the signals represent binary or logic signals. In particular, these signals may have a high voltage that may be approximately equal to the supply voltage or a low voltage that may be approximately equal to the reference voltage. In the examples described below, the activate / precharge signal 722 has a low voltage to enable precharge or a high voltage to enable activation. The word line off flag 806 may have a low voltage to enable precharge or a high voltage to disable precharge.

[0107] Prior to a normal read operation 726 or a normal write operation 728, the multi-bank control circuit 126 initiates activation of the row by driving the activate / precharge signal 722 from low to high. The activate / precharge signal 722 causes the word line shutdown circuit 802 to drive the word line shutdown flag 806 high. The word line shutdown circuit 802 maintains driving the word line shutdown flag 806 high for the duration of the normal read operation 726, the normal write operation 728, and the array counter update process 132.

[0108] The local bank control circuit 128 initiates the array counter update process 132 based on the internal precharge command 526. To generate the internal precharge command 526, the multi-bank control circuit 126 drives the activate / precharge signal 722 low. Based on the internal precharge command 526, the usage-based disturb control circuit 510 initiates a usage-based disturb read operation 730 by driving the read strobe 712 high and the write strobe 714 low. This causes the column address strobe circuit 506 to generate a column address strobe 804 in a manner that enables the usage-based disturb circuitry 120 to read the activation count. After the first delay 710-1, the usage-based disturb control circuit 510 initiates a usage-based disturb write operation 732 by driving the read strobe 712 low and the write strobe 714 high. This causes the column address strobe circuit 506 to generate a column address strobe 804 in a manner that enables the usage-based disturb circuitry 120 to write the updated activation count. After the second delay 710-2, the word line off circuit 802 initiates the precharge operation 734 by driving the word line off flag 806 low. This causes the row address strobe circuit 508 to generate the row address strobe 808 in a manner that causes the activated row to be precharged.

[0109] Instance Methods

[0110] References in this section Figures 9 to 11 The flowchart of the embodiment of the present invention describes an example method for implementing aspects of controlling usage-based interference mitigation. These descriptions may also be referred to by way of example only. Figures 1 to 8-2 The components, entities and other aspects depicted in the description are not necessarily limited to being performed by one entity or multiple entities operating on one device.

[0111] Fig. 9 Method 900 is described, and includes operations 902 to 908. In one aspect, the operations of method 900 are performed as described in reference Figure 1 At 902, an activation count is stored in a subset of memory cells in a row of a memory bank. For example, a subset of memory cells in a row of a memory bank 310 stores an activation count, the activation count representing Figure 2 The usage-based interference data 214 shown in FIG.

[0112] At 904, a row of the memory bank is activated. For example, the control circuitry 122 activates a row of the memory bank 310. The control circuitry 122 may activate the row based on an external activation command received from the memory controller 114.

[0113] At 906 , an array counter update process is initiated based on the external precharge command received from the memory controller. For example, the control circuitry 122 initiates the array counter update process 132 based on the external precharge command 522 received from the memory controller 114 .

[0114] At 908, precharging of the activated rows is initiated after a time interval has elapsed since initiation of the array counter update process. The time interval enables the array counter update process to complete prior to precharging of the activated rows. For example, the control circuitry 122 initiates precharging of the activated rows after a time interval has elapsed since initiation of the array counter update process 132. The time interval enables the usage-based interference circuitry 120 to complete the array counter update process 132 before the activated rows are precharged.

[0115] Fig.10 Method 1000 is described, and includes operations 1002 through 1006. In one aspect, the operations of method 1000 are performed as described with reference to Figure 1 At 1002, an activation count is stored in a subset of memory cells corresponding to a row within a memory bank. For example, a subset of memory cells within a row of memory bank 310 stores an activation count representing Figure 2 The usage-based interference data 214 shown in FIG.

[0116] At 1004, an array counter update process is performed to update the activation count based on the row being activated. For example, the usage-based interference circuitry 120 performs the array counter update process 132 to update the activation count based on the row being activated. More specifically, the usage-based interference circuitry 120 reads the activation count from the activated row, updates the activation count (e.g., increments the activation count), and writes the updated activation count to the subset of memory cells.

[0117] At 1006, precharging of the row is delayed for a time interval to enable the array counter update process to complete. For example, the control circuitry 122 delays precharging of the row for the time interval at a multi-bank level or a local bank level to enable the usage-based interference circuitry 120 to complete the array counter update process 132. Figure 7-2 and 8-2 Example delays 710 - 1 and 710 - 2 are shown in FIG.

[0118] Fig.11 Method 1100 is described, and includes operations 1102 through 1106. In one aspect, the operations of method 1100 are performed as described in reference Figure 1At 1102, the timing parameters are stored in a mode register of the memory device. For example, the mode register 124 of the memory device 108 stores the timing parameters 130, such as Figure 1 The timing parameters 130 may be stored by a shared operand 604, a usage-based interference-specific operand 606, or a non-usage-based interference operand 608, such as Figure 6 As shown in .

[0119] At 1104, a time interval associated with performing the array counter update process is determined by the control circuitry of the memory device based on the timing parameters. For example, the control circuitry 122 determines the time interval based on the timing parameters 130. In some examples, the timing parameters 130 may directly specify the time interval using the shared operands 604 or based on the interference-specific operands 606 used. In other examples, the timing parameters 130 may be calculated based on the timing parameters 130. For example, the timing parameters 130 may represent the speed of the host device 104, and the control circuitry 122 may determine the time interval based on the speed of the host device 104.

[0120] At 1106, precharging of the activated row is delayed by the time interval to enable the array counter update process to complete. For example, the control circuitry 122 delays precharging of the activated row by the time interval at a multi-bank level or a local bank level to enable the usage-based interference circuitry 120 to complete the array counter update process 132. Figure 7-2 and 8-2 Example delays 710 - 1 and 710 - 2 are shown in FIG.

[0121] With respect to the figures described above, the order in which operations are shown and / or described is not intended to be construed as limiting. Any number or combination of the described process operations may be combined or rearranged in any order to implement a given method or an alternative method. Operations may also be omitted from or added to the described methods. In addition, the described operations may be implemented in a manner that is fully or partially overlapping.

[0122] Aspects of these methods may be implemented in, for example, hardware (e.g., fixed circuitry or a processor in conjunction with a memory), firmware, software, or some combination thereof. The methods may be implemented using Figures 1 to 8-2 The present invention is implemented by one or more of the devices or components shown in the figure, and its components can be further divided, combined, rearranged, etc. The devices and components in these figures generally represent hardware, such as electronic devices, packaged modules, IC chips or circuits; firmware or its actions; software; or a combination thereof. Therefore, these figures illustrate some of the many possible systems or devices that can implement the described methods.

[0123] Computer-readable media includes both non-transitory computer storage media and communication media, including any media that facilitates the transfer of computer programs (e.g., applications) or data from one entity to another. Non-transitory computer storage media can be any available media that can be accessed by a computer, such as RAM, ROM, flash memory, EEPROM, optical media, and magnetic media.

[0124] In the following, various examples for implementing aspects of controlling usage-based interference mitigation are described:

[0125] Example 1: A device comprising:

[0126] A memory device comprising:

[0127] at least one memory bank comprising a plurality of rows of memory cells, each row of the plurality of rows being configured to store activation counts within a subset of the memory cells;

[0128] circuitry configured to perform an array counter update process to update the activation count corresponding to an activated row within the at least one memory bank; and

[0129] A control circuit system configured to:

[0130] receiving an external precharge command from a memory controller; and

[0131] Precharging of the activated row is initiated after a time interval has elapsed since the receipt of the external precharge command, the time interval being sufficient to enable the array counter update process to complete prior to initiating the precharging of the activated row.

[0132] Example 2: The apparatus of example 1 or any other example, wherein the control circuitry is configured to:

[0133] initiating reading of the activation count within the activated row based on the receipt of the external precharge command;

[0134] initiating writing of the updated activation count within the activated row based on a portion of the time interval elapsed since the initiation of the reading of the activation count; and

[0135] The precharging of the activated row is initiated based on a remainder of the time interval elapsed since the initiation of the writing of the updated activate count.

[0136] Example 3: The apparatus of example 1 or any other example, wherein the control circuitry is configured to determine that the time interval has elapsed based on a clock signal.

[0137] Example 4: The apparatus of example 1 or any other example, wherein the control circuitry is configured to determine that the time interval has elapsed based on a delay that is independent of a clock signal.

[0138] Example 5: The apparatus of example 1 or any other example, wherein the control circuit system comprises:

[0139] at least one local memory bank control circuit coupled to the at least one memory bank; and

[0140] A multi-bank control circuit is coupled to the at least one local bank control circuit and is configured to initiate the precharging of the activated row after the time interval has elapsed.

[0141] Example 6: The apparatus of example 5 or any other example, wherein the multi-bank control circuit is configured to generate a flag that causes the at least one local bank control circuit to perform operations associated with the array counter update process.

[0142] Example 7: The apparatus of example 5 or any other example, wherein:

[0143] The multi-bank control circuit comprises:

[0144] series circuit; and

[0145] control circuitry configured to initiate the array counter update process and initiate the activation of the activated row

[0146] The pre-charging control circuit comprises:

[0147] a read control circuit coupled to an input of the column circuit and configured to initiate the reading of the activation count as part of the array counter update process;

[0148] a write control circuit coupled to another input of the column circuit, the write control circuit configured to initiate the writing of the updated activation count as part of the array counter update process;

[0149] a first delay circuit coupled between the read control circuit and the write control circuit, the first delay circuit configured to delay the writing of the updated activation count by a first portion of the time interval to enable the reading of the activation count to complete before the writing of the updated activation count; and

[0150] A second delay circuit is coupled to the write control circuit and is configured to delay the precharge of the activated row by a remaining portion of the time interval to enable the writing of the updated activation count to complete prior to the precharge of the activated row.

[0151] Example 8: The apparatus of example 7 or any other example, wherein the first and second delay circuits may each include one of:

[0152] a clock-based sequential circuit configured to determine that a certain amount of time has elapsed based on a clock signal; or

[0153] Another timing circuit is configured to determine that the amount of time has elapsed based on a delay independent of the clock signal.

[0154] Example 9: The apparatus of example 8 or any other example, wherein:

[0155] The first delay circuit includes the other sequential circuit; and

[0156] The second delay circuit includes the clock-based sequential circuit.

[0157] Example 10 The apparatus of example 5 or any other example, wherein a distance between the at least one local memory bank control circuit and the at least one memory bank is shorter than a distance between the multi-bank control circuit and the at least one memory bank.

[0158] Example 11: The apparatus of example 5 or any other example, wherein:

[0159] The memory device includes a command decoder; and

[0160] The multi-bank control circuit is positioned near the command decoder such that a distance between the multi-bank control circuit and the command decoder is shorter than a distance between the multi-bank control circuit and the at least one memory bank.

[0161] Example 12: The apparatus of example 5 or any other example, wherein:

[0162] The control circuitry includes clock circuitry; and

[0163] The multi-bank control circuit is positioned proximate to the clock circuitry such that a distance between the multi-bank control circuitry and the clock circuitry is shorter than a distance between the at least one local bank control circuitry and the clock circuitry.

[0164] Example 13: The apparatus of example 5 or any other example, wherein:

[0165] The at least one memory bank comprises a first memory bank and a second memory bank;

[0166] The at least one local memory bank control circuit comprises:

[0167] A first local memory bank control circuit coupled to the first memory bank; and

[0168] a second local memory bank control circuit coupled to the second memory bank;

[0169] The first memory bank and the first local memory bank control circuit are positioned on a first side of the multi-bank control circuit; and

[0170] The second memory bank and the second local memory bank control circuit are positioned on a second side of the multi-bank control circuit opposite the first side.

[0171] Example 14: The apparatus of example 5 or any other example, wherein:

[0172] The at least one memory bank includes a plurality of memory banks having respective rows activated;

[0173] The at least one local memory bank control circuit comprises a plurality of local memory bank control circuits respectively coupled to the plurality of memory banks; and

[0174] The multi-bank control circuit is coupled to the plurality of local bank control circuits and is configured to generate a plurality of flags to cause the local bank control circuits to perform operations associated with the array counter update process based on corresponding rows being activated.

[0175] Example 15: The apparatus of example 1 or any other example, wherein the control circuit system comprises:

[0176] A multi-bank control circuit configured to:

[0177] receiving the external precharge command from the memory controller; and

[0178] generating an internal precharge command based on the external precharge command; and

[0179] At least one local bank control circuit is coupled to the multi-bank control circuit and the at least one local bank, the at least one local bank control circuit being configured to initiate the precharge of the activated row after the time interval has elapsed since the receipt of the internal precharge command.

[0180] Example 16: The apparatus of example 15 or any other example, wherein:

[0181] The at least one memory bank comprises a plurality of memory banks;

[0182] The at least one local memory bank control circuit comprises a plurality of local memory bank control circuits coupled to the multi-memory bank control circuit and respectively coupled to the plurality of memory banks; and

[0183] Each of the plurality of local memory bank control circuits comprises a control circuit configured to:

[0184] determining that the time interval has elapsed; and

[0185] The precharge of the corresponding activated row is initiated based on the determination.

[0186] Example 17: The apparatus of example 16 or any other example, wherein:

[0187] Each of the plurality of local memory bank control circuits comprises:

[0188] a column address strobe circuit configured to generate a column address strobe; and

[0189] a row address strobe circuit configured to generate a row address strobe; and

[0190] The control circuit comprises:

[0191] a read control circuit coupled to an input of the column address strobe circuit and configured to generate a read strobe;

[0192] a write control circuit coupled to another input of the column address strobe circuit and configured to generate a write strobe;

[0193] a word line off circuit coupled to an input of the row address gating circuit and configured to generate a word line off flag;

[0194] A first delay circuit coupled between the read control circuit and the write control circuit; and

[0195] A second delay circuit is coupled between the write control circuit and the word line shut-down circuit.

[0196] Example 18: The apparatus of example 17 or any other example, wherein:

[0197] The first delay circuit is configured to determine that a first portion of the time interval has elapsed; and

[0198] The second delay circuit is configured to determine that a remaining portion of the time interval has elapsed.

[0199] Example 19: The apparatus of example 1 or any other example, wherein:

[0200] The control circuitry includes a mode register configured to store timing parameters; and

[0201] The control circuitry is configured to determine the time interval based on the timing parameter.

[0202] Example 20: The apparatus of example 19 or any other example, wherein the timing parameter represents an integer number of clock cycles associated with the time interval.

[0203] Example 21: The apparatus of example 19 or any other example, wherein:

[0204] The mode register includes a shared operand configured to store the timing parameter; and

[0205] The shared operand has a first meaning associated with the timing parameter and a second meaning associated with another parameter of the memory device.

[0206] Example 22: The apparatus of example 21 or any other example, wherein the other parameter comprises a write recovery time.

[0207] Example 23: The apparatus of example 19 or any other example, wherein:

[0208] The memory device is configured to be coupled to a host device; and

[0209] The timing parameter represents a speed utilized by the host device.

[0210] Example 24: A method performed by a memory device, the method comprising:

[0211] storing activation counts in a subset of memory cells of a row of a memory bank;

[0212] activating the row of the memory bank;

[0213] Initiating an array counter update process based on an external precharge command received from a memory controller; and

[0214] Precharging of the activated row is initiated after a time interval has elapsed since the initiation of the array counter update process, the time interval enabling the array counter update process to complete prior to precharging the activated row.

[0215] Example 25: The method of example 24 or any other example, wherein the initiation of the array counter update process comprises:

[0216] initiating reading of the activation count within the row based on the receipt of the external precharge command;

[0217] initiating writing of an updated activation count within the row based on a first portion of the time interval elapsed since the initiation of the reading of the activation count; and

[0218] The precharging of the activated row is initiated based on a remainder of the time interval elapsed since the initiation of the writing of the updated activate count.

[0219] Example 26: The method of example 24 or any other example, wherein:

[0220] The initiation of the array counter update process includes generating, by multi-bank control circuitry of the memory device, a flag that causes local bank control circuitry coupled to the memory bank to perform operations associated with the array counter update process; and

[0221] The initiation of the pre-charging includes determining, by the multi-bank control circuit, that the time interval has elapsed.

[0222] Example 27: The method of example 24 or any other example, wherein:

[0223] The initiation of the array counter update process includes receiving, by a local bank control circuit of the memory device coupled to the memory bank, an internal precharge command from a multi-bank control circuit of the memory device; and

[0224] The initiation of the pre-charging includes determining, by the local bank control circuitry, that the time interval has elapsed.

[0225] Example 28: A device comprising:

[0226] A memory device comprising:

[0227] a plurality of memory banks, each memory bank of the plurality of memory banks comprising a plurality of rows of memory cells, each row of the plurality of rows being configured to store activation counts within a subset of the memory cells;

[0228] circuitry configured to perform an array counter update process to update the activation count corresponding to an activated row within a memory bank of the plurality of memory banks; and

[0229] Control circuitry includes a multi-bank control circuit coupled to the plurality of memory banks and including a timing circuit configured to delay precharging of the activated row for a time interval to enable completion of the array counter update process.

[0230] Example 29: The apparatus of example 28 or any other example, wherein:

[0231] The control circuitry includes a plurality of local memory bank control circuits respectively coupled to the plurality of memory banks; and

[0232] The multi-bank control circuit is coupled to the plurality of local bank control circuits and is configured to send a signal to each of the plurality of local bank control circuits that initiates the array counter update process.

[0233] Example 30: The apparatus of example 29 or any other example, wherein the multi-bank control circuit is centrally located relative to the plurality of local bank control circuits.

[0234] Example 31 The apparatus of example 28 or any other example, wherein the timing circuit is configured to determine that the time interval has elapsed based on a delay associated with a first number of clock cycles of a clock signal.

[0235] Example 32: The apparatus of example 28 or any other example, wherein the timing circuit is configured to determine that the time interval has elapsed based on a delay that is independent of a clock signal.

[0236] Example 33: The apparatus of example 28 or any other example, wherein the timing circuit comprises:

[0237] a first delay circuit configured to cause a write operation associated with the array counter update process to be initiated after a first portion of the time interval has elapsed; and

[0238] A second delay circuit is configured to cause the precharging of the activated row to be initiated after a remainder of the time interval has elapsed.

[0239] Example 34: A device comprising:

[0240] A memory device comprising:

[0241] a plurality of memory banks, each memory bank of the plurality of memory banks comprising a plurality of rows of memory cells, each row of the plurality of rows being configured to store activation counts within a subset of the memory cells;

[0242] circuitry configured to perform an array counter update process to update the activation count corresponding to an activated row; and

[0243] A control circuit system includes a plurality of local memory bank control circuits respectively coupled to the plurality of memory banks, each of the plurality of local memory bank control circuits including a timing circuit configured to delay precharging of the activated row in the corresponding memory bank for a time interval to enable completion of the array counter update process.

[0244] Example 35: The apparatus of example 34 or any other example, wherein the timing circuit is configured to:

[0245] determining that the time interval has elapsed based on a delay associated with a first number of clock cycles of the clock signal; and

[0246] Precharging of the activated row is initiated based on the determination that the timing interval has elapsed.

[0247] Example 36: The apparatus of example 34 or any other example, wherein the timing circuit is configured to determine that the time interval has elapsed based on a delay that is independent of a clock signal.

[0248] Example 37: The apparatus of example 34 or any other example, wherein the timing circuit comprises:

[0249] a first delay circuit configured to cause a write operation associated with the array counter update process to be initiated after a first portion of the time interval has elapsed; and

[0250] A second delay circuit is configured to cause the precharging of the activated row to be initiated after a remainder of the time interval has elapsed.

[0251] Example 38: A method performed by a memory device, the method comprising:

[0252] storing activation counts in a subset of memory cells corresponding to a row within a memory bank;

[0253] performing an array counter update process to update the activation count based on the row being activated; and

[0254] Precharging of the row is delayed for a time interval to enable the array counter update process to complete.

[0255] Example 39: The method of example 38 or any other example, wherein the delay of the pre-charging comprises determining, by multi-bank control circuitry of the memory device, that the time interval has elapsed.

[0256] Example 40 The method of Example 38 or any other example, wherein the delay of the pre-charging comprises determining, by local bank control circuitry of the memory device coupled to the bank, that the time interval has elapsed.

[0257] Example 41: A method performed by a memory device, the method comprising:

[0258] storing timing parameters in a mode register of the memory device;

[0259] determining, by control circuitry of the memory device, a time interval associated with performing an array counter update process based on the timing parameters; and

[0260] Precharging of activated rows is delayed by the control circuitry for the time interval to enable the array counter update process to complete.

[0261] Example 42: The method of example 41 or any other example, wherein:

[0262] The storing of the timing parameters comprises storing the timing parameters in a shared operand of the mode register; and

[0263] The method further includes specifying a value of another parameter and a value of the timing parameter based on the value of the shared operand.

[0264] Example 43: The method of example 42 or any other example, wherein the other parameter comprises a write recovery time.

[0265] Example 44: The method of example 41 or any other example, wherein:

[0266] The storing of the timing parameters comprises storing information associated with a speed utilized by a host device coupled to the memory device; and

[0267] The method further includes determining the time interval based on the speed utilized by the host device.

[0268] Unless the context dictates otherwise, use of the word "or" herein may be considered use of an "inclusive or" or permitting inclusion or application of one or more items linked by the word "or" (e.g., the phrase "A or B" may be interpreted as permitting only "A," permitting only "B," or permitting both "A" and "B"). Moreover, as used herein, a phrase referring to "at least one" of a list of items refers to any combination of those items, including single members. For example, "at least one of a, b, or c" may encompass a, b, c, ab, ac, bc, and abc, as well as any combination with multiple identical elements (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc, or any other ordering of a, b, and c). Furthermore, the items represented in the drawings and the items discussed herein may indicate one or more items or items, and thus the items and items in singular or plural form may be referred to interchangeably in this written description.

[0269] in conclusion

[0270] Although aspects of controlling usage-based interference mitigation have been described in language specific to certain features and / or methods, the subject matter of the appended claims is not necessarily limited to the specific features or methods described. Rather, the specific features and methods are disclosed as various example implementations of aspects of controlling usage-based interference mitigation.

Claims

1. A device comprising: A memory device comprising: at least one memory bank comprising a plurality of rows of memory cells, each row of the plurality of rows being configured to store activation counts within a subset of the memory cells; circuitry configured to perform an array counter update process to update the activation count corresponding to an activated row within the at least one memory bank; and A control circuit system configured to: receiving an external precharge command from a memory controller; and Precharging of the activated row is initiated after a time interval has elapsed since the receipt of the external precharge command, the time interval being sufficient to enable the array counter update process to complete prior to initiating the precharging of the activated row.

2. The apparatus of claim 1 , wherein the control circuitry is configured to: initiating reading of the activation count within the activated row based on the receipt of the external precharge command; initiating writing of the updated activation count within the activated row based on a portion of the time interval elapsed since the initiation of the reading of the activation count; and The precharging of the activated row is initiated based on a remainder of the time interval elapsed since the initiation of the writing of the updated activate count.

3. The apparatus of claim 1, wherein the control circuitry is configured to determine that the time interval has elapsed based on a clock signal.

4. The apparatus of claim 1, wherein the control circuitry is configured to determine that the time interval has elapsed based on a delay that is independent of a clock signal.

5. The apparatus of claim 1 , wherein the control circuitry comprises: at least one local memory bank control circuit coupled to the at least one memory bank; and A multi-bank control circuit is coupled to the at least one local bank control circuit and is configured to initiate the precharging of the activated row after the time interval has elapsed.

6. The apparatus of claim 5, wherein the multi-bank control circuitry is configured to generate a flag that causes the at least one local bank control circuitry to perform an operation associated with the array counter update process.

7. The apparatus of claim 5, wherein: The multi-bank control circuit comprises: series circuit; and a control circuit configured to initiate the array counter update process and to initiate the precharging of the activated rows, the control circuit comprising: a read control circuit coupled to an input of the column circuit and configured to initiate the reading of the activation count as part of the array counter update process; a write control circuit coupled to another input of the column circuit, the write control circuit configured to initiate the writing of the updated activation count as part of the array counter update process; a first delay circuit coupled between the read control circuit and the write control circuit, the a first delay circuit configured to delay the writing of the updated activation count by a first portion of the time interval to enable the reading of the activation count to complete before the writing of the updated activation count; and A second delay circuit is coupled to the write control circuit and is configured to delay the precharge of the activated row by a remaining portion of the time interval to enable the writing of the updated activation count to complete prior to the precharge of the activated row.

8. The apparatus of claim 7, wherein the first and second delay circuits can each comprise one of: a clock-based sequential circuit configured to determine that a certain amount of time has elapsed based on a clock signal; or Another timing circuit is configured to determine that the amount of time has elapsed based on a delay independent of the clock signal.

9. The apparatus according to claim 8, wherein: The first delay circuit includes the other sequential circuit; and The second delay circuit includes the clock-based sequential circuit.

10. The apparatus of claim 5, wherein a distance between the at least one local memory bank control circuit and the at least one memory bank is shorter than a distance between the multi-bank control circuit and the at least one memory bank.

11. The apparatus of claim 5, wherein: The memory device includes a command decoder; and The multi-bank control circuit is positioned near the command decoder such that a distance between the multi-bank control circuit and the command decoder is shorter than a distance between the multi-bank control circuit and the at least one memory bank.

12. The apparatus of claim 5, wherein: The control circuitry includes clock circuitry; and The multi-bank control circuit is positioned proximate to the clock circuitry such that a distance between the multi-bank control circuitry and the clock circuitry is shorter than a distance between the at least one local bank control circuitry and the clock circuitry.

13. The apparatus of claim 5, wherein: The at least one memory bank comprises a first memory bank and a second memory bank; The at least one local memory bank control circuit comprises: A first local memory bank control circuit coupled to the first memory bank; and a second local memory bank control circuit coupled to the second memory bank; The first memory bank and the first local memory bank control circuit are positioned on a first side of the multi-bank control circuit; and The second memory bank and the second local memory bank control circuit are positioned on a second side of the multi-bank control circuit opposite the first side.

14. The apparatus of claim 5, wherein: The at least one memory bank includes a plurality of memory banks having respective rows activated; The at least one local memory bank control circuit comprises a plurality of local memory bank control circuits respectively coupled to the plurality of memory banks; and The multi-bank control circuit is coupled to the plurality of local bank control circuits and is configured to generate a plurality of flags to cause the local bank control circuits to perform operations associated with the array counter update process based on corresponding rows being activated.

15. The apparatus of claim 1, wherein the control circuitry comprises: A multi-bank control circuit configured to: receiving the external precharge command from the memory controller; and generating an internal precharge command based on the external precharge command; and At least one local bank control circuit is coupled to the multi-bank control circuit and the at least one local bank, the at least one local bank control circuit being configured to initiate the precharge of the activated row after the time interval has elapsed since the receipt of the internal precharge command.

16. The apparatus of claim 15, wherein: The at least one memory bank comprises a plurality of memory banks; The at least one local memory bank control circuit comprises a plurality of local memory bank control circuits coupled to the multi-memory bank control circuit and respectively coupled to the plurality of memory banks; and Each of the plurality of local memory bank control circuits comprises a control circuit configured to: determining that the time interval has elapsed; and The precharge of the corresponding activated row is initiated based on the determination.

17. The apparatus of claim 16, wherein: Each of the plurality of local memory bank control circuits comprises: a column address strobe circuit configured to generate a column address strobe; and a row address strobe circuit configured to generate a row address strobe; and The control circuit comprises: a read control circuit coupled to an input of the column address strobe circuit and configured to generate a read strobe; a write control circuit coupled to another input of the column address strobe circuit and configured to generate a write strobe; a word line off circuit coupled to an input of the row address gating circuit and configured to generate a word line off flag; A first delay circuit coupled between the read control circuit and the write control circuit; and A second delay circuit is coupled between the write control circuit and the word line shut-down circuit.

18. The apparatus of claim 17, wherein: The first delay circuit is configured to determine that a first portion of the time interval has elapsed; and The second delay circuit is configured to determine that a remaining portion of the time interval has elapsed.

19. The apparatus of claim 1, wherein: The control circuitry includes a mode register configured to store timing parameters; and The control circuitry is configured to determine the time interval based on the timing parameter.

20. The apparatus of claim 19, wherein the timing parameter represents an integer number of clock cycles associated with the time interval.

21. The apparatus of claim 19, wherein: The mode register includes a shared operand configured to store the timing parameter; and The shared operand has a first meaning associated with the timing parameter and a second meaning associated with another parameter of the memory device.

22. The apparatus of claim 21, wherein the another parameter comprises a write recovery time.

23. The apparatus of claim 19, wherein: The memory device is configured to be coupled to a host device; and The timing parameter represents a speed utilized by the host device.

24. A method performed by a memory device, the method comprising: storing activation counts in a subset of memory cells of a row of a memory bank; activating the row of the memory bank; initiating an array counter update process based on an external precharge command received from a memory controller; and Precharging of the activated row is initiated after a time interval has elapsed since the initiation of the array counter update process, the time interval enabling the array counter update process to complete prior to precharging the activated row.

25. The method of claim 24, wherein said initiation of said array counter update process comprises: initiating reading of the activation count within the row based on the receipt of the external precharge command; initiating writing of an updated activation count within the row based on a first portion of the time interval elapsed since the initiation of the reading of the activation count; and The precharging of the activated row is initiated based on a remainder of the time interval elapsed since the initiation of the writing of the updated activate count.

26. The method of claim 24, wherein: The initiation of the array counter update process includes generating, by multi-bank control circuitry of the memory device, a flag that causes local bank control circuitry coupled to the memory bank to perform operations associated with the array counter update process; and The initiation of the pre-charging includes determining, by the multi-bank control circuit, that the time interval has elapsed.

27. The method of claim 24, wherein: The initiation of the array counter update process includes receiving, by a local bank control circuit of the memory device coupled to the memory bank, an internal precharge command from a multi-bank control circuit of the memory device; and The initiation of the pre-charging includes determining, by the local bank control circuitry, that the time interval has elapsed.

28. An apparatus comprising: A memory device comprising: a plurality of memory banks, each memory bank of the plurality of memory banks comprising a plurality of rows of memory cells, each row of the plurality of rows being configured to store activation counts within a subset of the memory cells; circuitry configured to perform an array counter update process to update the activation count corresponding to an activated row within a memory bank of the plurality of memory banks; and Control circuitry includes a multi-bank control circuit coupled to the plurality of memory banks and including a timing circuit configured to delay precharging of the activated row for a time interval to enable completion of the array counter update process.

29. The apparatus of claim 28, wherein: The control circuitry includes a plurality of local memory bank control circuits respectively coupled to the plurality of memory banks; and The multi-bank control circuit is coupled to the plurality of local bank control circuits and is configured to send a signal to each of the plurality of local bank control circuits that initiates the array counter update process.

30. The apparatus of claim 29, wherein the multi-bank control circuit is centrally located relative to the plurality of local bank control circuits.

31. The apparatus of claim 28, wherein the timing circuit is configured to determine that the time interval has elapsed based on a delay associated with a first number of clock cycles of a clock signal.

32. The apparatus of claim 28, wherein the timing circuit is configured to determine that the time interval has elapsed based on a delay that is independent of a clock signal.

33. The apparatus of claim 28, wherein the sequential circuit comprises: a first delay circuit configured to cause a write operation associated with the array counter update process to be initiated after a first portion of the time interval has elapsed; and A second delay circuit is configured to cause the precharging of the activated row to be initiated after a remainder of the time interval has elapsed.

34. An apparatus comprising: A memory device comprising: a plurality of memory banks, each memory bank of the plurality of memory banks comprising a plurality of rows of memory cells, each row of the plurality of rows being configured to store activation counts within a subset of the memory cells; circuitry configured to perform an array counter update process to update the activation count corresponding to an activated row; and A control circuit system includes a plurality of local memory bank control circuits respectively coupled to the plurality of memory banks, each of the plurality of local memory bank control circuits including a timing circuit configured to delay precharging of the activated row in the corresponding memory bank for a period of time to enable completion of the array counter update process.

35. The apparatus of claim 34, wherein the timing circuit is configured to: determining that the time interval has elapsed based on a delay associated with a first number of clock cycles of the clock signal; and Precharging of the activated row is initiated based on the determination that the timing interval has elapsed.

36. The apparatus of claim 34, wherein the timing circuit is configured to determine that the time interval has elapsed based on a delay that is independent of a clock signal.

37. The apparatus of claim 34, wherein the sequential circuit comprises: a first delay circuit configured to cause a write operation associated with the array counter update process to be initiated after a first portion of the time interval has elapsed; and A second delay circuit is configured to cause the precharging of the activated row to be initiated after a remainder of the time interval has elapsed.

38. A method performed by a memory device, the method comprising: storing activation counts in a subset of memory cells corresponding to a row within a memory bank; executing an array counter update process to update the activation count based on the row being activated; and Precharging of the row is delayed for a time interval to allow the array counter update process to complete.

39. The method of claim 38, wherein the delay of the pre-charging comprises determining, by multi-bank control circuitry of the memory device, that the time interval has elapsed.

40. The method of claim 38, wherein the delay of the pre-charging comprises determining, by local bank control circuitry of the memory device coupled to the bank, that the time interval has elapsed.

41. A method performed by a memory device, the method comprising: storing timing parameters in a mode register of the memory device; determining, by control circuitry of the memory device, a time interval associated with performing an array counter update process based on the timing parameters; and Precharging of activated rows is delayed by the control circuitry for the time interval to enable the array counter update process to complete.

42. The method of claim 41, wherein: The storing of the timing parameters comprises storing the timing parameters in a shared operand of the mode register; and The method further includes specifying a value of another parameter and a value of the timing parameter based on the value of the shared operand.

43. The method of claim 42, wherein the another parameter comprises a write recovery time.

44. The method of claim 41, wherein: The storing of the timing parameters comprises storing information associated with a speed utilized by a host device coupled to the memory device; and The method further includes determining the time interval based on the speed utilized by the host device.

Images