Method for diagnosing die data line and address line faults and test system

Abstract

The application discloses a diagnosis method and a test system for DIE data line and address line faults, relates to the technical field of semiconductor integrated circuit testing, and discloses a diagnosis method for DIE data line and address line faults, which is used for testing a plurality of to-be-tested dies (DIEs). The method comprises the following steps: pre-writing and / or pre-reading a plurality of to-be-tested dies to determine actual sampling intervals of read-write data of each to-be-tested die; acquiring a pattern vector test program, wherein the pattern vector test program is used for generating third data for testing faults; writing the third data into each to-be-tested die at a corresponding actual sampling interval; reading data in the to-be-tested die at the actual sampling interval to obtain fourth data; and positioning faults of a data line or an address line according to the third data and the fourth data. The application can adapt to the testing of dies of different brands and different capacity DRAMs, and can position faults of a data line or an address line.

Description

Technical Field

[0001] This application relates to the field of semiconductor integrated circuit testing technology, and in particular to diagnostic methods and testing systems for DIE data line and address line faults. Background Technology

[0002] Dynamic random access memory (DRAM) is a type of semiconductor memory. Because DRAM can only retain data for a short period, it must be refreshed periodically to maintain data. The basic memory cell of DRAM consists of a transistor and a capacitor. Its operation is as follows: when the word line (WL) is activated, the transistor conducts, allowing information stored on the capacitor to be read via the bit line (BL), the data line. The state of the capacitor determines the logical state of the memory cell, which is either 1 or 0. Specifically, a charged capacitor is considered a logical 1 in digital electronics, while an "empty" capacitor is considered a 0.

[0003] With technological advancements, DRAM performance is increasing, and manufacturing processes are shrinking. To improve the stability of DRAM operation, performance testing is necessary. However, current DRAM testing methods are merely preliminary, simple read / write tests, unable to accurately pinpoint faulty data and address lines.

[0004] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art. Summary of the Invention

[0005] The main purpose of this application is to provide a diagnostic method and testing system for DIE data line and address line faults, which aims to locate the faulty data line and address line.

[0006] To achieve the above objectives, this application proposes a diagnostic method for DIE data line and address line faults, used to test multiple DIEs under test. The method includes:

[0007] Pre-write and / or pre-read of the multiple DIEs under test to determine the actual sampling interval of the read and write data of each DIE under test;

[0008] Obtain a pattern vector test program, which is used to generate third data for testing faults;

[0009] The third data is written to each DIE under test at the corresponding actual sampling interval;

[0010] The fourth data is obtained by reading data from the DIE under test at the actual sampling interval, and the fault of the data line or address line is located based on the third data and the fourth data.

[0011] In one embodiment, the step of pre-writing and / or pre-reading the plurality of DIEs under test to determine the actual sampling interval of the read / write data for each DIE under test includes:

[0012] In response to the write enable signal, first data is written to the first storage space of the DIE under test at a first sampling interval;

[0013] In response to the read enable signal, data is read from the DIE under test at a first sampling interval to obtain second data;

[0014] When the second data is inconsistent with the first data, the first sampling interval is adjusted and then the first data is written to the first storage space of the DIE under test in response to the write enable signal at the first sampling interval.

[0015] When the second data matches the first data, the first sampling interval is recorded as the actual sampling interval.

[0016] In one embodiment, the step of adjusting the first sampling interval and then writing the first data into the first storage space of the DIE under test at the first sampling interval in response to the write enable signal when the second data is inconsistent with the first data further includes:

[0017] Adjusting the first sampling interval includes increasing the value of the first sampling interval by a preset step value.

[0018] In one embodiment, the step of adjusting the first sampling interval includes increasing the value of the first sampling interval by a preset step value.

[0019] The value of the first sampling interval is less than a quarter of a clock cycle.

[0020] In one embodiment, when the value of the first sampling interval is greater than a quarter clock cycle and the second data is inconsistent with the first data, the step of pre-writing and / or pre-reading the plurality of DIEs under test to determine the actual sampling interval of the read / write data of each DIE under test includes:

[0021] Based on the first and second data, faults in the data lines or address lines corresponding to the first storage space are located.

[0022] In one embodiment, the third data includes 0x0000000000000000 and 0xFFFFFFFFFFFFFFFF;

[0023] The steps of writing the third data to each DIE under test at the corresponding actual sampling interval, reading the data in the DIE under test at the actual sampling interval to obtain the fourth data, and locating the fault of the data line or address line based on the third data and the fourth data include:

[0024] Write either 0x0000000000000000 or 0xFFFFFFFFFFFFFFFF to the first row address line of the second storage space of the DIE, read the data in the second storage space to obtain the fourth data, and compare each data bit in the fourth data with each data bit in the third data.

[0025] If the fourth data is inconsistent with the third data, identify the data bits that differ, i.e., there is an erroneous storage unit. If the fourth data is consistent with the third data, write 0x0000000000000000 and 0xFFFFFFFFFFFFFFFF to the first row address line of the second storage space of the DIE, read the data in the second storage space to obtain the fourth data, and compare each data bit in the fourth data with each data bit in the third data.

[0026] If the fourth data is inconsistent with the third data, identify the data bits that are different, i.e., there is an erroneous storage unit. If the fourth data is consistent with the third data, diagnose the first row of address lines as normal.

[0027] In one embodiment, the third data includes 0xAAAAAAAAAAAAAAAA and 0x5555555555555555;

[0028] The steps of writing the third data to each DIE under test at the corresponding actual sampling interval, reading the data in the DIE under test at the actual sampling interval to obtain the fourth data, and locating the fault of the data line or address line based on the third data and the fourth data include:

[0029] Write either 0xAAAAAAAAAAAAAAAA or 0x5555555555555555 to the first row address line of the second storage space of the DIE, read the data in the second storage space to obtain the fourth data, and compare each data bit in the fourth data with each data bit in the third data.

[0030] If the fourth data is inconsistent with the third data, identify the data bits that differ, i.e., there is an erroneous storage unit. If the fourth data is consistent with the third data, write 0xAAAAAAAAAAAAAAAA or 0x5555555555555555 to the first row address line of the second storage space of the DIE. Read the data in the second storage space to obtain the fourth data, and compare each data bit in the fourth data with each data bit in the third data.

[0031] If the fourth data is inconsistent with the third data, identify the data bits that are different, i.e., there is an erroneous storage unit. If the fourth data is consistent with the third data, diagnose the first row of address lines as normal.

[0032] Furthermore, to achieve the above objectives, this application also proposes a testing system for DIE data line and address line faults, comprising:

[0033] The host computer is connected to the test board and is used to send the pattern vector test program, the DIE specification parameters under test and the test start / reset command to the test board.

[0034] The test board receives the pattern vector test program, the DIE specification parameters under test, and the test start / reset command, and is used to output the timing bus signal driving the DRAM to the probe card board according to the pattern vector test program and the DIE specification parameters under test.

[0035] At least one probe board receives timing bus signals from the driving DRAM and is used to perform DRAM bus timing training and calibration and read / write pattern vector testing on the DIE.

[0036] In one embodiment, the test board is further configured to cache the test data read by the probe board during the read operation and then send it to the host computer;

[0037] The host computer is used to receive the test data, perform algorithm analysis, locate the fault in the address line or data line of the DIE, and obtain the test results.

[0038] In one embodiment, the test board includes:

[0039] The control unit is communicatively connected to the host computer and electrically connected to the functional test unit. It is used to receive the pattern vector test program, configuration parameters, test start command or test reset command issued by the host computer and send them to the functional test unit.

[0040] The functional test unit, electrically connected to the interface adapter unit, is used to execute pattern vector test programs, parameter configurations, test start commands, or test reset commands issued by the control unit, and output timing bus signals driving the DRAM to the interface adapter unit.

[0041] The test data read during the probe card reading operation is cached and sent to the host computer through the interface conversion unit and the control unit.

[0042] The interface conversion unit is electrically connected to the probe board and is used to convert the signals and commands generated by the functional test unit and send them to the probe board.

[0043] The power adapter unit is electrically connected to the functional test unit and the interface conversion unit, and is used to supply power to the functional test unit and the interface conversion unit, providing the required core voltage and I / O interface standard voltage.

[0044] This application first determines the timing by pre-writing and / or pre-reading multiple DIEs under test to determine the actual sampling interval of the read and write data for each DIE. This allows for testing of DIEs with different brands and capacities of DRAM, ensuring that test data can be correctly written and read to locate faults in the data lines and address lines of the DIE. Secondly, a pattern vector test program generates third data for testing data line and address line faults. Then, the third data is written to each DIE under test at the corresponding actual sampling interval, and the data in the DIE under test is read at the actual sampling interval to obtain fourth data. The difference between the third and fourth data is used to locate the faults in the data lines or address lines. Attached Figure Description

[0045] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0046] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 This is a flowchart illustrating an embodiment of the diagnostic method for DIE data line and address line faults in this application.

[0048] Figure 2This is a flowchart illustrating a second embodiment of the diagnostic method for DIE data line and address line faults in this application.

[0049] Figure 3 This is a flowchart illustrating Embodiment 3 of the diagnostic method for DIE data line and address line faults in this application.

[0050] Figure 4 This is a flowchart illustrating Embodiment 4 of the diagnostic method for DIE data line and address line faults in this application.

[0051] Figure 5 This is a flowchart illustrating Embodiment 5 of the diagnostic method for DIE data line and address line faults in this application.

[0052] Figure 6 This is a flowchart illustrating a sixth embodiment of the diagnostic method for DIE data line and address line faults in this application.

[0053] Figure 7 This is a schematic diagram of the device structure of the test system for DIE data line and address line faults in the embodiments of this application.

[0054] The following are the reference numerals: 1. Host computer; 2. Test board; 21. Control unit; 22. Functional test unit; 23. Interface adapter unit; 24. Power adapter unit; 3. Probe board.

[0055] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0056] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0057] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0058] The main solution of this application embodiment is: to pre-write and / or pre-read multiple DIEs under test to determine the actual sampling interval of the read and write data of each DIE under test; to obtain a pattern vector test program, which is used to generate third data for testing faults; to write the third data to each DIE under test at the corresponding actual sampling interval; to read the data in the DIE under test at the actual sampling interval to obtain fourth data; and to locate the fault of the data line or address line based on the third data and the fourth data.

[0059] Die testing, or chip testing, is the functional and performance testing of individual chips (dies) using automated testing equipment during the semiconductor manufacturing process. These tests are typically performed after the chip has been cut from the wafer, but in some cases, they may also be performed on the wafer (Wafer Level Test).

[0060] DDR (Double Data Rate) DRAM (Dynamic Random Access Memory) die testing is a crucial step in ensuring the quality of memory chips. A DDR die refers to a bare memory chip that undergoes a series of tests before packaging. These tests aim to verify the functional integrity of each die and ensure that they meet performance and reliability standards.

[0061] Currently, DRAM die testing methods are only preliminary and simple read / write tests, which can only verify whether each memory cell can store and retrieve data. They cannot accurately pinpoint the faulty data lines and address lines.

[0062] This application determines timing by pre-writing and / or pre-reading multiple DRAMs under test to determine the actual sampling interval of read and write data for each DRAM under test. This allows for testing of DRAMs of different brands and capacities, ensuring that test data can be correctly written and read to locate faults in the data lines and address lines of the DRAM. Secondly, a pattern vector test program is used to generate third data for testing data line and address line faults. Then, the third data is written to each DRAM under test at the corresponding actual sampling interval, and then the data in the DRAM under test is read at the actual sampling interval to obtain fourth data. The difference between the third data and the fourth data is used to locate the faults in the data lines or address lines.

[0063] It should be noted that the execution subject in this embodiment can be a DIE testing system, or a computing service device with data processing, network communication, and program execution functions, such as automated test equipment (ATE), or a DIE testing device capable of performing the above functions. This embodiment does not specifically limit it in this way. The following uses an automated test device as the execution subject as an example to describe this embodiment and the following embodiments.

[0064] Automated Test Equipment (ATE) is a highly integrated test platform used for the automated testing of semiconductor devices. An ATE system typically includes test heads, probe cards, test software, and various auxiliary devices. It automatically applies test signals to the chip under test (DUT) and collects and analyzes the response signals. ATE can perform various types of tests, including functional tests, timing tests, and performance tests, to ensure that the chip's functionality, reliability, and performance meet specifications. ATE systems are widely used in wafer-level testing (WLT), chip-level testing (CP), and final product testing after packaging, and are one of the indispensable key pieces of equipment in semiconductor manufacturing and testing processes.

[0065] Based on this, this application proposes a diagnostic method for DIE data line and address line faults according to the first embodiment, used to test multiple DIEs under test. Please refer to... Figure 1 The diagnostic method for DIE data line and address line faults includes steps S100 to S300:

[0066] Step S100: Pre-write and / or pre-read the multiple DIEs under test to determine the actual sampling interval of the read and write data of each DIE under test;

[0067] Step S200: Obtain the pattern vector test program, which is used to generate third data for testing faults;

[0068] Step S300: Write the third data to each DIE under test at the corresponding actual sampling interval, read the data in the DIE under test at the actual sampling interval to obtain the fourth data, and locate the fault of the data line or address line based on the third data and the fourth data.

[0069] DDR (Double Data Rate) memory transmits data on both the rising and falling edges of the clock signal, enabling two data transfers within a single clock cycle. Therefore, the waveform of a data write operation shows two data bits per clock cycle, sampled at each of the two clock edges. This design allows DDR memory to achieve a transfer rate twice the clock frequency.

[0070] Sampling time is a critical moment for reading or writing data in DDR memory. The DDR memory controller samples data on the rising and falling edges of the clock, so the data waveform must be stable at these moments. To ensure reliable data transmission, DDR memory must strictly adhere to timing parameters that define data validity, hold time, and latency for various operations.

[0071] Timing parameters directly affect the relationship between the data waveform and the sampling time. For example, t DQSS (Data deviation from clock signal) and t DQSQ Timing parameters such as the deviation between the data and the data strobe signal determine the stability of the data waveform at the clock edge, thus affecting whether the memory controller can accurately acquire data during sampling. Improper timing settings may cause the data to be unstable at the sampling moment, resulting in errors.

[0072] Because the timing of DRAMs of different brands and capacities is different, the timing of data writing or reading during testing may be mismatched. The controller may sample data at the wrong time, which may cause the data to fail to be written to memory correctly. The data read may be inconsistent with the actual stored data, resulting in data loss or inaccurate stored content. In some cases, some data bits may even fail to be written successfully.

[0073] In actual testing, due to differences in test equipment hardware, such as PCB design, signal integrity, temperature, voltage, etc., even if the test is performed according to the standard timing in the manufacturer's design specifications, the write operation may still fail, the data waveform may be unstable, and the data write may fail.

[0074] In this embodiment, the actual sampling interval of the read and write data of each DIE under test is determined by pre-writing and / or pre-reading multiple DIEs under test. The timing parameters are then further adjusted and optimized to determine the timing parameters corresponding to the current hardware environment and chip characteristics. This allows for the testing of DIEs of different brands and capacities of DRAM, ensuring that test data can be correctly written and read out in order to locate faults in the data lines and address lines of the DIE.

[0075] In this embodiment, after determining the actual sampling interval, a third data for testing data line and address line faults is generated through a pattern vector test program. Then, the third data is written to each DIE under test according to the corresponding actual sampling interval. The data in the DIE under test is then read according to the actual sampling interval to obtain the fourth data. The fault of the data line or address line is located based on the difference between the third data and the fourth data.

[0076] In DDR die (Dynamic Random Access Memory) chip testing, a pattern vector test program is used to generate test vectors. A test vector refers to a specific data pattern used to test the memory; in other words, it is the third data used in this application to test for faults. These vectors are typically a series of binary values ​​written to different locations in the memory and subsequently read back to verify whether the memory behaves as expected.

[0077] For example, the pattern vector test program generates a set of predetermined data patterns, which are typically simple binary sequences such as all zeros (0x00), all ones (0xFF), alternating 0 / 1 sequences (e.g., 0x55, 0xAA), diagonal sequences (e.g., 0x11, 0x22, etc.), and more complex pseudo-random sequences (PRBS). The test program writes these predefined data patterns into specific addresses or address ranges in the DDR memory. This process may cover the entire memory or selectively test only certain areas.

[0078] After the write operation is complete, the test program reads data from the same address, in other words, the fourth data in this application, and compares it with the previously written third data. If the read fourth data matches the written third data perfectly, it indicates that this part of the memory is working correctly. If any mismatch is found, it indicates that the memory may be defective or faulty.

[0079] Known failure modes can be used to test different address ranges one by one, gradually increasing or decreasing the address range to narrow down the range of failure locations, so as to determine which address(s) the failure occurred on.

[0080] Once the faulty address has been identified, you can further test each data line at that address. For example, you can write different patterns to each data line individually and check if the read results are correct. In this way, you can determine which data line is causing the problem.

[0081] Example 1: Location data cable failure

[0082] Suppose that during testing, we find that data reading from a certain address is consistently incorrect. We can use the following steps to locate which data line is causing the problem:

[0083] 1. Select test mode:

[0084] Choose a simple test mode, such as all zeros (0x00) or all ones (0xFF).

[0085] 2. Bit-by-bit testing:

[0086] Write an all-zero pattern to a known fault address in memory.

[0087] Read the data and check if any bit has a non-zero value. If so, the data line corresponding to that bit may be faulty.

[0088] Repeat the above process, this time writing in all-one mode, and check if any bit value is not 1.

[0089] 3. Locate the fault location:

[0090] If the same bit value is found to be inconsistent with expectations in both tests, then there is likely a problem with this data line.

[0091] Record the location of the faulty bit and perform similar tests on other addresses to confirm whether the fault is global or limited to a specific address.

[0092] Example 2: Location address line failure

[0093] If tests show that certain addresses cannot be accessed correctly, we can use the following steps to locate which address line is causing the problem:

[0094] 1. Select test mode:

[0095] Choose a simple test pattern, such as alternating 01 sequences (0x55, 0xAA).

[0096] 2. Address-by-address test:

[0097] Write different addresses in memory using alternating 01 sequences and read the data.

[0098] Check if the read data matches the write pattern. If a certain address consistently fails to read data correctly, the address line associated with that address may be faulty.

[0099] 3. Pattern Change Test:

[0100] Keeping the data mode unchanged, modify the address line values ​​one by one and observe whether the change of a specific address line causes the fault.

[0101] If changing a certain address line consistently causes a malfunction, then that address line is likely faulty.

[0102] By using the above method and through multiple iterations and adjustments to the test plan, the specific data line or address line fault in the memory can be located relatively accurately.

[0103] Reference Figure 2 In another feasible implementation, step S100, the step of pre-writing and / or pre-reading the plurality of DIEs under test to determine the actual sampling interval of the read / write data of each DIE under test, may include steps S110 to S140:

[0104] Step S110: In response to the write enable signal, write first data into the first storage space of the DIE under test at a first sampling interval;

[0105] Step S120: In response to the read enable signal, read the data in the DIE under test at a first sampling interval to obtain the second data;

[0106] Step S130: When the second data is inconsistent with the first data, the first sampling interval is adjusted and then the first data is written to the first storage space of the DIE under test in response to the write enable signal at the first sampling interval.

[0107] Step S140: When the second data is consistent with the first data, record the first sampling interval as the actual sampling interval.

[0108] In this embodiment, the write enable signal (WE# or WE) is a signal used to control the write operation of the memory chip, indicating when the memory should receive data and write it to a specified address. When the write enable signal is activated (usually low level, represented as WE#, where "#" indicates active low), it indicates that the memory chip is ready to accept data writing. Simultaneously, signals on the address and data lines, as well as other possible control signals (such as CAS#, column address strobe signal), determine the exact location of the data to be written. After the write enable signal is activated, after a first sampling interval, the first data to be written to the memory chip is sampled at the rising and / or falling edge of the clock signal, and then written to the first storage space of the DIE under test. The first storage space can be any storage capacity in the DDR die; it is understood that a smaller value can be selected in this application to achieve rapid verification. Preferably, the first storage space can be the first 32 bytes of the DDR die's address space.

[0109] In this embodiment, assuming the starting address of the memory is 0x0000, the address range of the first 32 bytes is 0x0000 to 0x001F (hexadecimal representation). A series of predetermined test patterns are generated, such as all zeros, all one, alternating 0 / 1 sequences, etc., and these patterns are written into the address space of the first 32 bytes. After writing is complete, data is read from these addresses and compared with the initially written test patterns. If the read data is completely consistent with the written pattern, it indicates that the sampling interval is correct, that is, the sampling time point for reading the data is appropriate, and this part of the memory is functioning normally. If there is any mismatch, it indicates that this part of the memory may have a defect or fault. If data inconsistency is found during the reading process, the sampling interval (i.e., the time point for reading the data) is adjusted to try to find a suitable sampling time point so that the read data is consistent with the written data. When a sampling interval that makes the data consistent is found, this sampling interval is recorded as the actual sampling interval for subsequent tests or other operations.

[0110] By pre-writing and / or pre-reading the first 32 bytes of the memory address space, the sampling interval of the DDR die, i.e. the time point for reading data, can be quickly determined, ensuring that test data can be correctly written and read out in order to locate faults in the data lines and address lines of the DIE.

[0111] Reference Figure 3 In another feasible implementation, step S130, when the second data is inconsistent with the first data, adjusting the first sampling interval and then performing the step of writing the first data to the first storage space of the DIE under test at the first sampling interval in response to the write enable signal, may include step S131:

[0112] Step S131: Increase the value of the first sampling interval by a preset step value.

[0113] In this embodiment, to find a suitable sampling interval to ensure correct data reading, a method of gradually adjusting the sampling interval is adopted. The initial value of the first sampling interval can be set to 1 ns, and one of 1 ns, 2 ns, 3 ns...5 ns can be used as a step value to gradually increase the value of the first sampling interval.

[0114] Specifically, the first sampling interval is set to 1 ns. First data is written to the first storage space of the DIE under test. Second data is obtained by reading data at 1 ns sampling intervals. The second data is compared with the first data. If they match, step S140 is executed, and the current sampling interval (1 ns) is recorded as the actual sampling interval. If they do not match, step S131 is executed, a step value is selected, such as 1 ns, and the first sampling interval is increased by 1 ns, becoming 2 ns. The steps of writing the first data to the first storage space of the DIE under test and reading the data to obtain the second data are repeated, i.e., writing and reading data at 2 ns sampling intervals and comparing them. The sampling interval is gradually increased by the selected step value, such as 3 ns, 4 ns, 5 ns, etc., until a sampling interval that makes the second data consistent with the first data is found.

[0115] Because the sampling interval needs to allow sufficient margin to meet the requirements of the setting and hold times, if the sampling interval is greater than a quarter of a clock cycle, the data may not be stable at the time of sampling or may change immediately after sampling, leading to reading errors. To prevent clock edge overlap, in this embodiment, the value of the first sampling interval is less than a quarter of a clock cycle. This method allows for gradual adjustment of the sampling interval until a sampling interval that ensures correct data reading without being too large is found. This ensures that the data has sufficient time to remain stable before and after the sampling point, while also making full use of the two sampling opportunities within each clock cycle, thereby improving the efficiency and reliability of data transmission.

[0116] Reference Figure 4 In another feasible implementation, when the value of the first sampling interval is greater than a quarter clock cycle and the second data is inconsistent with the first data, step 100, the step of pre-writing and / or pre-reading the multiple DIEs under test to determine the actual sampling interval of the read / write data of each DIE under test, includes step 150:

[0117] Step S150: Locate the fault in the data line or address line corresponding to the first storage space based on the first data and the second data.

[0118] In this embodiment, if the value of the first sampling interval is greater than a quarter of a clock cycle and the second data is inconsistent with the first data, it means that there is a fault in the data line or address line in the first storage space, and it is necessary to locate the specific location of the fault in the data line or address line in the first storage space.

[0119] Specifically, assuming the first sampling interval is set to 0.5ns, the clock period is 1ns (i.e., a quarter period is 0.25ns), and the second data is found to be inconsistent with the first data, a simple test mode is selected, such as all zeros, all one, or alternating 01 sequences. The all-zero mode is written to address 0x0000 in memory, and data is read at 0.5ns sampling intervals. The data lines are tested bit by bit, changing the data mode of only one bit at a time. If the data of a certain bit is consistently inconsistent, the data line corresponding to that bit may be faulty.

[0120] Use the same test pattern, but test each address individually. If the data at a certain address is consistently inconsistent, the address line may be faulty. Record the specific location of the fault (e.g., data line DQ[7], address line A

[10] ).

[0121] By following the steps described above, specific data line or address line faults can be gradually located, thus helping to pinpoint the problem within the memory chip. This step-by-step location method can effectively narrow down the scope of the fault and ultimately find the root cause of the problem.

[0122] Reference Figure 5 In another feasible implementation,

[0123] In step S300, the third data is written to each DIE under test at the corresponding actual sampling interval, and the fourth data is obtained by reading the data in the DIE under test at the actual sampling interval. In the step of locating the fault of the data line or address line based on the third data and the fourth data, the third data includes 0x0000000000000000 and 0xFFFFFFFFFFFFFFFF. Step S300 also includes steps S310 to S330:

[0124] Step S310: Write 0x0000000000000000 and 0xFFFFFFFFFFFFFFFF to the first row address line of the second storage space of the DIE; read the data in the second storage space to obtain the fourth data; and compare each data bit in the fourth data with each data bit in the third data.

[0125] Step S320: If the fourth data is inconsistent with the third data, find the data bits that are different, i.e., there is an erroneous storage unit. If the fourth data is consistent with the third data, write 0x0000000000000000 and 0xFFFFFFFFFFFFFFFF to the first row address line of the second storage space of the DIE, read the data of the second storage space to obtain the fourth data, and compare each data bit in the fourth data with each data bit in the third data.

[0126] Step S330: If the fourth data is inconsistent with the third data, find the data bits that are different, that is, there is an erroneous storage unit; if the fourth data is consistent with the third data, then diagnose the first row of address lines as normal.

[0127] Because the internal structure of DRAM (Dynamic Random Access Memory) consists of a series of memory cells, these cells are typically arranged in a matrix. Each memory cell can only store one bit (0 or 1). Each memory cell in DRAM typically consists of a transistor and a capacitor. The capacitor stores electrical charge, representing a data bit (0 or 1). The transistor controls the charging and discharging of the capacitor, thereby enabling data read and write operations. To access these memory cells, DRAM uses address lines and data lines to specify and transmit data. The memory cells of DRAM are arranged in a two-dimensional matrix, forming a row and column structure. This matrix structure allows the location of a memory cell to be uniquely determined by its row and column addresses.

[0128] Address lines are used to specify the location of the memory cell to be accessed. Address lines are divided into row address lines and column address lines. Row address lines select the row containing the memory cell, and column address lines select the column containing the memory cell. The combination of row and column address lines uniquely determines the location of a memory cell. For example, an 8x8 matrix requires 3 row address lines and 3 column address lines (because 2... 3 =8).

[0129] Data lines are used for data transmission. During a read operation, the data lines transmit data from the memory cell to the external circuitry; during a write operation, the data lines transmit data from the external circuitry to the memory cell.

[0130] In this embodiment, the third data includes first test data and second test data, where the second test data is the inverse of the first test data. To detect the integrity and independence of the data lines and address lines, the first test data is written first, followed by the inverse of the first test data, i.e., the second test data, such as 0x00000000 and 0xFFFFFFFF. This ensures that each data line can correctly transmit 0 and 1. If a data line cannot correctly transmit 0 or 1, this will be detected immediately. For example, if 0x00000000 is written and then 0x00000001 is read back, it indicates that a data line may be short-circuited with other data lines.

[0131] Furthermore, writing 0x00000000 and 0xFFFFFFFF to different addresses ensures the correctness of the address lines. For example, if you write 0x00000000 to address 0x0000 and then write 0xFFFFFFFF to address 0x0001, the readback data should return 0x00000000 and 0xFFFFFFFF respectively. If the readback data is inconsistent, it indicates a possible error in the address lines.

[0132] Reference Figure 6In another feasible implementation,

[0133] In step S300, the third data is written to each DIE under test at the corresponding actual sampling interval, and the fourth data is obtained by reading the data in the DIE under test at the actual sampling interval. In the step of locating the fault of the data line or address line based on the third data and the fourth data, the third data includes 0xAAAAAAAAAAAAAAAA and 0x5555555555555555. Step S300 also includes steps S340 to S360:

[0134] S340, write 0xAAAAAAAAAAAAAAAA and 0x5555555555555555 to the first row address line of the second storage space of the DIE, read the data in the second storage space to obtain the fourth data, and compare each data bit in the fourth data with each data bit in the third data;

[0135] S350, if the fourth data is inconsistent with the third data, find the data bits that are different, i.e., there is an erroneous storage unit; if the fourth data is consistent with the third data, write 0xAAAAAAAAAAAAAAAA or 0x5555555555555555 to the first row address line of the second storage space of the DIE, read the data of the second storage space to obtain the fourth data, and compare each data bit in the fourth data with each data bit in the third data;

[0136] S360, if the fourth data is inconsistent with the third data, find the data bits that are different, that is, there is an erroneous storage unit; if the fourth data is consistent with the third data, then diagnose the first row of address lines as normal.

[0137] In this embodiment, the third data includes first test data and second test data, wherein the second test data is the inverse of the first test data. To detect the integrity and independence of the data lines and address lines, the first test data is written first, followed by the inverse of the first test data, i.e., the second test data, such as 0xAAAAAAAAAAAAAAAA and 0x5555555555555555. This can detect short circuits or interference between the data lines. If there is a short circuit between the data lines, the data read back after writing 0x00000000 may contain some 0s that are incorrectly read as 1s, and vice versa.

[0138] The following explanation uses an 8-bit data bus with an address range from 0 to 7 as an example:

[0139] The binary representation of 0xAAAAAAAAAAAAAAAA is:

[0140] 1010101010101010101010101010101010101010101010101010101010101010101010.

[0141] The binary representation of 0x55555555555555 is:

[0142] 01 ...

[0143] If a short circuit occurs between two adjacent data lines, the written data may interfere with each other, leading to data errors. If there is electromagnetic interference between two adjacent data lines, the written data may be read or written incorrectly.

[0144] Detection steps

[0145] 1. Write alternation mode:

[0146] Write an alternating pattern of 0s and 1s (0xAAAAAAAAAAAAAAAA) into a range of memory addresses.

[0147] Write an alternating pattern of 1s and 0s (0x55555555555555555) to another address range in memory.

[0148] 2. Read back the data:

[0149] Read back data from the address range that was written in an alternating 0 and 1 pattern.

[0150] Read back data from the address range where alternating 1 and 0 patterns are written.

[0151] 3. Validate the data:

[0152] Compare the read data with the written data to see if they are consistent.

[0153] If the data read back is inconsistent with the data written, it indicates that there may be a short circuit or interference problem.

[0154] Specific examples

[0155] Suppose we have an 8-bit data bus with an address range from 0 to 7.

[0156] 1. Write alternating 0 and 1 mode:

[0157] Write the data to address 0: 0xAAAAAAAA (binary: 10101010).

[0158] Data written to address 1: 0xAAAAAAAA (binary: 10101010).

[0159] Data written to address 2: 0xAAAAAAAA (binary: 10101010).

[0160] Data written to address 3: 0xAAAAAAAA (binary: 10101010).

[0161] 2. Write alternating 1 and 0 mode:

[0162] Write the data to address 4: 0x55555555 (binary: 01010101).

[0163] Data written to address 5: 0x55555555 (binary: 01010101).

[0164] Data written to address 6: 0x55555555 (binary: 01010101).

[0165] Data written to address 7: 0x55555555 (binary: 01010101).

[0166] 3. Read back the data:

[0167] Data read back from address 0: 10101010.

[0168] Data read back from address 1: 10101010.

[0169] Data read back from address 2: 10101010.

[0170] Data read back from address 3: 10101010.

[0171] Data read back from address 4: 01010101.

[0172] Data read back from address 5: 01010101.

[0173] Data read back from address 6: 01010101.

[0174] Data read back from address 7: 01010101.

[0175] 4. Validate the data:

[0176] Compare the read data with the written data to see if they are consistent.

[0177] If the data read back is inconsistent with the data written, it indicates that there may be a short circuit or interference problem.

[0178] Analysis results: Short circuit detection: If a short circuit occurs between adjacent data lines, the written data may affect each other between the two lines. For example, if a short circuit occurs between data line 0 and data line 1, writing 10101010 may result in 11111111 or 00000000.

[0179] Interference detection: If there is electromagnetic interference between adjacent data lines, the written data may be read or written incorrectly. For example, writing 10101010 may result in reading back 10101011 or 10101000.

[0180] This method can help to effectively detect and locate short circuits and interference problems between data lines.

[0181] In this embodiment, writing the opposite data pattern can cover more test scenarios, ensuring that all parts of the memory are fully tested. For example, writing 0x00000000 and 0xFFFFFFFF can detect all 0s and all 1s, while writing 0xAAAAAAAA and 0x55555555 can detect alternating patterns.

[0182] It should be noted that the above examples are only for understanding this application and do not constitute a limitation on the diagnostic method for DIE data line and address line faults in this application. Any simple modifications based on this technical concept are within the protection scope of this application.

[0183] This application also provides a testing system for DIE data line and address line faults; please refer to [reference needed]. Figure 7 The testing system for DIE data line and address line faults includes: a host computer, a test board, and at least one probe card.

[0184] The host computer is connected to the test board and is used to send the pattern vector test program, the DIE specification parameters under test, and the test start / reset command to the test board.

[0185] The test board is used to receive the pattern vector test program, the DIE specification parameters under test, and the test start / reset command, and is used to output the timing bus signal driving the DRAM to the probe card board according to the pattern vector test program and the DIE specification parameters under test.

[0186] The probe board receives the timing bus signal of the driving DRAM and is used to perform DRAM bus timing training and calibration and read / write pattern vector testing on the DIE.

[0187] In some implementations, the test board is further configured to cache the test data read by the probe card during the read operation and then send it to the host computer. The host computer receives the test data, performs algorithm analysis, locates the address line or data line fault of the DIE, and obtains the test results.

[0188] In some implementations, the test board includes a control unit, a functional test unit, an interface adapter, and a power adapter unit.

[0189] The control unit is communicatively connected to the host computer and electrically connected to the functional test unit, and is used to receive the pattern vector test program, configuration parameters, test start command or test reset command issued by the host computer and send them to the functional test unit.

[0190] The functional test unit is electrically connected to the interface conversion unit and is used to execute the pattern vector test program, parameter configuration, test start command or test reset command issued by the control unit, and output the timing bus signal driving the DRAM to the interface conversion unit.

[0191] The functional testing unit caches the test data read during the probe card reading operation and sends it to the host computer through the interface transfer unit and the control unit.

[0192] The interface conversion unit is electrically connected to the probe board and is used to convert the signals and instructions generated by the functional test unit and send them to the probe board.

[0193] The power adapter unit is electrically connected to the functional test unit and the interface conversion unit, and is used to supply power to the functional test unit and the interface conversion unit, providing the required core voltage and IO interface standard voltage.

[0194] The above description is only a part of the embodiments of this application and does not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. A method for diagnosing faults in DIE data lines and address lines, used to test multiple DIEs under test, characterized in that, The method includes: Pre-write and / or pre-read of multiple DIEs under test are performed to determine the actual sampling interval of the read and write data of each DIE under test, wherein each DIE under test is a DIE of dynamic random access memory; Obtain a pattern vector test program, which is used to generate third data for testing faults; The third data is written to each DIE under test at the corresponding actual sampling interval, and the fourth data is obtained by reading the data in the DIE under test at the actual sampling interval. The fault of the data line or address line is located according to the third data and the fourth data. The step of pre-writing and / or pre-reading multiple DIEs under test to determine the actual sampling interval of the read / write data for each DIE under test includes: In response to the write enable signal, first data is written to the first storage space of the DIE under test at a first sampling interval; In response to the read enable signal, data is read from the DIE under test at a first sampling interval to obtain second data; When the second data is inconsistent with the first data, the first sampling interval is adjusted and then the first data is written to the first storage space of the DIE under test in response to the write enable signal at the first sampling interval. When the second data matches the first data, the first sampling interval is recorded as the actual sampling interval.

2. The method as described in claim 1, characterized in that, The step of adjusting the first sampling interval and writing the first data to the first storage space of the DIE under test at the first sampling interval in response to the write enable signal when the second data is inconsistent with the first data further includes: The value of the first sampling interval is increased by a preset step value.

3. The method as described in claim 2, characterized in that, In the step of adjusting the first sampling interval, the value of the first sampling interval is increased by a preset step value. The value of the first sampling interval is less than a quarter of a clock cycle.

4. The method as described in claim 3, characterized in that, When the value of the first sampling interval is greater than one-quarter of a clock cycle, and the second data is inconsistent with the first data, the step of pre-writing and / or pre-reading the multiple DIEs under test to determine the actual sampling interval of the read / write data of each DIE under test includes: Based on the first and second data, faults in the data lines or address lines corresponding to the first storage space are located.

5. The method as described in claim 1, characterized in that, The third data includes 0x0000000000000000 and 0xFFFFFFFFFFFFFFFF; The steps of writing the third data to each DIE under test at the corresponding actual sampling interval, reading the data in the DIE under test at the actual sampling interval to obtain the fourth data, and locating the fault of the data line or address line based on the third data and the fourth data include: Write either 0x0000000000000000 or 0xFFFFFFFFFFFFFFFF to the first row address line of the second storage space of the DIE, read the data in the second storage space to obtain the fourth data, and compare each data bit in the fourth data with each data bit in the third data. If the fourth data is inconsistent with the third data, identify the data bits that differ, i.e., there is an erroneous storage unit. If the fourth data is consistent with the third data, write 0x0000000000000000 and 0xFFFFFFFFFFFFFFFF to the first row address line of the second storage space of the DIE, read the data in the second storage space to obtain the fourth data, and compare each data bit in the fourth data with each data bit in the third data. If the fourth data is inconsistent with the third data, identify the data bits that are different, i.e., there is an erroneous storage unit. If the fourth data is consistent with the third data, diagnose the first row of address lines as normal.

6. The method as described in claim 5, characterized in that, The third data includes 0xAAAAAAAAAAAAAAAA and 0x5555555555555555; The steps of writing the third data to each DIE under test at the corresponding actual sampling interval, reading the data in the DIE under test at the actual sampling interval to obtain the fourth data, and locating the fault of the data line or address line based on the third data and the fourth data include: Write either 0xAAAAAAAAAAAAAAAA or 0x5555555555555555 to the first row address line of the second storage space of the DIE, read the data in the second storage space to obtain the fourth data, and compare each data bit in the fourth data with each data bit in the third data. If the fourth data is inconsistent with the third data, identify the data bits that differ, i.e., there is an erroneous storage unit. If the fourth data is consistent with the third data, write 0xAAAAAAAAAAAAAAAA or 0x5555555555555555 to the first row address line of the second storage space of the DIE. Read the data in the second storage space to obtain the fourth data, and compare each data bit in the fourth data with each data bit in the third data. If the fourth data is inconsistent with the third data, identify the data bits that are different, i.e., there is an erroneous storage unit. If the fourth data is consistent with the third data, diagnose the first row of address lines as normal.

7. A testing system for DIE data line and address line faults, used to perform the method as described in claims 1-6, characterized in that, include: The host computer is connected to the test board and is used to send the pattern vector test program, the DIE specification parameters under test and the test start / reset command to the test board. The test board receives the pattern vector test program, the DIE specification parameters under test, and the test start / reset command, and is used to output the timing bus signal driving the DRAM to the probe card board according to the pattern vector test program and the DIE specification parameters under test. At least one probe board receives timing bus signals from the driving DRAM and is used to perform DRAM bus timing training and calibration and read / write pattern vector testing on the DIE.

8. The testing system for DIE data line and address line faults as described in claim 7, characterized in that, The test board is also used to cache the test data read by the probe board during the read operation and then send it to the host computer; The host computer is used to receive the test data, perform algorithm analysis, locate the fault in the address line or data line of the DIE, and obtain the test results.

9. The testing system for DIE data line and address line faults as described in claim 8, characterized in that, The test board includes: The control unit is communicatively connected to the host computer and electrically connected to the functional test unit. It is used to receive the pattern vector test program, configuration parameters, test start command or test reset command issued by the host computer and send them to the functional test unit. Interface conversion unit; The functional test unit, electrically connected to the interface adapter unit, is used to execute pattern vector test programs, parameter configurations, test start commands, or test reset commands issued by the control unit, and output timing bus signals driving the DRAM to the interface adapter unit. The test data read by the probe card during the read operation is cached by the interface conversion unit and the control unit and then sent to the host computer. The interface conversion unit is electrically connected to the probe board and is used to convert the signals and instructions generated by the functional test unit and send them to the probe board. The power adapter unit is electrically connected to the functional test unit and the interface conversion unit, and is used to supply power to the functional test unit and the interface conversion unit, providing the required core voltage and I / O interface standard voltage.

Images