A method for repairing sparse failed cells in a memory chip

Abstract

The present invention relates to the field of chip testing technology, and specifically discloses a method for repairing sparse failure units in a memory chip, comprising: step 1: a chip tester runs a test program to obtain the failure unit circuit information of the entire memory chip; firstly, a repair scheme for the failure unit circuit of a preset area is allocated, and the remaining sparse failure unit circuits are stored in a hash table data structure; step 2: the failure unit circuit information of all memory chips obtained in step 1 is obtained, and an adjacency matrix of a failure unit set is constructed; step 3: according to the adjacency matrix obtained in step 2, a repair scheme is allocated to the failure unit circuit; step 4: steps 2-3 are repeated until all data in the set is cleared, and a repair scheme for the entire memory chip is obtained. The present invention can effectively reduce the usage of spare circuits and improve product yield.

Description

Technical Field

[0001] The present invention relates to the field of chip testing technology, and in particular to a method for repairing sparse failure units in a storage chip. Background Art

[0002] Memory chip testing is mainly aimed at memory, including random access memory, flash memory, etc., which are semiconductor components used to store and read data or program codes. The test content includes some performance parameters, such as read time, write recovery time, data retention time, etc. The purpose of these tests is to ensure that the memory can reliably and accurately store and read data under various conditions.

[0003] Compared with the testing of system-level chips, memory chips have additional repair processes. The tester obtains the failed circuit information of each chip according to the test requirements and forms a log file of the failed unit circuit. The repair analysis program of the tester loads the log file, generates a repair plan, and uses spare circuits to repair the damaged circuit. Spare circuits are mainly divided into two types: row spare circuits and column spare circuits. The above figure shows a group of row spare circuits and two groups of column spare circuits. In the circuit repair process, if there is a failed unit circuit in the normal circuit, a group of rows or columns needs to be allocated to repair the area. If the number of spare circuits on each chip cannot repair the damaged circuit area on the chip, the chip is discarded and does not enter the subsequent process.

[0004] Failed cell circuits are divided into row or column specific repair type failed cell circuits and sparse failed cell circuit areas. The repair spare circuit allocation scheme for row or column specific repair type failed cell areas is generally a fixed solution due to spare circuit design. However, for sparse failed cell circuits, since row spare circuits or column spare circuits can be used for repair, the repair scheme is flexible and changeable.

[0005] Since sparse failure unit circuits do not require a specific type of spare circuit to repair, the repair scheme is flexible and changeable. Different repair schemes for the same sparse failure unit circuit have different row or column circuit repair ranges. The same failure unit circuit may be repaired by row or column spare circuits at the same time, and the number of spare circuits used is also different. Based on the above scenario, it can be understood that the repair allocation algorithm of the test machine for handling failed unit circuits can affect the yield of memory chips in the test packaging process. The optimal repair scheme can maximize the economic value of chip production, but due to the complexity of chip repair failure information, the program allocation solution can only achieve a relatively optimal solution. Summary of the invention

[0006] The purpose of the present invention is to provide a method for repairing sparse failed cells in a memory chip to solve the above technical problems.

[0007] The purpose of the present invention can be achieved through the following technical solutions:

[0008] A method for repairing sparse failed cells in a memory chip comprises the following steps:

[0009] Step 1: The chip tester runs the test program to obtain the failure unit circuit information of the entire memory chip; first, the repair scheme of the failure unit circuit in the preset area is allocated, and the remaining sparse failure unit circuits are stored in the hash table data structure, which is recorded as , n represents the number of sparse failure unit circuits, d i Indicates i sparse failure unit circuits and i ≤ n , Respectively represent the block number, data bit number, X address and Y address of the sparse failure unit circuit;

[0010] Step 2: Obtain the failed unit circuit information of all memory chips obtained in step 1, and record the sparse failed unit circuit set of different blocks under different data bits of each memory chip as , in , build The adjacency matrix of the set of failed units;

[0011] Step 3: According to the adjacency matrix obtained in step 2, a repair scheme is assigned to the failed unit circuit;

[0012] Step 4: Repeat steps 2-3 until All data in the collection is cleared, and a repair plan for the entire storage chip is obtained.

[0013] As a further solution of the present invention: in the step 2, construct The specific method of the adjacency matrix of the failed unit set is as follows:

[0014] Get the maximum number of units in the X-axis direction of each block max_ x , the maximum number of units in the Y-axis direction max_ y , create a max_ x *max_ y The two-dimensional matrix M is initialized with all values ​​0;

[0015] Traverse the information of all failed units under the data bit and update the two-dimensional matrix M;

[0016] Create a one-dimensional matrix from the two-dimensional matrix M , respectively record the number of failed units at different coordinates in the X-axis direction of the two-dimensional matrix M and the number of failed units at different coordinates in the Y-axis direction.

[0017] As a further solution of the present invention: In step 3, the specific method of assigning a repair solution to the failed unit circuit is as follows:

[0018] When the row and column spare circuits are not used up, the one-dimensional matrix V is obtained respectively. X and V Y The maximum value in the X-axis coordinate system is recorded. x and the corresponding number of failed units v x , Y-axis coordinate value y and the corresponding number of failed units v y , and calculate the actual repair efficiency γ corresponding to these two coordinates x , γ y ;

[0019] The calculation formula is:

[0020] ;

[0021] Among them, H X It represents the number of failed cells that can be repaired by a set of row spare circuits, H Y It indicates the number of failed cells that can be repaired by a set of column spare circuits;

[0022] If γ x ≥γ y , then assign the X-axis coordinate value x As a repair solution, on the contrary, assign the Y axis coordinate value y As a repair solution;

[0023] From a collection of sparsely failed cell circuits Delete the failed unit where the assigned repair solution is located, and update median;

[0024] Update the two-dimensional matrix M and set the coordinate position of the repair solution to 0;

[0025] Update V X and V Y If the repair solution is the coordinate value on the X axis, then V X The corresponding coordinate value in is set to 0, V Y All non-zero values ​​in the y-axis are reduced by 1. If the repair solution is the coordinate value on the Y axis, V Y The corresponding coordinate value in is set to 0, V X All non-zero values ​​in are decremented by 1.

[0026] As a further solution of the present invention: in step 3, the method of allocating a repair solution to the failed unit circuit further includes:

[0027] When the row backup circuit is used up, get V Y The number of non-zero values ​​of the matrix, if the V Y If the number of non-zero values ​​in the matrix is ​​less than the number of column spare circuits, then V Y The Y coordinate set corresponding to the non-zero value in is used as the repair solution;

[0028] from Delete the failed unit where the assigned repair solution is located in the collection, and update , and return to step 2.

[0029] As a further solution of the present invention: when the row standby circuit is used up and V Y When the number of non-zero values ​​of the matrix is ​​greater than the number of column spare circuits, it returns directly, determines that the current tested memory chip is unrepairable, and stops iteration.

[0030] As a further solution of the present invention: in step 3, the method of allocating a repair solution to the failed unit circuit further includes:

[0031] When the column spare circuit is used up, get V X The number of non-zero values ​​of the matrix, if the V X If the number of non-zero values ​​in the matrix is ​​less than the number of row spare circuits, then V X The set of X coordinates in the middle is used as the repair solution;

[0032] from Delete the failed unit where the assigned repair solution is located in the collection, and update , and return to step 2.

[0033] As a further solution of the present invention: when the column standby circuit is used up and the V X When the number of non-zero values ​​of the matrix is ​​greater than the number of row spare circuits, it returns directly, determines that the current tested memory chip is unrepairable, and stops iteration.

[0034] As a further solution of the present invention: the specific method of traversing the information of all failed units under the data bit and updating the two-dimensional matrix M is:

[0035] When the X address of the failed unit A is x 1 , the Y address of the failed unit A is y 1 , update the two-dimensional matrix M and transform the node x 1 and y1 The value of the indicated position is updated to 1.

[0036] Beneficial effects of the present invention: The present invention has important applications in the process of memory chip repair, especially for the calculation of repair solutions for sparse failed unit circuits. In this process, the key indicator of actual repair efficiency is introduced. This indicator can play a guiding role in the operation of the method, so that the whole process is always carried out in the direction of selecting a relatively better repair solution. This method can effectively avoid the problem of low utilization of row and column spare circuits when repairing sparse failed unit circuits. Furthermore, the usage of spare circuits can be effectively reduced, and for the memory chip repair process (this process is in the later stage), the yield will also be improved, ensuring the high-quality completion of the memory chip repair work. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The present invention will be further described below in conjunction with the accompanying drawings.

[0038] Figure 1 is a schematic diagram of a failed unit circuit and a normal circuit in the present invention;

[0039] Figure 2 It is a memory chip area spare circuit repair diagram in the present invention;

[0040] Figure 3 It is another memory chip area spare circuit repair diagram in the present invention;

[0041] Figure 4 is a failure unit distribution diagram provided in an embodiment of the present invention;

[0042] Figure 5 is a diagram of a final repair solution for a sparse failure unit circuit provided in an embodiment of the present invention;

[0043] Figure 6 It is a flow chart of a method for repairing sparse failed cells in a memory chip of the present invention. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0045] What makes memory chips special compared to other types of chips is that the repair process of failed unit circuits can use spare circuits to repair damaged circuits.

[0046] The test program on the test machine will analyze whether the circuit functions normally according to the characteristics of the memory chip. If the circuit functions abnormally, the circuit information is recorded. This circuit is called a failure unit circuit. Figure 1 In order to ensure the normal working function of the chip, the memory chip has a built-in backup circuit to repair the failed unit circuit. The backup circuit is mainly divided into two types: row backup circuit and column backup circuit. Figure 1 There is one set of row spare circuits and two sets of column spare circuits; in the circuit repair process, if there is a failed unit circuit in the normal circuit, a set of rows or columns needs to be allocated to repair the area.

[0047] In the present invention, the failed cell circuit is divided into a row or column specific repair type failed cell circuit and a sparse failed cell circuit. For the repair of the row or column specific repair type failed cell, the spare circuit allocation scheme is generally a fixed solution due to the spare circuit design. For the sparse failed cell circuit, the repair scheme is flexible and changeable because the row spare circuit or column spare circuit can be used for repair.

[0048] In fact, the repair range of the memory chip row and column spare circuits is different, such as Figure 2-Figure 3 As shown in the figure, the normal working circuit range of a memory chip die is composed of multiple regions, each of which contains row spare circuits and column spare circuits (rows and columns are reversed because the actual coordinate system of the chip on the hardware is reversed);

[0049] at the same time, Figure 2-Figure 3 The failed circuit in the figure belongs to a sparse failed unit circuit, which does not require a specific type of spare circuit to repair. The repair scheme is flexible and varied, such as Figure 2-Figure 3 In the above scenario, the repair schemes of scheme 1 and scheme 2 for the same sparse failure unit circuit are different, and the number of spare circuits used is also different. Based on the above scenario, it can be understood that the repair allocation algorithm of the test machine for handling failed unit circuits can affect the yield of memory chips in the test packaging process. The optimal repair scheme can maximize the economic value of chip production, but due to the complexity of chip repair failure information, the program allocation solution can only achieve a relatively optimal solution.

[0050] When the row or column spare circuit repair coverage is considered to be in the current optimal state (using a greedy strategy), the repair scheme of the entire memory chip is searched in a heuristic way. This method can achieve better results than directly repairing the failed unit circuit. However, this method has the problem of complex calculations. Since all the scheme algorithms need to be analyzed, its operation speed is relatively slow.

[0051] like Figure 6As shown, in order to solve the problem of complex calculation, a method for repairing sparse failed cells in a memory chip is proposed, which is mainly used in chip testing equipment and mainly includes the following steps:

[0052] Step 1: The chip tester runs the test program to obtain the failure unit circuit information of the entire memory chip. According to the backup circuit design, the specific type of failure unit is processed. First, a repair plan is assigned to the failure unit circuit in a specific area. At this time, there are still sparse failure unit circuits that have not been assigned a repair plan. These sparse failure unit information is stored in a hash table data structure, recorded as , n represents the number of sparse failure unit circuits, d i Indicates the information of each failed unit. Respectively represent the block number, data bit number, X address, and Y address of the failed unit circuit;

[0053] Step 2: Obtain the failed unit circuit information of all memory chips obtained in step 1, and record the failed unit circuit set of different blocks under different data bits of each memory chip as , in , build The adjacency matrix of the failed unit set; the specific process is as follows,

[0054] Get the maximum number of units in the X-axis direction of each block max_ x , the maximum number of units in the Y-axis direction max_ y , create a max_ x *max_ y The two-dimensional matrix M is initialized with all values ​​0;

[0055] Traverse the information of all failed cells under this data bit and update the two-dimensional matrix M; for example, the X address of failed cell A is , the Y address of the failed unit A is , update the two-dimensional matrix M and transform the node The value of the position represented is updated to 1;

[0056] Create a one-dimensional array from a two-dimensional matrix M , respectively record the number of failed units at different coordinates in the X-axis direction of the two-dimensional matrix M and the number of failed units at different coordinates in the Y-axis direction; , means the number of failed units with X coordinate value 1 is 2, the number of failed units with X coordinate value 1 is 1, and so on;

[0057] Step 3: According to the two-dimensional matrix M and one-dimensional matrix obtained in step 2 , a repair scheme is assigned to the failed unit circuit, and the specific process is as follows;

[0058] When the row and column spare circuits are not used up, the one-dimensional matrix V is obtained respectively. X and V Y The maximum value in the X-axis coordinate system is recorded. x and the corresponding number of failed units v x , Y-axis coordinate value y and the corresponding number of failed units v y , and calculate the actual repair efficiency γ corresponding to these two coordinates x , γ y , and its calculation formula is , where H X It represents the number of failed cells that can be repaired by a set of row spare circuits, H Y It represents the number of failed cells that can be repaired by a set of column spare circuits, H X and H Y Generally, it is a fixed value; if γ x ≥γ y , then assign the X-axis coordinate value x As a repair solution, on the contrary, assign the Y axis coordinate value y As a repair solution; from Delete the failed unit where the assigned repair solution is located in the failed unit set, and update Median; Update the two-dimensional matrix M, set the coordinate position of the repair solution to 0; Update V X and V Y If the repair solution is the coordinate value on the X axis, then V X The corresponding coordinate value in is set to 0, V Y All non-zero values ​​in the y-axis are reduced by 1. If the repair solution is the coordinate value on the Y axis, V Y The corresponding coordinate value in is set to 0, V X All non-zero values ​​in are reduced by 1;

[0059] When the backup circuit is used up, get V Y The number of non-zero values ​​in the matrix. If this value is less than the number of column spare circuits, directly set V Y The Y coordinate set corresponding to the non-zero value in is used as the repair solution, and then, from Delete the failed unit where the assigned repair solution is located in the collection, and update If the value is not the median, return to step 2; otherwise, return directly, the tested memory chip cannot be repaired, and the iteration stops;

[0060] When the column backup circuit is used up, obtain V XThe number of non-zero values ​​in the matrix. If this value is less than the number of row spare circuits, directly set V X The X coordinate set in is used as the repair solution, and then, from Delete the failed unit where the assigned repair solution is located in the collection, and update If the value is not the median, return to step 2; otherwise, return directly, the tested memory chip cannot be repaired, and the iteration stops;

[0061] Step 4: Repeat steps 2 and 3 until All data in the collection is cleared, and a repair plan for the entire storage chip is obtained.

[0062] In a more specific embodiment, Figure 4 As shown, it is a distribution diagram of failed cells in a block under a certain data bit of the tested memory chip, assuming that the block has three groups of downlink spare circuits and two groups of column spare circuits;

[0063] Among them, max_ x =13,max_ y =15, H X =13,H Y =15, and the matrix in the initial state is:

[0064] ;

[0065] V X =[0,2,0,0,1,3,0,1,0,0,1,0,0];

[0066] V Y =[0,3,0,0,0,0,2,0,2,0,0,1,0,0];

[0067] First, 6 X Corresponding The repair efficiency is the highest in the X-axis coordinate, 2 y Corresponding , γ x >γ y , at this time 6 X The actual repair efficiency is the highest, so a set of row spare circuits is allocated to repair 6 X Position, at this time, update the failed unit circuit set, the failed unit two-dimensional matrix M, the one-dimensional matrix V X and V Y , repeat the steps to get the final repair solution as Figure 5 shown.

[0068] The invention has important applications in the memory chip repair process, especially for the calculation of the repair scheme for sparse failed unit circuits. In this process, the key indicator of actual repair efficiency is introduced. This indicator can play a guiding role in the operation of the method, so that the whole process is always carried out in the direction of selecting a relatively better repair solution. This method can effectively avoid the problem of low utilization of row and column spare circuits when repairing sparse failed unit circuits. Furthermore, the use of spare circuits can be effectively reduced, and for the memory chip repair process (this process is in the later stage), the yield will also be improved, ensuring the high-quality completion of the memory chip repair work.

[0069] The above is a detailed description of an embodiment of the present invention, but the content is only a preferred embodiment of the present invention and cannot be considered to limit the scope of implementation of the present invention. All equivalent changes and improvements made within the scope of the present invention should still fall within the scope of the patent coverage of the present invention.

Claims

1. A method for repairing sparse failed cells in a memory chip, characterized in that: The following steps are involved: Step 1: The chip tester runs the test program to obtain the failure unit circuit information of the entire memory chip; first, the repair plan of the failure unit circuit in a specific area is allocated, and the remaining sparse failure unit circuits are stored in the hash table data structure, recorded as , n represents the number of sparse failure unit circuits, d i Indicates i sparse failure unit circuits and i ≤ n , Respectively represent the block number, data bit number, X address and Y address of the sparse failure unit circuit; Step 2: Obtain the failed unit circuit information of all memory chips obtained in step 1, and record the sparse failed unit circuit set of different blocks under different data bits of each memory chip as ,in , build The adjacency matrix of the set of failed units; Step 3: According to the adjacency matrix obtained in step 2, a repair scheme is assigned to the failed unit circuit; Step 4: Repeat steps 2-3 until All data in the collection is cleared, and a repair solution for the entire storage chip is obtained; In step 2, build The specific method of the adjacency matrix of the failed unit set is as follows: Get the maximum number of units in the X-axis direction of each block max_ x , the maximum number of units in the Y-axis direction max_ y， Create a max_ x *max_ y The two-dimensional matrix M is initialized with all values ​​0; Traverse the information of all failed units under the data bit and update the two-dimensional matrix M; Create a one-dimensional matrix from the two-dimensional matrix M and , respectively record the number of failed units at different coordinates in the X-axis direction and the number of failed units at different coordinates in the Y-axis direction of the two-dimensional matrix M; In step 3, the specific method of assigning a repair solution to the failed unit circuit is as follows: When the row and column spare circuits are not used up, the one-dimensional matrix V is obtained respectively. X and V Y The maximum value in the X-axis coordinate system is recorded. x and the corresponding number of failed units v x , Y-axis coordinate value y and the corresponding number of failed units v y , and calculate the actual repair efficiency γ corresponding to these two coordinates x , γ y ; The calculation formula is: ； Among them, H X It represents the number of failed cells that can be repaired by a set of row spare circuits, H Y It indicates the number of failed cells that can be repaired by a set of column spare circuits; If γ x ≥γ y , then assign the X-axis coordinate value x As a repair solution, on the contrary, assign the Y axis coordinate value y As a repair solution; From a collection of sparsely failed cell circuits Delete the failed unit where the assigned repair solution is located, and update median; Update the two-dimensional matrix M and set the coordinate position of the repair solution to 0; Update V X and V Y If the repair solution is the coordinate value on the X axis, then V X The corresponding coordinate value in is set to 0, V Y All non-zero values ​​in the y-axis are reduced by 1. If the repair solution is the coordinate value on the Y axis, V Y The corresponding coordinate value in is set to 0, V X All non-zero values ​​in are decremented by 1.

2. The method for repairing sparse failed cells in a memory chip according to claim 1, characterized in that: In the step 3, the method of allocating a repair solution to the failed unit circuit further includes: When the row backup circuit is used up, get V Y The number of non-zero values ​​of the matrix, if the V Y If the number of non-zero values ​​in the matrix is ​​less than the number of column spare circuits, then V Y The Y coordinate set corresponding to the non-zero value in is used as the repair solution; from Delete the failed unit where the assigned repair solution is located in the collection, and update , and return to step 2.

3. The method for repairing sparse failed cells in a memory chip according to claim 2, characterized in that: When the row backup circuit is used up and V Y When the number of non-zero values ​​of the matrix is ​​greater than the number of column spare circuits, it returns directly, determines that the current tested memory chip is unrepairable, and stops iteration.

4. The method for repairing sparse failed cells in a memory chip according to claim 1, characterized in that: In the step 3, the method of allocating a repair solution to the failed unit circuit further includes: When the column spare circuit is used up, get V X The number of non-zero values ​​of the matrix, if the V X If the number of non-zero values ​​in the matrix is ​​less than the number of row spare circuits, then V X The set of X coordinates in the middle is used as the repair solution; from Delete the failed unit where the assigned repair solution is located in the collection, and update , and return to step 2.

5. The method for repairing sparse failed cells in a memory chip according to claim 4, characterized in that: When the column standby circuit is used up and the V X When the number of non-zero values ​​of the matrix is ​​greater than the number of row spare circuits, it returns directly, determines that the current tested memory chip is unrepairable, and stops iteration.

6. The method for repairing sparse failed cells in a memory chip according to claim 1, characterized in that: The specific method of traversing the information of all failed cells under the data bit and updating the two-dimensional matrix M is: When the X address of the failed unit A is x 1 , the Y address of the failed unit A is y 1 , update the two-dimensional matrix M and transform the node x 1 and y 1 The value of the indicated position is updated to 1.

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