Novel FOWLP substrate-based packaging body and packaging method

Abstract

The invention discloses a novel FOWLP substrate-based packaging body and a novel FOWLP substrate-based packaging method, and belongs to the technical field of FOWLP packaging. Typical single-row pins are improved into double-row pins, the chip and the bonding pad are bonded by using a bottom filling mode of the conductive silver adhesive, and the chip and the substrate are interconnected by using a lead bonding mode; according to the invention, the packaging volume is greatly reduced, the thickness is reduced, the chip spacing is narrower, and the packaging structure is suitable for application scenarios requiring compact layout; the electric appliance transmission path of the packaging body is short, and the packaging body has excellent electrical performance and data transmission; the packaging body can accommodate more leads, and the I / O number is obviously increased; according to the invention, high-efficiency packaging materials and technology are adopted, the packaging integration level is high, and the cost is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of FOWLP packaging, and in particular relates to a novel FOWLP substrate-based packaging body and a packaging method. Background Art

[0002] In the field of semiconductor packaging, the traditional quad flat package (QFP) has some limitations. The pin design of QFP results in a longer conductive path, which not only increases the self-inductance and wiring resistance, but also limits the optimization of its electrical performance. In addition, when the center spacing of the pins is small, the pins are prone to bending, which may cause problems such as poor connection or short circuit. To solve these problems, the industry began to adopt the pinless quad flat package (QFN), which has a shorter conductive path and lower self-inductance and wiring resistance, thereby providing better electrical performance. The QFN package also has good thermal performance because it is equipped with a large area of ​​heat dissipation pads at the bottom of the package. In addition, the QFN package is smaller and lighter, which makes it more popular in miniaturized and portable devices.

[0003] However, the manufacturing process of QFN packaging usually relies on leadframe, which may be insufficient in production efficiency and cost. In order to further improve performance and reliability while reducing costs, the industry has begun to explore fan-out packaging (FOStrip) technology. Fan-out packaging allows more input / output (I / O) points by expanding the wiring area around the chip, which has significant advantages in improving integration and performance. Based on this, the present invention proposes a new FOWLP substrate-based package and packaging method. Summary of the invention

[0004] In view of the above situation, in order to overcome the defects of the prior art, the present invention solves the limitations of the existing QFP and QFN packaging technologies, and can achieve a significant reduction in packaging volume and thickness.

[0005] In order to achieve the above object, the following technical solution is adopted: The present invention provides a novel FOWLP substrate-based packaging method, comprising the following steps:

[0006] S1. UV tape fixing: stick UV tape on the glass substrate or other substrate to ensure a firm connection between the substrate and other process materials;

[0007] S2. Coating PI layer: coating a polyimide (PI) layer on the substrate by spin coating, which has a certain buffer protection effect after curing;

[0008] S3, sputtering Ti / Cu layer: sputtering a layer of titanium / copper on the PI glue to prevent subsequent processes from damaging the substrate;

[0009] S4, photoresist coating: coating a layer of PR glue on the titanium / copper metal layer to prepare for the subsequent exposure and development process;

[0010] S5, Exposure: Through the exposure process, the part of the photoresist exposed to light undergoes chemical changes to achieve the definition of high-precision patterns;

[0011] S6, Development: The development process transfers the pattern of the mask to the photoresist, leaving the desired pattern on the substrate;

[0012] S7, electroplating copper: electroplating copper on the titanium layer to provide electrical connection between the chip and the external circuit, serving as the interconnection structure between the chip and the external pins;

[0013] S8, stripping photoresist: Use dry or wet method to strip all photoresist to prevent residual photoresist from interfering with subsequent processes;

[0014] S9, etching: using an etching solution to remove a titanium / copper metal layer sputtered on the PI;

[0015] S10, chip mounting: Use conductive silver glue to mount the chip on the pad on the substrate;

[0016] S11, wire bonding: Use metal wires to connect the chip to the external circuit;

[0017] S12, plastic encapsulation: perform plastic encapsulation to completely encapsulate the chip and its connecting lines in the plastic package, effectively protecting the chip from physical impact from the external environment;

[0018] S13, substrate removal: removing the substrate to achieve fan-out packaging, so that the I / O interface can be connected to a larger packaging area;

[0019] S14, laser drilling: laser drilling is performed to form through holes as channels for signal transmission, and the pads are exposed by grinding the plate;

[0020] S15, through-hole tinning: Tinning is applied to through-holes to form a continuous metal path in the through-holes, allowing the current to pass smoothly.

[0021] S16, Package cutting: Cut the package to expose the metal pads for subsequent welding or other electrical connections.

[0022] Furthermore, the novel FOWLP substrate-based package is obtained by packaging using the packaging method.

[0023] Furthermore, the size of the package body is 10×10 mm.

[0024] Furthermore, the pad spacing on the package body is 0.5 mm, the pad width is 0.23 mm, the pad length is 0.4 mm, and the pad height is 0.2 mm.

[0025] Furthermore, the I / O of the package may be single-row or double-row.

[0026] Furthermore, when the I / O of the package body is in a single row, the number of the I / Os is 68; when the I / O of the package body is in a double row, the total number of the I / Os is 136.

[0027] The beneficial effects of the present invention are:

[0028] (1) The present invention improves the typical single-row pins into double-row pins, adheres the chip to the pad by using the bottom filling method of conductive silver glue, and interconnects the chip to the substrate by wire bonding;

[0029] (2) The package volume of the present invention is greatly reduced, the thickness is reduced, and the chip spacing is narrower, which is suitable for application scenarios requiring a compact layout;

[0030] (3) The package of the present invention has a short electrical transmission path and has excellent electrical performance and data transmission;

[0031] (4) The package of the present invention can accommodate more leads, and the number of I / Os is significantly increased;

[0032] (5) The present invention adopts high-efficiency packaging materials and processes, with high packaging integration and reduced costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a schematic diagram of the process of the novel FOWLP substrate-based packaging method of the present invention;

[0034] Figure 2 This is a typical single-row QFN component package and pad design diagram of the present invention;

[0035] Figure 3 This is a double-row QFN component package and pad design diagram of the present invention.

[0036] The accompanying drawings are used to provide further understanding of the present invention and constitute a part of the specification. They are used to explain the present invention together with the embodiments of the present invention and do not constitute a limitation of the present invention.

[0037] Legend: 1. Substrate; 2. UV layer; 3. PI layer; 4. Titanium / copper layer; 5. PR glue; 6. Exposure light; 7. Light-exposed part; 8. Pattern; 9. Copper plating layer; 10. Conductive silver glue; 11. Chip; 12. Metal wire; 13. Plastic package; 14. Through hole; 15. Tin plating layer. DETAILED DESCRIPTION

[0038] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0039] Unless otherwise defined, all professional and scientific terms used herein have the same meanings as those familiar to those skilled in the art. In addition, any methods and materials similar or equivalent to those described herein may be applied to the present invention. The preferred implementation methods and materials described herein are for demonstration purposes only and are not intended to limit the content of this application.

[0040] Example

[0041] Novel FOWLP substrate-based package and packaging method

[0042] The packaging method comprises the following steps:

[0043] S1. UV tape fixing: stick UV tape on the glass substrate or other substrate to ensure a firm connection between the substrate and other process materials;

[0044] S2. Coating PI layer: coating a polyimide (PI) layer on the substrate by spin coating, which has a certain buffer protection effect after curing;

[0045] S3, sputtering Ti / Cu layer: sputtering a layer of titanium / copper on the PI glue to prevent subsequent processes from damaging the substrate;

[0046] S4, photoresist coating: coating a layer of PR glue on the titanium / copper metal layer to prepare for the subsequent exposure and development process;

[0047] S5, Exposure: Through the exposure process, the part of the photoresist exposed to light undergoes chemical changes to achieve the definition of high-precision patterns;

[0048] S6, Development: The development process transfers the pattern of the mask to the photoresist, leaving the desired pattern on the substrate;

[0049] S7, electroplating copper: electroplating copper on the titanium layer to provide electrical connection between the chip and the external circuit, serving as the interconnection structure between the chip and the external pins;

[0050] S8, stripping photoresist: Use dry or wet method to strip all photoresist to prevent residual photoresist from interfering with subsequent processes;

[0051] S9, etching: using an etching solution to remove a titanium / copper metal layer sputtered on the PI;

[0052] S10, chip mounting: Use conductive silver glue to mount the chip on the pad on the substrate;

[0053] S11, wire bonding: Use metal wires to connect the chip to the external circuit;

[0054] S12, plastic encapsulation: perform plastic encapsulation to completely encapsulate the chip and its connecting lines in the plastic package, effectively protecting the chip from physical impact from the external environment;

[0055] S13, substrate removal: removing the substrate to achieve fan-out packaging, so that the I / O interface can be connected to a larger packaging area;

[0056] S14, laser drilling: laser drilling is performed to form through holes as channels for signal transmission, and the pads are exposed by grinding the plate;

[0057] S15, through-hole tinning: Tinning is applied to through-holes to form a continuous metal path in the through-holes, allowing the current to pass smoothly.

[0058] S16, Package cutting: Cut the package to expose the metal pads for subsequent welding or other electrical connections.

[0059] The novel FOWLP substrate-based package is packaged by the packaging method.

[0060] The size of the package body is 10×10 mm.

[0061] The pad spacing on the package body is 0.5 mm, the pad width is 0.23 mm, the pad length is 0.4 mm, and the pad height is 0.2 mm.

[0062] The I / O of the package may be single-row or double-row.

[0063] Depend on Figure 2 It can be seen that when Z of the package body is 10mm, assuming that the pad pitch of a single-row typical QFN is Pitch = 0.5mm, the pad width is X = 0.23mm, the pad length is Y = 0.4mm, and H = 0.15mm, then G = 10-(2*0.4) = 9.2, and the number of I / Os on one side is: (Z-2H-2Y) / Pitch = 17.8, taking 17, the total number of I / Os = 68.

[0064] Depend on Figure 3It can be seen that when the package body Z = 10mm, assuming the pad pitch of the double-row QFN is Pitch = 0.5mm, the pad width X = 0.23mm, the pad length Y = 0.4mm, H = 0.2mm, then G = 10-(4*0.4)-(2*0.2) = 8.0, the number of I / Os on one side: 17+(10-2Y-2H) / 0.5 = 34.6, take 34, then the total number of I / Os = 136.

[0065] The difference between the two can be observed: the number of I / Os increases.

[0066] With both sizes being 10×10mm and the pitch being 0.5mm, a typical single-row QFN has only 68 I / Os, while a double-row has twice as many, at 136.

[0067] In addition, the Line / Space package of the present invention can achieve a thickness of 5 μm or less, which cannot be achieved by the lead frame package.

[0068] In terms of package size, the thinnest lead frame package can only be about 150 μm, while the package size of the present invention can reach tens of microns, so the package size can be thin and small, and the number of I / Os is greater.

[0069] The pad size and pad spacing of the lead frame package can only be 150 μm and 250 μm respectively, while the package of the present invention can be 40-50 μm and 80 μm respectively.

[0070] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

[0071] The present invention and its implementation methods are described above, which is not restrictive. The drawings are only one of the implementation methods of the present invention, and the actual application is not limited thereto. In short, if ordinary technicians in the field are inspired by it and design methods and embodiments similar to the technical solution without creativity without departing from the purpose of the invention, they should all fall within the protection scope of the present invention.

Claims

1. A novel FOWLP substrate-based packaging method, characterized by: The steps include: S1. UV tape fixing: stick UV tape on the glass substrate or other substrate to ensure a firm connection between the substrate and other process materials; S2. Coating PI layer: coating a polyimide (PI) layer on the substrate by spin coating, which has a certain buffer protection effect after curing; S3, sputtering Ti / Cu layer: sputtering a layer of titanium / copper on the PI glue to prevent subsequent processes from damaging the substrate; S4, photoresist coating: coating a layer of PR glue on the titanium / copper metal layer to prepare for the subsequent exposure and development process; S5, Exposure: Through the exposure process, the part of the photoresist exposed to light undergoes chemical changes to achieve the definition of high-precision patterns; S6, Development: The development process transfers the pattern of the mask to the photoresist, leaving the desired pattern on the substrate; S7, electroplating copper: electroplating copper on the titanium layer to provide electrical connection between the chip and the external circuit, serving as the interconnection structure between the chip and the external pins; S8, stripping photoresist: Use dry or wet method to strip all photoresist to prevent residual photoresist from interfering with subsequent processes; S9, etching: using an etching solution to remove a titanium / copper metal layer sputtered on the PI; S10, chip mounting: Use conductive silver glue to mount the chip on the pad on the substrate; S11, wire bonding: Use metal wires to connect the chip to the external circuit; S12, plastic encapsulation: perform plastic encapsulation to completely encapsulate the chip and its connecting lines in the plastic package, effectively protecting the chip from physical impact from the external environment; S13, substrate removal: removing the substrate to achieve fan-out packaging, so that the I / O interface can be connected to a larger packaging area; S14, laser drilling: laser drilling is performed to form through holes as channels for signal transmission, and the pads are exposed by grinding the plate; S15, through-hole tinning: Tinning is applied to through-holes to form a continuous metal path in the through-holes, allowing the current to pass smoothly. S16, Package cutting: Cut the package to expose the metal pads for subsequent welding or other electrical connections.

2. A novel FOWLP substrate-based package according to claim 1, characterized in that: The packaging is obtained by packaging using the packaging method.

3. The novel FOWLP substrate-based package according to claim 2, characterized in that: The size of the package body is 10×10 mm.

4. The novel FOWLP substrate-based package according to claim 2, characterized in that: The pad spacing on the package body is 0.5 mm, the pad width is 0.23 mm, the pad length is 0.4 mm, and the pad height is 0.2 mm.

5. The novel FOWLP substrate-based package according to claim 2, characterized in that: The I / O of the package may be single-row or double-row.

6. The novel FOWLP substrate-based package according to claim 2, characterized in that: When the I / O of the package body is in single row, the number of the I / O is 68; when the I / O of the package body is in double row, the total number of the I / O is 136.

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