Semiconductor packaging method and packaging system

Abstract

The invention relates to the technical field of semiconductor packaging, and discloses a semiconductor packaging method and system, and the method comprises the steps: obtaining the demand parameters of a to-be-packaged chip, and the demand parameters comprise the demand chip specification and the demand pin number; cutting a wafer according to the required chip specification to obtain a required chip; a substrate is processed according to the required chip specification, the substrate is divided into a chip mounting area, a limiting area, a bonding pad area and a non-bonding pad area, and the limiting area is arranged at the edge of the chip mounting area; coating a bonding agent on the chip mounting area to form a bonding layer; mounting the required chip on the bonding layer, and curing the bonding agent; and carrying out lead bonding in the bonding pad area, and carrying out plastic packaging on the bonded chip. According to the semiconductor packaging method provided by the invention, the inside and the outside of the limiting area can be effectively protected, the adhesive is prevented from overflowing to the bonding pad area on the substrate, and the manufacturing process and the yield of products are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and particularly to a semiconductor packaging method and a packaging system. Background Art

[0002] In today's rapidly developing electronics industry, semiconductor packaging technology is a key link in ensuring the performance and reliability of integrated circuits (ICs). With the trend of electronic devices towards high performance and miniaturization, higher requirements are put forward for semiconductor packaging technology. In existing packaging methods, the chip may move, or the adhesive may be excessive and cause overflow, resulting in the failure of the final packaged product and making it difficult to meet the diverse requirements such as current high performance, high density, and miniaturization. Therefore, the present invention proposes a semiconductor packaging method and a packaging system, aiming to solve the deficiencies in the prior art and further improve the performance and reliability of semiconductor products. Summary of the Invention

[0003] The object of the present invention is to provide a semiconductor packaging method and a packaging system, which solve the problems in the existing packaging method that the chip may move, or the adhesive may be excessive and cause overflow, resulting in the failure of the final packaged product and making it difficult to meet the diverse requirements such as current high performance, high density, and miniaturization.

[0004] The present invention provides a semiconductor packaging method, and the method includes:

[0005] Obtain the requirement parameters of the chip to be packaged, where the requirement parameters include the required chip specifications and the required number of pins;

[0006] Cut the wafer according to the required chip specifications to obtain the required chips;

[0007] Process the substrate according to the required chip specifications, divide the substrate into a chip mounting area, a limiting area, a pad area, and a non-pad area, and the limiting area is arranged at the edge of the chip mounting area;

[0008] Coat an adhesive in the chip mounting area to form an adhesive layer;

[0009] Mount the required chip on the adhesive layer and cure the adhesive;

[0010] Perform wire bonding in the pad area and encapsulate the chip after the bonding is completed.

[0011] In some embodiments of the present application, when processing the substrate, the number of pad areas is set according to the required number of pins.

[0012] In some embodiments of the present application, the specification of the chip mounting area is larger than the specification of the required chip.

[0013] In some embodiments of the present application, the limiting area is disposed on the surface of the non-pad area; the horizontal position of the limiting area is higher than the horizontal positions of the chip mounting area and the pad area.

[0014] In some embodiments of the present application, both the chip mounting area and the pad area are recessed areas, and the depths of the chip mounting area and the pad area are the same.

[0015] In some embodiments of the present application, the height of the required chip is greater than the sum of the heights of the chip mounting area and the limiting area.

[0016] In some embodiments of the present application, the substrate is one of an organic substrate, an inorganic substrate, and a metal substrate.

[0017] In some embodiments of the present application, the adhesive is a conductive adhesive or a non-conductive adhesive. The conductive adhesive is an epoxy resin adhesive added with silver powder, and the non-conductive adhesive is an epoxy resin adhesive or a glass adhesive.

[0018] In some embodiments of the present application, the thickness of the adhesive layer is 5 - 10 μm.

[0019] The present invention also discloses a semiconductor packaging system for applying the above semiconductor packaging method. The system includes:

[0020] An acquisition module for acquiring the required parameters of the chip to be packaged, where the required parameters include the required chip specifications and the required number of pins;

[0021] A cutting module for cutting the wafer according to the required chip specifications to obtain the required chips;

[0022] A processing module for processing the substrate according to the required chip specifications, dividing the substrate into a chip mounting area, a limiting area, a pad area, and a non-pad area, and the limiting area is disposed at the edge of the chip mounting area;

[0023] A mounting module for coating an adhesive on the chip mounting area to form an adhesive layer; and mounting the required chip on the adhesive layer and curing the adhesive;

[0024] A wire bonding and encapsulation module for performing wire bonding in the pad area; and encapsulating the chip after the bonding is completed.

[0025] Compared with the prior art, the beneficial effects of the present invention are as follows. The present invention is customized according to the required chip specifications and the number of pins, and can meet the requirements of different products. Through the setting of the bonding layer and the limiting area, the present invention ensures the stability and reliability of the chip after mounting; and the specially divided pad area is conducive to improving the accuracy and quality of wire bonding, and encapsulating the chip after wire bonding can effectively protect the chip and the leads. At the same time, the concave design of the chip mounting area and the pad area of the present invention facilitates chip installation and lead layout. According to the semiconductor packaging method of the present invention, by setting the limiting area, the adhesive coating area and the prohibited coating area can be effectively distinguished, and the inside and outside of the limiting area are protected, effectively avoiding the adhesive from overflowing onto the bonding pad area on the substrate, and improving the product process and yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present invention, and those of ordinary skill in the art can obtain other drawings according to the provided drawings without creative efforts.

[0027] Figure 1 is a schematic flow chart of a semiconductor packaging method of the present invention;

[0028] Figure 2 is a schematic diagram of the substrate without mounting the required chip in the embodiment of the present invention;

[0029] Figure 3 is a schematic diagram of the substrate after mounting the required chip in the embodiment of the present invention;

[0030] Figure 4 is a functional block diagram of a semiconductor packaging system of the present invention.

[0031] Wherein, 1, required chip; 2, substrate; 3, chip mounting area; 4, limiting area; 5, pad area; 6, non-pad area; 7, bonding layer. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0032] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0033] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the present application.

[0034] The terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present application, unless otherwise specified, the meaning of "a plurality" is two or more.

[0035] In the description of the present application, it should be noted that unless otherwise clearly specified and limited, the terms "mounted", "connected" and "coupled" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific situations.

[0036] Embodiment 1

[0037] As Figures 1-3 shown, the present invention provides a semiconductor packaging method, which includes:

[0038] S1. Obtain the required parameters of the chip to be packaged, where the required parameters include the required chip specifications and the required number of pins.

[0039] S2. Cut the wafer according to the required chip specifications to obtain the required chips.

[0040] S3. Process the substrate according to the required chip specifications, divide the substrate into a chip mounting area, a limiting area, a pad area and a non-pad area, and the limiting area is arranged at the edge of the chip mounting area.

[0041] S4. Coat an adhesive in the chip mounting area to form an adhesive layer.

[0042] S5. Mount the required chips on the adhesive layer and cure the adhesive.

[0043] S6. Perform wire bonding in the pad area and encapsulate the chip after the bonding is completed.

[0044] In this embodiment, first, the specific required parameters of the chip to be encapsulated are determined. These required parameters define in detail the specifications of the required chip and the number of pins required. This step is the basis of the entire encapsulation process, ensuring that the subsequent steps can be operated strictly in accordance with the established parameters. Next, the wafer is precisely cut. This step requires that the cut chips must meet the specifications determined previously. The cutting accuracy of the wafer directly affects the quality and performance of the final encapsulated product. Therefore, high-precision cutting equipment and techniques are required in this step. Immediately afterwards, the substrate 2 is processed and carefully divided into several different regions: the chip mounting area 3, the limiting area 4, the pad area 5, and the non-pad area 6. Among them, the limiting area 4 is specifically set at the edge of the chip mounting area 3. Such a layout is designed to provide an accurate position reference and limitation for the placement and soldering of the chip to ensure the accurate position of the chip during the encapsulation process. A layer of adhesive is coated on the chip mounting area 3. This layer of adhesive will form a solid bonding layer 7 for fixing the chips to be mounted subsequently. Then, according to the required specifications determined previously, the required chip 1 is placed on the prepared bonding layer 7, and the adhesive is cured after placement to ensure that the chip can be stably bonded to the substrate 2. Finally, the wire bonding operation is performed in the pad area 5. This is to connect the leads to the solder joints of the chip through a fine process to form the circuit connection. After the bonding is completed, the chip is encapsulated. This step is designed to protect the chip and the leads, prevent damage to them caused by the external environment, and at the same time provide a certain structural support for the chip. Encapsulation usually uses specific plastic materials to be cast or molded at high temperature to ensure the integrity and long-term stability of the package.

[0045] In some embodiments of the present application, when processing the substrate 2, the number of pad areas 5 is set according to the required number of pins.

[0046] In this embodiment, different chips have different application ranges and different required numbers of pins. Therefore, the number of pad areas 5 needs to be set according to the requirements of the chip to be encapsulated.

[0047] It is understandable that due to the differences in their functions and designs, various chips are applicable to different fields and application scenarios. This leads to certain differences in the physical structures of different types of chips, and one of the most significant differences is the varying number of their pins. The pins of a chip are the key interfaces for connecting it to external circuits, and the number and layout of the pins are directly related to the complexity of the functions that the chip can achieve. Therefore, before encapsulating the chip to be encapsulated, it is necessary to conduct a detailed analysis and understanding of it in order to accurately set the number of pad areas 5. The pad area 5 is a very important link in the chip encapsulation process, which is directly related to whether the chip can work properly after encapsulation and the stability of its performance. If the number of pad areas 5 is set improperly, it may cause the chip to fail to be correctly connected to the external circuit after encapsulation, thereby affecting the realization of its functions and even possibly causing the chip to fail to work properly. Therefore, it is necessary to set the number of pad areas 5 according to the specific requirements of the chip to be encapsulated to ensure that the chip can be smoothly connected to the external circuit after encapsulation, thus ensuring its normal operation.

[0048] In some embodiments of the present application, the specification of the chip mounting area 3 is larger than that of the required chip 1.

[0049] In this embodiment, to ensure that the chip can be completely mounted on the chip mounting area 3 and also to reduce some errors, the specification of the chip mounting area 3 is set to be larger than that of the required chip 1. When mounting the chip, ensure that the chip is located at the center position of the chip mounting area 3.

[0050] It is understandable that in order to ensure that the chip can be completely and accurately installed in the chip mounting area 3 and also to minimize various errors during the installation process as much as possible, the size of the chip mounting area 3 is designed to be larger than the specification of the chip to be installed. Such a design can provide more operating space for the operator when mounting the chip, thereby better controlling the position of the chip and ensuring that the chip can be placed at the center position of the chip mounting area 3. In this way, not only can the accuracy of chip mounting be improved, enabling the chip to be steadily placed at the center position of the mounting area, but also problems such as poor mounting caused by chip position deviation can be effectively avoided, thus achieving precise positioning and improving the efficiency and quality of the entire chip mounting process.

[0051] In some embodiments of the present application, the limiting area 4 is provided on the surface of the non-pad area 6; the horizontal position of the limiting area 4 is higher than the horizontal positions of the chip mounting area 3 and the pad area 5.

[0052] In this embodiment, the limiting area 4 is provided on the surface of the non-pad area 6, and the horizontal position of the limiting area 4 is higher than the horizontal plane of the non-pad area 6. At the same time, the horizontal position of the limiting area 4 is higher than the horizontal positions of the chip mounting area 3 and the pad area 5.

[0053] It can be understood that the pad area 5 is arranged around the chip mounting area 3. The limiting area 4 is arranged on the surface position of the non-pad area 6. The other areas on the surface of the substrate 2 except the pad area 5 are non-pad areas 6. Such a design is to ensure that the limiting area 4 can play the expected function during the operation. At the same time, the horizontal position of the limiting area 4 is also higher than the horizontal positions of the chip mounting area 3 and the pad area 5. Such an arrangement is to ensure the stability and accuracy of the entire welding process and avoid any deviation in position during the welding process. Such a design of the limiting area 4 also makes the welding process more precise, improves the welding quality, and ensures the performance and reliability of the electronic product.

[0054] It can be seen that when applying the adhesive, due to the blocking of the limiting area 4, the adhesive can be limited to the chip mounting area 3 and will not overflow to the non-pad area 6, which will affect the performance of the packaged chip.

[0055] In some embodiments of the present application, both the chip mounting area 3 and the pad area 5 are concave areas, and the depths of the chip mounting area 3 and the pad area 5 are the same.

[0056] In this embodiment, both the chip mounting area 3 and the pad area 5 are designed in a concave form, and the depths of these two areas are equal. Such a design is to ensure that the chip can be firmly mounted on the chip mounting area 3 and is also convenient for the welding process. Since their depths are the same, when performing mounting and welding, the force and position can be more precisely controlled, thereby improving the efficiency and quality of the entire welding process.

[0057] In some embodiments of the present application, the height of the required chip 1 is greater than the sum of the heights of the chip mounting area 3 and the limiting area 4.

[0058] In this embodiment, the height value of the required chip 1 is greater than the sum of the heights of the chip mounting area 3 and the limiting area 4. When designing the chip mounting area 3 and the limiting area 4, the height of the required chip 1 itself must be considered to ensure that the chip can be stably and accurately placed in the designed position to ensure the stability and reliability of the chip during operation.

[0059] It can be understood that since the height of the chip exceeds the sum of the heights of the chip mounting area 3 and the limiting area 4, this indicates that the position of the chip in the horizontal direction is the highest among these three areas. Therefore, when performing subsequent wire bonding operations, the height of the limiting area 4 has no influence on the bonding process. Because the limiting area 4 is located under the chip, and the chip mounting area 3 is also located under the chip, the height of the chip determines that the position corresponding to the chip during bonding is higher than the height of the limiting area 4. Therefore, the height of the limiting area 4 will not cause any interference or influence on the bonding operation.

[0060] In some embodiments of the present application, the substrate 2 is one of an organic substrate 2, an inorganic substrate 2, and a metal substrate 2.

[0061] In this embodiment, there are mainly three types of substrate 2 materials for the present application, namely organic substrate 2, inorganic substrate 2, and metal substrate 2. These substrates 2 can play a crucial role in the semiconductor packaging process according to their specific physical and chemical properties and process requirements. Organic substrates 2 are widely used due to their good insulation performance, flexibility, and processing convenience. They are usually made of polymer materials and can provide sufficient mechanical support while adapting to the thermal expansion and contraction of semiconductor components. Inorganic substrates 2 are favored for their high thermal stability and electrical insulation and are commonly used in semiconductor packaging for high-performance or high-temperature environments. Metal substrates 2 are an ideal choice for high-power or high-frequency applications due to their excellent thermal conductivity and mechanical strength. They are usually made of metal materials such as copper and aluminum and can effectively dissipate heat to ensure the stable operation of semiconductor components in high-temperature environments. Therefore, when selecting a substrate 2 for semiconductor packaging, it is necessary to determine which type of substrate 2 to use according to the specific application scenario and performance requirements of the semiconductor device.

[0062] In some embodiments of the present application, the adhesive is a conductive adhesive or a non-conductive adhesive. The conductive adhesive is an epoxy resin adhesive added with silver powder, and the non-conductive adhesive is an epoxy resin adhesive or a glass adhesive.

[0063] In this embodiment, the adhesive can be selected as a conductive adhesive or a non-conductive adhesive, depending on the application requirements. Conductive adhesives refer to those epoxy resin adhesives with a large amount of fine silver powder and a small amount of gold powder added inside. This type of adhesive has extremely high electrical conductivity, so this material is widely used in the electronics industry due to its excellent electrical conductivity. On the other hand, non-conductive adhesives are a special type of adhesive that does not contain conductive materials, including epoxy resin adhesives and glass adhesives, and thus have extremely low electrical conductivity. This type of adhesive is usually used in places where electrical insulation is required in electronic devices, for example, to prevent short circuits between different circuits on a circuit board. In addition, non-conductive adhesives usually have good heat resistance and chemical stability, so they are also used to protect the circuit board from heat and chemical substances.

[0064] In some embodiments of the present application, the thickness of the bonding layer 7 is 5 - 10 μm.

[0065] It can be understood that in semiconductor packaging, controlling the thickness of the bonding layer 7 within a certain range can effectively improve the thermal conductivity, reduce stress concentration, and optimize the package size and weight.

[0066] Embodiment Two

[0067] The present invention discloses a semiconductor packaging system for applying the above semiconductor packaging method, such asFigure 4 As shown, the system comprises:

[0068] The acquisition module is used to acquire the required parameters of the chip to be packaged, wherein the required parameters include the required chip specifications and the required number of pins.

[0069] The cutting module is used to cut the wafer according to the required chip specifications to obtain the required chips.

[0070] The processing module is used to process the substrate according to the required chip specifications, and divide the substrate into a chip mounting area, a limiting area, a pad area and a non-pad area, wherein the limiting area is arranged at the edge of the chip mounting area.

[0071] The mounting module is used to apply adhesive to the chip mounting area to form an adhesive layer; mount the required chip on the adhesive layer, and cure the adhesive.

[0072] The bonding and plastic encapsulation module is used to perform wire bonding in the pad area and to perform plastic encapsulation on the chip after bonding.

[0073] The present invention obtains the required parameters of the chip to be packaged, including the required chip specifications and the required number of pins, through an acquisition module, which provides a clear goal and basis for the subsequent processing process and ensures the flexibility and adaptability of the packaging system. Secondly, the cutting module can accurately cut the wafer according to the required chip specifications, so as to obtain a chip that meets the requirements, reduce material waste, and improve packaging efficiency. At the same time, the processing module finely processes the substrate according to the required chip specifications, divides the chip mounting area, the limit area, the pad area and the non-pad area, and provides a good foundation for the subsequent mounting and bonding process. In the mounting module, the required chip is firmly mounted on the substrate by coating the adhesive in the chip mounting area and curing it. This process not only ensures the accurate position of the chip, but also enhances the stability of the chip. At the same time, the setting of the limit area further prevents the movement and dislocation of the chip in the subsequent processing process. Finally, the bonding plastic sealing module performs wire bonding in the pad area to realize the connection between the chip and the external circuit. The chip after bonding is plastic sealed to protect the chip from the influence of the external environment and improve the reliability and stability of the chip. In summary, the technical solution disclosed in the present invention realizes full automation and precise control from demand acquisition to packaging completion in the semiconductor packaging process, improves packaging efficiency and quality, reduces packaging costs, and has significant beneficial effects.

[0074] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions of the present invention or make equivalent replacements, and these modifications or equivalent replacements cannot make the modified technical solutions deviate from the spirit and scope of the technical solutions of the present invention.

[0075] For the system provided in the above embodiments, only the division of the above functional modules is used as an example for illustration. In actual applications, the above functions can be allocated to different functional modules according to needs, that is, the modules or steps in the embodiments of the present invention can be further decomposed or combined. For example, the modules in the above embodiments can be combined into one module, or further split into multiple sub-modules to complete all or part of the functions described above. For the names of the modules and steps involved in the embodiments of the present invention, they are only used to distinguish each module or step and are not regarded as an improper limitation of the present invention.

[0076] Those skilled in the art should be able to realize that the modules and method steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. The programs corresponding to the software modules and method steps can be placed in a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium well known in the technical field. To clearly illustrate the interchangeability of electronic hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in the form of electronic hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

Claims

1. A semiconductor packaging method, characterized in that: The method comprises: Obtaining required parameters of the chip to be packaged, wherein the required parameters include required chip specifications and required pin quantity; Cutting the wafer according to the required chip specifications to obtain the required chips; Processing the substrate according to the required chip specifications, dividing the substrate into a chip mounting area, a limiting area, a pad area, and a non-pad area, wherein the limiting area is arranged at the edge of the chip mounting area; Applying adhesive to the chip mounting area to form an adhesive layer; Mounting the required chip on the adhesive layer and curing the adhesive; Wire bonding is performed on the pad area, and the chip is plastic-sealed after bonding.

2. The semiconductor packaging method according to claim 1, wherein: When processing the substrate, the number of pad areas is set according to the required number of pins.

3. The semiconductor packaging method according to claim 1, wherein: The specification of the chip mounting area is larger than the specification of the required chip.

4. The semiconductor packaging method according to claim 1, wherein: The limiting area is arranged on the surface of the non-pad area; the horizontal position of the limiting area is higher than the horizontal positions of the chip mounting area and the pad area.

5. The semiconductor packaging method according to claim 1, wherein: The chip mounting area and the pad area are both recessed areas, and the chip mounting area and the pad area have the same depth.

6. The semiconductor packaging method according to claim 1, wherein: The required chip has a height greater than the sum of the heights of the chip mounting area and the limiting area.

7. The semiconductor packaging method according to claim 1, wherein: The substrate is one of an organic substrate, an inorganic substrate and a metal substrate.

8. The semiconductor packaging method according to claim 1, wherein: The adhesive is a conductive glue or a non-conductive glue. The conductive glue is an epoxy resin glue added with silver powder, and the non-conductive glue is an epoxy resin glue or a glass glue.

9. The semiconductor packaging method according to claim 1, wherein: The thickness of the bonding layer is 5-10 μm.

10. A semiconductor packaging system, used for applying the semiconductor packaging method according to any one of claims 1 to 9, characterized in that: The system comprises: An acquisition module is used to acquire the required parameters of the chip to be packaged, wherein the required parameters include the required chip specifications and the required number of pins; A cutting module, used for cutting the wafer according to the required chip specifications to obtain the required chips; A processing module, used for processing the substrate according to the required chip specifications, dividing the substrate into a chip mounting area, a limiting area, a pad area and a non-pad area, wherein the limiting area is arranged at the edge of the chip mounting area; A mounting module is used to apply an adhesive to the chip mounting area to form an adhesive layer; mount the required chip on the adhesive layer, and cure the adhesive; The bonding and plastic encapsulation module is used to perform wire bonding in the pad area and to perform plastic encapsulation on the chip after bonding.

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