Defect detection method, electronic equipment, storage medium and program product

Abstract

The embodiment of the invention provides a defect detection method, electronic equipment, a storage medium and a program product, and the method comprises the steps: obtaining the actual morphology data of one or more local regions of a target wafer and a global layout of the target wafer, and carrying out the global layout of the target wafer for each local region based on the mapping relation between the wafer morphology and technological parameters, determining a prediction process parameter corresponding to the actual morphology data of the local region, and predicting the wafer morphology of the global layout under the prediction process parameter of the local region for each local region based on a mapping relationship between the wafer morphology and the process parameter to obtain wafer morphology prediction data, and determining the defective pixel areas of the target wafer based on the predicted wafer morphology prediction data corresponding to each local area, determining a to-be-detected area from all the defective pixel areas, and scanning the to-be-detected area of the target wafer by using defect scanning equipment to obtain a defect detection result, so as to effectively improve the efficiency and precision of defect detection.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to a defect detection method, electronic device, storage medium and program product. Background Technology

[0002] In the semiconductor technology field, defect detection is a crucial method for monitoring yield. By scanning wafers with defect detection equipment, defects can be detected. However, while some defect detection devices offer high scanning accuracy, their slow scanning speed and low detection efficiency limit their application.

[0003] Although methods such as random selection and manual selection have been used to predetermine the defect detection area and then use defect detection equipment to conduct detection within a small area, which has improved detection efficiency to some extent, these defect detection schemes either lack specificity or rely too much on past experience of manual selection. Therefore, the defect detection accuracy and efficiency of current defect detection schemes are still insufficient. Summary of the Invention

[0004] This application provides a defect detection method, electronic device, storage medium, and program product to effectively improve the accuracy and efficiency of defect detection.

[0005] In a first aspect, embodiments of this application provide a defect detection method, including:

[0006] Acquire the actual topographic data of one or more local regions of the target wafer and the global layout of the target wafer;

[0007] Based on the mapping relationship between wafer morphology and process parameters, for each local region, the predicted process parameters corresponding to the actual morphology data of that local region are determined.

[0008] Based on the mapping relationship between wafer morphology and process parameters, for each local region, the wafer morphology of the global layout under the predicted process parameters in that local region is predicted, and wafer morphology prediction data is obtained.

[0009] Based on the predicted wafer morphology data corresponding to each local region, the defective areas of the target wafer are determined.

[0010] From all areas with bad pixels, determine the area to be detected;

[0011] Using a defect scanning device, the area to be inspected on the target wafer is scanned to obtain the defect detection results.

[0012] Secondly, embodiments of this application provide a defect detection device, comprising:

[0013] The acquisition unit is used to acquire the actual topographic data of one or more local regions of the target wafer and the global layout of the target wafer;

[0014] The parameter determination unit is used to determine the predicted process parameters corresponding to the actual morphology data of each local region based on the mapping relationship between wafer morphology and process parameters.

[0015] The data prediction unit is used to predict the wafer morphology of the global layout under the predicted process parameters in each local area based on the mapping relationship between wafer morphology and process parameters, and obtain wafer morphology prediction data.

[0016] The defect determination unit is used to determine the defect area of ​​the target wafer based on the predicted wafer morphology data corresponding to each local region.

[0017] The region determination unit is used to determine the region to be detected from all the bad pixel regions;

[0018] The result acquisition unit is used to scan the area to be detected on the target wafer using a defect scanning device to obtain the defect detection results.

[0019] Thirdly, embodiments of this application provide an electronic device, which includes a processor, a memory, and a program or instructions stored in the memory and executable on the processor. When the program or instructions are executed by the processor, they implement the steps of the defect detection method of any embodiment of this application.

[0020] Fourthly, embodiments of this application provide a readable storage medium on which a program or instructions are stored, and when the program or instructions are executed by a processor, the steps of the defect detection method of any embodiment of this application are implemented.

[0021] Fifthly, embodiments of this application provide a computer program product in which instructions, when executed by a processor of an electronic device, enable the electronic device to perform the steps of the defect detection method of any embodiment of this application.

[0022] The technical solution provided in this application has at least the following beneficial effects:

[0023] The technical solution provided in this application obtains the actual morphology data of one or more local regions of the target wafer and the global layout of the target wafer. Based on the mapping relationship between wafer morphology and process parameters, for each local region, the predicted process parameters corresponding to the actual morphology data of that local region are determined. This enables the rapid and accurate prediction of the defective areas that may be generated during wafer fabrication under the influence of the predicted process parameters of that local region. Then, the area to be detected can be selected from these predicted defective areas, and defect scanning can be further performed using defect detection equipment within this small area, effectively improving the accuracy and efficiency of defect detection.

[0024] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0025] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 A schematic diagram illustrating the selection of a scheme for the current defect detection area;

[0027] Figure 2 A flowchart illustrating a defect detection method provided in one embodiment of this application;

[0028] Figure 3 A flowchart illustrating a defect detection method provided in another embodiment of this application;

[0029] Figure 4 A flowchart illustrating a defect detection method provided in yet another embodiment of this application;

[0030] Figure 5 A flowchart illustrating a defect detection method provided in another embodiment of this application;

[0031] Figure 6 This is a schematic diagram of the structure of a defect detection device provided in one embodiment of this application;

[0032] Figure 7 This is a schematic diagram of the structure of a defect detection device provided in one embodiment of this application. Detailed Implementation

[0033] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0034] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0035] The acquisition, storage, use, and processing of data in this application comply with relevant national laws and regulations. In the embodiments of this application, certain existing industry solutions such as software, components, and models may be mentioned. These should be considered exemplary, intended only to illustrate the feasibility of implementing the technical solution of this application, and do not imply that the applicant has already used or necessarily used such solutions.

[0036] With the development of semiconductor technology, manufacturing processes are gradually moving towards smaller process nodes. The smaller the process node, the denser and more complex the patterns on the wafer. For wafers with such dense and complex patterns, defect inspection equipment is needed for defect detection. However, some defect inspection equipment has slow scanning speeds and low inspection efficiency. For example, electron beam scanning inspection equipment is a defect inspection device used to detect defects on wafers. Electron beam scanning inspection equipment uses an electron beam to scan and image the wafer, providing high scanning resolution and high detection accuracy even for small defects. However, the slow scanning imaging speed limits the application of electron beam scanning inspection equipment.

[0037] Currently, some schemes predetermine defect detection areas using methods such as random selection or manual selection. For example, such as... Figure 1 The defect detection area selection scheme shown includes:

[0038] Random selection scheme: In step S110, the detection time is determined (e.g., 4 hours); in step S111, the area that can be scanned is calculated (e.g., 10% of the chip area); in step S112, the defect detection area is randomly selected with the area that can be scanned as a constraint.

[0039] Manual selection scheme: In step S120, the detection time is determined (e.g., 4 hours); in step S121, the area that can be scanned (e.g., 10% of the chip area) is calculated; in step S122, the defect detection area within the chip area is selected according to the manually set selection rules. For example, the manually set selection rules may include: selecting any one or more locations such as dense and sparse graphics, memory cells, and logic cells as defect detection areas. Figure 1 The text uses Rule 1 and Rule 2 to illustrate the selection rules that are set by the user.

[0040] Although pre-determining the defect detection area through random selection or manual selection, and then using defect detection equipment to perform detection within a small area of ​​the defect detection area, can improve detection efficiency to some extent, these methods of determining the defect detection area are still difficult to quickly and accurately locate the defect detection area, resulting in insufficient defect detection accuracy and efficiency.

[0041] To address the aforementioned technical problems, embodiments of this application provide a defect detection method, electronic device, storage medium, and program product. The technical solution provided in this application, after acquiring actual topographic data of one or more local regions of a target wafer and the global layout of the target wafer, determines the predicted process parameters corresponding to the actual topographic data of each local region based on the mapping relationship between wafer topography and process parameters. This allows for the rapid and accurate prediction of potential defective areas that may arise during wafer fabrication under the influence of the predicted process parameters in that local region. Subsequently, a region to be detected can be selected from these predicted defective areas, and further defect scanning is performed within this small area using defect detection equipment, effectively improving the accuracy and efficiency of defect detection.

[0042] For example, the technical solution provided in this application embodiment can be applied to the pre-step of defect detection of wafers by electron beam scanning inspection equipment to detect bad areas of the wafer, so that the electron beam scanning inspection equipment can perform scanning imaging within a small area of ​​the bad area, thereby improving the detection efficiency and accuracy of defect detection.

[0043] It should be noted that the application scenarios described in the above embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. Those skilled in the art will understand that with the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems. The defect detection method provided by the embodiments of this application can be applied to various application scenarios that require defect detection.

[0044] In practical applications, the execution subject of the defect detection method in this embodiment can be an electronic device. The electronic device can be, for example, a desktop computer, a laptop computer, or other terminal device; it can also be a single server or a server in a server cluster; or it can be a defect scanning device. This application does not strictly limit the execution subject of the technical solution in this embodiment, and the subject can be flexibly selected according to the actual application scenario and requirements.

[0045] This application provides specific embodiments of a defect detection method, an electronic device, a storage medium, and a program product. First, the defect detection method is described.

[0046] Figure 2 This is a flowchart illustrating a defect detection method provided in one embodiment of this application.

[0047] like Figure 2 As shown in the figure, the defect detection method provided in this application embodiment includes steps S201 to S206.

[0048] S201: Obtain the actual topographic data of one or more local regions of the target wafer and the global layout of the target wafer.

[0049] The target wafer can be a physically fabricated wafer. There can be one or more target wafers, and the wafer surface exhibits a complex morphology, with significant differences in morphology under different processes.

[0050] Topographic data is used to describe the surface morphology of a wafer. It can be represented as two-dimensional or three-dimensional data, depending on the measurement and representation method. For example, topographic data can be represented as two-dimensional numerical data to describe the surface morphology of a wafer, such as graphic contour data reflected by quantitative parameters such as linewidth and depth.

[0051] A local region is a portion of the target wafer. The size of the local region can be set according to the needs of the actual application scenario. In some embodiments, the local region can be represented as an exposure area (Shot) or a chip area (Die). In step S201, the actual morphology data of each of one or more exposure areas and one or more chip areas of the target wafer can be obtained. An exposure area is the area covered by a single exposure of the target wafer by the lithography machine in the photolithography process. A chip area, also known as a die, is an independent single chip area on the target wafer. An exposure area can contain multiple chip areas.

[0052] By acquiring actual morphological data of one or more exposure areas or one or more chip areas of a target wafer, the true morphological condition of the exposure area or chip area can be more accurately reflected based on this data, providing a reliable and effective data foundation for subsequent prediction of process parameters for that area. After predicting the process parameters for the exposure area or chip area, it is possible to predict the potential defect areas that may arise during wafer fabrication under the influence of these predicted process parameters. By detecting the corresponding defect areas in different exposure areas or chip areas, the accuracy of defect detection is effectively improved.

[0053] A global layout is a detailed layout diagram designed for the entire target wafer, containing the location and geometric information of various circuit elements, interconnects, functional modules, etc. on the target wafer.

[0054] The global layout can be obtained from wafer design files or related databases. In some embodiments, the global layout can be an initial global design layout, or an optimized layout obtained by optical proximity correction (OPC) of the global design layout. By performing optical proximity correction on the global design layout, the graphics are optimized and adjusted, such as moving edges and adding extra polygons, which can compensate for errors that may occur during the photolithography process, making the final pattern on the wafer closer to the design requirements.

[0055] In practical applications, the execution of step S201 can be triggered by a user request or by a specified event, and this application embodiment does not impose any restrictions on this.

[0056] For example, when a user is preparing to use an electron beam scanning inspection device to scan and image a target wafer, the user can send an upload request through the user interface of the electronic device, requesting to upload the actual topographic data of a local area of ​​the target wafer and the global layout of the target wafer. The electronic device responds to the user's upload request and obtains the actual topographic data and global layout uploaded by the user.

[0057] For example, in response to the scanning task of an electron beam scanning inspection device about to perform scanning imaging on a target wafer, an electronic device can automatically control a measurement device to collect actual topographic data of a local area of ​​the target wafer and automatically obtain the global layout of the target wafer from a relevant database.

[0058] For example, step S201, which involves acquiring actual topographic data of one or more local regions of the target wafer, may include:

[0059] S2011: Using measurement equipment, obtain images of one or more local areas of the target wafer.

[0060] S2012: Extract the actual morphological data of each local region from the image of each local region.

[0061] The measuring equipment may include any one or more of the following: critical dimension scanning electron microscope (CD-SEM), atomic force microscope (AFM), X-ray measuring equipment, etc.

[0062] For example, the image can be preprocessed by removing noise and correcting the background, and then the graphic contour can be extracted from the preprocessed image as the actual shape data.

[0063] In the embodiments of steps S2011-S2012, the actual shape data of the local area is obtained through the measurement device, which can directly obtain the real shape data and improve the defect detection efficiency.

[0064] In step S201, by acquiring the actual morphology data of a local area of ​​the target wafer, the actual morphology data of the local area can effectively reflect the true morphology of the local area of ​​the target wafer, providing a true and effective data basis for the subsequent prediction of the predicted process parameters of the local area; by acquiring the global layout of the target wafer, an accurate and effective data basis can be provided for the subsequent prediction of the wafer morphology of the global layout under the influence of the predicted process parameters of the local area.

[0065] S202: Based on the mapping relationship between wafer morphology and process parameters, for each local region, determine the predicted process parameters corresponding to the actual morphology data of that local region.

[0066] Process parameters are quantifications of process conditions, which can be expressed as specific values ​​or ranges, used to precisely control the wafer fabrication process. There are numerous process parameters for wafer fabrication, and different process stages have different parameters. For example, in the photolithography stage, process parameters may include: light source-related parameters, photoresist-related parameters, development-related parameters, etc. The process parameters in the embodiments of this application can be represented as a collection of numerous process parameters.

[0067] The mapping relationship between wafer morphology and process parameters is a bidirectional one. Based on this mapping relationship, it is possible to predict the corresponding process parameters from the wafer morphology, and vice versa. This mapping relationship can be constructed in various ways. In some embodiments, a machine learning model can be trained using massive sample data to learn the mapping relationship between wafer morphology and process parameters. In other embodiments, a hybrid model with the mapping relationship between wafer morphology and process parameters can be constructed by fitting a physical model to data.

[0068] By leveraging the mapping relationship between wafer morphology and process parameters, in step S202, the predicted process parameters corresponding to the actual morphology data of each local region can be determined. The predicted process parameters are calculated in reverse, based on the mapping relationship between wafer morphology and process parameters, for the actual morphology data of a local region.

[0069] S203: Based on the mapping relationship between wafer morphology and process parameters, for each local region, the wafer morphology of the global layout under the predicted process parameters in that local region is predicted to obtain wafer morphology prediction data.

[0070] The mapping relationship between wafer morphology and process parameters can be pre-constructed in various ways. For example, a mathematical model describing the impact of the process on wafer morphology can be established based on physical laws and equations, and the mapping relationship between wafer morphology and process parameters can be expressed through a data model. Another example is the use of actual morphology data from a large number of defective region samples and process parameters to train a machine learning model, enabling the machine learning model to learn the mapping relationship between wafer morphology and process parameters.

[0071] The predicted wafer morphology data corresponding to a local region is based on the mapping relationship between wafer morphology and process parameters. It simulates the lithography process for the global layout and the predicted process parameters of the local region, thus predicting the overall wafer morphology of the target wafer. For example, wafer morphology prediction data can be represented as two-dimensional numerical morphology data.

[0072] S204: Based on the predicted wafer morphology data corresponding to each local region, determine the defective areas of the target wafer.

[0073] Defective regions are areas that may contain defects, determined based on wafer morphology prediction data. A defective region is a location where a function fails due to a defect. It is understood that areas containing defective regions are usually accompanied by specific morphological characteristics. Therefore, areas exhibiting specific morphologies can be identified as defective regions based on wafer morphology prediction data.

[0074] For example, the process of determining the defective region of a target wafer based on the predicted wafer morphology data corresponding to a local region may include: extracting features related to defects from the wafer morphology prediction data. For example, features such as key dimension changes and height differences of the wafer surface pattern can be calculated. Based on the extracted features, it is determined whether there are features that meet the defect determination criteria, and the region containing the features that meet the defect determination criteria is designated as the defective region. The defect determination criteria can be set based on the wafer's quality requirements and process specifications. For example, when the key dimension of the pattern in a certain region exceeds a preset deviation range, that region can be determined as a defective region. In the case of a region being determined as a defective region, the location and related features of the defective region can be recorded, thereby achieving the localization of the defective region.

[0075] S205: Determine the area to be tested from all areas with bad pixels.

[0076] In some embodiments, the region to be detected can be randomly selected from all bad pixel regions.

[0077] In other embodiments, to further improve detection accuracy, step S205, which determines the area to be detected, may include:

[0078] S2051: Determine the severity of defects in all bad pixel areas.

[0079] The specific implementation method for determining the severity of defects in each defective area is not limited. For example, for each defective area, multi-dimensional defect quantification indicators such as critical size deviation, edge placement error, and abnormal shape characteristics can be calculated. After normalizing the multi-dimensional defect quantification indicators, the severity of defects in the defective area can be calculated by combining the severity weights of each dimension and using a comprehensive scoring method such as weighted summation or weighted averaging.

[0080] S2052: Based on the severity of defects in all bad pixel areas, select the areas to be inspected from all bad pixel areas.

[0081] After determining the severity of defects in all defective areas, they can be sorted from highest to lowest severity, from front to back. For defective areas with the same severity, those with larger or more complex shapes can be ranked higher. Then, the areas to be inspected can be selected from the sorted list of defective areas according to a preset filtering strategy.

[0082] For example, a preset screening strategy may include: selecting a preset number of defective areas from the sorted list of defective areas, ranked from highest to lowest severity, as areas to be detected.

[0083] For example, a preset screening strategy may include: further grouping the sorted defective areas according to function, and selecting a preset number of defective areas in each group as the targets to be detected according to the severity of the defects from high to low. This can ensure that at least a certain proportion of the areas to be detected are covered in each group.

[0084] In the embodiments of steps S2051-S2052, the areas to be detected are screened based on the severity of defects, which can prioritize the detection of defective areas with higher severity, thereby accurately improving the accuracy and efficiency of defect detection.

[0085] S206: Using a defect scanning device, scan the area to be inspected on the target wafer to obtain the defect detection results.

[0086] It should be noted that the defective region determined in step S204 is indirectly derived from the prediction of the wafer morphology and may not actually exist on the actual target wafer. Therefore, in step S206, a defect scanning device is needed to scan the area to be inspected on the physically existing target wafer to capture the actual physical structural anomalies on the surface of the area to be inspected. In some embodiments, the defective region may have explicit defective descriptive information to describe the details and type of the defect; in other embodiments, the defective region may not have explicit defective descriptive information, and the presence of a defect may be indicated by the overall area of ​​the defective region.

[0087] The defect detection result is the result obtained by the defect scanning device scanning the area to be detected. In some embodiments, the defect detection result may include at least one or more descriptive information such as the specific coordinates, size, and features of a certain type of defect; in other embodiments, the defect detection result may be represented as Boolean data indicating whether a defect exists in the area to be detected.

[0088] In some embodiments, the defect scanning device may be an electron beam scanning detection device.

[0089] After the area to be inspected is selected, the defect scanning and inspection equipment can be controlled to scan the area to obtain more accurate defect detection results.

[0090] In some embodiments, step S206 may include:

[0091] S2061, Determine the graphic density of the area to be detected.

[0092] Graphic density is the distribution density of graphics per unit area, which characterizes the graphic complexity of the area to be detected.

[0093] For example, the graphic outline of the area to be detected can be extracted, and one or more of the following can be counted, such as the total length of lines and the area of ​​the graphic per unit area. The graphic density can be equal to the total length of lines divided by the unit area, or the graphic density can be equal to the area of ​​the graphic divided by the unit area.

[0094] S2062, based on the pattern density, determines the scanning parameters of the area to be detected.

[0095] For example, a mapping table between different graphic densities and their corresponding scanning parameters can be pre-established. From this mapping table, the scanning parameters corresponding to the graphic density of the region to be detected can be selected. The scanning parameters corresponding to different graphic densities can be set based on the principle that higher graphic densities require higher scanning accuracy. Scanning parameters can include resolution, sampling rate, etc. As another example, historical detection data can be collected to obtain historical scanning parameters corresponding to historical graphic densities. This data can then be used to train a scanning parameter prediction model, which can then be used to predict the scanning parameters corresponding to the graphic density of the region to be detected.

[0096] S2063, based on the scanning parameters of the area to be detected, controls the defect scanning device to scan the area to be detected and obtain the defect detection result.

[0097] For example, the scanning step size of the defect scanning device can be set based on the resolution; the movement speed of the defect scanning device can be set based on the scanning speed, and so on.

[0098] In the embodiments of steps S2061-S2063, the corresponding scanning parameters are determined based on the image density, so that high-density areas can be scanned with high precision and low-density areas can be scanned quickly. This improves both detection accuracy and detection efficiency, and avoids the time waste caused by high-precision scanning of the entire area.

[0099] In the embodiments of steps S201-S206, after obtaining the actual topographic data of one or more local regions of the target wafer and the global layout of the target wafer, based on the mapping relationship between wafer topography and process parameters, for each local region, the predicted process parameters corresponding to the actual topographic data of that local region are determined. This enables the rapid and accurate prediction of the defective areas that may be generated during wafer fabrication under the influence of the predicted process parameters of that local region. Then, the area to be detected can be selected from these predicted defective areas, and the defect detection equipment can be used to further scan defects within this small area, effectively improving the accuracy and efficiency of defect detection.

[0100] In some embodiments, for each of the multiple local regions of the target wafer, the wafer morphology under the predicted process parameters of the global layout in that local region can be predicted to obtain predicted morphology data. Based on this, the defective areas of the target wafer are determined according to the predicted morphology data corresponding to each local region. Compared with other schemes that can only provide one static detection result for a target wafer, this embodiment can detect potentially identical or different defective areas for different local regions. This is equivalent to dynamically providing dynamic detection results for different local regions under the corresponding process parameters for a target wafer, effectively capturing the subtle process differences between different local regions and achieving higher detection accuracy.

[0101] Figure 3 This is a flowchart illustrating a defect detection method according to another embodiment of this application. Figure 3 As shown, in the defect detection method provided in the embodiments of this application, step S202 in other embodiments is specifically manifested as step S302, and step S203 is specifically manifested as step S303.

[0102] S302: Using a defect prediction model, for each local region, predict the predicted process parameters corresponding to the actual morphology data of that local region. The defect prediction model is pre-trained to learn the mapping relationship between wafer morphology and process parameters.

[0103] In some embodiments of this application, if the actual topography data of each exposure area or each chip area of ​​the target wafer can be obtained in step S201, then in step S302, the actual topography data of each exposure area or each chip area, along with the global layout, can be input into the bad spot prediction model to predict the process parameters of each exposure area or each chip area, and to predict the overall wafer topography under the influence of the process parameters of each exposure area or each chip area.

[0104] Defect prediction models can be built based on machine learning or deep learning algorithms, using a large amount of actual morphology data of defective regions and process parameters for training. For example, a defect prediction model can be built using one or more models such as convolutional neural networks, graph neural networks, and Bayesian neural networks. Through training, the defect prediction model can learn the mapping relationship between the morphology of defective regions and process parameters. The mapping relationship between morphology and process parameters is many-to-many, that is, multiple morphological features correspond to multiple process parameters. Based on the learned mapping relationship, the defect prediction model can predict the corresponding process parameters based on the input morphology, predict the corresponding morphology based on the input process parameters, and predict the defective regions that may be generated during wafer fabrication under the influence of the predicted process parameters.

[0105] S303: Using a bad pixel prediction model, the wafer morphology of the global layout under the predicted process parameters in each local area is predicted, and the wafer morphology prediction data is obtained.

[0106] Wafer morphology prediction data is obtained by a defect prediction model based on the global layout and local region prediction process parameters, simulating the photolithography process, and predicting the overall morphology of the wafer.

[0107] Figure 3 For parts not described in detail in the embodiments, please refer to the relevant descriptions of steps S201-S206 in other embodiments, which will not be repeated here.

[0108] because Figure 3 The technical solution provided in this embodiment acquires the actual morphology data of a local area of ​​the target wafer and the global layout of the target wafer during defect detection. The actual morphology data of the local area and the global layout are input into a defect prediction model. The defect prediction model determines the predicted process parameters of the local area, thereby quickly and accurately predicting the wafer morphology of the wafer prepared under the influence of the predicted process parameters. Based on the wafer morphology predicted by the defect prediction model, the possible defect areas can be determined. Then, defect scanning can be performed on a small area of ​​the defect area using defect detection equipment, effectively improving the accuracy and efficiency of defect detection.

[0109] Figure 4 This is a flowchart illustrating a defect detection method provided in yet another embodiment of this application. Figure 4 As shown, the defect detection method provided in this application embodiment also includes a training process for a bad spot prediction model, including steps S401-S405.

[0110] S401: Obtain multiple global layout samples with different process parameters and the corresponding bad pixel region labels for the multiple global layout samples.

[0111] For example, multiple global layout samples with different process parameters can be obtained in various ways. In some embodiments, process parameters can be adjusted within a controllable range through experimental design to generate global layout samples with different parameter sets. In other embodiments, global layout samples with different process parameter sets can be selected from historical data of actual production. One global layout sample corresponds to a set of process parameters including numerous process parameters. In the process parameter sets corresponding to different global layout samples, at least one process parameter has a different value.

[0112] The bad pixel region label is used to characterize the actual bad pixel region that exists on the actual wafer corresponding to the global layout sample.

[0113] S402: By using a bad pixel prediction model, the wafer morphology of multiple global layout samples with different process parameters is predicted, and the wafer morphology prediction data corresponding to multiple global layout samples is obtained.

[0114] The defect prediction model simulates the wafer generation process of each global layout sample under the influence of its process parameters, and obtains the wafer morphology prediction data corresponding to each global layout sample.

[0115] S403: Based on the wafer morphology prediction data corresponding to multiple global layout samples, determine the predicted bad spot regions corresponding to multiple global layout samples.

[0116] For example, features related to bad pixels can be extracted from the wafer morphology prediction data corresponding to each global layout sample, and the region where the feature that meets the bad pixel judgment condition is located can be used as the predicted bad pixel region.

[0117] S404: Calculate the prediction loss of the bad pixel prediction model based on the predicted bad pixel regions and bad pixel region labels corresponding to multiple global map samples.

[0118] In step S404, various loss functions can be used to calculate the prediction loss. For example, the prediction loss can be calculated using any combination of one or more loss functions such as the cross-entropy loss function and the Descein loss function.

[0119] S405: Based on the prediction loss, adjust the model parameters of the bad pixel prediction model to obtain the trained bad pixel prediction model.

[0120] In this embodiment of the application, the predicted bad pixel region corresponding to the global map sample is predicted, and the prediction loss is calculated based on the bad pixel region label. Then, the model parameters of the bad pixel prediction model are adjusted based on the prediction loss to achieve the training of the bad pixel prediction model.

[0121] The above content is an exemplary training process of the bad pixel prediction model involved in the embodiments of this application.

[0122] In some embodiments, the defect prediction model can be built based on a process model, which can be trained using actual wafer topography data and process parameters. By training the process model to learn the mapping relationship between wafer topography and process parameters, the process model can predict process parameters based on wafer topography, and predict wafer topography based on process parameters. This leads to a defect prediction model with higher prediction accuracy that can be obtained based on the trained process model.

[0123] In some embodiments of this application, to further improve the accuracy and efficiency of defect detection, the local area includes an exposure area or a chip area. For example, the defective area can be determined based on the actual morphology of a single exposure area or a single chip area in the target wafer.

[0124] Figure 5 This is a flowchart illustrating a defect detection method provided in another embodiment of this application. Figure 5 As shown, in the defect detection method provided in this application embodiment, the local area includes the exposure area or the chip area, and the method specifically includes steps S501-S507.

[0125] S501: Using measurement equipment, an image of each exposure area or each chip area of ​​the target wafer is obtained by measurement.

[0126] For example, measurement equipment can be used to measure multiple exposure areas or multiple chip areas of the target wafer area by area to obtain the actual morphology data of each exposure area or each chip area.

[0127] S502: Extract the actual topographic data of each exposure area or chip area from the image of each exposure area or chip area.

[0128] S503: Using a bad pixel prediction model, predict the predicted process parameters corresponding to the actual morphology data of each exposure area or each chip area.

[0129] In this step, the actual topographic data of each exposure area or each chip area can be input into the bad pixel prediction model area by area, so that the bad pixel prediction model can predict bad pixels area by area.

[0130] In some embodiments, to improve defect detection efficiency, the chip type corresponding to each region can be determined based on the actual morphology data of each exposure area or each chip region. Different chip types correspond to defect prediction models with different parameter scales. Thus, the actual morphology data of each exposure area or each chip region can be input into the defect prediction model corresponding to the appropriate chip type to predict defect areas, effectively improving defect detection efficiency. More advanced chip types correspond to defect prediction models with larger parameter scales.

[0131] Specifically, before predicting the predicted process parameters corresponding to the actual morphology data of each exposed area or chip area using the bad pixel prediction model, the method further includes:

[0132] Determine the target chip type corresponding to the exposure area or the chip area;

[0133] Based on the chip model correspondence, a bad pixel prediction model corresponding to the target chip type is determined. This model is used to predict the process parameters and morphology data of the exposed area or the chip area. The chip model correspondence includes the correspondence between bad pixel prediction models of different chip types and different parameter scales.

[0134] Furthermore, after the defect prediction model has been pre-trained to learn the mapping relationship between wafer morphology and process parameters, the method also includes:

[0135] The trained bad pixel prediction model is scaled to obtain bad pixel prediction models with different parameter scales, and a correspondence is established between different chip types and bad pixel prediction models with different parameter scales.

[0136] This embodiment, by establishing the correspondence between chip type and defect prediction models with different parameter scales, can maximize the improvement of model prediction efficiency while ensuring detection accuracy.

[0137] S504: Using a defect prediction model, the global layout of the target wafer is predicted for each exposure area or each chip area under the corresponding predicted process parameters, resulting in predicted wafer morphology data for each exposure area or each chip area.

[0138] S505: Determine the defective areas of the target wafer based on the predicted wafer morphology data corresponding to each exposure area or each chip area.

[0139] S506: Determine the area to be inspected from all areas with bad pixels.

[0140] For example, the area to be detected can be sampled from the bad pixel area corresponding to each exposure area or each chip area.

[0141] S507: Using a defect scanning device, scan the area to be inspected on the target wafer to obtain the defect detection results.

[0142] For example, the area to be inspected can be output to an electron beam scanning inspection device for inspection to obtain defect detection results.

[0143] For the processing procedures not described in detail in steps S501-S507 above, please refer to the relevant descriptions in other embodiments, which will not be repeated here.

[0144] In the embodiments of steps S501-S507, since the potential defective areas of the target wafer are predicted for each exposure area or chip area when the global layout is fabricated under the influence of its corresponding process parameters, the actual topographic data of each exposure area or chip area of ​​the target wafer can be input into the defective area prediction model one by one during the entire inspection process to predict the potential defective areas of the target wafer under the process parameters of each exposure area or chip area. Compared with other schemes that can only provide one static inspection result for a target wafer, the embodiments of this application can detect multiple defective areas that may be the same or different for different exposure areas or chip areas, which is equivalent to dynamically providing dynamic inspection results for different defective areas for a target wafer, resulting in higher detection accuracy.

[0145] In one embodiment of this application, defect detection is achieved through three stages, combining the implementation methods of the above-described multiple embodiments.

[0146] In the first stage, the process model is trained to learn the mapping relationship between wafer morphology and process parameters.

[0147] In the second stage, the process model is used to predict the bad pixel region on global layout samples with different process parameters in order to train the bad pixel prediction model and obtain the trained bad pixel prediction model.

[0148] In the third stage, for the target wafer to be inspected for defects, the actual topographic data of each exposure area or chip area is first collected on the target wafer using measurement equipment. Then, for each exposure area or chip area, the actual topographic data of the exposure area or chip area and the global layout are input into the defect prediction model to predict the defect area. Next, all predicted defect areas are sorted and sampled to obtain the area to be inspected. Finally, the area to be inspected is scanned with an electron beam scanning inspection device to obtain the defect detection result.

[0149] This embodiment comprehensively utilizes metrology technology and process simulation modeling technology. In the above three stages, the actual morphology of the exposure area or chip area of ​​the wafer is back-inferred through the defect prediction model to obtain the predicted process parameters. Based on the predicted process parameters, the overall wafer morphology prediction data of the target wafer is forward-inferred. Based on the wafer morphology prediction data, the defect area on the target wafer is determined. The area to be detected is selected from the defect area. Then, the defect scanning and detection equipment performs efficient and accurate defect detection within a small area of ​​the area to be detected, thereby improving the efficiency and accuracy of defect detection.

[0150] Taking electron beam scanning inspection equipment for defect scanning as an example, this embodiment can predict the bad spot area of ​​the wafer through a bad spot prediction model before the electron beam scanning inspection equipment performs scanning, instead of randomly or manually selecting. The selection of bad spot area is more accurate, and all predicted bad spot areas can be sampled to form the area to be inspected, so that the electron beam scanning inspection equipment can scan within a small area of ​​the area to be inspected, which effectively improves the inspection efficiency and accuracy.

[0151] Based on the defect detection method provided in the above embodiments, this application also provides specific implementation methods of the defect detection device, as detailed in the following embodiments.

[0152] Figure 6 The present invention provides a schematic diagram of the structure of a defect detection device 600 according to another embodiment of the present application. The defect detection device 600 includes: an acquisition unit 601, a parameter determination unit 602, a data prediction unit 603, a bad spot determination unit 604, a region determination unit 605, and a result acquisition unit 606.

[0153] The acquisition unit 601 is used to acquire the actual topographic data of one or more local regions of the target wafer and the global layout of the target wafer;

[0154] The parameter determination unit 602 is used to determine the predicted process parameters corresponding to the actual morphology data of each local region based on the mapping relationship between wafer morphology and process parameters.

[0155] The data prediction unit 603 is used to predict the wafer morphology of the global layout under the predicted process parameters in each local area based on the mapping relationship between wafer morphology and process parameters, and obtain wafer morphology prediction data.

[0156] The defect determination unit 604 is used to determine the defect region of the target wafer based on the predicted wafer morphology data corresponding to each local region.

[0157] The region determination unit 605 is used to determine the region to be detected from all the bad pixel regions;

[0158] The result acquisition unit 606 is used to scan the area to be detected on the target wafer using a defect scanning device to obtain the defect detection result.

[0159] In one embodiment, the region determination unit 605 is specifically used to determine the defect severity of all bad pixel regions; based on the defect severity of all bad pixel regions, it selects regions to be detected from all bad pixel regions.

[0160] In one embodiment, the result acquisition unit 606 is specifically used to determine the graphic density of the area to be detected, and based on the graphic density, determine the scanning parameters of the area to be detected; based on the scanning parameters of the area to be detected, control the defect scanning device to scan the area to be detected, and obtain the defect detection result.

[0161] In one embodiment, the acquisition unit 601 is specifically used to measure one or more local regions of the target wafer using a measurement device; and to extract the actual morphology data of each local region from the image of each local region.

[0162] In one embodiment, the parameter determination unit 602 is specifically used to predict the predicted process parameters corresponding to the actual morphology data of each local area through a bad spot prediction model. The bad spot prediction model has been trained in advance to learn the mapping relationship between wafer morphology and process parameters.

[0163] The data prediction unit 603 is specifically used to predict the wafer morphology of the global layout under the predicted process parameters in each local area using a bad spot prediction model, thereby obtaining wafer morphology prediction data.

[0164] In one embodiment, the defect detection device further includes a model training module, used to acquire multiple global layout samples with different process parameters and corresponding defective region labels for the multiple global layout samples; predict the wafer morphology of the multiple global layout samples with different process parameters using a defective spot prediction model to obtain wafer morphology prediction data corresponding to the multiple global layout samples; determine the predicted defective regions corresponding to the multiple global layout samples based on the wafer morphology prediction data corresponding to the multiple global layout samples; calculate the prediction loss of the defective spot prediction model based on the predicted defective regions and defective region labels corresponding to the multiple global layout samples; and adjust the model parameters of the defective spot prediction model based on the prediction loss to obtain the trained defective spot prediction model.

[0165] In one embodiment, the local area includes: an exposure area or a chip area.

[0166] Figure 7 This is a schematic diagram of the structure of a defect detection device provided in another embodiment of this application.

[0167] The defect detection device may include a processor 701 and a memory 702 storing computer program instructions.

[0168] Specifically, the processor 701 may include a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits that can be configured to implement the embodiments of this application.

[0169] Memory 702 may include mass storage for data or instructions. For example, and not limitingly, memory 702 may include a hard disk drive (HDD), floppy disk drive, flash memory, optical disk, magneto-optical disk, magnetic tape, or Universal Serial Bus (USB) drive, or a combination of two or more of these. Where appropriate, memory 702 may include removable or non-removable (or fixed) media. Where appropriate, memory 702 may be internal or external to the integrated gateway disaster recovery device. In a particular embodiment, memory 702 is non-volatile solid-state memory.

[0170] In a particular embodiment, memory 702 includes read-only memory (ROM). Where appropriate, the ROM may be a mask-programmed ROM, a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), an electrically rewritable ROM (EAROM), or flash memory, or a combination of two or more of these.

[0171] The processor 701 implements any of the defect detection methods described in the above embodiments by reading and executing computer program instructions stored in the memory 702.

[0172] In one example, the defect detection device may also include a communication interface 703 and a bus 710. Wherein, as... Figure 7 As shown, the processor 701, memory 702, and communication interface 703 are connected through bus 710 and complete communication with each other.

[0173] The communication interface 703 is mainly used to realize communication between various modules, devices, units and / or equipment in the embodiments of this application.

[0174] Bus 710 includes hardware, software, or both, that couples components of an online data traffic metering device together. For example, and not limitingly, the bus may include an Accelerated Graphics Port (AGP) or other graphics bus, an Enhanced Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), HyperTransport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an Infinite Bandwidth Interconnect, a Low Pin Count (LPC) bus, a memory bus, a Microchannel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local (VLB) bus, or other suitable buses, or combinations of two or more of these. Where appropriate, bus 710 may include one or more buses. Although specific buses are described and illustrated in embodiments of this application, any suitable bus or interconnect is contemplated herein.

[0175] Furthermore, in conjunction with the defect detection methods in the above embodiments, this application embodiment can provide a computer storage medium for implementation. The computer storage medium stores computer program instructions; when these computer program instructions are executed by a processor, they implement any of the defect detection processing methods in the above embodiments.

[0176] This application also provides a computer program product, including a computer program, which, when executed, implements any of the defect detection methods described in the above embodiments.

[0177] It should be clarified that this application is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of this application is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of this application.

[0178] The functional blocks shown in the above-described structural diagram can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this application are programs or code segments used to perform the required tasks. Programs or code segments can be stored on a machine-readable medium or transmitted over a transmission medium or communication link via data signals carried on a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio frequency (RF) links, etc. Code segments can be downloaded via computer networks such as the Internet, intranets, etc.

[0179] It should also be noted that the exemplary embodiments mentioned in this application describe methods or systems based on a series of steps or apparatus. However, this application is not limited to the order of the above steps; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0180] The aspects of this disclosure have been described above with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block in the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that these instructions, executable via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field-programmable logic circuit. It is also understood that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can also be implemented by special-purpose hardware performing the specified functions or actions, or can be implemented by a combination of special-purpose hardware and computer instructions.

[0181] The above description is merely a specific implementation of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.

Claims

1. A defect detection method, characterized in that, include: Obtain actual topographic data of one or more local regions of the target wafer and the global layout of the target wafer; Based on the mapping relationship between wafer morphology and process parameters, for each local region, the predicted process parameters corresponding to the actual morphology data of that local region are determined. Based on the mapping relationship between the wafer morphology and process parameters, for each local region, the wafer morphology of the global layout under the predicted process parameters in that local region is predicted to obtain wafer morphology prediction data. Based on the predicted wafer morphology data corresponding to each of the local regions, the defective areas of the target wafer are determined. From all the aforementioned bad pixel regions, determine the region to be detected; Using a defect scanning device, the area to be detected on the target wafer is scanned to obtain defect detection results.

2. The method according to claim 1, characterized in that, From all the aforementioned bad pixel regions, determine the region to be detected, including: Determine the severity of defects in all of the aforementioned bad pixel regions; Based on the severity of defects in all the aforementioned bad pixel regions, regions to be detected are selected from all the aforementioned bad pixel regions.

3. The method according to claim 1, characterized in that, Using a defect scanning device, the area to be inspected on the target wafer is scanned to obtain defect detection results, including: Determine the graphic density of the region to be detected; Based on the graphic density, the scanning parameters of the region to be detected are determined; Based on the scanning parameters of the area to be detected, the defect scanning device is controlled to scan the area to be detected, and the defect detection result is obtained.

4. The method according to claim 1, characterized in that, Obtain actual topographic data of one or more local regions of the target wafer, including: Using measurement equipment, images of one or more local regions of the target wafer are obtained by measurement; From the image of each local region, extract the actual topographic data of each local region.

5. The method according to claim 1, characterized in that, Based on the mapping relationship between wafer morphology and process parameters, for each local region, the predicted process parameters corresponding to the actual morphology data of that local region are determined, including: The defect prediction model predicts the process parameters corresponding to the actual morphology data of each local region. The defect prediction model has been trained in advance to learn the mapping relationship between wafer morphology and process parameters. Based on the mapping relationship between the wafer morphology and process parameters, for each local region, the wafer morphology of the global layout under the predicted process parameters in that local region is predicted to obtain wafer morphology prediction data, including: Using the defect prediction model, for each local region, the wafer morphology of the global layout under the predicted process parameters in that local region is predicted, and wafer morphology prediction data is obtained.

6. The method according to claim 5, characterized in that, The bad pixel prediction model is trained through the following steps: Obtain multiple global layout samples with different process parameters and the corresponding bad pixel region labels for the multiple global layout samples; The defect prediction model is used to predict the wafer morphology of multiple global layout samples with different process parameters, and the wafer morphology prediction data corresponding to the multiple global layout samples is obtained. Based on the wafer morphology prediction data corresponding to the multiple global layout samples, the predicted bad spot regions corresponding to the multiple global layout samples are determined. Based on the predicted bad pixel regions and bad pixel region labels corresponding to the multiple global map samples, the prediction loss of the bad pixel prediction model is calculated. Based on the prediction loss, the model parameters of the bad pixel prediction model are adjusted to obtain the trained bad pixel prediction model.

7. The method according to any one of claims 1-6, characterized in that, The local area includes: the exposure area or the chip area.

8. An electronic device, characterized in that, The electronic device includes a processor, a memory, and a program or instructions stored in the memory and executable on the processor. When the program or instructions are executed by the processor, they implement the steps of the defect detection method as described in any one of claims 1-7.

9. A readable storage medium, characterized in that, The readable storage medium stores a program or instructions that, when executed by a processor, implement the steps of the defect detection method as described in any one of claims 1-7.

10. A computer program product, characterized in that, When the instructions in the computer program product are executed by the processor of the electronic device, the electronic device performs the defect detection method as described in any one of claims 1-7.

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