Updating method and device of photoetching mask, electronic equipment and storage medium

Abstract

The embodiment of the invention discloses a photoetching mask updating method and device, electronic equipment and a storage medium. The method comprises the following steps: acquiring a target chip layout, constructing a mask pattern and a level set function, and performing photoetching simulation on the mask pattern to obtain a wafer pattern; determining target loss according to the difference between the target chip layout and the wafer pattern, obtaining a first optimization item through a conjugate gradient optimizer, and obtaining a second optimization item through an adaptive moment estimation optimizer; performing attention processing on the target chip layout to obtain a target attention map, and adjusting the second optimization item based on the target attention map; updating the level set function based on the first optimization item and the adjusted second optimization item, and updating the mask pattern based on the updated level set function; according to the embodiment of the invention, while the complexity of the mask pattern is reduced, the pattern error of the mask pattern is effectively reduced, so that the correction precision of the mask pattern is improved, and the method can be widely applied to scenes such as cloud technology and chip manufacturing.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of computer, and in particular, to a photomask updating method and device, electronic equipment and storage medium. BACKGROUND

[0002] With the continuous reduction of feature size of integrated circuits, the diffraction-limited property of the photolithography system leads to significant optical proximity effects, which reduces the photolithography imaging quality. Therefore, the optical diffraction and proximity effect in photolithography are increasingly important and greatly affect the yield of integrated circuit manufacturing.

[0003] In related technologies, a photomask updating method based on optical proximity correction (OPC) is provided. The photomask updating method corrects the pattern on the photomask so that the pattern projected onto the photoresist conforms to the design requirements as much as possible, which is a photolithography resolution enhancement technology. However, the correction accuracy of the traditional OPC algorithm for the mask pattern is low, resulting in a large pattern error of the mask pattern, which is difficult to meet the design requirements of high-precision chips. SUMMARY

[0004] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of protection of the claims.

[0005] The embodiments of the present disclosure provide a photomask updating method, device, electronic equipment and storage medium, which can effectively reduce the pattern error of the mask pattern while reducing the complexity of the mask pattern, thereby improving the correction accuracy of the mask pattern.

[0006] In one aspect, the embodiments of the present disclosure provide a photomask updating method, comprising:

[0007] obtaining a target chip layout, constructing a mask pattern of the target chip layout, constructing a level set function based on a mask boundary of the mask pattern, and performing photolithography simulation on the mask pattern to obtain a wafer pattern;

[0008] determining a target loss according to the difference between the target chip layout and the wafer pattern, determining the gradient of the target loss according to the level set function, inputting the gradient of the target loss into a conjugate gradient optimizer to obtain a first optimization term, and inputting the gradient of the target loss into an adaptive moment estimation optimizer to obtain a second optimization term;

[0009] performing attention processing on the target chip layout to obtain a target attention map, and adjusting the second optimization term based on the target attention map;

[0010] update the level set function based on the first optimization item and the adjusted second optimization item, and update the mask map based on the updated level set function.

[0011] In another aspect, the embodiments of the present disclosure also provide an updating device for a photomask, comprising:

[0012] a simulation module, configured to obtain a target chip layout, construct a mask map of the target chip layout, construct a level set function based on a mask boundary of the mask map, and perform photolithography simulation on the mask map to obtain a wafer pattern;

[0013] a processing module, configured to determine a target loss according to a difference between the target chip layout and the wafer pattern, determine a gradient of the target loss according to the level set function, input the gradient of the target loss into a conjugate gradient optimizer to obtain a first optimization item, and input the gradient of the target loss into an adaptive moment estimation optimizer to obtain a second optimization item;

[0014] an adjusting module, configured to perform attention processing on the target chip layout to obtain a target attention map, and adjust the second optimization item based on the target attention map;

[0015] an updating module, configured to update the level set function based on the first optimization item and the adjusted second optimization item, and update the mask map based on the updated level set function.

[0016] Further, the updating module is specifically configured to:

[0017] perform weighted summation on the first optimization item and the adjusted second optimization item to obtain a parameter update amount;

[0018] update the level set function based on the parameter update amount.

[0019] Further, the updating module is specifically configured to:

[0020] obtain a current iteration number, determine a first weight corresponding to the first optimization item and a second weight corresponding to the second optimization item based on the current iteration number, wherein the first weight increases with an increase of the current iteration number, and the second weight decreases with an increase of the current iteration number;

[0021] perform weighted summation on the first optimization item and the adjusted second optimization item based on the first weight and the second weight to obtain a parameter update amount.

[0022] Further, the target chip layout comprises a graphic region, and the adjusting module is specifically configured to:

[0023] obtaining a target scaling ratio;

[0024] In the target chip layout, the graphic region is scaled at a same scale based on the target scaling ratio to obtain a target attention region, and a target attention map is determined according to the target attention region.

[0025] Further, the target chip layout includes a graphic region, and the adjusting module is specifically configured to:

[0026] perform attention processing on the graphic region to obtain a first attention region and a second attention region in the target chip layout, wherein the first attention region is located within the graphic region, and the second attention region is located outside the graphic region.

[0027] In the target chip layout, a target attention map is determined according to a difference between the second attention region and the first attention region.

[0028] Further, the adjusting module is specifically configured to:

[0029] obtain a first scaling ratio and a second scaling ratio, wherein the first scaling ratio is less than a preset ratio, and the second scaling ratio is greater than the preset ratio;

[0030] In the target chip layout, the graphic region is scaled at a same scale based on the first scaling ratio to obtain a first attention region, and the graphic region is scaled at a same scale based on the second scaling ratio to obtain a second attention region.

[0031] Further, the adjusting module is specifically configured to:

[0032] In the target chip layout, the graphic region is eroded based on a preset first convolution kernel to obtain a first initial region, and the graphic region is dilated based on a preset second convolution kernel to obtain a second initial region.

[0033] obtain a first attention weight of the first initial region and a second attention weight corresponding to the second initial region;

[0034] The first initial region is weighted based on the first attention weight to obtain a first attention region, and the second initial region is weighted based on the second attention weight to obtain a second attention region.

[0035] Further, the number of the second initial regions is multiple, any two of the second initial regions are determined based on different sizes of the second convolution kernels, the second attention weights corresponding to any two of the second initial regions are different, the second attention weight decreases with the increase of the corresponding second convolution kernel, and the first attention weight is equal to the sum of all the second attention weights, and the adjustment module is specifically used for:

[0036] weighting the second initial region corresponding to each of the second attention weights respectively to obtain a plurality of weighted regions;

[0037] determining a second attention region according to the sum of all the weighted regions.

[0038] Further, the simulation module is specifically used for:

[0039] inputting the preset process parameters and the mask pattern into a photolithography physical model to perform photolithography simulation to obtain light intensity distribution;

[0040] performing normalization processing on the light intensity distribution to obtain a wafer pattern.

[0041] Further, the process parameters include defocus parameters and exposure dose deviation parameters, and the processing module is specifically used for:

[0042] determining a target perimeter according to the length of the graphic boundary of the target chip layout, determining an initial error according to the difference between the target chip layout and the wafer pattern, and determining an imaging error according to the ratio of the initial error to the target perimeter;

[0043] constructing a first distribution function according to the defocus parameters, sampling the defocus parameters to obtain a defocus sampling point, inputting the defocus sampling point into the first distribution function to obtain a first adjustment factor;

[0044] constructing a second distribution function according to the exposure dose deviation parameters, sampling the exposure dose deviation parameters to obtain an exposure dose deviation sampling point, and inputting the exposure dose deviation sampling point into the second distribution function to obtain a second adjustment factor;

[0045] adjusting the imaging error based on the first adjustment factor and the second adjustment factor to obtain a target loss.

[0046] Further, the processing module is specifically used for:

[0047] determining the gradient of the imaging error according to the mask pattern;

[0048] determine a gradient of the target loss according to the first adjustment factor, the second adjustment factor, a gradient of the imaging error and a gradient of the level set function;

[0049] determine a penalty term according to the level set function, and adjust the gradient of the target loss based on the penalty term.

[0050] Further, the processing module is specifically configured to:

[0051] input the gradient of the target loss into a conjugate gradient optimizer to obtain a first optimization direction;

[0052] input the gradient of the target loss into a self-adaptive matrix estimation optimizer to obtain a second optimization direction;

[0053] determine a first optimization step based on the first optimization direction and a preset step factor, and obtain a first optimization term according to a product of the first optimization direction and the first optimization step;

[0054] determine a second optimization step based on the second optimization direction and the step factor, and obtain a second optimization term according to a product of the second optimization direction and the second optimization step.

[0055] Further, the updating device of the photolithography mask further comprises an optimization module, and the optimization module is specifically configured to:

[0056] obtain a current iteration number, and if the current iteration number is less than a preset number threshold, update the level set function again based on the target chip layout and the updated mask pattern, update the mask pattern again based on the updated level set function, and update the current iteration number until the current iteration number is greater than or equal to the number threshold;

[0057] Alternatively, if an imaging error determined based on the target chip layout and the wafer pattern is greater than a preset error threshold, update the level set function again based on the target chip layout and the updated mask pattern, update the mask pattern again based on the updated level set function until the imaging error is less than or equal to the error threshold.

[0058] In another aspect, the embodiments of the present disclosure further provide an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the above-mentioned updating method of the photolithography mask when executing the computer program.

[0059] In another aspect, the embodiments of the present disclosure further provide a computer readable storage medium, wherein the storage medium stores a computer program, and the computer program is executed by a processor to implement the above-mentioned updating method of the photolithography mask.

[0060] In another aspect, the embodiments of the present disclosure further provide a computer program product, which comprises a computer program stored in a computer readable storage medium. A processor of a computer device reads the computer program from the computer readable storage medium, and the processor executes the computer program to enable the computer device to perform the method for updating a photomask described above.

[0061] The embodiments of the present disclosure have at least the following beneficial effects: by constructing a mask graph of a target chip layout, then constructing a level set function through a mask boundary of the mask graph, and performing photolithography simulation on the mask graph to obtain a wafer pattern, then determining a target loss through a difference between the wafer pattern and the target chip layout, then obtaining a first optimization item through a gradient of the target loss processed by a conjugate gradient optimizer, and obtaining a second optimization item through the gradient of the target loss processed by an adaptive moment estimation optimizer, then adjusting the second optimization item by using a target attention map obtained through attention processing, and then updating the level set function through the first optimization item and the adjusted second optimization item, that is, optimizing the mask graph through the conjugate gradient optimizer and the adaptive moment estimation optimizer, the conjugate gradient optimizer can control the complexity of the mask graph, and the target attention map is used to limit the optimization range of the adaptive moment estimation optimizer, so that the adaptive moment estimation optimizer can reduce the pattern error of the mask graph while ensuring the manufacturability of the mask graph. Therefore, by combining the low mask complexity of the conjugate gradient optimizer and the strong optimization capability of the adaptive moment estimation optimizer, the pattern error of the mask graph can be effectively reduced while reducing the complexity of the mask graph, thereby improving the correction accuracy of the mask graph.

[0062] Other features and advantages of the present disclosure will be described in the following description, and some will become apparent from the description, or will be learned through implementation of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0063] The accompanying drawings are included to provide a further understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and are used together with the embodiments of the present disclosure to explain the technical solutions of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure.

[0064] Figure 1 A schematic diagram of an optional implementation environment provided for the embodiments of the present disclosure;

[0065] Figure 2 An optional flowchart of the method for updating a photomask provided for the embodiments of the present disclosure;

[0066] Figure 3 An optional structural schematic diagram of an initial mask graph provided for the embodiments of the present disclosure;

[0067] Figure 4 An optional structural schematic diagram of determining a target attention map provided by an embodiment of the present disclosure;

[0068] Figure 5 An optional flow schematic diagram of determining a second attention region provided by an embodiment of the present disclosure;

[0069] Figure 6 An optional flow schematic diagram of determining a wafer pattern provided by an embodiment of the present disclosure;

[0070] Figure 7 An optional evaluation schematic diagram of a pattern error provided by an embodiment of the present disclosure;

[0071] Figure 8 An optional structural schematic diagram of an updating device of a photolithography mask provided by an embodiment of the present disclosure;

[0072] Figure 9 A partial structural block diagram of a terminal provided by an embodiment of the present disclosure;

[0073] Figure 10 A partial structural block diagram of a server provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0074] In order to make the objectives, technical solutions and advantages of the present disclosure clearer, the present disclosure will be further described in detail below in combination with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present disclosure and do not limit the present disclosure.

[0075] It should be noted that in each specific embodiment of the present disclosure, when it is necessary to perform relevant processing according to data related to the characteristics of the target object, such as target object attribute information or attribute information set, the permission or consent of the target object will be obtained first, and the collection, use and processing of these data will comply with relevant laws, regulations and standards. Among them, the target object can be a user. In addition, when the embodiment of the present disclosure needs to obtain target object attribute information, it will obtain the separate permission or separate consent of the target object through a pop-up window or by jumping to a confirmation page, and after obtaining the separate permission or separate consent of the target object, the necessary target object related data for enabling the embodiment of the present disclosure to operate normally will be obtained.

[0076] In the embodiments of the present disclosure, the term "module" or "unit" refers to a computer program or a part of a computer program with a predetermined function, and works together with other related parts to achieve a predetermined target, and can be implemented entirely or partially by using software, hardware (such as a processing circuit or a memory) or a combination thereof. Similarly, one processor (or multiple processors or memories) can be used to implement one or more modules or units. In addition, each module or unit can be a part of an integral module or unit that contains the function of the module or unit.

[0077] To facilitate understanding of the technical solutions provided by the embodiments of the present disclosure, some key terms used by the embodiments of the present disclosure are explained first:

[0078] Cloud technology refers to a hosting technology that unifies a series of resources such as hardware, software, network, etc. in a wide area network or local area network to realize data calculation, storage, processing and sharing. Cloud technology is a general term for network technology, information technology, integration technology, management platform technology, application technology, etc. based on cloud computing business model application, which can form a resource pool, and can be used on demand, flexibly and conveniently. Cloud computing technology will become an important support. The background service of the technical network system needs a large amount of computing and storage resources, such as video websites, picture websites and more portal websites. With the high development and application of the Internet industry, in the future, every item may have its own identification mark and needs to be transmitted to the background system for logical processing. Different levels of data will be processed separately, and various industry data needs strong system support, which can only be realized through cloud computing.

[0079] Artificial Intelligence (AI) is the theory, method, technology and application system of using digital computer or digital computer controlled machine to simulate, extend and expand human intelligence, perceive environment, acquire knowledge and use knowledge to obtain the best results. In other words, artificial intelligence is a comprehensive technology of computer science, which attempts to understand the essence of intelligence and produce a new intelligent machine that can react in a similar way to human intelligence. Artificial intelligence is to study the design principles and implementation methods of various intelligent machines, so that machines have the functions of perception, reasoning and decision making. Artificial intelligence technology is a comprehensive discipline, involving a wide range of fields, both hardware and software technologies. Artificial intelligence basic technologies generally include sensors, special artificial intelligence chips, cloud computing, distributed storage, big data processing technology, pre-training model technology, operation / interaction system, mechatronics, etc. Among them, the pre-training model is also called large model, basic model, which can be widely applied to downstream tasks in various directions of artificial intelligence after fine tuning. Artificial intelligence software technology mainly includes computer vision technology, speech processing technology, natural language processing technology and machine learning / deep learning, etc.

[0080] Machine Learning (ML) is a multi-disciplinary subject, involving probability theory, statistics, approximation theory, convex analysis, algorithm complexity theory, etc. It is a subject that studies how computers simulate or realize human learning behavior to acquire new knowledge or skills, and reorganize existing knowledge structure to continuously improve their performance. Machine learning is the core of artificial intelligence and the fundamental approach to making computers intelligent, and its applications are widespread in various fields of artificial intelligence. Machine learning and deep learning usually include artificial neural networks, belief networks, reinforcement learning, transfer learning, inductive learning, and teaching learning.

[0081] Photolithography mask, also known as mask, is a kind of mask film for light. Its function is similar to photography. Through photolithography mask, a part of light under photolithography mask can be photosensitive and insoluble in organic chemicals, and a part of light can not be photosensitive and soluble in organic chemicals, so as to obtain the required pattern. In the manufacturing process of planar transistor and integrated circuit, multiple photolithography is required. Therefore, a set of photolithography masks with specific geometric patterns must be prepared. The preparation of photolithography mask is to prepare the mask pattern required by production in terms of size and precision according to the selected method according to the geometric pattern required by the parameters of transistor and integrated circuit, and to arrange the pattern repeatedly on the mask substrate with a certain pitch and layout, and then mass-produce photolithography mask for photolithography exposure.

[0082] In the related art, an optical proximity correction (OPC) based photomask updating method is provided. The photomask updating method corrects a pattern on a photomask, so that a pattern projected onto a photoresist conforms to design requirements as much as possible, and is a photolithography resolution enhancement technology. However, the correction accuracy of a traditional OPC algorithm for a mask pattern is low, resulting in a large pattern error of the mask pattern, and it is difficult to meet the design requirements of high-precision chips.

[0083] Based on this, the embodiments of the present disclosure provide a photomask updating method and device, electronic equipment and storage medium, which can effectively reduce the pattern error of the mask pattern while reducing the complexity of the mask pattern, thereby improving the correction accuracy of the mask pattern.

[0084] Reference Figure 1 , Figure 1 An optional implementation environment provided by the embodiments of the present disclosure is shown in a schematic diagram, which includes a terminal 101 and a server 102, wherein the terminal 101 and the server 102 are connected through a communication network.

[0085] Exemplarily, the server 102 can obtain a target chip layout sent by the terminal, construct a mask pattern of the target chip layout, construct a level set function based on a mask boundary of the mask pattern, perform photolithography simulation on the mask pattern to obtain a wafer pattern, determine a target loss according to a difference between the target chip layout and the wafer pattern, determine a gradient of the target loss according to the level set function, input the gradient of the target loss into a conjugate gradient optimizer to obtain a first optimization term, input the gradient of the target loss into an adaptive moment estimation optimizer to obtain a second optimization term, perform attention processing on the target chip layout to obtain a target attention map, adjust the second optimization term based on the target attention map, update the level set function based on the first optimization term and the adjusted second optimization term, update the mask pattern based on the updated level set function, and send the updated mask pattern to the terminal 101 by the server 102.

[0086] The server 102 builds a mask graph of the target chip layout, then builds a level set function through the mask boundary of the mask graph, and obtains a wafer pattern through photolithography simulation on the mask graph, and then determines a target loss through the difference between the wafer pattern and the target chip layout, then obtains a first optimization item through the gradient of the target loss processed by a conjugate gradient optimizer, and obtains a second optimization item through the gradient of the target loss processed by an adaptive moment estimation optimizer, then adjusts the second optimization item by using the target attention map obtained through attention processing, and then updates the level set function through the first optimization item and the adjusted second optimization item, that is, optimizes the mask graph through the conjugate gradient optimizer and the adaptive moment estimation optimizer, the conjugate gradient optimizer can control the complexity of the mask graph, and at the same time, the target attention map is used to limit the optimization range of the adaptive moment estimation optimizer, so that the adaptive moment estimation optimizer can reduce the pattern error of the mask graph on the premise of ensuring the manufacturability of the mask graph. Therefore, by combining the low mask complexity of the conjugate gradient optimizer and the strong optimization capability of the adaptive moment estimation optimizer, the pattern error of the mask graph can be effectively reduced while reducing the complexity of the mask graph, thereby improving the correction accuracy of the mask graph.

[0087] The server 102 can be a stand-alone physical server, a server cluster or a distributed system composed of multiple physical servers, or a cloud server providing cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, CDN (Content Delivery Network), and basic cloud computing services such as big data and artificial intelligence platforms. In addition, the server 102 can also be a node server in a blockchain network.

[0088] The terminal 101 can be a mobile phone, a computer, a smart voice interaction device, a smart home appliance, a vehicle-mounted terminal, etc., but is not limited thereto. The terminal 101 and the server 102 can be connected directly or indirectly through wired or wireless communication, and the present disclosure is not limited thereto.

[0089] The method provided by the present disclosure can be applied to various scenarios, including but not limited to cloud technology, chip manufacturing, etc.

[0090] Reference Figure 2 , Figure 2 An optional flowchart of the photomask updating method provided by the present disclosure is provided, which can be executed by a server, or can be executed by a terminal, or can be executed by a server in cooperation with a terminal. The photomask updating method includes but is not limited to the following steps 201 to 204.

[0091] Step 201: obtaining a target chip layout, constructing a mask graph of the target chip layout, constructing a level set function based on a mask boundary of the mask graph, and performing photolithography simulation on the mask graph to obtain a wafer pattern.

[0092] The target chip layout belongs to an integrated circuit layout, which is a planar geometric shape description of the physical situation of a real integrated circuit. The integrated circuit layout is the result of the physical design of the bottom step in the integrated circuit design. The physical design converts the result of logic synthesis into a layout file through layout and wiring technology. The layout file contains the shape, area, and position information of each hardware unit on the chip. In short, the target chip layout specifically refers to the graphical representation of the target chip. The target chip layout includes a graphical area where circuit elements need to be laid out and a blank area where circuit elements do not need to be laid out. The circuit elements include but are not limited to transistors, resistors, capacitors, wires, and the like. The graphical area is a complete and closed area, i.e., an area enclosed by a closed curve. The target chip layout can be a binary image, for example, the pixel value of a pixel point in the graphical area is 1, and the pixel value of a pixel point in the blank area is 0.

[0093] Specifically, the target chip layout can be the layout of a functional layer of the target chip, such as a connection layer, a metal line layer, and the like. The embodiments of the present disclosure are not limited here. In addition, the type of chip layout can also be divided according to the application field, for example, quantum chip, home appliance chip, mobile phone chip, computer chip, wearable device chip, industrial robot chip, and the like. The target chip layout can be any type of layout, and the embodiments of the present disclosure are not limited here.

[0094] The manufacturing process of the target chip is described below.

[0095] In the photolithography process, the target chip is usually obtained on a thin silicon wafer (or other semiconductor material wafer), and the target chip layout is the target design requirement of the wafer. Specifically, the manufacturing process of the target chip includes but is not limited to: setting a plating layer on the surface of the wafer, then coating a thin layer of photoresist on the surface of the plating layer, then exposing the photoresist, then dissolving part of the photoresist with a developing solution, then etching the plating layer not covered by the photoresist, and then removing the remaining photoresist.

[0096] In the exposure process, light emitted from a lithography machine passes through a photomask to expose a thin wafer coated with photoresist. The photomask is a graphical representation of the lithography mask, comprising transparent and opaque areas. It can be a binary image; for example, pixels in the transparent area have a value of 0, while pixels in the opaque area have a value of 1. During the exposure step of the lithography process, the opaque areas of the mask block the light emitted from the lithography machine, while the light passes through the transparent areas and illuminates the photoresist-coated wafer. Therefore, the exposed photoresist can include exposed and unexposed areas. The exposed area is the region where the photoresist is exposed, also known as the photosensitive area. The unexposed area is the region where the photoresist is not exposed, also known as the non-photosensitive area. Photoresist can be classified into two types based on whether the exposed area is removed or retained during the development process: positive photoresist and negative photoresist. Photoresist and negative photoresist: In positive photoresist, the exposed areas are soluble in the developer while the unexposed areas are insoluble. In this case, the transparent areas of the mask directly determine the final pattern formed on the wafer, and there is a direct mapping relationship between the transparent areas of the mask and the patterned areas of the target chip layout. Conversely, in negative photoresist, the unexposed areas are soluble in the developer while the exposed areas are insoluble. In this case, the opaque areas of the mask directly determine the final pattern formed on the wafer, and there is a direct mapping relationship between the opaque areas of the mask and the patterned areas of the target chip layout.

[0097] The manufacturing process of photolithography masks is described below.

[0098] First, an initial mask pattern can be constructed based on the target chip layout and the type of photoresist. For example, when the photoresist is positive, a mask pattern can be constructed that matches the target chip layout. Figure 1 The image is used as a mask image. For example, when the photoresist is negative, the target chip layout is inverted to obtain a mask image. Specifically, refer to... Figure 3 , Figure 3 This is a schematic diagram of an optional structure for an initial mask pattern provided in an embodiment of this disclosure. It can be seen that the mask pattern and the target chip layout have the same dimensions, and the pattern of the initial mask pattern is consistent with the pattern of the target chip layout. However, due to optical diffraction and proximity effects, the pattern on the photoresist and the pattern on the mask pattern are usually inconsistent, meaning the pattern of the target chip layout is usually inconsistent with the pattern on the mask pattern. Since the pattern of the initial mask pattern is consistent with the pattern of the target chip layout, the mask pattern needs to be corrected.

[0099] Then, the initial wafer pattern can be obtained by performing photolithography simulation on the initial mask pattern. Subsequently, the target chip layout can be used as a design requirement of the wafer pattern to inversely calculate the required pattern of the mask pattern, and then the mask pattern is updated. The updated mask pattern is used to manufacture a corresponding photolithography mask. The difference between the wafer pattern obtained based on the photolithography mask and the target chip layout is effectively reduced, the precision and accuracy of the wafer pattern are improved, and the electrical performance of the circuit on the wafer is avoided.

[0100] Therefore, the mask boundary is used to indicate the contour of the pattern of the mask pattern. The mask boundary specifically refers to the junction of the light-transmitting region and the non-light-transmitting region of the mask pattern. The pattern of the mask pattern is complete and closed. The mask boundary forms a closed curve. The mask boundary of the mask pattern is represented as a zero level set of a level set function by using a level set method, that is, the level set function is constructed based on the mask boundary of the mask pattern, which is also called an initial level set function. The level set function is a signed distance function (SDF). For example, the function value of the level set function is set to 0 for a pixel point located on the mask boundary, the function value of the level set function is less than 0 for a pixel point located inside the mask boundary, and the function value of the level set function is greater than 0 for a pixel point located outside the mask boundary. The level set function is the basis for adjusting the mask pattern in the optimization process. Subsequently, the shape of the mask boundary can be changed by adjusting the level set function, so as to optimize the photolithography effect and the layout fidelity. The wafer pattern can be predicted by performing photolithography simulation on the mask pattern, and then the projection effect of the mask pattern on the wafer is verified.

[0101] Specifically, an optional determination formula of the level set function is as follows:

[0102]

[0103] wherein ψ(x, y) is the level set function, (x, y) is used to indicate a pixel point in the mask pattern, x is the horizontal coordinate of the pixel point, y is the vertical coordinate of the pixel point, C is the mask boundary, (x, y) ∈ inside(C) means that the pixel point (x, y) is located inside the mask boundary C, (x, y) ∈ (C) means that the pixel point (x, y) is located on the mask boundary C, (x, y) ∈ outside(C) means that the pixel point (x, y) is located outside the mask boundary C, and d(x, y) is the distance between the pixel point (x, y) and the mask boundary C. For example, d(x, y) is the shortest Euclidean distance from the pixel point (x, y) to the mask boundary. Therefore, d(x, y) is a non-negative number. As can be seen, when the pixel point (x, y) is located inside the mask boundary C, the level set function ψ(x, y) is less than 0. When the pixel point (x, y) is located on the mask boundary C, the level set function ψ(x, y) is equal to 0. When the pixel point (x, y) is located outside the mask boundary C, the level set function ψ(x, y) is greater than 0.

[0104] Step 202: determining a target loss according to the difference between the target chip layout and the wafer pattern, determining a gradient of the target loss according to the level set function, inputting the gradient of the target loss into a conjugate gradient optimizer to obtain a first optimization item, and inputting the gradient of the target loss into an adaptive moment estimation optimizer to obtain a second optimization item.

[0105] wherein the difference between the target chip layout and the wafer pattern can be obtained by subtracting the wafer pattern from the target chip layout, and then the target loss is determined based on the difference, so the target loss is a function for evaluating the difference between the target chip layout and the wafer pattern, and the gradient of the target loss according to the level set function specifically refers to determining the gradient of the target loss with respect to the level set function, for example, assuming that the target loss is L LS , and the level set function is ψ, then the gradient of the target loss is

[0106] As can be seen, in the target loss, since the wafer pattern is obtained by photolithography simulation based on the mask pattern, the design parameters of the mask pattern corresponding to the wafer pattern are the current design parameters, while the design parameters of the mask pattern corresponding to the target chip layout as the target design requirement are the target design parameters, so the target loss can represent the deviation degree between the current design parameters and the target design parameters of the mask pattern, when the difference between the target chip layout and the wafer pattern is larger, the target loss is larger, and the deviation degree between the current design parameters and the target design parameters of the mask pattern is larger, on the contrary, when the difference between the target chip layout and the wafer pattern is smaller, the target loss is smaller, and the deviation degree between the current design parameters and the target design parameters of the mask pattern is smaller.

[0107] Based on this, the gradient of the target loss is used to indicate the direction in which the target loss grows fastest and the change rate under the current design parameters, the gradient of the target loss is processed by the conjugate gradient optimizer to obtain the first optimization item, and when the iterative optimization is performed based on the first optimization item, not only the gradient direction at the current step is considered, but also the optimization direction at the previous step is considered, so as to ensure that the new optimization direction is conjugate to the previous optimization direction, thereby improving the convergence speed.

[0108] In addition, the gradient of the target loss is processed by the adaptive moment estimation optimizer to obtain the second optimization item, and when the iterative optimization is performed based on the second optimization item, not only the gradient direction at the current step is considered, but also the exponential decay average of the historical gradient is integrated, which is equivalent to adding the influence of the historical gradient to the current optimization step in the form of momentum, so as to accelerate along the direction in which the gradient continuously decreases, and slow down the fluctuation in the unstable direction; at the same time, the adaptive moment estimation optimizer can also realize the adaptive learning rate by calculating the square of the exponential decay average of the gradient, so as to improve the efficiency and stability of the overall optimization process.

[0109] Step 203: performing attention processing on the target chip layout to obtain a target attention map, and adjusting the second optimization item based on the target attention map.

[0110] The attention processing is used to determine the correction region of the mask boundary in the target chip layout. For any pixel point of the target chip layout, the attention score of the pixel point with respect to the pattern of the target chip layout can be determined through the attention processing. When the attention score of the pixel point is higher, that is, the attention degree of the pixel point is higher, it represents that the probability of the pixel point belonging to the correction region of the mask boundary is higher. For example, when the pixel point is closer to the pattern of the target chip layout, the attention score of the pixel point is usually higher. Conversely, when the attention score of the pixel point is lower, that is, the attention degree of the pixel point is lower, it represents that the probability of the pixel point belonging to the correction region of the mask boundary is lower. For example, when the pixel point is farther away from the pattern of the target chip layout, the attention score of the pixel point is usually lower.

[0111] Therefore, the attention score of each pixel point of the target chip layout is determined through the attention processing, and then the target attention map is determined through each attention score. The value of any pixel point in the target attention map is the attention score of the corresponding pixel point in the target chip layout. It can be seen that the target attention map is aligned with the target chip layout at the pixel level, and the size of the target attention map is consistent with the size of the target chip layout. The target attention map can include an attention region with a higher attention degree and a non-attention region with a lower attention degree. The attention region with a higher attention degree is the correction region of the mask boundary. The correction of the mask boundary in the correction region can improve the correction efficiency of the mask boundary.

[0112] For example, the attention score of the pixel point located in the attention region can be set to 1, and the attention score of the pixel point located in the non-attention region can be set to 0. The adjustment of the second optimization item based on the target attention map can adjust the optimization step of the pixel point located in the non-attention region to 0, which is equivalent to limiting the optimization range of the adaptive moment estimation optimizer in the attention region of the target attention map. This can effectively reduce the optimization range, thereby reducing the mask complexity and enabling the adaptive moment estimation optimizer to reduce the pattern error of the mask pattern while ensuring the manufacturability of the mask pattern. In addition to 0 or 1, the attention score can also be set to other score values, which are not limited in the embodiments of the present disclosure.

[0113] Specifically, the target attention map can be the result of expansion of the target chip layout, or the result of reduction of the target chip layout, which are not limited in the embodiments of the present disclosure.

[0114] Taking the target attention map as the result of expansion of the target chip layout as an example, referring to FIG. 2, the target attention map is obtained by expanding the target chip layout, and the target attention map is obtained by adjusting the target chip layout.Figure 4 , Figure 4 An optional structural schematic diagram for determining the target attention map is provided for the embodiments of the present disclosure.

[0115] In the figure, the graphic region of the target chip layout is the region enclosed by the solid line, and the attention region of the target attention map is the region enclosed by the dashed line. It can be seen that the target chip layout includes multiple graphic regions, and the graphic regions are located in the corresponding attention regions, which is equivalent to expanding the target chip layout to obtain the target attention map.

[0116] Step 204: updating the level set function based on the first optimization item and the adjusted second optimization item, and updating the mask map based on the updated level set function.

[0117] In the figure, the graphic region of the target chip layout is the region enclosed by the solid line, and the attention region of the target attention map is the region enclosed by the dashed line. It can be seen that the target chip layout includes multiple graphic regions, and the graphic regions are located in the corresponding attention regions, which is equivalent to expanding the target chip layout to obtain the target attention map.

[0118] Specifically, when the level set function is updated by the first optimization item, since the gradient optimizer only needs to consider the current gradient direction and the optimization direction of the previous step, a smoother and more continuous optimization path is formed, avoiding drastic changes in the mask map, thereby preventing unnecessary complex details from appearing in the mask map, and the simplicity and manufacturability of the mask map can be maintained. Therefore, the conjugate gradient optimizer has the advantage of low mask complexity. In addition, when the level set function is updated by the second optimization item, since the adaptive moment estimation optimizer adjusts the learning rate of each parameter by calculating the first and second moments of the gradient, the adaptive learning rate enables the adaptive moment estimation optimizer to reduce the learning step when approaching the local minimum, which helps to more accurately find the optimal point. Therefore, the adaptive moment estimation optimizer has high global optimization capability and can effectively reduce the graphic error of the mask map, and the adaptive moment estimation optimizer has the advantage of strong optimization capability. Generally, when only the conjugate gradient optimizer is used for optimization, the optimization result is often a local minimum, and when only the adaptive moment estimation optimizer is used for optimization, the complexity of the generated mask map is high and it is difficult to manufacture.

[0119] Based on this, the level set function is updated based on the first optimization term and the adjusted second optimization term, that is, the mask boundary is optimized, and then the updated mask graph is determined, which is equivalent to optimizing the mask graph by using the conjugate gradient optimizer and the adaptive moment estimation optimizer, the conjugate gradient optimizer can control the complexity of the mask graph, and the optimization range of the adaptive moment estimation optimizer is limited by using the target attention graph, so that the adaptive moment estimation optimizer can reduce the pattern error of the mask graph while ensuring the manufacturability of the mask graph. Therefore, the updating method of the photomask provided in the embodiments of the present disclosure can effectively reduce the pattern error of the mask graph while reducing the complexity of the mask graph by combining the low mask complexity of the conjugate gradient optimizer and the strong optimization capability of the adaptive moment estimation optimizer, thereby improving the correction accuracy of the mask graph.

[0120] Specifically, an optional determination formula of the mask graph is as follows:

[0121]

[0122] wherein M(x, y) is a pixel value of a pixel point at a coordinate (x, y) in the mask graph M, (x, y) is used to indicate a pixel point in the mask graph, x is the horizontal coordinate of the pixel point, y is the vertical coordinate of the pixel point, and ψ(x, y) is the level set function. It can be seen that, in the mask graph, when the level set function ψ(x, y) is less than or equal to 0, the pixel value of the pixel point (x, y) is 1, that is, the pixel value of the pixel point located on or in the mask boundary is 1, and when the level set function ψ(x, y) is greater than 0, the pixel value of the pixel point (x, y) is 0, that is, the pixel value of the pixel point located outside the mask boundary is 0. Therefore, the mask graph is a binary image, for example, the pixel value of the pixel point in the mask boundary is 0, and the pixel value of the pixel point outside the mask boundary is 1.

[0123] In a possible implementation, the level set function is updated based on the first optimization term and the adjusted second optimization term. Specifically, the first optimization term and the adjusted second optimization term can be weighted and summed to obtain a parameter update amount, and the level set function is updated based on the parameter update amount. The parameter update amount refers to the adjustment amount of each parameter in the level set function.

[0124] Based on this, in the updating process of the level set function, the balance between the optimization tasks of the conjugate gradient optimizer and the adaptive moment estimation optimizer can be adjusted by adjusting the weights allocated to the first optimization term and the second optimization term. Therefore, the complexity of the mask graph can be controlled by the conjugate gradient optimizer, and the pattern error of the mask graph can be effectively reduced by the adaptive moment estimation optimizer.

[0125] The determination manner of the weights allocated to the first optimization term and the second optimization term will be described in detail below.

[0126] In a possible implementation of determining the weight, the first optimization term and the adjusted second optimization term are weighted and summed to obtain the parameter update amount, specifically, a current iteration number can be obtained, a first weight corresponding to the first optimization term and a second weight corresponding to the second optimization term are determined based on the current iteration number, the first weight increases with an increase of the current iteration number, and the second weight decreases with an increase of the current iteration number; the first optimization term and the adjusted second optimization term are weighted and summed based on the first weight and the second weight to obtain the parameter update amount.

[0127] Based on this, when the level set function is iteratively optimized, the current iteration number needs to be obtained at each step, the initial current iteration number can be set to 0, the current iteration number can be increased by 1 each time the level set function is updated, and then the first weight and the second weight are determined based on the current iteration number, so that the first weight and the second weight can be continuously adjusted during the iterative optimization, thereby reasonably adjusting the balance between the optimization task of the conjugate gradient optimizer and the optimization task of the adaptive moment estimation optimizer. Since the second weight decreases with an increase of the current iteration number, the influence degree of the optimization task of the adaptive moment estimation optimizer on the parameter update amount can be increased in the early stage of optimization, and the influence degree of the optimization task of the adaptive moment estimation optimizer on the parameter update amount can be reduced in the later stage of optimization, so that the complexity of the mask map can be avoided to be too high, and the manufacturability of the mask map can be ensured.

[0128] For example, the current iteration number is input into a preset weight calculation formula to obtain the second weight, the sum of the first weight and the second weight is limited to be equal to one, the first weight is calculated based on the second weight, and the first weight is 1-w assuming that the second weight is w. The specific form of the weight calculation formula is not limited in the embodiments of the present disclosure.

[0129] For example, an optional calculation formula of the weight calculation formula can be:

[0130] w=α1*λ1 t

[0131] wherein w is the second weight, α1 and λ1 are hyperparameters, α1 and λ1 are greater than 0 and less than 1, t is the current iteration number, and λ1 is used to control the adjustment rate of the second weight. For example, α1 can be set to 0.05, and λ1 can be set to 0.9.

[0132] For another example, another optional calculation formula of the weight calculation formula can be:

[0133] w=α2 / (1+λ2t)

[0134] wherein w is the second weight, a2 and l2 are both hyperparameters, a2 is greater than 0 and less than 1, l2 is greater than 0, t is the current iteration number, and l2 is used to control the adjustment rate of the second weight; for example, a2 can be set to 0.05, and l2 can be set to 0.9.

[0135] In another possible implementation of determining the weight, the first optimization term and the adjusted second optimization term are weighted and summed to obtain the parameter update amount, and specifically, the first weight and the second weight can be determined based on the target loss, wherein the first weight increases as the target loss increases, and the second weight decreases as the target loss increases; and the first optimization term and the adjusted second optimization term are weighted and summed based on the first weight and the second weight to obtain the parameter update amount. Based on this, the first weight and the second weight are dynamically adjusted according to the target loss, which can reasonably adjust the balance between the optimization task of the conjugate gradient optimizer and the optimization task of the adaptive moment estimation optimizer, thereby avoiding excessively high complexity of the mask graph and ensuring the manufacturability of the mask graph.

[0136] The determination manner of the target attention map is described in detail below.

[0137] In a first possible implementation of determining the target attention map, the target chip layout includes a graphic region, and the target chip layout is subjected to attention processing to obtain the target attention map, and specifically, a target scaling ratio can be obtained, the graphic region in the target chip layout is scaled in proportion based on the target scaling ratio to obtain a target attention region, and the target attention map is determined according to the target attention region.

[0138] wherein the target chip layout includes a graphic region and a blank region, the pixel value of a pixel point in the graphic region is 1, the pixel value of a pixel point in the blank region is 0, the target scaling ratio is greater than 0, and the target attention region is a region scaled in proportion from the target chip layout, therefore, the pixel value of a pixel point in the target attention region is also 1, which is equivalent to that the attention score of a pixel point in the target attention region is 1, and the target attention region is specifically a region that needs to be paid special attention to in the target chip layout, and the target attention region is specifically a correction region of a mask boundary; wherein in addition to being set to 1, the attention score can also be set to other score values, for example, after the target attention region is determined, the attention score of a pixel point in the target attention region is set to 0.8, which is not limited in the embodiments of the present disclosure.

[0139] wherein since the target chip layout can include multiple graphic regions, the target attention map can include multiple target attention regions, and there is no overlapping region between any two target attention regions.

[0140] Therefore, the target attention region is obtained by performing the equal-ratio scaling processing on the graphic region based on the target scaling ratio, the proportion between the side lengths of the graphics can be ensured to be unchanged, the target attention map can be quickly determined, and the optimization efficiency is improved. On this basis, the optimization range of the adaptive moment estimation optimizer is limited in the target attention region of the target attention map, the optimization range is effectively reduced, the mask complexity is reduced, and the adaptive moment estimation optimizer can reduce the graphic error of the mask map under the premise of ensuring the manufacturability of the mask map.

[0141] Specifically, the target scaling ratio is greater than 0, when the target scaling ratio is greater than 1, the graphic region is located in the target attention region, and when the target scaling ratio is less than 1, the graphic region is located outside the target attention region, and the specific value of the target scaling ratio is not limited in the embodiment of the disclosure.

[0142] For example, in the target attention map, the attention score of the pixel point located in the target attention region can be 1, and the attention score of the pixel point located outside the target attention region can be 0. The second optimization term is adjusted based on the target attention map, the optimization step of the pixel point located outside the target attention region is adjusted to 0, therefore, the optimization range of the adaptive moment estimation optimizer is in the target attention region, the optimization range is effectively reduced, the mask complexity is reduced, and the adaptive moment estimation optimizer can reduce the graphic error of the mask map under the premise of ensuring the manufacturability of the mask map.

[0143] In a second possible implementation manner of determining the target attention map, the target chip layout includes a graphic region, and the target chip layout is subjected to attention processing to obtain a target attention map. Specifically, the graphic region can be subjected to attention processing to obtain a first attention region and a second attention region in the target chip layout, wherein the first attention region is located in the graphic region, and the second attention region is located outside the graphic region; and the target attention map is determined according to the difference between the second attention region and the first attention region in the target chip layout.

[0144] The graphic region is subjected to attention processing to obtain regions with different importance degrees in the graphic region, the first attention region is located in the graphic region, the first attention region is a core region with a relatively high importance degree in the graphic region, and the second attention region is located outside the graphic region, the second attention region includes the core region with the relatively high importance degree and a peripheral region with a relatively low importance degree in the graphic region.

[0145] Based on this, the target attention map is determined according to the difference between the second attention region and the first attention region, and then the optimization range of the adaptive moment estimation optimizer is limited within the target attention map, which is equivalent to determining the peripheral region between the second attention region and the first attention region as the correction region of the mask boundary, which can not only ensure the integrity and performance of the core function, but also effectively reduce the optimization range, thereby reducing the mask complexity, so that the adaptive moment estimation optimizer can reduce the pattern error of the mask map while ensuring the manufacturability of the mask map.

[0146] Specifically, the pixel value of a pixel point in the target attention map is the attention score of the pixel point, and in the target chip layout, the peripheral region is a region with a higher attention degree, and the region outside the peripheral region is a region with a lower attention degree. Therefore, in the target attention map, the attention score of the pixel point located in the peripheral region is higher, and the attention score of the pixel point located outside the peripheral region is lower, so that the optimization range of the adaptive moment estimation optimizer is limited within the peripheral region.

[0147] Illustratively, the attention score of the pixel point located in the first attention region can be set to 1, and the attention score of the pixel point located in the second attention region can be set to 1. The target attention map is obtained by subtracting the first attention region from the second attention region. In the target attention map, the attention score of the pixel point located in the region between the second attention region and the first attention region is 1, and the attention score of the pixel point located in the first attention region is 0. Based on the target attention map, the second optimization term is adjusted, which can adjust the optimization step of the pixel point located in the first attention region to 0. Therefore, the optimization range of the adaptive moment estimation optimizer is the region between the second attention region and the first attention region, which can effectively reduce the optimization range. In addition to being set to 1, the attention score can also be set to other score values, which are not limited in the embodiments of the present disclosure.

[0148] In a possible implementation, the graphic region is subjected to attention processing to obtain the first attention region and the second attention region in the target chip layout. Specifically, the first scaling ratio and the second scaling ratio can be obtained, where the first scaling ratio is less than a preset ratio, and the second scaling ratio is greater than the preset ratio. In the target chip layout, the graphic region is subjected to equal-ratio scaling based on the first scaling ratio to obtain the first attention region, and the graphic region is subjected to equal-ratio scaling based on the second scaling ratio to obtain the second attention region.

[0149] The preset ratio can be set to 1, and the preset ratio can also be set to other numerical values, so that the first attention region obtained by equal-ratio scaling is located within the graphic region, and the second attention region obtained by equal-ratio scaling is located outside the graphic region, which are not limited in the embodiments of the present disclosure.

[0150] Therefore, by scaling the graphic region by the first scaling ratio and the second scaling ratio, the proportionality between the side lengths of the graphic can be ensured, and the first attention region and the second attention region can be quickly determined, thereby improving the optimization efficiency.

[0151] In a possible implementation, the graphic region is subjected to attention processing to obtain the first attention region and the second attention region in the target chip layout. Specifically, in the target chip layout, the graphic region is eroded based on a preset first convolution kernel to obtain a first initial region, and the graphic region is dilated based on a preset second convolution kernel to obtain a second initial region; a first attention weight of the first initial region and a second attention weight corresponding to the second initial region are obtained; the first initial region is weighted based on the first attention weight to obtain the first attention region, and the second initial region is weighted based on the second attention weight to obtain the second attention region.

[0152] The first convolution kernel can be a structural element with all elements being 1. The graphic region is eroded based on the first convolution kernel. Specifically, each pixel point of the target chip layout is scanned by using the first convolution kernel. The value of the currently scanned pixel point is the minimum value of the pixel points covered by the first convolution kernel. Therefore, the erosion processing can reduce the edge of the graphic region, thereby eliminating small details to obtain the first initial region located within the graphic region. The first initial region is weighted based on the first attention weight, which is equivalent to obtaining the first attention region by spatial attention processing. For example, assuming that the pixel value of the pixel point located in the first initial region is 1, and the first attention weight is 1, the attention score of the pixel point located in the first attention region is 1.

[0153] The second convolution kernel can be a structural element with all elements being 1. The graphic region is dilated based on the second convolution kernel. Specifically, each pixel point of the target chip layout is scanned by using the second convolution kernel. The value of the currently scanned pixel point is the maximum value of the pixel points covered by the second convolution kernel. Therefore, the dilation processing can expand the edge of the graphic region to fill small cracks or small holes in the graphic to obtain the second initial region located outside the graphic region. The second initial region is weighted based on the second attention weight, which is equivalent to obtaining the second attention region by spatial attention processing. For example, assuming that the pixel value of the pixel point located in the second initial region is 1, and the second attention weight is 0.5, the attention score of the pixel point located in the second attention region is 0.5.

[0154] Based on this, the first initial region is a core region with relatively high importance in the graphic region, a suitable first attention weight is obtained first, and then a first attention region with reasonable attention scores is obtained by weighting. The second initial region includes the core region with relatively high importance and a peripheral region with relatively low importance in the graphic region. Similarly, a suitable second attention weight is obtained first, and then a second attention region with reasonable attention scores is obtained by weighting. Therefore, the target attention map is determined according to the difference between the second attention region and the first attention region, so that the attention scores of the pixel points in the peripheral region are relatively high, and the attention scores of the pixel points in the core region are relatively low, which can not only ensure the integrity and performance of the core function, but also effectively reduce the optimization range, thereby reducing the mask complexity, so that the adaptive mask estimation optimizer can reduce the graphic error of the mask map while ensuring the manufacturability of the mask map.

[0155] In a possible implementation, the number of the second initial regions is multiple, any two second initial regions are determined based on second convolution kernels of different sizes, the second attention weights corresponding to any two second initial regions are different, the second attention weight decreases with the increase of the corresponding second convolution kernel, the first attention weight is equal to the sum of all second attention weights, and the second initial regions are weighted based on the second attention weights to obtain the second attention region. Specifically, each second initial region can be weighted based on the corresponding second attention weight to obtain multiple weighted regions; and the second attention region is determined according to the sum of all weighted regions.

[0156] When the second convolution kernel for determining the second initial region is larger, the edge of the graphic region is expanded to a higher degree, and the second initial region is generally larger. Conversely, when the second convolution kernel for determining the second initial region is smaller, the edge of the graphic region is expanded to a lower degree, and the second initial region is generally smaller. Therefore, different sizes of second initial regions can be determined by using second convolution kernels of different sizes.

[0157] Based on this, the second attention weight decreases with the increase of the corresponding second convolution kernel, and the second initial regions are weighted based on the second attention weights to obtain weighted regions, so that the attention scores of the pixel points in the larger second initial region are lower, and the attention scores of the pixel points in the smaller second initial region are higher. Adding all the weighted regions is equivalent to superimposing the attention scores of each weighted region, so that the attention scores of the internal region of the second attention region are the highest, and the attention scores of the external region present a state of decreasing from inside to outside.

[0158] Specifically, the second attention region includes a plurality of levels of peripheral regions and inner regions, and since the first attention weight is equal to the sum of all second attention weights, assuming that the first attention weight is 1, the attention score of the inner region is 1, and specifically, the second initial regions can be arranged from large to small, and the region between two adjacent second initial regions is determined as a peripheral region of a high level to a low level, so that the distance between the peripheral region of a higher level and the edge of the graphic region is larger, and the distance between the peripheral region of a lower level and the edge of the graphic region is smaller, and in the mask graph, the probability of the corrected mask boundary being located in the peripheral region of a higher level is lower, and the probability of the corrected mask boundary being located in the peripheral region of a lower level is higher, so that the attention score of the peripheral region of a higher level is lower, and the attention score of the peripheral region of a lower level is lower, which can finely reduce the optimization range of the self-adaptive matrix estimator optimizer and further reduce the mask complexity.

[0159] wherein the size of the first convolution kernel and the plurality of second convolution kernels can be determined by reinforcement learning, optimization algorithm, heuristic method, deep learning, etc., which are not limited in the embodiments of the present disclosure.

[0160] For example, referring to Figure 5 , Figure 5 An optional flowchart for determining the second attention region is provided in the embodiments of the present disclosure.

[0161] wherein the number of the second convolution kernels is 4, which are K2, K3, K4 and K5 respectively, the size of the first convolution kernel K1 is 10, the size of the second convolution kernel K2 is 30, the size of the second convolution kernel K3 is 50, the size of the second convolution kernel K4 is 70, the size of the second convolution kernel K4 is 90, and the calculation formula of the second attention region is as follows:

[0162] S2=σ2*m2+σ3*m3+σ4*m4+σ5*m5-σ1*m1

[0163] wherein S2 is the second attention region, σ1 is the first attention weight, which can be set as 1, m1 is the first initial region, σ2 is the second attention weight corresponding to the second convolution kernel K2, which can be set as 0.4, m2 is the second initial region obtained by dilating the second convolution kernel K2, σ3 is the second attention weight corresponding to the second convolution kernel K3, which can be set as 0.3, m3 is the second initial region obtained by dilating the second convolution kernel K3, σ4 is the second attention weight corresponding to the second convolution kernel K4, which can be set as 0.2, m4 is the second initial region obtained by dilating the second convolution kernel K4, σ5 is the second attention weight corresponding to the second convolution kernel K5, which can be set as 0.1, and m5 is the second initial region obtained by dilating the second convolution kernel K5.

[0164] In a third possible implementation of the determining the target attention map, the target attention map can be a result of uniform expansion or uniform contraction of the target chip layout.

[0165] When the target attention map is a result of uniform expansion of the target chip layout, the target chip layout includes a graphic region, the target chip layout is subjected to attention processing to obtain the target attention map, specifically, normal vectors corresponding to each edge in the graphic region can be determined, wherein the normal vectors point to the outside of the graphic region; a length adjustment parameter can be obtained, wherein the length adjustment parameter can be obtained by multiplying a preset adjustment ratio and the length of the shortest edge in the graphic region; for any first vertex in the graphic region, the normal vectors of two edges connected to the first vertex are summed to obtain a moving direction of the first vertex, the length adjustment parameter and an internal angle of the first vertex are input into a distance calculation formula to determine a moving distance of the first vertex, the first vertex is moved based on the moving direction and the moving distance to determine a second vertex; the second vertices are connected to obtain the target attention map. Based on this, by uniformly expanding the target chip layout, it can be ensured that each edge of the graphic region is uniformly expanded outward by the same distance, maintaining the integrity of the original shape.

[0166] When the target attention map is a result of uniform contraction of the target chip layout, the target chip layout includes a graphic region, the target chip layout is subjected to attention processing to obtain the target attention map, specifically, normal vectors corresponding to each edge in the graphic region can be determined, wherein the normal vectors point to the inside of the graphic region; a length adjustment parameter can be obtained, wherein the length adjustment parameter can be obtained by multiplying a preset adjustment ratio and the length of the shortest edge in the graphic region; for any first vertex in the graphic region, the normal vectors of two edges connected to the first vertex are summed to obtain a moving direction of the first vertex, the length adjustment parameter and an internal angle of the first vertex are input into a distance calculation formula to determine a moving distance of the first vertex, the first vertex is moved based on the moving direction and the moving distance to determine a second vertex; the second vertices are connected to obtain the target attention map. Based on this, by uniformly contracting the target chip layout, it can be ensured that each edge of the graphic region is uniformly contracted inward by the same distance, maintaining the integrity of the original shape.

[0167] Specifically, the distance calculation formula is as follows:

[0168] d′=d / sin(θ / 2)

[0169] wherein d' is the moving distance, d is the length adjustment parameter, and θ is the internal angle of the vertex.

[0170] In a possible implementation, the mask pattern is subjected to photolithography simulation to obtain a wafer pattern, specifically, a preset process parameter and the mask pattern can be input into a photolithography physical model to perform photolithography simulation, to obtain an optical intensity distribution; the optical intensity distribution is subjected to normalization processing to obtain the wafer pattern.

[0171] The photolithography physical model is a mathematical physical simulation model based on optical principles, for example, the photolithography physical model can be a Hopkins diffraction photolithography physical model of a partially coherent imaging system.

[0172] Specifically, referring to Figure 6 , Figure 6 An optional flowchart for determining a wafer pattern is provided in the embodiments of the present disclosure. A selected process parameter (such as a standard process parameter) and a mask pattern are input into a photolithography physical model, and the photolithography physical model generates an optical intensity distribution I corresponding to the process parameter and the mask pattern M. Since the photolithography physical model can be decomposed into a sum of coherent optical systems by singular value decomposition, the light source and the optical projection process can be represented by a series of coherent optical kernels, and therefore the optical intensity distribution I can be obtained by convolution of the mask pattern M and the series of coherent optical kernels h. An optional calculation formula of the optical intensity distribution I is as follows:

[0173]

[0174] wherein I(x, y; h μ ) is the optical intensity distribution, M(x, y) is a pixel value of a pixel point at coordinates (x, y) in the mask pattern M, (x, y) is used to indicate a pixel point in the mask pattern, x is the horizontal coordinate of the pixel point, y is the vertical coordinate of the pixel point, the process parameter includes a defocus parameter h μ , h k (x, y; h μ ) is a coherent optical kernel with defocus h μ obtained by singular value decomposition of the photolithography physical model, ω k (h μ ) is a weight corresponding to the coherent optical kernel h k (x, y; h μ ), is a convolution operation, and K is the total number of coherent optical kernels, for example, K can take a value of 24, which means that the photolithography physical model is decomposed into a sum of 24 coherent optical systems by singular value decomposition.

[0175] Then, since the wafer pattern is a binary image, the wafer pattern is also a binary matrix, and a binary constraint condition is usually relaxed by a sigmoid function to make a discrete variable become a continuous value. Therefore, the wafer pattern can be obtained by normalization processing of the optical intensity distribution I by the sigmoid function, which can improve the simulation effect of the wafer pattern. An optional calculation formula of the wafer pattern is as follows:

[0176]

[0177] wherein Z(x, y; h μ , t q ) is the wafer pattern, I(x, y; h μ ) is the light intensity distribution, the process parameters include defocus parameter h μ and exposure dose deviation parameter t q , sig(I(x, y; h μ )) is the normalization processing of the light intensity distribution I by sigmod function, θ Z is a hyperparameter for controlling the steepness of the sigmoid function, for example, θ Z may be set to 50, I th is a hyperparameter, for example, I th may be set to 0.225, and exp is an exponential function with natural number e as the base.

[0178] In a possible implementation, the process parameters include a defocus parameter and an exposure dose deviation parameter, the target loss is determined according to the difference between the target chip layout and the wafer pattern, specifically, the target perimeter can be determined according to the length of the graphic boundary of the target chip layout, the initial error is determined according to the difference between the target chip layout and the wafer pattern, and the imaging error is determined according to the ratio of the initial error to the target perimeter; the first distribution function is constructed according to the defocus parameter, the defocus sampling points are obtained by sampling the defocus parameter, and the first adjustment factor is obtained by inputting the defocus sampling points into the first distribution function; the second distribution function is constructed according to the exposure dose deviation parameter, the exposure dose deviation sampling points are obtained by sampling the exposure dose deviation parameter, and the second adjustment factor is obtained by inputting the exposure dose deviation sampling points into the second distribution function; and the imaging error is adjusted based on the first adjustment factor and the second adjustment factor to obtain the target loss.

[0179] wherein the length of the graphic boundary is the perimeter of the graphic, and assuming that the target chip layout includes multiple graphics, the target perimeter is the sum of the lengths of the graphic boundaries of all the graphics.

[0180] Based on this, since the initial error is determined according to the difference between the target chip layout and the wafer pattern, the dimension of the initial error is an area unit, and since the imaging error is the ratio of the initial error to the target perimeter, the dimension of the imaging error is a length unit, so that the dimension of the imaging error is consistent with the dimension of the chip node size, which can improve the accuracy of the imaging error, the chip node size refers to the size of the transistor gate circuit on the surface of the chip, such as 14 nm, 10 nm, 7 nm, 5 nm, etc.; the target loss is obtained by adjusting the imaging error through the first adjustment factor determined by the defocus sampling points and the second adjustment factor determined by the exposure dose deviation sampling points, which can improve the accuracy of the target loss.

[0181] Specifically, one optional calculation formula of the imaging error is as follows:

[0182]

[0183] wherein, L Aerial is the imaging error, Z(x, y; h μ , t q ) is the wafer pattern, Z t (x, y) is the target chip layout, γ is an adjustable parameter, for example, γ can be set as 2, L is the target perimeter, (x, y) is a pixel point with x as the horizontal coordinate and y as the vertical coordinate, the wafer pattern and the target chip layout have the same size, and N is the width and length of the target chip layout.

[0184] Specifically, one optional calculation formula of the target loss is as follows:

[0185]

[0186] wherein, L LS is the target loss, L Aerial is the imaging error, ξ(h μ ) is a first distribution function, h μ is a defocus sampling point, σ h is a spread of the first distribution function, and U is the length of the array h μ , for example, U can be set as 3, h μ is respectively set as [-80nm, 0nm, 80nm], and all the function values of ξ(h μ ) are first adjustment factors, ζ(t q ) is a second distribution function, t q is an exposure dose deviation sampling point, σ q is a spread of the second distribution function, exp is an exponential function with the natural number e as the base number, and Q is the length of the array t q , for example, Q can be set as 3, t q is respectively set as [-0.1, 0, 0.1], and all the function values of ζ(t q ) are second adjustment factors, and multiplying ξ(h μ ), ζ(t q ) and L Aerial is equivalent to adjusting the imaging error based on the first adjustment factors and the second adjustment factors. In addition, if the process parameter variation is not considered, h μ can be set as 0nm, and t q can be set as 0%.

[0187] In a possible implementation, the gradient of the target loss is determined according to the level set function, and specifically, the gradient of the imaging error can be determined according to the mask map; the gradient of the target loss is determined according to the first adjustment factor, the second adjustment factor, the gradient of the imaging error, and the gradient of the level set function; and the penalty term is determined according to the level set function, and the gradient of the target loss is adjusted based on the penalty term.

[0188] Specifically, the gradient of the imaging error determined according to the mask map is specifically a gradient of the imaging error with respect to the mask map, for example, assuming that the imaging error is L Aerial , and the mask map is M, the gradient of the imaging error is

[0189] In order to control the smoothness of the mask map and eliminate noise points, a penalty function is introduced, and the calculation formula of the penalty function is as follows:

[0190]

[0191] Wherein, R TV is the penalty function, ψ is the level set function, x is the horizontal coordinate of the pixel point, y is the vertical coordinate of the pixel point, and the velocity expression of the boundary of the penalty function is as follows:

[0192]

[0193] Wherein, κ is the penalty term, R TV is the penalty function, is used to calculate the divergence of R TV , is the gradient of the level set function, is the modulus of the gradient of the level set function, is the normalized gradient vector, is used to calculate the divergence of .

[0194] Therefore, the penalty term κ is used to represent the bending degree of the curve of the level set function, and the penalty term κ is equivalent to the curvature term. The penalty term κ controls and adjusts the curve shape of the level set function in the optimization process, so as to ensure that the generated mask boundary is smooth and has no noise, and the smoothness of the mask map can be controlled and the noise points can be eliminated.

[0195] Specifically, the final calculation formula of the gradient of the target loss is as follows:

[0196]

[0197] Wherein, g is the gradient of the target loss, L LS is the target loss, ψ is the level set function, ξ(h μ ) is the first distribution function, h μ is the defocus sampling point, and U is the array hμ the length of array h μ , all the function values of ξ(h q ) are first adjustment factors, ζ(t q ) is a second distribution function, t q is an exposure dose bias sampling point, Q is the length of array t q , all the function values of ζ(t t ) are second adjustment factors, is the gradient of the imaging error mentioned above, is the modulus of the gradient of the level set function, is the penalty term mentioned above, λ is an adjustable parameter, for example, λ can be set to 0.01.

[0198] The calculation process of the gradient of the target loss is described in detail below.

[0199] First, the gradient of the imaging error is calculated, and the calculation formula of the gradient of the imaging error is as follows:

[0200]

[0201] wherein, is the gradient of the imaging error, L is the target perimeter, γ is an adjustable parameter, Z is a wafer pattern, Z t is a target chip layout, M is a mask pattern, θ Z is a preset constant, H is a series of coherent optical kernels of a photolithography physical model, H flip is obtained by turning H by 180°, H * is the complex conjugate of H, and is a matrix point multiplication operation, is a matrix convolution operation.

[0202] Then, the evolution speed of the mask boundary is calculated, and the calculation formula of the evolution speed of the mask boundary is as follows:

[0203]

[0204] wherein, ve is the evolution speed of the mask boundary, ξ(h μ ) is a first distribution function, h μ is a defocus sampling point, U is the length of array h μ , all the function values of ξ(h μ ) are first adjustment factors, ζ(t q ) is a second distribution function, t a is an exposure dose bias sampling point, Q is the length of array t q , all the function values of ζ(t q ) are second adjustment factors, is the gradient of the imaging error.

[0205] Then, the gradient of the target loss is preliminarily determined as:

[0206] Then, the gradient of the target loss about the mask map is adjusted based on the penalty term, and the gradient of the target loss is finally determined as:

[0207] In a possible implementation, the gradient of the target loss is input into a conjugate gradient optimizer to obtain a first optimization term, and the gradient of the target loss is input into an adaptive moment estimation optimizer to obtain a second optimization term. Specifically, the gradient of the target loss can be input into the conjugate gradient optimizer to obtain a first optimization direction; the gradient of the target loss can be input into the adaptive moment estimation optimizer to obtain a second optimization direction; a first optimization step can be determined based on the first optimization direction and a preset step factor, and a first optimization term can be obtained according to a product of the first optimization direction and the first optimization step; a second optimization step can be determined based on the second optimization direction and the step factor, and a second optimization term can be obtained according to a product of the second optimization direction and the second optimization step.

[0208] The step factor can be a fixed hyperparameter, and the step factor is greater than 0. For example, the step factor can be set as 0.26. The step factor can also be a changeable parameter. For example, the step factor can be optimized by an optimization algorithm while the mask map is updated, so as to further reduce the pattern error.

[0209] The first optimization direction refers to a direction in which a parameter is updated when the conjugate gradient optimizer is used for optimization, and the level set function can be quickly and effectively optimized when the parameter is updated along the first optimization direction. The first optimization step is used to represent the amplitude of the parameter update. The second optimization direction refers to a direction in which a parameter is updated when the adaptive moment estimation optimizer is used for optimization, and the level set function can be quickly and effectively optimized when the parameter is updated along the first optimization direction. The second optimization step is used to represent the amplitude of the parameter update.

[0210] Therefore, the first optimization direction is determined by the conjugate gradient optimizer, and then the first optimization step is determined by the first optimization direction and the step factor. Further, the first optimization term is obtained by the product of the first optimization direction and the first optimization step, so that the first optimization term is optimal in the update direction and the update amplitude of the parameter of the level set function, and the simplicity and manufacturability of the mask map can be maintained. The second optimization direction is determined by the adaptive moment estimation optimizer, and then the second optimization step is determined by the second optimization direction and the step factor. Further, the second optimization term is obtained by the product of the second optimization direction and the second optimization step, so that the second optimization term is optimal in the update direction and the update amplitude of the parameter of the level set function, and the pattern error of the mask map can be effectively reduced.

[0211] Specifically, the calculation formula of the first optimization direction is as follows:

[0212]

[0213] where k is the current iteration number, V k is the first optimization direction at the kth optimization, V k-1 is the first optimization direction at the (k-1)th optimization, g k is the gradient of the target loss at the kth optimization, η k is the conjugate gradient update parameter at the kth optimization; at the first optimization, i.e., k = 0, the first optimization direction is the same as the gradient of the target loss.

[0214] η k is calculated as follows:

[0215]

[0216] where g k-1 is the gradient of the target loss at the (k-1)th optimization, ||g k || 2 is the square of the two-norm of g k , ||g k-1 || 2 is the square of the two-norm of g k-1 .

[0217] The first optimization step is calculated as follows:

[0218]

[0219] where ω c，k is the first optimization step at the kth optimization, ε is the step factor, V k is the first optimization direction at the kth optimization, |V k | is the modulus of V k , and max(|V k |) is used to determine the maximum value of |V k |.

[0220] The second optimization direction is calculated as follows:

[0221]

[0222] where P k is the second optimization step at the kth optimization, ∈ is an adjustable parameter, for example, ∈ can be set to 1 × 10 -8 , is the bias-corrected first moment of momentum at the kth optimization, is the bias-corrected second moment of momentum at the kth optimization.

[0223] The calculation formula of m

[0224]

[0225] wherein m k is the momentum first moment at the kth optimization, β1 is an adjustable parameter, for example, β1 can be set as 0.9, β1 k is the kth power of β1; at the first optimization, that is, k = 0, the momentum first moment is taken as 0.

[0226] m k The calculation formula of m

[0227] m k = β1m k-1 + (1-β1)g k

[0228] wherein m k-1 is the momentum first moment at the k-1th optimization, g k is the gradient of the target loss at the kth optimization.

[0229] The calculation formula of s

[0230]

[0231] wherein s k is the momentum second moment at the kth optimization, β2 is an adjustable parameter, for example, β2 can be set as 0.999, β2 k is the kth power of β2; at the first optimization, that is, k = 0, the momentum second moment is taken as 0.

[0232] s k The calculation formula of s

[0233] s k = β2s k-1 + (1-β2)g k 2

[0234] wherein s k-1 is the momentum second moment at the k-1th optimization, g k 2 is the square of the gradient of the target loss at the kth optimization.

[0235] The calculation formula of the second optimization step length is as follows:

[0236]

[0237] wherein ω n，k is the second optimization step length at the kth optimization, ε is a step length factor, P k|P k | is the modulus of P k , max(|P k |) is used to determine the maximum value of |P k |.

[0238] On this basis, when the first optimization term and the adjusted second optimization term are weighted and summed based on the first weight and the second weight to obtain the parameter update amount, the update formula of the level set function is as follows:

[0239] ψ k+1 = ψ k + (1-w)ω c，k V k +wω n，k P k S

[0240] Wherein, ψ k+1 is the level set function after the k+1 optimization, ψ k is the level set function after the k optimization, (1-w) is the first weight, w is the second weight, ω c，k is the first optimization step size at the k optimization, V k is the first optimization direction at the k optimization, ω c，k V k is the first optimization term, ω n，k is the second optimization step size at the k optimization, P k is the second optimization direction at the k optimization, ω n，k P k is the second optimization term, S is the target attention map, ω n，k P k S is the adjusted second optimization term, (1-w)ω c，k V k +wω n，k P k S is the parameter update amount.

[0241] Then determine the mask map based on the zero level set of the level set function, and the determination formula of the mask map is as follows:

[0242]

[0243] Wherein, M(x, y) is the pixel value of the pixel point where the coordinate (x, y) in the mask graph M is located, (x, y) is used to indicate the pixel point in the mask graph, x is the horizontal coordinate of the pixel point, y is the vertical coordinate of the pixel point, and ψ(x, y) is a level set function. It can be seen that in the mask graph, when the level set function ψ(x, y) is less than or equal to 0, the pixel value of the pixel point (x, y) is 1, that is, the pixel value of the pixel point located on or in the mask boundary is 1, and when the level set function ψ(x, y) is greater than 0, the pixel value of the pixel point (x, y) is 0, that is, the pixel value of the pixel point located outside the mask boundary is 0.

[0244] In a possible implementation, the method for updating the photomask further includes:

[0245] obtaining the current iteration number, if the current iteration number is less than the preset number threshold, updating the level set function again based on the target chip layout and the updated mask graph, updating the mask graph again based on the updated level set function, and updating the current iteration number until the current iteration number is greater than or equal to the number threshold;

[0246] Or, if the imaging error determined based on the target chip layout and the wafer pattern is greater than the preset error threshold, the level set function is updated again based on the target chip layout and the updated mask graph, the mask graph is updated again based on the updated level set function, and the imaging error is less than or equal to the error threshold.

[0247] Based on this, when updating the level set function and the mask graph, the stop optimization condition needs to be set in advance, and the level set function and the mask graph are not updated when the stop optimization condition is met, which is equivalent to stopping optimization when the stop optimization condition is met. The first stop optimization condition is that the current iteration number is greater than or equal to the number threshold, that is, the current iteration number reaches the number threshold, and the number threshold is usually set to a large value, which can ensure that the pattern error of the mask graph is low and improve the correction accuracy of the mask graph. The second stop optimization condition is that the imaging error is less than or equal to the error threshold, that is, the imaging error is reduced to the expected value, and the error threshold is usually set to a small value, which can ensure that the pattern error of the mask graph is low and improve the correction accuracy of the mask graph.

[0248] Specifically, optimization can be stopped only when the first stop optimization condition is met, optimization can be stopped only when the second stop optimization condition is met, or optimization can be stopped when any one of the first stop optimization condition and the second stop optimization condition is met. In addition to the above stop optimization conditions, other stop optimization conditions can also be set, which are not limited in the embodiments of the present disclosure.

[0249] The complete process of the method for updating the photomask is described in detail below.

[0250] Firstly, a target chip layout is acquired, a mask graph of the target chip layout is constructed, and a level set function is constructed based on a mask boundary of the mask graph.

[0251] Then, preset process parameters and the mask graph are input into a lithography physical model for lithography simulation to obtain a light intensity distribution, wherein the process parameters include a defocus parameter and an exposure dose deviation parameter.

[0252] Then, the light intensity distribution is normalized to obtain a wafer pattern.

[0253] Then, a target perimeter is determined according to a length of a graphic boundary of the target chip layout, an initial error is determined according to a difference between the target chip layout and the wafer pattern, and an imaging error is determined according to a ratio of the initial error to the target perimeter.

[0254] Then, a first distribution function is constructed according to the defocus parameter, a defocus sampling point is obtained by sampling the defocus parameter, and a first adjustment factor is obtained by inputting the defocus sampling point into the first distribution function.

[0255] Then, a second distribution function is constructed according to the exposure dose deviation parameter, an exposure dose deviation sampling point is obtained by sampling the exposure dose deviation parameter, and a second adjustment factor is obtained by inputting the exposure dose deviation sampling point into the second distribution function.

[0256] Then, the imaging error is adjusted based on the first adjustment factor and the second adjustment factor to obtain a target loss.

[0257] Then, a gradient of the imaging error is determined according to the mask graph.

[0258] Then, a gradient of the target loss is determined according to the first adjustment factor, the second adjustment factor, the gradient of the imaging error, and a gradient of the level set function.

[0259] Then, a penalty term is determined according to the level set function, and the gradient of the target loss is adjusted based on the penalty term.

[0260] Then, the gradient of the target loss is input into a conjugate gradient optimizer to obtain a first optimization direction.

[0261] Then, the gradient of the target loss is input into an adaptive moment estimation optimizer to obtain a second optimization direction.

[0262] Then, a first optimization step is determined based on the first optimization direction and a preset step factor, and a first optimization term is obtained according to a product of the first optimization direction and the first optimization step.

[0263] Then, a second optimization step is determined based on the second optimization direction and the step factor, and a second optimization term is obtained according to a product of the second optimization direction and the second optimization step.

[0264] Then, a target scaling ratio is obtained. In the target chip layout, the graphic region is scaled isometrically based on the target scaling ratio to obtain a target attention region, and a target attention map is determined according to the target attention region. Alternatively, the graphic region is subjected to attention processing to obtain a first attention region and a second attention region in the target chip layout, wherein the first attention region is located within the graphic region, and the second attention region is located outside the graphic region. In the target chip layout, the target attention map is determined according to a difference between the second attention region and the first attention region.

[0265] Then, the second optimization term is adjusted based on the target attention map.

[0266] Then, a current iteration number is obtained, a first weight corresponding to the first optimization term and a second weight corresponding to the second optimization term are determined based on the current iteration number, wherein the first weight increases with an increase of the current iteration number, and the second weight decreases with an increase of the current iteration number.

[0267] Then, the first optimization term and the adjusted second optimization term are weighted and summed based on the first weight and the second weight to obtain a parameter update amount.

[0268] Then, the level set function is updated based on the parameter update amount.

[0269] Then, the mask map is updated based on the updated level set function.

[0270] Then, a current iteration number is obtained, and if the current iteration number is less than a preset number threshold, the level set function is updated again based on the target chip layout and the updated mask map, the mask map is updated again based on the updated level set function, and the current iteration number is updated until the current iteration number is greater than or equal to the number threshold; or if an imaging error determined based on the target chip layout and the wafer pattern is greater than a preset error threshold, the level set function is updated again based on the target chip layout and the updated mask map, and the mask map is updated again based on the updated level set function until the imaging error is less than or equal to the error threshold.

[0271] Based on this, by constructing a mask graph of the target chip layout, then constructing a level set function through the mask boundary of the mask graph, and performing photolithography simulation on the mask graph to obtain a wafer pattern, and then determining a target loss through the difference between the wafer pattern and the target chip layout, then processing the gradient of the target loss through a conjugate gradient optimizer to obtain a first optimization item, and processing the gradient of the target loss through an adaptive moment estimation optimizer to obtain a second optimization item, then adjusting the second optimization item using the target attention map obtained through attention processing, and then updating the level set function through the first optimization item and the adjusted second optimization item, that is, optimizing the mask graph using the conjugate gradient optimizer and the adaptive moment estimation optimizer, the conjugate gradient optimizer can control the complexity of the mask graph, and at the same time, the target attention map is used to limit the optimization range of the adaptive moment estimation optimizer, so that the adaptive moment estimation optimizer can reduce the pattern error of the mask graph on the premise of ensuring the manufacturability of the mask graph. Therefore, by combining the low mask complexity of the conjugate gradient optimizer and the strong optimization ability of the adaptive moment estimation optimizer, the pattern error of the mask graph can be effectively reduced while reducing the complexity of the mask graph, thereby improving the correction accuracy of the mask graph.

[0272] It can be seen that the photomask updating method provided by the embodiments of the present disclosure can be applied to various scenes.

[0273] For example, in the chip manufacturing scene, the photomask updating method is loaded on an electronic design automation (EDA) computing platform, which can be deployed on a cloud server or a local server. The chip enterprise inputs the target chip layout into the EDA computing platform, and the EDA computing platform can determine a high-quality photomask by calling the photomask updating method provided by the embodiments of the present disclosure, thereby reducing the computing time and cost of the chip enterprise to generate the photomask.

[0274] For another example, in the teaching scene, the photomask updating method is applied to a simulation system, which can improve the correction accuracy of the simulation result of the mask graph, and is helpful for researching and developing new photolithography technology.

[0275] The following describes various evaluation results of the photomask updating method provided by the present disclosure in detail.

[0276] Specifically, the first evaluation result is the measurement result of the pattern error, which is described with reference to Figure 7 , Figure 7 is an optional evaluation schematic diagram of the pattern error provided by the embodiments of the present disclosure.

[0277] The horizontal coordinate is the index of the measurement point, each index is used to indicate the corresponding measurement point, the vertical coordinate is the graphic error, the unit of the graphic error is nanometer, the dotted line is the graphic error of the optimization mode using the conjugate gradient optimizer, and the solid line is the graphic error of the optimization mode of the disclosure. It can be seen that, compared with the optimization mode using the conjugate gradient optimizer, the graphic error of the mask graph updated by the photomask updating method provided by the disclosure is generally lower, thereby improving the correction accuracy of the mask graph.

[0278] Specifically, the second evaluation result is the calculation result of the total variation term, and the total variation term is generally used to characterize the complexity of the mask graph. The calculation formula of the total variation term is as follows:

[0279]

[0280] Wherein, R TV is the total variation term, L is the target perimeter, f = |M-Z t |, M is the mask graph, Z t is the target chip layout, x is the horizontal coordinate of the pixel point, y is the horizontal coordinate of the pixel point, is the partial derivative of f with respect to x, is the norm of , D is the matrix first derivative, D is the first derivative of the target chip layout, is the partial derivative of f with respect to y, is the norm of , D is the matrix first derivative, D is the first derivative of the target chip layout, is the matrix multiplication operation, is the norm of , D T is the transpose result of D, is the norm of , so the average total variation of the plurality of optimization modes can be determined by the calculation formula of the total variation term, and the evaluation results of the plurality of optimization modes are shown in Table 1:

[0281] Optimization mode Average graph error (nm) Average total variation Using a conjugate gradient optimizer 0.654 1.595 Using an adaptive moment estimation optimizer 0.395 20.961 Using an Adamax optimizer 0.406 58.769 Using an NAdam optimizer 0.397 31.089 The present disclosure 0.608 1.626

[0282] It can be seen that, compared with the optimization mode using the conjugate gradient optimizer, the average graphic error of the mask graph updated by the photomask updating method provided by the disclosure is lower, which can improve the correction accuracy of the mask graph; and compared with the optimization mode using the adaptive moment estimation optimizer, the Adamax optimizer or the NAdam optimizer, the complexity of the mask graph updated by the photomask updating method provided by the disclosure is greatly reduced, which can ensure the manufacturability of the mask graph.

[0283] The chip layout used in the evaluation process can come from a public dataset, and the chip layout is generated based on certain design rules and can meet the 32nm process node.

[0284] It can be understood that, although each step in each of the above flowcharts is displayed in sequence according to the direction of the arrow, these steps are not necessarily executed in the order indicated by the arrow. Unless otherwise specified in the present embodiment, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least part of the steps in the above flowcharts can include multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least part of other steps or steps or stages in other steps.

[0285] Reference Figure 8 , Figure 8 An optional structure schematic diagram of the photolithography mask updating device provided by the embodiment of the present disclosure is provided, and the photolithography mask updating device 800 includes:

[0286] The simulation module 801 is configured to obtain a target chip layout, construct a mask graph of the target chip layout, construct a level set function based on a mask boundary of the mask graph, and perform photolithography simulation on the mask graph to obtain a wafer pattern.

[0287] The processing module 802 is configured to determine a target loss according to a difference between the target chip layout and the wafer pattern, determine a gradient of the target loss according to the level set function, input the gradient of the target loss into a conjugate gradient optimizer to obtain a first optimization item, and input the gradient of the target loss into a self-adaptive matrix estimation optimizer to obtain a second optimization item.

[0288] The adjustment module 803 is configured to perform attention processing on the target chip layout to obtain a target attention graph, and adjust the second optimization item based on the target attention graph.

[0289] The updating module 804 is configured to update the level set function based on the first optimization item and the adjusted second optimization item, and update the mask graph based on the updated level set function.

[0290] Further, the updating module 804 is specifically configured to:

[0291] Weighted sum the first optimization item and the adjusted second optimization item to obtain a parameter update amount;

[0292] Update the level set function based on the parameter update amount.

[0293] Further, the update module 804 is specifically configured to:

[0294] obtain a current iteration number, determine a first weight corresponding to the first optimization item and a second weight corresponding to the second optimization item based on the current iteration number, wherein the first weight increases with an increase of the current iteration number, and the second weight decreases with an increase of the current iteration number;

[0295] perform weighted summation on the first optimization item and the adjusted second optimization item based on the first weight and the second weight to obtain the parameter update amount.

[0296] Further, the target chip layout includes a graphic region, and the adjustment module 803 is specifically configured to:

[0297] obtain a target scaling ratio;

[0298] perform equal-ratio scaling on the graphic region based on the target scaling ratio to obtain a target attention region in the target chip layout, and determine a target attention map according to the target attention region.

[0299] Further, the target chip layout includes a graphic region, and the adjustment module 803 is specifically configured to:

[0300] perform attention processing on the graphic region to obtain a first attention region and a second attention region in the target chip layout, wherein the first attention region is located within the graphic region, and the second attention region is located outside the graphic region;

[0301] determine the target attention map according to a difference between the second attention region and the first attention region in the target chip layout.

[0302] Further, the adjustment module 803 is specifically configured to:

[0303] obtain a first scaling ratio and a second scaling ratio, wherein the first scaling ratio is less than a preset ratio, and the second scaling ratio is greater than the preset ratio;

[0304] perform equal-ratio scaling on the graphic region based on the first scaling ratio to obtain the first attention region in the target chip layout, and perform equal-ratio scaling on the graphic region based on the second scaling ratio to obtain the second attention region in the target chip layout.

[0305] Further, the adjustment module 803 is specifically configured to:

[0306] perform erosion on the graphic region based on a preset first convolution kernel to obtain a first initial region in the target chip layout, and perform inflation on the graphic region based on a preset second convolution kernel to obtain a second initial region in the target chip layout.

[0307] obtain a first attention weight of the first initial region and a second attention weight corresponding to the second initial region;

[0308] weight the first initial region based on the first attention weight to obtain a first attention region, and weight the second initial region based on the second attention weight to obtain a second attention region.

[0309] Further, the number of the second initial regions is multiple, any two second initial regions are determined based on second convolution kernels of different sizes, the second attention weights corresponding to any two second initial regions are not the same, the second attention weight decreases with the increase of the corresponding second convolution kernel, the first attention weight is equal to the sum of all second attention weights, and the adjustment module 803 is specifically configured to:

[0310] weight the respective second initial region based on the respective second attention weight to obtain a plurality of weighted regions;

[0311] determine the second attention region according to the sum of all weighted regions.

[0312] Further, the simulation module 801 is specifically configured to:

[0313] input the preset process parameters and mask pattern into a photolithography physical model to perform photolithography simulation and obtain light intensity distribution;

[0314] perform normalization processing on the light intensity distribution to obtain a wafer pattern.

[0315] Further, the process parameters include defocus parameters and exposure dose deviation parameters, and the processing module 802 is specifically configured to:

[0316] determine a target perimeter according to the length of the graphic boundary of the target chip layout, determine an initial error according to the difference between the target chip layout and the wafer pattern, and determine an imaging error according to the ratio of the initial error to the target perimeter;

[0317] construct a first distribution function according to the defocus parameters, sample the defocus parameters to obtain defocus sampling points, and input the defocus sampling points into the first distribution function to obtain a first adjustment factor;

[0318] construct a second distribution function according to the exposure dose deviation parameters, sample the exposure dose deviation parameters to obtain exposure dose deviation sampling points, and input the exposure dose deviation sampling points into the second distribution function to obtain a second adjustment factor;

[0319] adjust the imaging error based on the first adjustment factor and the second adjustment factor to obtain a target loss.

[0320] Further, the processing module 802 is specifically configured to:

[0321] determine a gradient of the imaging error according to the mask pattern;

[0322] determine a gradient of the target loss according to the first adjustment factor, the second adjustment factor, the gradient of the imaging error and the gradient of the level set function;

[0323] determine a penalty term according to the level set function, and adjust the gradient of the target loss based on the penalty term.

[0324] Further, the processing module 802 is specifically configured to:

[0325] input the gradient of the target loss into a conjugate gradient optimizer to obtain a first optimization direction;

[0326] input the gradient of the target loss into a self-adaptive matrix estimation optimizer to obtain a second optimization direction;

[0327] determine a first optimization step based on the first optimization direction and a preset step factor, and obtain a first optimization term according to a product of the first optimization direction and the first optimization step;

[0328] determine a second optimization step based on the second optimization direction and the step factor, and obtain a second optimization term according to a product of the second optimization direction and the second optimization step.

[0329] Further, the updating device of the photolithography mask further comprises an optimization module (not shown in the figure), and the optimization module is specifically configured to:

[0330] obtain a current iteration number, and if the current iteration number is less than a preset number threshold, update the level set function again based on the target chip layout and the updated mask pattern, update the mask pattern again based on the updated level set function, and update the current iteration number until the current iteration number is greater than or equal to the number threshold;

[0331] Alternatively, if the imaging error determined based on the target chip layout and the wafer pattern is greater than a preset error threshold, the level set function is updated again based on the target chip layout and the updated mask pattern, the mask pattern is updated again based on the updated level set function until the imaging error is less than or equal to the error threshold.

[0332] The updating device 800 of the photolithography mask and the updating method of the photolithography mask are based on the same inventive concept. By constructing a mask graph of a target chip layout, then constructing a level set function through the mask boundary of the mask graph, and performing photolithography simulation on the mask graph to obtain a wafer pattern, the difference between the wafer pattern and the target chip layout is determined to obtain a target loss, then the gradient of the target loss is processed by a conjugate gradient optimizer to obtain a first optimization item, and the gradient of the target loss is processed by an adaptive moment estimation optimizer to obtain a second optimization item, then the target attention map obtained by attention processing is used to adjust the second optimization item, and then the first optimization item and the adjusted second optimization item are used to update the level set function, that is, to optimize the mask boundary, and then the updated mask graph is determined. It is equivalent to optimizing the mask graph by using the conjugate gradient optimizer and the adaptive moment estimation optimizer. The conjugate gradient optimizer can control the complexity of the mask graph, and at the same time, the target attention map is used to limit the optimization range of the adaptive moment estimation optimizer, so that the adaptive moment estimation optimizer can reduce the pattern error of the mask graph while ensuring the manufacturability of the mask graph. Therefore, by combining the low mask complexity of the conjugate gradient optimizer and the strong optimization capability of the adaptive moment estimation optimizer, the mask complexity can be reduced while effectively reducing the pattern error of the mask graph, thereby improving the correction accuracy of the mask graph.

[0333] The electronic device provided by the embodiments of the present disclosure for executing the above photolithography mask updating method can be a terminal. For reference Figure 9 , Figure 9 A partial structural block diagram of the terminal provided by the embodiments of the present disclosure is shown in FIG. 9. The terminal includes a camera assembly 910, a first memory 920, an input unit 930, a display unit 940, a sensor 950, an audio circuit 960, a wireless fidelity (WiFi) module 970, a first processor 980, and a first power supply 990, and the like. Those skilled in the art can understand that Figure 9 The terminal structure shown in the figure does not constitute a limitation on the terminal, and can include more or fewer components than shown, or combine certain components, or different component arrangements.

[0334] The camera assembly 910 can be used to capture images or videos. Optionally, the camera assembly 910 includes a front camera and a rear camera. Typically, the front camera is disposed on the front panel of the terminal, and the rear camera is disposed on the back of the terminal. In some embodiments, the rear camera is at least two, which are any one of a main camera, a depth-of-field camera, a wide-angle camera, and a long-focus camera, to realize the background blur function of the main camera and the depth-of-field camera, the panorama shooting and VR (Virtual Reality) shooting function of the main camera and the wide-angle camera, or other fusion shooting functions.

[0335] The first memory 920 can be used to store software programs and modules, and the first processor 980 can execute various function applications and data processing of the terminal by running the software programs and modules stored in the first memory 920.

[0336] The input unit 930 can be used to receive inputted digital or character information, and to generate key signal input related to the setting and function control of the terminal. Specifically, the input unit 930 can include a touch panel 931 and other input devices 932.

[0337] The display unit 940 can be used to display inputted information or provided information and various menus of the terminal. The display unit 940 can include a display panel 941.

[0338] The audio circuit 960, the speaker 961, and the microphone 962 can provide an audio interface.

[0339] The first power supply 990 can be an alternating current, a direct current, a disposable battery, or a rechargeable battery.

[0340] The number of the sensor 950 can be one or more, and the one or more sensors 950 can include, but are not limited to, an acceleration sensor, a gyroscope sensor, a pressure sensor, an optical sensor, and the like. Among them:

[0341] The acceleration sensor can detect the acceleration magnitude in three coordinate axes of the coordinate system established by the terminal. For example, the acceleration sensor can be used to detect the components of the gravitational acceleration in three coordinate axes. The first processor 980 can control the display unit 940 to display the user interface in a landscape view or a portrait view according to the gravitational acceleration signal collected by the acceleration sensor. The acceleration sensor can also be used for game or user motion data collection.

[0342] The gyroscope sensor can detect the body direction and rotation angle of the terminal, and the gyroscope sensor can collect 3D actions of the user on the terminal in cooperation with the acceleration sensor. The first processor 980 can realize the following functions according to the data collected by the gyroscope sensor: motion sensing (such as changing the UI according to the user's tilt operation), image stabilization when shooting, game control, and inertial navigation.

[0343] The pressure sensor can be disposed at a side bezel of the terminal and / or a lower layer of the display unit 940. When the pressure sensor is disposed at the side bezel of the terminal, a grip signal of a user on the terminal can be detected, and left / right hand recognition or a shortcut operation can be performed by the first processor 980 according to the grip signal collected by the pressure sensor. When the pressure sensor is disposed at the lower layer of the display unit 940, a pressure operation of a user on the display unit 940 can be detected by the first processor 980, and a control of an operability control on a UI screen can be performed according to the pressure operation. The operability control includes at least one of a button control, a scroll bar control, an icon control, and a menu control.

[0344] The optical sensor is used to collect an ambient light intensity. In an embodiment, the first processor 980 can control a display brightness of the display unit 940 according to the ambient light intensity collected by the optical sensor. Specifically, when the ambient light intensity is high, the display brightness of the display unit 940 can be increased, and when the ambient light intensity is low, the display brightness of the display unit 940 can be decreased. In another embodiment, the first processor 980 can also dynamically adjust a photographing parameter of the camera assembly 910 according to the ambient light intensity collected by the optical sensor.

[0345] In the embodiment, the first processor 980 included in the terminal can perform the method for updating the photomask of the foregoing embodiment.

[0346] The electronic device for performing the method for updating the photomask provided by the embodiments of the present disclosure can also be a server, and the server is described in detail with reference to Figure 10 , Figure 10 The server provided by the embodiments of the present disclosure can have a large difference due to different configurations or performances, and can include one or more second processors 1010 and a second memory 1030, and one or more storage media 1040 (for example, one or more mass storage devices) storing application programs 1043 or data 1042. The second memory 1030 and the storage medium 1040 can be temporary storage or persistent storage. The programs stored in the storage medium 1040 can include one or more modules (not shown in the figure), and each module can include a series of instruction operations in the server. Furthermore, the second processor 1010 can be configured to communicate with the storage medium 1040 and execute the series of instruction operations in the storage medium 1040 on the server.

[0347] The server can also include one or more second power supplies 1020, one or more wired or wireless network interfaces 1050, one or more input / output interfaces 1060, and / or one or more operating systems 1041, such as Windows ServerTM, Mac OS XTM, UnixTM, LinuxTM, FreeBSDTM, etc.

[0348] The second processor 1010 in the server can be configured to execute the method for updating a photomask.

[0349] The embodiments of the present disclosure further provide a computer readable storage medium for storing a computer program, the computer program being configured to execute the method for updating a photomask of the foregoing embodiments.

[0350] The embodiments of the present disclosure further provide a computer program product, which comprises a computer program stored in a computer readable storage medium. A processor of a computer device reads the computer program from the computer readable storage medium, and executes the computer program, so that the computer device executes the method for updating a photomask as described above.

[0351] The terms "first", "second", "third", "fourth" and the like used in the description of the present disclosure and the above drawings, if any, are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "comprise" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0352] It should be understood that in the present disclosure, "at least one" means one or more, and "multiple" means two or more. "And / or" is used to describe the association relationship of the associated objects, which means that there can be three relationships, for example, "A and / or B" can mean that there are three cases of only A, only B and A and B at the same time, where A and B can be singular or plural. The character " / " generally represents that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions means any combination of these items, including any combination of single or multiple items. For example, at least one of a, b or c can mean a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0353] It should be understood that in the description of the embodiments of the present disclosure, the meaning of multiple (or multiple items) is two or more, and greater than, less than, more than, etc. are not included in the number, and above, below, etc. are included in the number.

[0354] In several embodiments provided in the present disclosure, it should be understood that the disclosed system, device and method can be implemented in other manners. For example, the described device embodiments are merely schematic. For example, the division of the units is merely logical function division. There can be another division manner for the actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections can be indirect couplings or communication connections through some interfaces, devices or units, and can be in electrical, mechanical or other forms.

[0355] The units described as separated components can or can not be physically separated, and the components displayed as units can or can not be physical units, i.e., can be located in one place, or can be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purposes of the embodiments.

[0356] In addition, each functional unit in the various embodiments of the present disclosure can be integrated in one processing unit, or each unit can exist physically as a separate unit, or two or more units can be integrated in one unit. The integrated unit can be implemented in the form of hardware, or in the form of a software functional unit.

[0357] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on such an understanding, the technical solutions of the present disclosure essentially or substantially, or all or part of the technical solutions, can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods in the various embodiments of the present disclosure. The foregoing storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk, and various media that can store program codes.

[0358] It should also be understood that the various embodiments provided by the present disclosure can be combined in any manner to achieve different technical effects.

[0359] The above is a specific description of the preferred implementation of the present disclosure, but the present disclosure is not limited to the above implementation, and those skilled in the art can make various equivalent modifications or replacements without departing from the spirit and scope of the present disclosure, and these equivalent modifications or replacements are all included in the scope defined by the claims of the present disclosure.

Claims

1. A method for updating a photolithographic mask, characterized in that, include: Obtain the target chip layout, construct a mask image of the target chip layout, construct a level set function based on the mask boundary of the mask image, and perform photolithography simulation on the mask image to obtain a wafer pattern; The target loss is determined based on the difference between the target chip layout and the wafer pattern. The gradient of the target loss is determined based on the level set function. The gradient of the target loss is input into the conjugate gradient optimizer to obtain the first optimization term. The gradient of the target loss is input into the adaptive moment estimation optimizer to obtain the second optimization term. Attention processing is performed on the target chip layout to obtain a target attention map, and the second optimization term is adjusted based on the target attention map; The level set function is updated based on the first optimization term and the adjusted second optimization term, and the mask map is updated based on the updated level set function.

2. The method for updating a photolithographic mask according to claim 1, characterized in that, The step of updating the level set function based on the first optimization term and the adjusted second optimization term includes: The first optimization term and the adjusted second optimization term are weighted and summed to obtain the parameter update amount; The level set function is updated based on the parameter update amount.

3. The method for updating a photolithographic mask according to claim 2, characterized in that, The step of weighted summing of the first optimization term and the adjusted second optimization term to obtain the parameter update includes: Obtain the current iteration number, and determine the first weight corresponding to the first optimization term and the second weight corresponding to the second optimization term based on the current iteration number, wherein the first weight increases as the current iteration number increases, and the second weight decreases as the current iteration number increases; Based on the first weight and the second weight, the first optimization term and the adjusted second optimization term are weighted and summed to obtain the parameter update amount.

4. The method for updating a photolithographic mask according to claim 1, characterized in that, The target chip layout includes a graphic region, and the attention processing of the target chip layout to obtain a target attention map includes: Get the target scaling ratio; In the target chip layout, the graphic area is scaled proportionally based on the target scaling ratio to obtain the target attention region, and the target attention map is determined based on the target attention region.

5. The method for updating a photolithographic mask according to claim 1, characterized in that, The target chip layout includes a graphic region, and the attention processing of the target chip layout to obtain a target attention map includes: Attention processing is performed on the graphic region to obtain a first attention region and a second attention region in the target chip layout, wherein the first attention region is located within the graphic region and the second attention region is located outside the graphic region; In the target chip layout, a target attention map is determined based on the difference between the second attention region and the first attention region.

6. The method for updating a photolithographic mask according to claim 5, characterized in that, The attention processing of the graphic region to obtain the first attention region and the second attention region in the target chip layout includes: Obtain a first scaling ratio and a second scaling ratio, wherein the first scaling ratio is less than a preset ratio and the second scaling ratio is greater than the preset ratio; In the target chip layout, a first attention region is obtained by scaling the graphic area proportionally based on the first scaling ratio, and a second attention region is obtained by scaling the graphic area proportionally based on the second scaling ratio.

7. The method for updating a photolithographic mask according to claim 5, characterized in that, The attention processing of the graphic region to obtain the first attention region and the second attention region in the target chip layout includes: In the target chip layout, the pattern area is eroded based on a preset first convolution kernel to obtain a first initial region, and the pattern area is expanded based on a preset second convolution kernel to obtain a second initial region; Obtain the first attention weight of the first initial region and the second attention weight corresponding to the second initial region; The first attention region is obtained by weighting the first initial region based on the first attention weight, and the second attention region is obtained by weighting the second initial region based on the second attention weight.

8. The method for updating a photolithographic mask according to claim 7, characterized in that, The number of second initial regions is multiple, and any two second initial regions are determined based on second convolution kernels of different sizes. The second attention weights corresponding to any two second initial regions are different, and the second attention weights decrease as the corresponding second convolution kernel increases. The first attention weight is equal to the sum of all second attention weights. The step of weighting the second initial regions based on the second attention weights to obtain the second attention region includes: Each of the second attention weights is used to weight the corresponding second initial region to obtain multiple weighted regions. The second attention region is determined based on the sum of all the weighted regions.

9. The method for updating a photolithographic mask according to claim 1, characterized in that, The process of obtaining a wafer pattern by performing photolithography simulation on the mask image includes: The preset process parameters and the mask image are input into the photolithography physical model for photolithography simulation to obtain the light intensity distribution; The light intensity distribution is normalized to obtain a wafer pattern.

10. The method for updating a photolithographic mask according to claim 9, characterized in that, The process parameters include defocus parameters and exposure dose deviation parameters. Determining the target loss based on the difference between the target chip layout and the wafer pattern includes: The target perimeter is determined based on the length of the graphic boundary of the target chip layout, the initial error is determined based on the difference between the target chip layout and the wafer pattern, and the imaging error is determined based on the ratio of the initial error to the target perimeter. A first distribution function is constructed based on the defocus parameters, and defocus sampling points are obtained by sampling the defocus parameters. The defocus sampling points are then input into the first distribution function to obtain a first adjustment factor. A second distribution function is constructed based on the exposure dose deviation parameter. The exposure dose deviation parameter is sampled to obtain exposure dose deviation sampling points. The exposure dose deviation sampling points are input into the second distribution function to obtain a second adjustment factor. The imaging error is adjusted based on the first adjustment factor and the second adjustment factor to obtain the target loss.

11. The method for updating a photolithographic mask according to claim 10, characterized in that, Determining the gradient of the target loss based on the level set function includes: The gradient of the imaging error is determined based on the mask image; The gradient of the target loss is determined based on the first adjustment factor, the second adjustment factor, the gradient of the imaging error, and the gradient of the level set function; A penalty term is determined based on the level set function, and the gradient of the target loss is adjusted based on the penalty term.

12. The method for updating a photolithographic mask according to claim 1, characterized in that, The step of inputting the gradient of the target loss into the conjugate gradient optimizer to obtain a first optimization term, and inputting the gradient of the target loss into the adaptive moment estimation optimizer to obtain a second optimization term, includes: The gradient of the target loss is input into the conjugate gradient optimizer to obtain the first optimization direction; The gradient of the target loss is input into the adaptive moment estimation optimizer to obtain the second optimization direction; The first optimization step size is determined based on the first optimization direction and the preset step size factor, and the first optimization term is obtained by multiplying the first optimization direction and the first optimization step size. The second optimization step size is determined based on the second optimization direction and the step size factor, and the second optimization term is obtained by multiplying the second optimization direction and the second optimization step size.

13. The method for updating a photolithographic mask according to claim 1, characterized in that, The method for updating the photolithographic mask also includes: Obtain the current iteration number. If the current iteration number is less than a preset threshold, update the level set function again based on the target chip layout and the updated mask image, update the mask image again based on the updated level set function, and update the current iteration number until the current iteration number is greater than or equal to the threshold. Alternatively, if the imaging error determined based on the target chip layout and the wafer pattern is greater than a preset error threshold, the level set function is updated again based on the target chip layout and the updated mask image, and the mask image is updated again based on the updated level set function, until the imaging error is less than or equal to the error threshold.

14. A photolithographic mask updating device, characterized in that, include: The simulation module is used to acquire the target chip layout, construct a mask image of the target chip layout, construct a level set function based on the mask boundary of the mask image, and perform photolithography simulation on the mask image to obtain a wafer pattern. The processing module is used to determine the target loss based on the difference between the target chip layout and the wafer pattern, determine the gradient of the target loss based on the level set function, input the gradient of the target loss into a conjugate gradient optimizer to obtain a first optimization term, and input the gradient of the target loss into an adaptive moment estimation optimizer to obtain a second optimization term. An adjustment module is used to perform attention processing on the target chip layout to obtain a target attention map, and to adjust the second optimization term based on the target attention map; An update module is used to update the level set function based on the first optimization term and the adjusted second optimization term, and to update the mask image based on the updated level set function.

15. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the photomask updating method according to any one of claims 1 to 13.

16. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the photomask updating method according to any one of claims 1 to 13.

17. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the photomask updating method according to any one of claims 1 to 13.

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