Hybrid bonding structure based on interlocking structures and bonding method

Abstract

This invention provides a hybrid bonding structure and bonding method based on an interlocking structure. The hybrid bonding structure includes: a first chip to be bonded, having a silicon oxide layer and a first connector protruding from the silicon oxide layer; and a second chip to be bonded, having a polyimide layer, a recess within the polyimide layer, and a second connector at the bottom of the recess. The surface of the second connector is provided with a first adhesive layer. The materials of the first and second connectors include copper and / or aluminum. The first and second chips to be bonded are configured such that: before bonding, the height difference of the first connector protruding from the oxide layer is greater than the height difference between the top surface of the first adhesive layer and the top surface of the silicon oxide layer; after bonding, the silicon oxide layer and the polyimide layer are connected, and the first connector extends into the recess and is connected to the second connector using the first adhesive layer, thus forming an interlocking structure. This invention is used to optimize the performance of the hybrid bonding process and bonding structure.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing technology, and in particular to a hybrid bonding structure and bonding method based on an interlocking structure. Background Technology

[0002] As demands for electronic products shift towards miniaturization, multifunctionality, and environmental friendliness, numerous new technologies, materials, and designs have emerged. Improvements in process technology, circuit design, programming algorithms, and manufacturing processes have enabled the scaling down of planar semiconductor devices to smaller dimensions. However, as the feature sizes of semiconductor devices approach their physical limits, planar processes and manufacturing technologies have become challenging and costly. Three-dimensional stacked semiconductor device architectures can address some of the density limitations inherent in planar semiconductor devices.

[0003] Among the various technologies used for stacking semiconductor substrates, hybrid bonding (heterogeneous bonding) has become a key focus of current 3D integration technology research and development because it simultaneously connects circuit leads during the bonding process. For hybrid bonding processes, since electrical connections between wafers must be achieved while completing wafer bonding, extremely high requirements are placed on the surface morphology of the wafers to be bonded, especially on the uniformity and consistency of the bonding interface process.

[0004] Taking heteropolymer bonding processes involving copper as an example, after fabricating the Cu pads for bonding, the Cu surface needs to be polished using CMP (Chemical Metallurgy Processing). However, current industry requirements dictate that the surface roughness of the dielectric layer after CMP polishing must be below 0.5 nm to facilitate dielectric layer bonding, and the degree of indentation in the Cu pads is also highly demanding. Therefore, the aforementioned bonding method not only requires CMP equipment but also places extremely high demands on it, significantly increasing the complexity of the entire fabrication process. If the conditions for the CMP process are not met, it will severely impact the bonding yield, the performance of the bonded product, and its reliability. Summary of the Invention

[0005] The purpose of this invention is to provide a hybrid bonding structure and bonding method based on an interlocking structure, for optimizing the performance of the hybrid bonding process and the bonding structure.

[0006] To solve the above technical problems, the present invention provides a hybrid bonding structure based on an interlocking structure, comprising:

[0007] The first chip to be bonded has a silicon oxide layer and a first connector protruding from the silicon oxide layer;

[0008] The second chip to be bonded has a polyimide layer, a recess in the polyimide layer, and a second connector at the bottom of the recess. The surface of the second connector is provided with a first adhesive layer. The materials of the first connector and the second connector include copper and / or aluminum.

[0009] The first chip to be bonded and the second chip to be bonded are configured such that: before bonding, the height difference of the first connector protruding from the oxide layer is greater than the height difference between the top surface of the first adhesive layer and the top surface of the silicon oxide layer; after bonding, the silicon oxide layer is connected to the polyimide layer and the first connector extends into the recess and is connected to the second connector by the first adhesive layer to form an interlocking structure.

[0010] Optionally, the recess matches the cross-sectional shape of the first connector, and before bonding, the cross-sectional dimension of the recess is larger than the cross-sectional dimension of the first connector.

[0011] Optionally, the first connector may be made of aluminum, and the surface of the first connector may also be covered with a second adhesive layer.

[0012] Optionally, the materials of the first adhesive layer and the second adhesive layer include titanium.

[0013] According to another aspect of the present invention, a hybrid bonding method based on an interlocking structure is also provided, comprising:

[0014] A first chip to be bonded is provided, the surface of which is provided with a silicon oxide layer;

[0015] A plurality of protruding first connectors are formed on the silicon oxide layer;

[0016] Provide a second chip to be bonded;

[0017] A polyimide layer with a recess is formed on the second chip to be bonded, and a second connector and a first adhesive layer are formed at the bottom of the recess. The first adhesive layer covers the surface of the second connector. The materials of the first connector and the second connector include copper and / or aluminum. The height difference of the first connector protruding from the silicon oxide layer is greater than the height difference between the top surface of the first adhesive layer and the top surface of the polyimide layer.

[0018] The first chip and the second chip to be bonded are surface treated, and hot-press bonding is performed on the first chip and the second chip to be bonded at a first hot-pressing temperature and a first hot-pressing time, so that the silicon oxide layer is connected to the polyimide layer and the first connector extends into the recess and is connected to the second connector by the first adhesive layer, so as to form an interlocking structure.

[0019] Optionally, the material of the first connector includes aluminum, and the steps for forming the first connector include:

[0020] A first patterned mask layer is formed on the silicon oxide layer, having a first opening that exposes a portion of the silicon oxide layer.

[0021] Metallic aluminum is deposited within the first opening to form the first connector;

[0022] A second adhesive layer is formed to cover the first connector;

[0023] Remove the first graphical mask layer.

[0024] Optionally, the material of the first connector includes copper, and the steps for forming the first connector include:

[0025] A third adhesion layer and a copper seed layer are sequentially formed on the silicon oxide layer;

[0026] A first patterned mask layer is formed on the copper seed layer, having a first opening that exposes a portion of the copper seed layer.

[0027] A chemical electroplating process is performed to fill the first opening with a copper layer;

[0028] Remove the first patterned mask layer and perform a dry etching process to remove the exposed copper seed layer and the third adhesion layer below it, using the remaining third adhesion layer, the copper seed layer and the copper layer as the first connector.

[0029] Optionally, the step of forming the polyimide layer, the second connector, and the first adhesive layer includes:

[0030] A polyimide layer is formed on the surface of the second chip to be bonded;

[0031] A plurality of second openings are formed in the polyimide layer to expose a portion of the second chip surface, the width of the second openings being greater than the width of the first openings, and the second openings serving as the recesses;

[0032] A second patterned mask layer is formed on the surface of the polyimide layer, having a third opening that exposes a portion of the second chip surface, the third opening being directly opposite the second opening and the width of the third opening being smaller than the width of the second opening;

[0033] The second connector and the first adhesive layer are sequentially formed at the bottom of the second opening. The material of the second connector includes copper and / or aluminum. The height difference of the first connector protruding from the silicon oxide layer is greater than the height difference between the top surface of the first adhesive layer and the top surface of the polyimide layer.

[0034] Remove the second graphical mask layer.

[0035] Optionally, the process parameters for hot-press bonding include: the first hot-press temperature is 200℃~350℃, the hot-press time is 50 minutes~90 minutes, and the hot-press pressure is 100 Newtons~1000 Newtons.

[0036] Optionally, after surface treatment of the first chip and the second chip to be bonded, hot-press bonding is performed on the first chip and the second chip to be bonded at a second hot-press temperature and a second hot-press time, and then annealing is performed on the first chip and the second chip to be bonded, wherein the second hot-press temperature is lower than the first hot-press temperature and the second hot-press time is less than the first hot-press time.

[0037] In summary, the hybrid bonding structure and bonding method based on an interlocking structure provided by this invention include a first chip to be bonded, having a silicon oxide layer and a first connector protruding from the silicon oxide layer; and a second chip to be bonded, having a polyimide layer, a recess within the polyimide layer, and a second connector at the bottom of the recess, with a first adhesive layer on the surface of the second connector. The materials of the first and second connectors include copper and / or aluminum. The first and second chips to be bonded are configured such that, before bonding, the height difference of the first connector protruding from the oxide layer is greater than the height difference between the top surface of the first adhesive layer and the top surface of the silicon oxide layer; after bonding, the silicon oxide layer and the polyimide layer are connected, and the first connector extends into the recess and is connected to the second connector using the first adhesive layer, thus forming an interlocking structure. In this invention, simply extending the first connector of the first chip into the corresponding recess of the second chip easily achieves misalignment-free alignment of the first and second chips. Compared to direct copper-to-copper bonding, this invention utilizes a first adhesive layer to connect the first and second connectors, reducing the bonding temperature and the requirements for copper surface flatness. Considering that the coefficient of thermal expansion of polyimide is greater than that of the first connector, before bonding, the first connector extends into the recess and contacts the first adhesive layer. A gap is reserved between the polyimide layer and the silicon oxide layer (i.e., the difference between the height difference of the first connector protruding from the silicon oxide layer and the height difference between the top surface of the first adhesive layer and the top surface of the polyimide layer). During thermo-press bonding, the first adhesive layer connects the first and second connectors, while the polyimide layer gradually expands to contact the silicon oxide layer and the first connector, essentially filling the gaps reserved between the polyimide and silicon oxide layers and between the first connector and the sidewall of the recess before bonding, forming an interlocking structure. This improves the mechanical stability (mechanical strength) after bonding annealing, reduces bonding interface defects, prevents leakage current and other reliability problems caused by bonding interface defects, and also reduces the stress on the first and second chips after bonding. Furthermore, the fabrication of bonding interconnects on the first and second chips completely eliminates the need for CMP steps, thus avoiding the requirement for high-precision CMP equipment and processes. In addition, compared to silicon oxide layers, polyimide layers have higher dielectric constants and insulating properties, which can further reduce signal interference between bonded interconnects (between pads) while preventing leakage, thus facilitating further increases in interconnect density. Attached Figure Description

[0038] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention.

[0039] Figure 1 This is a flowchart of a hybrid bonding method based on an interlocking structure provided in an embodiment of the present invention;

[0040] Figures 2a to 2lThis is a schematic diagram of the corresponding steps of a hybrid bonding method based on an interlocking structure provided in an embodiment of the present invention.

[0041] Figures 3a-3d This is a schematic diagram of forming a first connector according to another embodiment of the present invention.

[0042] In the attached figures: 10-first chip; 11-silicon oxide layer; 12-third adhesion layer; 13-copper seed layer; 14-first patterned mask layer; 15-first opening; 16-first copper layer; 17-first connector; H1-first height difference; 21-second chip; 22-polyimide layer; 23-recess; 24-second patterned mask layer; 25-third opening; 26-second connector; 27-first adhesion layer; H2-second height difference; 18-second adhesion layer. Detailed Implementation

[0043] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0044] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; and the term “at least two” is generally used to mean “two or more”. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature, unless otherwise expressly indicated.

[0045] One embodiment of the present invention provides a hybrid bonding method based on an interlocking structure.

[0046] Figure 1 This is a flowchart of the hybrid bonding method based on an interlocking structure provided in this embodiment.

[0047] like Figure 1 As shown, the hybrid bonding method based on an interlocking structure provided in this embodiment includes:

[0048] S01: A first chip to be bonded is provided, the surface of which is provided with a silicon oxide layer;

[0049] S02: A plurality of protruding first connectors are formed on the silicon oxide layer;

[0050] S03: Provides the second chip to be bonded;

[0051] S04: A polyimide layer with a recess is formed on the second chip to be bonded, and a second connector and a first adhesive layer are formed at the bottom of the recess. The first adhesive layer covers the surface of the second connector. The material of the first connector and the second connector includes copper and / or aluminum. The height difference of the first connector protruding from the silicon oxide layer is greater than the height difference between the top surface of the first adhesive layer and the top surface of the polyimide layer.

[0052] S05: Perform surface treatment on the first chip to be bonded and the second chip to be bonded, and perform hot-press bonding on the first chip to be bonded and the second chip to be bonded at a first hot-pressing temperature and a first hot-pressing time, so that the silicon oxide layer is connected to the polyimide layer and the first connector extends into the recess and is connected to the second connector by the first adhesive layer, so as to form an interlocking structure.

[0053] Figures 2a-2i This is a schematic diagram of the corresponding steps of the hybrid bonding method based on interlocking structure provided in this embodiment. Next, we will combine... Figures 2a-2i The hybrid bonding method based on the interlocking structure is described in detail.

[0054] First, please refer to Figure 2a In step S01, a first chip 10 to be bonded is provided, on which a silicon oxide layer 11 is provided.

[0055] The first chip 10 to be bonded can be a semiconductor structure to be bonded in a broad sense, such as a wafer to be bonded, an interposer with through-silicon vias (TSVs), a semi-finished chip to be bonded, or a finished chip to be bonded. The first chip 10 has a region to be bonded (the region used for bonding), the surface of which is a silicon oxide layer 11, and the interconnect structures (e.g., plugs or interconnects) to be bonded are exposed in the silicon oxide layer 11. Of course, if the material of the surface of the bonding region of the first chip 10 is not silicon oxide, a silicon oxide layer 11 can be formed on its surface using a vapor deposition process to expose the interconnect structures to be bonded.

[0056] Next, step S02 is performed to form a plurality of protruding first connectors 17 on the silicon oxide layer 11. The material of the first connectors 17 includes copper.

[0057] Please refer to Figure 2bA third adhesion layer 12 and a copper seed layer 13 are sequentially formed on the silicon oxide layer 11. The third adhesion layer 12 and the copper seed layer 13 can be sequentially formed on the surface of the silicon oxide layer 11 using a physical vapor deposition process. The material of the third adhesion layer 12 can be titanium. A second barrier layer can preferably be formed between the third adhesion layer 12 and the copper seed layer 13. The material of the second barrier layer can include titanium nitride and / or titanium tungstenide.

[0058] Please refer to Figure 2c A first patterned mask layer 14 is formed on the copper seed layer 13, having a first opening 15 that exposes a portion of the copper seed layer 13. The first patterned mask layer 14 may be a patterned photoresist layer, with the first opening 15 exposing the copper seed layer 13 in the region corresponding to the interconnect structure to be bonded. The thickness of the first patterned mask layer 14 can be determined based on the height of the subsequent first connector 17, where the thickness of the first patterned mask layer 14 = height of the first connector (preset height) - thickness of the third adhesion layer 12 - thickness of the copper seed layer 13.

[0059] Please refer to Figure 2d A chemical electroplating process is performed to fill the first opening 15 with a first copper layer 16. The top surface of the first copper layer 16 may be substantially flush with or slightly exceed the thickness of the first patterned mask layer 14.

[0060] Please refer to Figure 2e The first patterned mask layer 14 is removed, and a dry etching process is performed to remove the exposed copper seed layer 13 and the third adhesion layer 12 below it, exposing the surface of the silicon oxide layer 11. The remaining third adhesion layer 12, copper seed layer 13, and first copper layer 16 serve as the first connector 17, which electrically leads out the interconnect structure to be bonded to the first chip 10. The height difference of the first connector 17 protruding from the silicon oxide layer 11 can be a first height difference H1.

[0061] Next, please refer to Figure 2f Step S03 is executed, providing the second chip 21 to be bonded.

[0062] The second chip 21 may be a semiconductor structure that is matched and bonded to the first chip 10. The second chip 21 has a region to be bonded (the region for bonding), the surface of which is an insulating dielectric layer, in which interconnect structures (e.g., plugs or interconnects) to be bonded are exposed.

[0063] Next, step S04 is performed to form a polyimide layer 22 with a recess 23 on the second chip 21 to be bonded, and a second connector 26 and a first adhesive layer 27 are formed at the bottom of the recess 23. The first adhesive layer 27 covers the surface of the second connector 26, wherein the height difference of the first connector 17 protruding from the first oxide layer is less than the height difference between the top surface of the first adhesive layer 27 and the top surface of the polyimide layer 22.

[0064] Please refer to Figure 2g A polyimide layer 22 is formed on the surface of the second chip 21 to be bonded. The polyimide layer 22 can be formed, for example, by spin coating on the surface of the bonding area of ​​the second chip 21, and photolithographic patterning and curing (e.g., heat curing) are performed on the polyimide layer 22 to form several second openings in the polyimide layer 22 to expose a portion of the surface of the second chip 21. The second opening is a recess 23, the bottom of which exposes the interconnect structure to be bonded to the second chip 21. The cross-sectional shape of the second opening is the same as the cross-sectional shape of the first opening 15, but the size (width) of the recess 23 is slightly larger than the size (width) of the first opening 15. The depth of the recess 23 is the thickness of the polyimide layer 22 and can match the protrusion height of the first connector 17. In addition, in some examples, a silicon oxide layer (or other dielectric layer) of several thicknesses may be formed on the surface of the second chip 21 before the polyimide layer 22 is formed, and after the second opening is formed in the polyimide layer 22, the surface of the second chip 21 in the exposed area of ​​the silicon oxide layer is etched to compress the thickness of the polyimide layer 22.

[0065] It is understood that the polyimide layer 22 in this embodiment is not limited to polyimide, but may also be a polyimide or other organic material including polyimide. Compared with inorganic dielectric layers such as silicon oxide, the organic material of the polyimide layer 22 in this embodiment has better dielectric constant and insulation properties, and is easier to prepare and can be directly compatible with photolithography processes.

[0066] Please refer to Figure 2h A second patterned mask layer 24 is formed on the surface of the polyimide layer 22, having a third opening 25 opposite the second opening (recess 23), exposing a portion of the surface of the second chip 21 (the bottom of the recess 23). The cross-sectional shape of the third opening 25 is the same as or similar to the cross-sectional shape of the recess 23, but the width of the third opening 25 is slightly smaller than the width of the second opening, for example, by 50 nm to 200 nm. In some examples, the size and shape of the third opening 25 may be the same as the size and shape of the first opening 15.

[0067] Please refer to Figure 2iA second connector 26 and a first adhesive layer 27 are sequentially formed at the bottom of the recess 23 for electrically leading out the interconnect structure of the second chip 21 to be bonded. The second connector 26 and the first adhesive layer 27 can be formed sequentially using a physical vapor deposition process. The material of the second connector 26 may include copper and / or aluminum, and the material of the first adhesive layer 27 may be titanium. When the material of the second connector 26 is copper, a first barrier layer can preferably be formed between it and the first adhesive layer 27. The material of the first barrier layer may include titanium nitride and / or titanium tungstenide. Of course, it is also feasible to form a very small amount of metal material on the sidewall of the recess 23. It should be noted that because the size of the third opening 25 is smaller than the size of the second opening, the second connector 26 and the first adhesive layer 27 only cover part of the bottom of the recess 23. In other words, a first gap is reserved between the second connector 26 and the first adhesive layer 27 and the sidewall of the recess 23.

[0068] Please refer to Figure 2j The second patterned mask layer 24 is removed, exposing the surface of the polyimide layer 22. The height difference between the first connector 17 protruding from the silicon oxide layer 11 is greater than the height difference between the top surface of the first adhesive layer 27 and the top surface of the polyimide layer 22. The second connector 26 and the first adhesive layer 27 electrically lead out the interconnect structure to be bonded to the second chip 21. In other words, the height difference between the top surface of the first adhesive layer 27 and the top surface of the polyimide layer 22 can be a second height difference H2, which is slightly smaller than the first height difference H1, for example, by 50 nm to 500 nm. Of course, the second connector 26 and the first adhesive layer 27 formed by the above physical vapor deposition process also cover the surface of the second patterned mask layer 24 (in...). Figure 2i and Figure 2j (not shown in the image) When removing the second patterned mask layer 24, the excess second connector 26 and first adhesive layer 27 on its surface are also removed, leaving only the second connector 26 and first adhesive layer 27 in the recess 23.

[0069] Next, please refer to Figure 2k In step S05, the first chip 10 to be bonded and the second chip 21 to be bonded are surface treated, and hot-press bonding is performed on the first chip 10 to be bonded and the second chip 21 to be bonded at a first hot-pressing temperature and a first hot-pressing time, so that the silicon oxide layer 11 is connected to the polyimide layer 22 and the first connector 17 extends into the recess 23 and is connected to the second connector 26 by the first adhesive layer 27, so as to form an interlocking structure.

[0070] The surface treatment steps for the first chip 10 and the second chip 21 to be bonded include: cleaning the first chip 10 and the second chip 21 to be bonded with a weak acid to improve their hydrophilicity; and bombarding the first chip 10 and the second chip 21 to be bonded with plasma to remove surface oxides from the first connector 17 and the first adhesion layer 27 and to improve the surface activity of the silicon oxide layer 11 and the polyimide layer 22. In practice, at least some of the above surface treatment steps can be selected according to actual needs. When surface treating the first chip 10 to be bonded, a low-concentration citric acid cleaning can be used first to reduce the contact angle and improve hydrophilicity, followed by bombardment with a mixed gas of argon / nitrogen / hydrogen to remove the oxide layer on the surface of the first connector 17. When performing surface treatment on the second chip 21 to be bonded, a mixed gas of argon / nitrogen / hydrogen can be used to bombard the polyimide layer 22 and the first adhesion layer 27 to improve the surface activity of the polyimide layer 22 and reduce the oxide content on the surface of the first adhesion layer 27 in the recess 23.

[0071] Before bonding, inserting the first connector 17 of the first chip 10 into the corresponding recess 23 of the second chip 21 (similar to interlocking) easily achieves misalignment-free alignment of the first chip 10 and the second chip 21. Then, the first chip 10 and the second chip 21 are thermo-bonded. The process parameters include: a first thermo-bonding temperature of 200℃~350℃, a thermo-bonding time of 50 minutes~90 minutes, and a thermo-bonding pressure of 100 Newtons~1000 Newtons. It should be noted that... (Please refer to...) Figure 2k After alignment, the first connector 17 extends into the recess 23 and contacts the surface of the first adhesive layer 27, but a gap (i.e., a second gap) is maintained between the sidewall of the first connector 17 and the sidewall of the recess 23. On the other hand, the silicon oxide layer 11 of the first chip 10 and the polyimide layer 22 of the second chip 21 do not contact each other, but maintain a preset gap (i.e., a third gap is reserved). Next, please refer to Figure 2l During the thermo-press bonding process, the silicon oxide layer 11, the polyimide layer 22, and the first connector 17 expand due to heat. The first adhesive layer 27 connects the first connector 17 and the second connector 26 under high temperature and external pressure. The polyimide layer 22 expands due to heat, gradually filling the aforementioned second and third gaps until it contacts and connects with the silicon oxide layer 11. Therefore, the aforementioned gaps (the first gap, the second gap, and the third gap) can be determined by the thickness of the polyimide layer 22, the dimensions (height and width) of the first connector 17, and the difference in the coefficients of thermal expansion between the first connector 17 and the polyimide layer 22.

[0072] Compared to direct bonding of copper to copper (or aluminum), using the first adhesion layer 27 to connect the first connector 17 and the second connector 26 can reduce the bonding temperature and the requirements for the surface flatness of the first connector 17 (second connector 26). During the aforementioned hot-press bonding process, considering that the coefficient of thermal expansion of the polyimide layer 22 is greater than that of the first connector 17 (copper) and the silicon oxide layer 11, the polyimide layer 22 gradually expands until it contacts and connects with the silicon oxide layer 11, essentially filling the first, second, and third gaps reserved after alignment to form an interlocking structure. This improves the mechanical stability (mechanical strength) after bonding, reduces bonding interface defects, prevents leakage current and other reliability problems caused by bonding interface defects, and also reduces the stress on the first chip 10 and the second chip 21 after bonding annealing.

[0073] More notably, the CMP step is completely unnecessary when fabricating the bonding connectors on the first chip 10 and the second chip 21, thus eliminating the need for high-precision CMP equipment and processes. This simplifies the process flow, reduces process complexity, and facilitates stable, reliable, and high-performance interconnection. As can be seen from the above connection process, even if the top surface morphology of the first connector 17 and / or the top morphology of the first adhesive layer 27 is uneven, the first connector 17 and the first adhesive layer 27 can still be confined in the corresponding recess 23 and connected through contact under high-temperature expansion and external pressure. In other words, the top surface morphology of the first connector 17 and / or the top morphology of the first adhesive layer 27 does not affect their bonding connection within the recess 23.

[0074] In addition, compared to the silicon oxide layer 11, the polyimide layer 22 has a higher dielectric constant and insulation properties, which can further reduce signal interference between bonded connectors (between pads) and prevent leakage, thus facilitating further improvement of interconnect density.

[0075] Another embodiment of the present invention provides a hybrid bonding method based on an interlocking structure. The hybrid bonding method of this embodiment is basically the same as the hybrid bonding method of other embodiments, the main difference being that the material of the first connector 17 on the first chip 10 in this embodiment includes aluminum or a copper-aluminum alloy, and the method of forming the first connector 17 on the silicon oxide layer 11 of the first chip 10 to be bonded is different.

[0076] Specifically, the steps for forming the first connector 17, which is mainly made of aluminum, include:

[0077] Please refer to Figure 3a A first patterned mask layer 14 is formed on the silicon oxide layer 11 of the first chip 10 to be bonded, which has a first opening 15 to expose a portion of the silicon oxide layer 11, that is, to expose the interconnect structure of the first chip 10 to be bonded.

[0078] Please refer to Figure 3b A physical vapor deposition process is performed to deposit metallic aluminum (or copper-aluminum alloy) in the first opening 15 to form the first connector 17.

[0079] Please refer to Figure 3c A physical vapor deposition process is performed to deposit a second adhesion layer 18 on the first connector 17 within the first opening 15 to cover the first connector 17. The material of the second adhesion layer 18 may include one or at least two of titanium, gold, tin, niobium or chromium.

[0080] Please refer to Figure 3d The first patterned mask layer 14 is removed, exposing the surface of the silicon oxide layer 11. It should be noted that the second adhesion layer 18 also serves to protect the first connector 17; it is also feasible to consider the second adhesion layer 18 as a passivation layer or protective layer. Of course, the first connector 17 and the second adhesion layer 18 formed by the physical vapor deposition process also cover the surface of the first patterned mask layer 14. When removing the first patterned mask layer 14, excess first connector 17 and second adhesion layer 18 on its surface are also removed, leaving only the first connector 17 and the second adhesion layer 18 on the silicon oxide layer 11.

[0081] Another embodiment of the present invention provides a hybrid bonding method based on an interlocking structure. The hybrid bonding method of this embodiment is basically the same as the hybrid bonding method of other embodiments, the main difference being that the process parameters and process steps for bonding the first chip 10 and the second chip 21 are slightly different in this embodiment. In this example, an annealing step is added after hot-press bonding to shorten the hot-press bonding time and improve the efficiency of hot-press bonding.

[0082] Specifically, the bonding steps after surface treatment and alignment of the first chip 10 and the second chip 21 to be bonded include: performing hot-press bonding on the first chip 10 and the second chip 21 at a second hot-press temperature and a second hot-press time, wherein the second hot-press temperature is lower than the first hot-press temperature and the second hot-press time is shorter than the first hot-press time; then annealing the hot-pressed first chip 10 and the second chip 21, wherein the annealing temperature can be greater than or equal to the first hot-press temperature. In one example, the second hot-press temperature can be 100℃~200℃, the second hot-press time can be 20 minutes~40 minutes, the hot-press pressure can be 100 Newtons~1000 Newtons, the annealing temperature can be 250℃~400℃, and the annealing time can be 30 minutes~90 minutes.

[0083] The present invention also provides a hybrid bonding structure based on an interlocking structure.

[0084] Figure 2e This is a schematic diagram of the structure of the first chip to be bonded. Figure 2j This is a schematic diagram of the structure of the second chip to be bonded.

[0085] like Figure 2e and Figure 2j As shown, the hybrid bonding structure based on an interlocking structure provided in this embodiment includes a first chip 10 to be bonded and a second chip 21 to be bonded. Both are semiconductor structures to be bonded in a broad sense, and may include, for example, a wafer to be bonded, an interposer with through-silicon vias, a semi-finished chip to be bonded, or a finished chip to be bonded. The first chip 10 and the second chip 21 each have a bonding region, in which interconnect structures (e.g., plugs or interconnects, not shown in the figure) to be bonded are exposed.

[0086] like Figure 2e As shown, the surface of the bonding area of ​​the first chip 10 is a first silicon oxide layer 11. Several protruding and spaced-apart first connectors 17 are provided on the first silicon oxide layer 11, each connecting to an interconnect structure to be bonded in the first chip 10. The primary material of the first connector 17 is copper. The first connector 17 may include a third adhesion layer 12, a copper seed layer 13, and a first copper layer 16 stacked sequentially from bottom to top. A second barrier layer may also be provided between the third adhesion layer 12 and the copper seed layer 13. The material of the third adhesion layer 12 may be titanium, and the material of the second barrier layer may include titanium nitride and / or titanium tungstenide. The height difference between the top surface of the first connector 17 and the surface of the first silicon oxide layer 11 is a first height difference H1.

[0087] In other examples of this embodiment, such as Figure 3d As shown, the main material of the first connector 17 can also be aluminum (i.e., an aluminum layer or a copper-aluminum alloy layer). A second adhesive layer 18 is also provided on the surface of the first connector 17. The height difference between the top surface of the first adhesive layer 27 and the surface of the first silicon oxide layer 11 can be a first height difference H1. The second adhesive layer 18 is used to protect the first connector 17. Therefore, it is also feasible to regard the second adhesive layer 18 as a passivation layer or a protective layer. The material of the second adhesive layer 18 can include one or at least two of titanium, gold, tin, niobium, or chromium.

[0088] like Figure 2jAs shown, the surface of the bonding area of ​​the second chip 21 is a polyimide layer 22. The polyimide layer 22 has several recesses 23 exposing the interconnect structures of the second chip 21 to be bonded. The positions of these recesses 23 match the corresponding first connectors 17 on the first chip 10. At the bottom of the recesses 23, i.e., on the interconnect structures of the second chip 21 to be bonded, a second connector 26 and a first adhesive layer 27 are sequentially provided. The material of the second connector 26 may include copper and / or aluminum, and the material of the first adhesive layer 27 may include titanium. In a preferred embodiment, the area of ​​the second connector 26 and the first adhesive layer 27 is smaller than the bottom area of ​​the recess 23, i.e., there is a gap between the second connector 26 and the first adhesive layer 27 and the sidewalls of the recess 23.

[0089] When the material of the second connector 26 is mainly copper, a first barrier layer may also be provided between the first adhesive layer 27 and the second connector 26. The material of the first barrier layer may include titanium nitride and / or titanium tungstenide. When the material of the second connector 26 is mainly aluminum, the first adhesive layer 27 can serve as an adhesive layer between the first connector 17 and the second connector 26, and can also serve as a protective layer for the second connector 26.

[0090] The cross-sectional shape of the recess 23 matches (is the same as) the cross-sectional shape of the first connector 17, but the cross-sectional dimension (width) of the recess 23 is slightly larger than that of the first connector 17. The height difference between the top surface of the first adhesive layer 27 and the surface of the polyimide layer 22 in the recess 23 can be a second height difference H2. The second height difference H2 is less than the first height difference H1. The difference between the second height difference H2 and the first height difference H1 is the reserved gap between the silicon oxide layer 11 and the polyimide layer 22 after the first connector 17 extends into the recess 23 and contacts the first adhesive layer 27. It can be determined by the dimensions (height and width) of the first connector 17, the thickness of the polyimide layer 22, and the difference in the coefficients of thermal expansion of the first connector 17 and the polyimide layer 22. In other words, after aligning the first chip 10 and the second chip 21, the first connector 17 contacts the first adhesive layer 27, while the silicon oxide layer 11 around the first connector 17 does not contact the polyimide layer 22 around the recess 23. During the thermo-press bonding process, the polyimide layer 22 gradually expands until it contacts and connects with the silicon oxide layer 11, and the first adhesive layer 27 connects the first connector 17 and the second connector 26, thereby filling the reserved gap between the polyimide layer 22 and the silicon oxide layer 11 and the gap between the first connector 17 and the sidewall of the recess 23, thus forming an interlocking structure.

[0091] In a specific example, the height of the first connector 17 (the first height difference H1) can be 1500 nm to 3000 nm, and the second height difference H2 can be 100 nm to 300 nm smaller than the first height difference H1.

[0092] In summary, the hybrid bonding structure and bonding method based on an interlocking structure provided by this invention include a first chip to be bonded, having a silicon oxide layer and a first connector protruding from the silicon oxide layer; and a second chip to be bonded, having a polyimide layer, a recess within the polyimide layer, and a second connector at the bottom of the recess, with a first adhesive layer on the surface of the second connector. The materials of the first and second connectors include copper and / or aluminum. The first and second chips to be bonded are configured such that, before bonding, the height difference of the first connector protruding from the oxide layer is greater than the height difference between the top surface of the first adhesive layer and the top surface of the silicon oxide layer; after bonding, the silicon oxide layer and the polyimide layer are connected, and the first connector extends into the recess and is connected to the second connector using the first adhesive layer, thus forming an interlocking structure. In this invention, simply extending the first connector of the first chip into the corresponding recess of the second chip easily achieves misalignment-free alignment of the first and second chips. Compared to direct copper-to-copper bonding, this invention utilizes a first adhesive layer to connect the first and second connectors, reducing the bonding temperature and the requirements for copper surface flatness. Considering that the coefficient of thermal expansion of polyimide is greater than that of the first connector, before bonding, the first connector extends into the recess and contacts the first adhesive layer. A gap is reserved between the polyimide layer and the silicon oxide layer (i.e., the difference between the height difference of the first connector protruding from the silicon oxide layer and the height difference between the top surface of the first adhesive layer and the top surface of the polyimide layer). During thermo-press bonding, the first adhesive layer connects the first and second connectors, while the polyimide layer gradually expands to contact the silicon oxide layer and the first connector, essentially filling the gaps reserved between the polyimide and silicon oxide layers and between the first connector and the sidewall of the recess before bonding, forming an interlocking structure. This improves the mechanical stability (mechanical strength) after bonding annealing, reduces bonding interface defects, prevents leakage current and other reliability problems caused by bonding interface defects, and also reduces the stress on the first and second chips after bonding. Furthermore, the fabrication of bonding interconnects on the first and second chips completely eliminates the need for CMP steps, thus avoiding the requirement for high-precision CMP equipment and processes. In addition, compared to silicon oxide layers, polyimide layers have higher dielectric constants and insulating properties, which can further reduce signal interference between bonded interconnects (between pads) while preventing leakage, thus facilitating further increases in interconnect density.

[0093] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. An interlocking structure based hybrid bonding structure, characterized by, include: The first chip to be bonded has a silicon oxide layer and a first connector protruding from the silicon oxide layer; The second chip to be bonded has a polyimide layer, a recess in the polyimide layer, and a second connector at the bottom of the recess. The surface of the second connector is provided with a first adhesive layer. The materials of the first connector and the second connector include copper and / or aluminum. The first chip to be bonded and the second chip to be bonded are configured such that: before bonding, the height difference of the first connector protruding from the silicon oxide layer is greater than the height difference between the top surface of the first adhesive layer and the top surface of the polyimide layer, and there is a gap between the second connector and the first adhesive layer and the recess; after bonding, the silicon oxide layer and the polyimide layer are connected, and the first connector extends into the recess and is connected to the second connector using the first adhesive layer; wherein, the polyimide layer expands due to heat during the hot-press bonding process to fill the reserved gap between the polyimide layer and the silicon oxide layer, the gap between the first connector and the sidewall of the recess, and the gap between the second connector and the first adhesive layer and the recess, and to form an interlocking structure.

2. The hybrid bonding structure based on an interlocking structure according to claim 1, characterized in that, The recess matches the cross-sectional shape of the first connector, and before bonding, the cross-sectional dimension of the recess is larger than the cross-sectional dimension of the first connector.

3. The hybrid bonding structure based on an interlocking structure according to claim 1, characterized in that, The first connector is made of aluminum, and its surface is also covered with a second adhesive layer.

4. The hybrid bonding structure based on an interlocking structure according to claim 3, characterized in that, The materials of the first adhesive layer and the second adhesive layer include titanium.

5. A hybrid bonding method based on an interlocking structure, characterized in that, include: A first chip to be bonded is provided, the surface of which is provided with a silicon oxide layer; A plurality of protruding first connectors are formed on the silicon oxide layer; Provide a second chip to be bonded; A polyimide layer with a recess is formed on the second chip to be bonded, and a second connector and a first adhesive layer are formed at the bottom of the recess. The first adhesive layer covers the surface of the second connector. The material of the first connector and the second connector includes copper and / or aluminum. The height difference of the first connector protruding from the silicon oxide layer is greater than the height difference between the top surface of the first adhesive layer and the top surface of the polyimide layer, and there is a gap between the second connector and the first adhesive layer and the recess. The first chip and the second chip to be bonded are surface treated, and thermo-press bonding is performed on the first chip and the second chip to be bonded at a first thermo-pressing temperature and a first thermo-pressing time, so that the silicon oxide layer is connected to the polyimide layer and the first connector extends into the recess and is connected to the second connector by the first adhesive layer. During the thermo-press bonding process, the polyimide layer expands due to heat to fill the reserved gap between the polyimide layer and the silicon oxide layer, the gap between the first connector and the sidewall of the recess, and the gap between the second connector and the first adhesive layer and the recess, so as to form an interlocking structure.

6. The hybrid bonding method based on an interlocking structure according to claim 5, characterized in that, The first connector is made of aluminum, and the steps for forming the first connector include: A first patterned mask layer is formed on the silicon oxide layer, having a first opening that exposes a portion of the silicon oxide layer. Metallic aluminum is deposited within the first opening to form the first connector; A second adhesive layer is formed to cover the first connector; Remove the first graphical mask layer.

7. The hybrid bonding method based on an interlocking structure according to claim 5, characterized in that, The first connector is made of copper, and the steps for forming the first connector include: A third adhesion layer and a copper seed layer are sequentially formed on the silicon oxide layer; A first patterned mask layer is formed on the copper seed layer, having a first opening that exposes a portion of the copper seed layer. A chemical electroplating process is performed to fill the first opening with a copper layer; Remove the first patterned mask layer and perform a dry etching process to remove the exposed copper seed layer and the third adhesion layer below it, using the remaining third adhesion layer, the copper seed layer and the copper layer as the first connector.

8. The hybrid bonding method based on an interlocking structure according to claim 6 or 7, characterized in that, The steps of forming the polyimide layer, the second connector, and the first adhesive layer include: A polyimide layer is formed on the surface of the second chip to be bonded; A plurality of second openings are formed in the polyimide layer to expose a portion of the second chip surface, the width of the second openings being greater than the width of the first openings, and the second openings serving as the recesses; A second patterned mask layer is formed on the surface of the polyimide layer, having a third opening that exposes a portion of the second chip surface, the third opening being directly opposite the second opening and the width of the third opening being smaller than the width of the second opening; The second connector and the first adhesive layer are sequentially formed at the bottom of the second opening. The material of the second connector includes copper and / or aluminum. The height difference of the first connector protruding from the silicon oxide layer is greater than the height difference between the top surface of the first adhesive layer and the top surface of the polyimide layer. Remove the second graphical mask layer.

9. The hybrid bonding method based on an interlocking structure according to claim 5, characterized in that, The hot-press bonding process parameters include: the first hot-press temperature is 200℃~350℃, the hot-press time is 50 minutes~90 minutes, and the hot-press pressure is 100 Newtons~1000 Newtons.

10. The hybrid bonding method based on an interlocking structure according to claim 5 or 9, characterized in that, After surface treatment of the first chip and the second chip to be bonded, hot-press bonding is performed on the first chip and the second chip to be bonded at a second hot-press temperature and a second hot-press time. Then, the first chip and the second chip to be bonded are annealed. The second hot-press temperature is lower than the first hot-press temperature and the second hot-press time is lower than the first hot-press time.

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