Power stage circuit with dual output and method thereof

Abstract

An integrated circuit includes a switch control pin, a first power unit, a second power unit, and a drive control circuit. The switch control pin is configured to receive a control signal. The first power unit has at least one power switch. The second power unit has at least one power switch. The drive control circuit is configured to provide a first drive signal to the first power unit in response to the control signal and provide a second drive signal to the second power unit in response to the control signal. In a first load condition, the first power unit is turned on to perform a switching operation, and the second power unit is turned off; and under a second load condition, both the first power unit and the second power unit are turned on to perform a switching operation.

Description

Technical Field

[0001] The present disclosure relates generally to power circuits and, more particularly but not exclusively, to voltage regulators. Background Art

[0002] Power converters such as switching voltage regulators are widely used to power electronic devices. For some portable electronic devices (such as laptops), power management is a key issue. These devices require higher power efficiency and lower power consumption under light load conditions. Various power modes or power saving functions are usually provided to save power consumption and support longer battery life. For example, in low power mode, certain functions are not executed, disabled or turned off to save quiescent current. Therefore, for power converters, it is expected to improve light load efficiency to extend the battery life of electronic devices. Summary of the invention

[0003] According to an embodiment of the present disclosure, an integrated circuit is provided. The integrated circuit includes a switch control pin, a first power unit, a second power unit and a drive control circuit. The switch control pin is configured to receive a control signal. The first power unit has at least one power switch. The second power unit has at least one power switch. The drive control circuit is configured to provide a first drive signal to the first power unit in response to the control signal, and to provide a second drive signal to the second power unit in response to the control signal. Under a first load condition, the first power unit is turned on to perform a switching operation, and the second power unit is turned off; and under a second load condition, both the first power unit and the second power unit are turned on to perform a switching operation.

[0004] According to another embodiment of the present disclosure, an integrated circuit is provided. The integrated circuit includes a switch control pin, a mode pin, a first power unit, a second power unit and a drive control circuit. The switch control pin is configured to receive a control signal. The mode pin is configured to receive a mode command. The first power unit has a first current capability. The second power unit has a second current capability, wherein the second current capability is greater than the first current capability. The drive control circuit is configured to provide a first drive signal to the first power unit in response to the control signal and the mode command, and to provide a second drive signal to the second power unit in response to the control signal and the mode command. The first power unit is located in a first region, and the second power unit is located in a second region. Each of the first power unit and the second power unit includes a first switch and a second switch. The first switch has a first end, a second end and a control end, wherein the first end of the first switch is configured to receive an input voltage. The second switch has a first end, a second end and a control end, wherein the first end of the second switch is coupled to the second end of the first switch, and the second end of the second switch is configured to be coupled to a reference voltage level.

[0005] According to another embodiment of the present disclosure, a multiphase voltage regulator is provided. The multiphase voltage regulator includes a plurality of power stage circuits and a control circuit. Each power stage circuit is configured to provide a phase current. Each power stage circuit includes at least one power switch. The control circuit is coupled to the plurality of power stage circuits. One of the plurality of power stage circuits includes a switch control pin, a first power unit, a second power unit, and a drive control circuit. The switch control pin is configured to receive a control signal from the control circuit. The first power unit has at least one power switch. The second power unit has at least one power switch. The drive control circuit is configured to provide at least one first drive signal to the first power unit in response to the control signal, and to provide at least one second drive signal to the second power unit in response to the control signal. Under a first load condition, the first power unit is turned on to perform a switching operation, and the second power unit is turned off; and under a second load condition, both the first power unit and the second power unit are turned on to perform a switching operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure may be further understood with reference to the following detailed description and accompanying drawings, in which like elements are labeled with like reference numerals. These drawings are for illustration purposes only and thus may only show a portion of a device and are not necessarily drawn to scale.

[0007] Figure 1 is a schematic block diagram of a multi-phase voltage regulator according to an embodiment of the present disclosure.

[0008] Figure 2 is a schematic diagram of a multi-phase voltage regulator according to an embodiment of the present disclosure.

[0009] Figure 3 is a schematic diagram of a multi-phase voltage regulator according to another embodiment of the present disclosure.

[0010] Figure 4A-4F is a schematic block diagram of a power stage circuit according to some embodiments of the present disclosure.

[0011] Figure 5 is a flow chart of a method 500 for controlling a power stage circuit according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0012] Various embodiments of the present disclosure will now be described. In the following description, some specific details, such as example circuits and example values ​​of these circuit components, are included to provide a comprehensive understanding of the embodiments. However, those skilled in the relevant art will recognize that the present disclosure can be implemented without one or more of the specific details, or using other methods, components, materials, etc. In other cases, in order to avoid confusing various aspects of the present disclosure, well-known structures, materials, processes, or operations are not shown or described in detail.

[0013] Throughout the specification and claims, the phrases "in one embodiment", "in some embodiments", "in one embodiment" and "in some embodiments" used include combinations and sub-combinations of the various features described herein and variations and modifications thereof. These phrases used herein do not necessarily refer to the same embodiment, although they may also refer to the same embodiment. It should be understood by those skilled in the art that the meanings of the above terms do not necessarily limit these terms, but are merely illustrative examples of these terms. Note that when an element is "connected to" or "coupled to" other elements, this means that the element is directly connected to or coupled to the other element, or indirectly connected to or coupled to the other element via another element. Specific features, structures or characteristics may be included in integrated circuits, electronic circuits, combinational logic circuits, or other suitable components that provide the described functions. In addition, it should be understood that the drawings provided herein are for explanation to those of ordinary skill in the art, and the drawings are not necessarily drawn to scale.

[0014] Figure 1is a schematic block diagram of a multi-phase voltage regulator 100 according to an embodiment of the present disclosure. The multi-phase voltage regulator 100 includes a control circuit 110 and a plurality of power stage circuits 120-1, 120-2, 120-3 ... and 120-n, where n is a natural number greater than 1. In one embodiment, each power stage circuit 120 includes at least one power switch and is configured to provide one phase of the multi-phase voltage regulator 100. The n power stage circuits are coupled in parallel, and each power stage circuit provides a phase current to the load. Each power stage circuit is configured to share an input voltage Vin and an output voltage Vout. In one embodiment, the n power stage circuits are interleaved in n phases to reduce current ripple at the input and output and improve efficiency.

[0015] In one embodiment, the multiphase voltage regulator 100 is a multiphase buck converter. However, the present disclosure is not limited thereto. The multiphase voltage regulator 100 may be a multiphase boost converter, a trans-inductor voltage regulator (TLVR), a multiphase DC-DC converter, or any multiphase converter. In some embodiments, the multiphase voltage regulator 100 is an isolated converter. In some other embodiments, the multiphase voltage regulator 100 is a non-isolated converter.

[0016] In one embodiment, the control circuit 110 is an integrated circuit (IC), and each power stage circuit in the power stage circuit 120 is an IC. Figure 1 As shown, the control circuit 110 includes n switch control pins (PWM1, PWM2, ..., PWMn) to provide n-phase control signals S to n power stage circuits 120-1, 120-2, 120-3, ..., 120-n respectively. PWM1 , S PWM2 ,……,S PWMn , used to control the corresponding power stage circuit 120. For example, the controller 110 provides a control signal S to the power stage circuit 120-1 through the switch control pin PWM1. PWM1 , providing a control signal S to the power stage circuit 120-2 through the switch control pin PWM2 PWM2 Each of the power stage circuits 120 includes a drive control circuit and power switches M1 and M2. Each of the power stage circuits 120 also includes a switch control pin PWM, a VIN pin, an output pin SW, and a PGND pin. Each of the switch control pins of the power stage circuits 120-1, 120-2, ..., 120-n receives a corresponding control signal S PWM For example, the switch control pin PWM of the power stage circuit 120-1 receives the control signal S PWM1, the switch control pin PWM of the power stage circuit 120-2 receives the control signal S PWM2 Each of the VIN pins is coupled to a voltage source terminal Vin to synchronously receive an input voltage. Each of the PGND pins is coupled to a reference voltage level (eg, ground). Each of the output pins SW is connected to a voltage source terminal Vin via an inductor L1, L2, ..., L n The corresponding inductor is coupled to the output voltage terminal Vout to provide an output voltage to the load.

[0017] Each of the drive control circuits (122-1, 122-2, . . . , and 122-n) of the power stage circuit 120 is based on the PWM control signal S PWM , providing a gate drive signal G1 to the control terminal of the power switch M1, and providing a gate drive signal G2 to the control terminal of the power switch M2. The first terminal of the power switch M1 is coupled to the VIN pin, the second terminal of the power switch M1 is coupled to the first terminal of the power switch M2 (for example, the output pin SW), and the second terminal of the power switch M2 is coupled to the PGND pin. The power switches M1 / M2 perform a switching operation by alternately turning on and off in response to the gate drive signal G1 / G2. For example, when the gate drive signal G1 / G2 is at a high voltage level (V GS ≥Vth), transistors M1 / M2 are turned on, and when the gate drive signal G1 / G2 is at a low voltage level (V GS When Vth is less than Vth), the transistors M1 / ​​M2 are turned off. The output capacitor Cout is coupled to the output voltage terminal Vout to filter the output voltage.

[0018] In one embodiment, the control circuit 110 detects the feedback signal and adjusts the control signal based on the detected feedback signal to control the power stage circuit 120. The feedback signal may be an output voltage or an output current. In another embodiment, the multi-phase voltage regulator 100 further includes a feedback circuit (not shown). The feedback circuit provides a feedback signal to the control circuit 110. The control circuit 110 provides a control signal based on the received feedback signal to adjust the operation of the power stage circuit 120. In yet another embodiment, the feedback signal is sent back to the control circuit 110 through the power stage circuit 120 so that the control signal provided to the power stage circuit 120 is adjusted by the control circuit 110. In some embodiments, the control circuit 110 adjusts the control signal provided to the power stage circuit 120 based on the data provided by the power stage circuit 120. In some embodiments, the data may include temperature information, current signals, voltage signals, fault signals, and other detection signals.

[0019] In one embodiment, each phase provides a corresponding output current, and the n phases in parallel can be switched synchronously to provide a total large output current to meet the load requirements while reducing input and output ripples. In another embodiment, the output current of each phase can be adjusted based on the load requirements.

[0020] In some embodiments, under light load conditions, i.e., when the load requires a lower output current, the multi-phase voltage regulator 100 operates in a single-phase mode. Specifically, the control circuit 110 receives a single-phase mode command, and the controller enables the first phase and disables the other phases (i.e., the second phase to the nth phase). Therefore, only the power stage circuit 120-1 is activated to provide the output load current, while the other power stage circuits 120-2 to 120-n are deactivated.

[0021] For certain light load conditions, multiphase voltage regulators are used in an out-of-phase configuration. Figure 2 is a schematic diagram of a multi-phase voltage regulator 200 according to an embodiment of the present disclosure. Figure 2 As shown, the multi-phase voltage regulator 200 includes a controller IC 210 and a plurality of power stage ICs 220-1, 220-2, and 220-3. Specifically, the power stage IC 220-1 for the first phase has a smaller power unit to provide a lower output current to the load. In addition, a larger inductor L1 is used for the power stage circuit 220-1 of the first phase. Therefore, the efficiency at light load is improved. On the other hand, for full-phase operation, all phases (i.e., all power stage ICs 220-1, 220-2, and 220-3) are activated to provide a larger output current to the load under heavy load conditions. In this case, since the power stage IC 220-1 of the first phase provides a lower output current to the load (e.g., I1<I), the current distribution and corresponding thermal power of all phases need to be considered, and the controller IC 210 must provide corresponding functions to control the power stage IC 220-1 of the first phase.

[0022] Figure 3Schematic diagram of a multiphase voltage regulator 300 according to another embodiment of the present disclosure. In this embodiment, the power stage IC 320-1 for the first phase has the same power capability as other power stage ICs 320-2 and 320-3 to provide the same phase current (e.g., I=35A) to the load. Specifically, under light load conditions, the multiphase voltage regulator 300 operates in single-phase mode. In this case, the power stage IC 320-1 includes a power unit 32 having a first current capability (e.g., I1=10A), which is turned on to perform a switching operation to provide a lower output current to the load, while another power unit 34 having a second current capability (e.g., I2=25A) is turned off. Under heavy load conditions, the multiphase voltage regulator 300 operates in full-phase mode, and all power stage ICs 320-1, 320-2, and 320-3 are turned on to perform a switching operation to provide a larger output current (e.g., 3*I=105A) to the load. In this case, both the power cell 32 and the power cell 34 of the power stage circuit 320 - 1 for phase 1 are turned on to perform a switching operation, thereby supplying a phase current (eg, I1 + I2 = I = 35 A) to the load.

[0023] Figure 4A FIG. 4 is a schematic diagram of a power stage circuit 400A according to an embodiment of the present disclosure. In this embodiment, the power stage circuit 400A is an IC. Figure 4A As shown, the power stage circuit 400A includes a first power unit 41, a second power unit 42 and a drive control circuit 430. In one embodiment, the first power unit 41 and the second power unit 42 are integrated in the power stage IC 400A but are physically separated. For example, the first power unit 41 is located in the first area and the second power unit 42 is located in the second area. The first power unit 410 includes at least one power switch M1. The second power unit 420 includes at least one power switch M2. In one embodiment, the first power unit 41 includes a drive circuit 412 for driving the power switch M1. In one embodiment, the second power unit 42 includes a drive circuit 422 for driving the power switch M2.

[0024] In one embodiment, the power stage circuit 400A further includes a switch control pin PWM and an output pin SW. The drive control circuit 430 is configured to respond to the control signal S PWM1 The first power unit 41 is provided with a first driving signal S1, and in response to the control signal S PWM1A second drive signal S2 is provided to the second power unit 42. In one embodiment, when the drive signal S1 / S2 is at a high voltage level, the power unit 41 / 42 is turned on to perform a switching operation, and when the drive signal S1 / S2 is at a low voltage level, the power unit 41 / 42 is turned off to stop the switching operation. The first power unit 41 receives the first drive signal S1 and provides an output voltage signal to the load at the output pin SW through the inductor L1. The second power unit 42 receives the second drive signal S2 and provides an output voltage signal to the load at the output pin SW through the inductor L1.

[0025] In one embodiment, the PWM control signal indicates a load condition. Under a first load condition, the first power unit 41 is turned on to perform a switching operation, and the second power unit is turned off. On the other hand, under a second load condition, both the first power unit 41 and the second power unit 42 are turned on to perform a switching operation.

[0026] For example, when the PWM indicates a light load condition, the first power unit 41 is enabled and the second power unit 42 is disabled to provide a first current (eg, 10 A) to the load.

[0027] In another embodiment, the PWM control signal indicates the power mode. For example, when the switch control signal S PWM1 When the low power mode is indicated, the first power unit 42 having a first current capability (eg, 10A) is enabled to provide a first current to the load, and the second power unit 42 is disabled. PWM1 When the high power mode is indicated, the second power unit 42 having a higher current capability (eg, 25A) than the first power unit 41 is enabled to provide a second current to the load, while the first power unit 41 is disabled. PWM1 When the normal operating mode is indicated, both the first power unit 41 and the second power unit 42 are enabled to provide a total output current (eg, 35 A) to the load.

[0028] Figure 4B4 is a schematic diagram of a power stage circuit 400B according to another embodiment of the present disclosure. It should be noted that the drive control circuit 430 is not shown. In this embodiment, each of the first power unit 410 and the second power unit 420 includes two power switches. Specifically, the switch MH1 has a first end configured to receive an input voltage Vin, a second end coupled to the first end of the switch ML1, and a control end receiving a gate drive signal from the drive circuit 412. The switch ML1 has a first end coupled to the switch MH1 and the output pin SW, a second end configured to be coupled to a reference voltage level (e.g., ground), and a control end receiving a gate drive signal from the drive circuit 412. Similarly, switches MH2 and ML2 are coupled in series between an input node receiving the input voltage Vin and a reference node receiving the reference voltage level. The control end of the switch MH2 is configured to receive a gate drive signal from the drive circuit 422. The control end of the switch ML2 is configured to receive a gate drive signal from the drive circuit 422.

[0029] Figure 4C FIG. 4 is a schematic diagram of a power stage circuit 400C according to another embodiment of the present disclosure. In this embodiment, the power stage circuit 400C includes a first output pin SW1 coupled to the first power unit 430, and a second output pin SW2 coupled to the second power unit 440. Figure 4C As shown, the first power unit 430 is connected to the inductor L P1 The first output pin SW1 provides a first current I1 to the load. The second power unit 410 is connected to the load through the inductor L P2 The second output pin SW2 provides a second current I2 to the load. In this embodiment, the inductor L P1 The inductance value is greater than the inductance L P2 The inductance value of the inductor L1 is greater than or equal to the inductance value of the inductor L1 to further improve the efficiency under light load conditions. The sum of the first current I1 and the second current I2 is a phase current I of the multi-phase voltage regulator.

[0030] Figure 4D 4 is a schematic diagram of a power stage circuit 400D according to another embodiment of the present disclosure. In this embodiment, the first power unit 43 includes drive circuits 412 and 414 to provide gate drive signals to switches MH1 and ML1, respectively. The second power unit 43 includes drive circuits 412 and 414 to provide gate drive signals to switches MH1 and ML1, respectively.

[0031] Figure 4Eis a schematic diagram of a power stage circuit 400E according to another embodiment of the present disclosure. In the present embodiment, the power stage circuit 400E further includes a mode pin PS coupled to the first power unit 450 and the second power unit 460. In this embodiment, a mode command is received from the controller IC via the mode pin PS. For example, the mode command indicates a load condition. A light load condition may include a standby mode, a sleep mode, an idle mode, or a low power mode. When the mode command indicates a light load condition, the first power unit 450 is turned on to perform a switching operation, and the second power unit 460 is turned off. When the mode command indicates a heavy load condition, the first power unit 450 and the second power unit 460 are turned on to perform a switching operation.

[0032] In one embodiment, the mode command indicates single-phase operation. When the mode command indicates single-phase operation, the first power unit 450 is turned on to perform a switching operation, and the second power unit 460 is turned off. In another embodiment, the mode command indicates full-phase operation. When the mode command indicates full-phase operation, the first power unit 450 and the second power unit 460 are turned on to perform a switching operation.

[0033] In certain embodiments, the mode command instructs the power unit 450 / 460 to enable and / or disable switching operations.

[0034] In some other embodiments, the mode command indicates continuous conduction mode (CCM) operation. When the mode command indicates CCM operation, the first power unit 450 and the second power unit 4601 are turned on to perform switching operation. In some other embodiments, the mode command indicates discontinuous conduction mode (DCM) operation. When the mode command indicates DCM operation, the first power unit 450 is turned on to perform switching operation, and the second power unit 460 is turned off.

[0035] Figure 4F4 is a schematic diagram of a power stage circuit 400F according to another embodiment of the present disclosure. In this embodiment, the power stage circuit 400F further includes a BST1 pin and a BST2 pin. The BST1 pin is configured to be coupled to a bootstrap circuit to receive a bootstrap voltage to drive the power switch MH1. For example, the BST capacitor is connected between the BST1 pin and the SW1 pin. Similarly, the BST2 pin is configured to be coupled to a bootstrap circuit to receive a bootstrap voltage to drive the power switch MH2. That is, the drive circuit 472 of the first power unit 470 and the drive circuit 482 of the second power unit 480 are physically separated. Therefore, when only the first power unit 470 is enabled under light load conditions, since the drive circuit 482 of the second power unit 480 is not connected to the drive circuit 472 and receives the bootstrap voltage through the independent BST2 pin, power loss can be reduced.

[0036] Figure 5 FIG. 5 is a flow chart of a method 500 for controlling a power stage circuit according to an embodiment of the present disclosure. The method may be performed as follows: Figure 4A-4F The method 500 is performed by the power stage circuit 400A-400F shown. The method 500 includes the following actions. In action 510, a switch control signal and a mode command are received. In action 520, it is determined whether the mode command indicates a light load condition. When the mode command indicates that a light load condition is received, as shown in action 530, a first current is provided to the load by turning on the first power unit and turning off the second power unit. In one embodiment, when the mode command indicates normal operation, as shown in action 540, a second current is provided to the load by turning on both the first power unit and the second power unit. In another embodiment, a third current is provided to the load by turning on the second power unit and turning off the first power unit in response to the mode command. Although Figure 5 The flow chart of FIG. 4 shows sequential actions. For those skilled in the art, it is obvious that these actions can be performed in any order.

[0037] It should be understood that the circuits and related components, circuit structures, signals and waveforms described or shown above in the present disclosure are for illustrative purposes only. However, the present disclosure is not limited thereto. It will be appreciated by those of ordinary skill in the art that, depending on the actual application, the control circuit of the present disclosure may be implemented by any other circuit having a different circuit structure, thereby being controlled by different types of corresponding signals to achieve the corresponding functions. For example, the circuit may be implemented by a digital circuit, an analog circuit, software, an automatically generated circuit by a hardware description language, or a combination thereof.

[0038] It will be appreciated by those skilled in the art that the present disclosure is not limited to what is specifically shown and described above. On the contrary, the scope of the present disclosure is defined by the claims, and includes combinations and sub-combinations of the various features described above, as well as changes and modifications that would occur to those skilled in the art upon reading the foregoing description and that are not in the prior art.

Claims

1. An integrated circuit, comprising: a switch control pin configured to receive a control signal; A first power unit having at least one power switch; A second power unit having at least one power switch; and a drive control circuit configured to provide a first drive signal to the first power unit in response to the control signal, and to provide a second drive signal to the second power unit in response to the control signal; Wherein, under a first load condition, the first power unit is turned on to perform a switching operation, and the second power unit is turned off; and under a second load condition, both the first power unit and the second power unit are turned on to perform a switching operation.

2. The power stage circuit according to claim 1, wherein: Each of the first power unit and the second power unit includes: A first switch having a first terminal, a second terminal and a control terminal, wherein the first terminal of the first switch is configured to receive an input voltage; and The second switch has a first end, a second end and a control end, wherein the first end of the second switch is coupled to the second end of the first switch, and the second end of the second switch is configured to be coupled to a reference voltage level.

3. The integrated circuit of claim 2, further comprising: An output pin is configured to provide a phase current of a multi-phase voltage regulator, wherein the output pin is coupled to the first end of the second switch of the first power unit and the first end of the second switch of the second power unit.

4. The integrated circuit of claim 2, further comprising: A first output pin coupled to the first end of the second switch of the first power unit, wherein the first output pin is configured to provide a first current; and a second output pin coupled to the first end of the second switch of the second power unit, wherein the second output pin is configured to provide a second current; The sum of the first current and the second current is a single-phase current of the multi-phase voltage regulator.

5. The integrated circuit according to claim 1, wherein: The control signal indicates a power mode.

6. The integrated circuit of claim 1, wherein: The control signal is indicative of a load condition.

7. The integrated circuit of claim 1 , further comprising: a mode pin coupled to the first power unit and the second power unit, wherein the mode pin is configured to receive a mode command; When the mode command indicates a light load condition, the first power unit is turned on and the second power unit is turned off.

8. The integrated circuit of claim 1 , further comprising: a mode pin coupled to the first power unit and the second power unit, wherein the mode pin is configured to receive a mode command; When the mode command indicates a heavy load condition, the first power unit and the second power unit are turned on to perform a switching operation.

9. The integrated circuit of claim 1 , further comprising: a mode pin coupled to the first power unit and the second power unit, wherein the mode pin is configured to receive a mode command; Wherein, when the mode command indicates a discontinuous conduction mode (DCM) operation, the first power unit is turned on to perform a switching operation, and the second power unit is turned off.

10. The integrated circuit of claim 1, further comprising: a mode pin coupled to the first power unit and the second power unit, wherein the mode pin is configured to receive a mode command; When the mode command indicates a continuous conduction mode (CCM) operation, the first power unit and the second power unit are turned on to perform a switching operation.

11. The integrated circuit of claim 1 , further comprising: a mode pin coupled to the first power unit and the second power unit, wherein the mode pin is configured to receive a mode command; When the mode command indicates single-phase operation, the first power unit is turned on to perform a switching operation, and the second power unit is turned off.

12. The integrated circuit of claim 1 , further comprising: a mode pin coupled to the first power unit and the second power unit, wherein the mode pin is configured to receive a mode command; Wherein, when the mode command indicates full-phase operation, the first power unit and the second power unit are turned on to perform switching operation.

13. An integrated circuit comprising: a switch control pin configured to receive a control signal; Mode pins, configured to receive mode commands; A first power unit having a first current capability; A second power unit having a second current capability, wherein the second current capability is greater than the first current capability; a drive control circuit configured to provide a first drive signal to the first power unit in response to the control signal and the mode command, and to provide a second drive signal to the second power unit in response to the control signal and the mode command; wherein the first power unit is located in a first region, and the second power unit is located in a second region; Wherein, each of the first power unit and the second power unit comprises: A first switch having a first terminal, a second terminal and a control terminal, wherein the first terminal of the first switch is configured to receive an input voltage; and The second switch has a first end, a second end and a control end, wherein the first end of the second switch is coupled to the second end of the first switch, and the second end of the second switch is configured to be coupled to a reference voltage level.

14. The power stage circuit according to claim 13, further comprising: a first output pin coupled to the first end of the second switch of the first power unit, wherein the first output pin is configured to be coupled to a first inductor; and A second output pin is coupled to the first end of the second switch of the second power unit, wherein the second output pin is configured to be coupled to a second inductor, wherein the inductance value of the first inductor is greater than the inductance value of the second inductor.

15. The integrated circuit of claim 14, wherein: When the mode command indicates a light load condition, the first power unit is turned on to provide a first current to a load via the first output pin.

16. The integrated circuit of claim 14, wherein: When the mode command indicates a heavy load condition, the first power unit is turned on to provide a first current to the load via the first output pin, and the second power unit is turned on to provide a second current to the load via the second output pin; wherein the sum of the first current and the second current is a phase current of the multi-phase voltage regulator.

17. A multiphase voltage regulator comprising: a plurality of power stage circuits, each power stage circuit being configured to provide a phase current, wherein each power stage circuit comprises at least one power switch; and a control circuit coupled to the plurality of power stage circuits; Wherein, one of the multiple power stage circuits comprises: a switch control pin configured to receive a control signal from a control circuit; A first power unit having at least one power switch; A second power unit having at least one power switch; and a drive control circuit configured to provide at least one first drive signal to the first power unit in response to the control signal, and to provide at least one second drive signal to the second power unit in response to the control signal, Wherein, under a first load condition, the first power unit is turned on to perform a switching operation, and the second power unit is turned off; and under a second load condition, both the first power unit and the second power unit are turned on to perform a switching operation.

18. The multiphase voltage regulator according to claim 17, wherein: Each of the first power unit and the second power unit includes: A first switch having a first terminal, a second terminal and a control terminal, wherein the first terminal of the first switch is configured to receive an input voltage; and The second switch has a first end, a second end and a control end, wherein the first end of the second switch is coupled to the second end of the first switch, and the second end of the second switch is configured to be coupled to a reference voltage level.

19. The multiphase voltage regulator of claim 17, further comprising: A first output pin coupled to the first end of the second switch of the first power unit, wherein the first output pin is configured to provide a first current; and a second output pin coupled to the first end of the second switch of the second power unit, wherein the second output pin is configured to provide a second current; The sum of the first current and the second current is a single-phase current.

20. The multiphase voltage regulator of claim 17, further comprising: a mode pin coupled to the first power unit and the second power unit, wherein the mode pin is configured to receive a mode command; When the mode command indicates a light load condition, the first power unit is turned on and the second power unit is turned off.

21. The multiphase voltage regulator of claim 17, further comprising: a mode pin coupled to the first power unit and the second power unit, wherein the mode pin is configured to receive a mode command; When the mode command indicates a discontinuous conduction mode (DCM) operation, the first power unit is turned on and the second power unit is turned off.

22. The multiphase voltage regulator of claim 17, further comprising: a mode pin coupled to the first power unit and the second power unit, wherein the mode pin is configured to receive a mode command; Wherein, when the mode command indicates full-phase operation, the first power unit and the second power unit are turned on.

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