Fault-tolerant dual active bridge converter based on half-bridge multiplexing and control method

Abstract

The application discloses a fault-tolerable dual active bridge converter based on half-bridge multiplexing and a control method, and belongs to the technical field of converters. m The capacitor C 11 and the capacitor C 12 are connected in series and are connected in parallel with the leading bridge, the primary end of the intermediate-tapped transformer is connected with the direct-current inductor L1 and the direct-current inductor L2 respectively, then the primary end of the intermediate-tapped transformer is connected with the leading bridge, the intermediate tap of the primary end of the intermediate-tapped transformer is connected between the capacitor C 11 and the capacitor C 12 ; the secondary end of the intermediate-tapped transformer is connected with the lagging bridge, the capacitor C 21 and the capacitor C 22 are connected in series and are connected in parallel with the lagging bridge, and the intermediate tap of the secondary end of the intermediate-tapped transformer is connected between the capacitor C 21 and the capacitor C 22 . The application can realize stable output in the case of wide-range voltage input and partial device failure.

Description

TECHNICAL FIELD

[0001] The application relates to a fault-tolerant dual active bridge converter based on half-bridge multiplexing and a control method, and belongs to the technical field of converters. BACKGROUND

[0002] With the increasing popularity of new power systems, in high-latitude cold regions, continuous cold and warm cycles may accelerate the aging process of components, causing device failure problems. In addition, in the face of the geographical feature of serious unevenness of solar radiation in winter and summer, the periodic sharp fluctuations of power production will also have a negative impact on the frequency modulation characteristics of the power grid and the stability of the system. Using a bidirectional DC-DC converter as a key component connecting the photovoltaic DC bus and the energy storage system can maintain the stability of the power grid voltage and improve the power quality of the DC power grid.

[0003] The dual active bridge converter DAB is widely used in various fields due to its advantages of current isolation, soft switching, and output wide range voltage. In order to improve the reliability of the system, many experts and scholars have conducted in-depth research on system faults and fault tolerance of DAB. In actual application, when the drain-source voltage of MOSFET changes too fast, the equivalent parallel NPN junction will be forced to conduct, which will cause the MOSFET to be short-circuited. In addition, the loss of MOSFET drive voltage, the disconnection of signal lines or poor contact of connection ports, etc. will also cause the MOSFET to be open-circuit fault, thereby affecting the stability and reliability of the system.

[0004] At present, for the medium and low voltage DC power distribution system containing the DAB converter, the fault current blocking module and the compensation capacitor branch are usually added in the system, and the current limiting inductor L c and the current limiting resistor R c, to slow down the capacitor discharge speed before the switch tube is blocked after the fault occurs and reduce the current peak value. During the fault duration, the system relies on the remaining power of the capacitor to provide short-term power supply for the load, reduces the impact of the voltage drop on the low-voltage side, and maximizes the impact of the inter-electrode short-circuit fault on the medium-voltage side. Since switch short-circuit fault usually causes switch damage, making the converter unable to operate normally, most existing researches on DAB converter short-circuit fault focus on fault ride-through of output short-circuit fault. Some researches deduce the transient expressions of internal current, output voltage and output current during the transient process of DAB converter under output short-circuit fault. The research proposes a method of connecting an inductor in series at the output end to reduce the overcurrent phenomenon and achieve short-circuit fault ride-through. This method can ensure that the circuit can run again after the fault is cleared, and provides a suitable value range for the inductor in series at the output end. In order to solve the problem of open-circuit fault OCSF, some documents propose to use redundancy technology to realize fault tolerance. There is also a scheme to add an additional redundant switch in the converter to ensure that the system can quickly recover to normal working state when open-circuit fault occurs. The fault switch can also be identified by the inductor current waveform and the change of the primary and secondary full-bridge output voltage waveform. This method can detect the position of the fault switch as soon as the fault impact occurs, the detection delay is short, and the OCSF can be detected quickly and the fault tolerance mode can be enabled immediately. The fault switch positioning method based on the information of the near-field magnetic field of the line can determine the position of the fault switch by observing the characteristics of a specific frequency through Fourier transform of the waveform containing magnetic field information. However, the accuracy of this method is affected by the position of the annular magnetic field probe, and Fourier analysis needs one cycle of time, so the detection delay is at least one cycle, and the system cannot switch to fault tolerance mode immediately after the fault occurs. SUMMARY

[0005] In view of the poor fault tolerance of the existing dual active bridge converter, the application provides a fault-tolerant dual active bridge converter based on half-bridge multiplexing and a control method.

[0006] The fault-tolerant dual active bridge converter based on half-bridge multiplexing comprises a multiplexing half-bridge, a direct-current inductor L m , a leading bridge, a capacitor C 11 , a capacitor C 12 , an intermediate tap transformer with a turn ratio of n:1, a direct-current inductor L1, a direct-current inductor L2, a lagging bridge, a capacitor C 21 and a capacitor C 22 ,

[0007] The multiplexing half-bridge is connected with the leading bridge through the direct-current inductor L m , the capacitor C 11 and the capacitor C 12After being connected in series, it is connected in parallel with the bridge. The two ends of the primary side of the center-tapped transformer are connected to DC inductors L1 and L2 respectively, and then connected to the bridge. The center tap of the primary side of the center-tapped transformer is connected to capacitor C. 11 and capacitor C 12 between;

[0008] The secondary side of the center-tapped transformer is connected to the hysteresis bridge, and capacitor C... 21 and capacitor C 22 After being connected in series, it is connected in parallel with the lag bridge. The center tap of the secondary side of the center-tapped transformer is connected to capacitor C. 21 and capacitor C 22 between.

[0009] According to the present invention, the fault-tolerant dual active bridge converter based on half-bridge multiplexing includes a switch Q1 and a switch Q2. The drain of switch Q1 is connected to the positive terminal of power supply V1, the source of switch Q1 is connected to the drain of switch Q2, and the source of switch Q2 is connected to the negative terminal of power supply V1. A capacitor C1 is connected between the drain of switch Q1 and the source of switch Q2.

[0010] The lead bridge includes switching transistors S1, S2, S3, and S4. The drain of switching transistor S1 is connected to the drain of switching transistor S3, the source of switching transistor S1 is connected to the drain of switching transistor S2, the source of switching transistor S2 is connected to the source of switching transistor S4, and the drain of switching transistor S4 is connected to the source of switching transistor S3; DC inductor L m It is connected between the source of switch Q1 and the source of switch S1;

[0011] The drain capacitor C of the switching transistor S1 11 One end of the capacitor C 11 The other end is connected to capacitor C 12 One end of the capacitor C 12 The other end is connected to the source of switching transistor S2; the source of switching transistor S1 is connected to one end of DC inductor L1, the other end of DC inductor L1 is connected to one end of the primary winding of the center-tapped transformer, the other end of the primary winding of the center-tapped transformer is connected to one end of DC inductor L2, the other end of DC inductor L2 is connected to the drain of switching transistor S4, and the center tap of the primary winding of the center-tapped transformer is connected to capacitor C. 11 The other end.

[0012] According to the fault-tolerant dual active bridge converter based on half-bridge multiplexing of the present invention, the hysteresis bridge includes switches S5, S6, S7, and S8. The drain of switch S5 is connected to the drain of switch S7, the source of switch S5 is connected to the drain of switch S6, the source of switch S6 is connected to the source of switch S8, and the drain of switch S8 is connected to the source of switch S7. One end of the secondary side of the intermediate tap transformer is connected to the source of switch S5, and the other end of the secondary side of the intermediate tap transformer is connected to the drain of switch S8. The drain of switch S7 is connected to capacitor C. 21 One end of the capacitor C 21 The other end is connected to capacitor C 22 One end of the capacitor C 22 The other end is connected to the source of the switching transistor S8; the center tap of the secondary side of the center-tapped transformer is connected to capacitor C. 21 The other end; capacitor C 21 one end and capacitor C 22 The other end is connected to the load R L .

[0013] The present invention also provides a control method for a fault-tolerant dual active bridge converter based on half-bridge multiplexing, wherein the fault-tolerant dual active bridge converter based on half-bridge multiplexing is controlled and one control cycle includes five modes.

[0014] In mode 1, during the time interval [t0, t1], before the gate drive signal of switch Q1 arrives, switch Q2 is turned off; when the gate drive signal of switch Q1 arrives, switch Q1 achieves zero-voltage turn-on; where t0 is the start time for switch Q1, switch S1 and switch S4 to turn on, and t1 is the start time for switch S5 and switch S8 to turn on.

[0015] In mode 2, during the time interval [t1, t2], switches S6 and S7 are turned off, and the voltages across switches S5 and S8 are clamped to zero. When the gate drive signal for switches S1 and S8 arrives at time t1, switches S5 and S8 are turned on with zero voltage. Time t2 is the start time when switch Q1 is turned off.

[0016] In mode 3, during the time interval [t2, t3], switch Q1 is turned off, and the voltage across switch Q2 is clamped to zero; when the gate drive signal for switch Q2 arrives at time t2, switch Q2 achieves zero-voltage turn-on; time t3 is the start time when switches S1 and S4 are turned off.

[0017] Mode four, in the time period [t3, t4], make switch tube S1 and switch tube S4 off, the voltage across switch tube S2 and switch tube S3 is clamped to zero; at t4, when the gate drive signal of switch tube S2 and switch tube S3 arrives, switch tube S2 and switch tube S3 realize zero voltage turn-on; t4 is the starting time of switch tube S5 and switch tube S8 off;

[0018] Mode five, in the time period [t4, t5], make switch tube S5 and switch tube S8 off, the voltage across switch tube S6 and switch tube S7 is clamped to zero; at t5, when the gate drive signal of switch tube S6 and switch tube S7 arrives, switch tube S6 and switch tube S7 realize zero voltage turn-on; t5 is the starting time of switch tube Q1, switch tube S1 and switch tube S4 turn-on again.

[0019] According to the control method of the fault-tolerant dual active bridge converter based on half-bridge multiplexing, in mode one, the current i m (t) of the DC inductor L Lm is:

[0020]

[0021] In the formula, t represents time,

[0022] C 11 =C 12 , let C k =C 11 =C 12 , V Ck represents the voltage across C k ;

[0023]

[0024] In the formula, v priL represents the lower voltage of the primary side AC square wave, v priH represents the upper voltage of the primary side AC square wave, v pri represents the primary side AC square wave, v secL represents the lower voltage of the secondary side AC square wave, v secH represents the upper voltage of the secondary side AC square wave, v sec represents the secondary side AC square wave;

[0025]

[0026] In the formula, v L1 is the voltage across the DC inductor L1, v L2 is the voltage across the DC inductor L2;

[0027]

[0028] In the formula, iLp1 is the inductive current on the primary side of the intermediate tap transformer, V2 is the load R L voltage across; i Lp2 is the inductive current on the primary side of the intermediate tap transformer, V2 is the load R

[0029] L k = L1 = L2.

[0030] According to the control method of the fault-tolerant dual active bridge converter based on half-bridge multiplexing of the application, in mode two,

[0031]

[0032] According to the control method of the fault-tolerant dual active bridge converter based on half-bridge multiplexing of the application, in mode three,

[0033]

[0034]

[0035] According to the control method of the fault-tolerant dual active bridge converter based on half-bridge multiplexing of the application, in mode four,

[0036] i Lm (t) = i Lm (t3),

[0037]

[0038] According to the control method of the fault-tolerant dual active bridge converter based on half-bridge multiplexing of the application, in mode five,

[0039] i Lm (t) = i Lm (t3),

[0040]

[0041] According to the control method of the fault-tolerant dual active bridge converter based on half-bridge multiplexing of the application, in mode five,

[0042]

[0043] i L1 = i Lp1 - i Lp2 = 0;

[0044] where k is the transformer input-output voltage ratio, f s is the switching frequency, D is the duty ratio of the switch Q1 and the switch Q2, d D is the phase shift ratio of the switch S1 and the switch S5, i L1The intermediate tap transformer intermediate tap branch current.

[0045] The present application is directed to the voltage instability phenomenon caused by device failure and serious unevenness of sunshine in high-latitude cold regions, and proposes a converter and control method. The converter can still have stable output under wide range voltage input and partial device failure, and can maintain grid voltage stability and improve DC grid power quality.

[0046] The present application introduces a multiplexing half-bridge on the basis of the traditional dual active DC-DC converter, and proposes an improved circuit with fault tolerance capability for switch tube failure. The multiplexing half-bridge can be applied to a wider input to adapt to unstable voltage of photovoltaic power generation. Through two auxiliary inductors and a transformer with a central tap, the equivalent half-bridge circuit can be flexibly reconfigured to adapt to the fault situation after fault response and system reconstruction. Compared with the traditional fault tolerance measures and the existing reconfigurable DAB converter, the topology structure of the present application can still maintain high efficient and stable power transmission capability when facing multiple open circuit faults, and exhibits excellent performance advantage. BRIEF DESCRIPTION OF DRAWINGS

[0047] Figure 1 is the topology structure diagram of the fault-tolerant dual active bridge converter based on half-bridge multiplexing according to the present application; D1 to D8 in the figure are body diodes corresponding to S1 to S8;

[0048] Figure 2 is the drive waveform diagram of the switch tube in the control method of the fault-tolerant dual active bridge converter based on half-bridge multiplexing according to the present application in one working cycle; T S is the switching period;

[0049] Figure 3 is the conversion waveform diagram corresponding to each time of Figure 2 ; v Lm is the DC inductor L m voltage across two ends, i Ls1 is the inductor current on the secondary side of the intermediate tap transformer;

[0050] Figure 4 is the circuit structure diagram of mode one;

[0051] Figure 5 is the circuit structure diagram of mode two;

[0052] Figure 6 is the circuit structure diagram of mode three;

[0053] Figure 7 is the circuit structure diagram of mode four;

[0054] Figure 8is the circuit structure diagram of mode five;

[0055] Figure 9 is the circuit structure diagram under fault condition 2;

[0056] Figure 10 is the drive waveform and transform waveform diagram under fault condition 2;

[0057] Figure 11 is the circuit structure diagram under fault condition 3;

[0058] Figure 12 is the drive waveform and transform waveform diagram under fault condition 3;

[0059] Figure 13 is the waveform diagram under normal working condition in the verification experiment; in the diagram, i Lp1 is the inductance current at the primary side of the intermediate-tapped transformer, V S1 is the voltage across the switch tube S1, V gs1 is the gate drive voltage of the switch tube S1, V S2 is the voltage across the switch tube S2, V gs2 is the gate drive voltage of the switch tube S2, V S5 is the voltage across the switch tube S5, V gs5 is the gate drive voltage of the switch tube S5, V S6 is the voltage across the switch tube S6, V gs6 is the gate drive voltage of the switch tube S6;

[0060] Figure 14 is the waveform diagram under fault tolerance condition 2 in the verification experiment; in the diagram, i Lp2 is the inductance current at the primary side of the intermediate-tapped transformer, V S3 is the voltage across the switch tube S3, V gs3 is the gate drive voltage of the switch tube S3, V S4 is the voltage across the switch tube S4, V gs4 is the gate drive voltage of the switch tube S4;

[0061] Figure 15 is the waveform diagram under fault tolerance condition 3 in the verification experiment; in the diagram, V S8 is the voltage across the switch tube S8, V gs8 is the gate drive voltage of the switch tube S8. DETAILED DESCRIPTION

[0062] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of the present application.

[0063] It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0064] The present application will be further described below in combination with the drawings and specific embodiments, but is not limited to the present application.

[0065] Specific embodiment one, in combination Figure 1 As shown in the drawings, the present application provides a fault-tolerant dual active bridge converter based on half-bridge multiplexing, which comprises a multiplexing half-bridge, a DC inductor L m , a leading bridge, a capacitor C 11 , a capacitor C 12 , an intermediate tap transformer with a turn ratio of n:1, a DC inductor L1, a DC inductor L2, a lagging bridge, a capacitor C 21 and a capacitor C 22 ,

[0066] The multiplexing half-bridge is connected with the leading bridge through the DC inductor L m , and the capacitor C 11 and the capacitor C 12 are connected in series and connected in parallel with the leading bridge, the primary side of the intermediate tap transformer is connected with the leading bridge after being connected with the DC inductor L1 and the DC inductor L2 respectively, and the intermediate tap of the primary side of the intermediate tap transformer is connected between the capacitor C 11 and the capacitor C 12 .

[0067] The secondary side of the intermediate tap transformer is connected with the lagging bridge, and the capacitor C 21 and the capacitor C 22 are connected in series and connected in parallel with the lagging bridge, and the intermediate tap of the secondary side of the intermediate tap transformer is connected between the capacitor C 21 and the capacitor C 22 .

[0068] In the present embodiment, the leading bridge and the lagging bridge are connected by an intermediate tap transformer with a turn ratio of n:1. The half-bridge capacitor is divided into two equal parts, i.e. C 11 / C 12 and C 21 / C 22 . In addition, the conventional auxiliary inductor is replaced by two symmetrical inductors L1 and L2. A multiplexing half-bridge composed of switch tubes Q1 and Q2 is added before the leading bridge, and a DC inductor Lm The input and output voltages are defined as VI and V2, respectively, whose resistance characteristics are related to the specific load and are represented as equivalent resistance R eq In addition, the center-tapped transformer replaces the transformer directly connected to the capacitor C 11 / C 12 or C 21 / C 22 in the traditional sense.

[0069] Further, the multiplexing half-bridge includes a switch tube Q1 and a switch tube Q2, the drain of the switch tube Q1 is connected to the positive pole of a power supply VI, the source of the switch tube Q1 is connected to the drain of the switch tube Q2, the source of the switch tube Q2 is connected to the negative pole of the power supply VI; a capacitor C1 is connected between the drain of the switch tube Q1 and the source of the switch tube Q2.

[0070] The leading bridge includes a switch tube S1, a switch tube S2, a switch tube S3 and a switch tube S4, the drain of the switch tube S1 is connected to the drain of the switch tube S3, the source of the switch tube S1 is connected to the drain of the switch tube S2, the source of the switch tube S2 is connected to the source of the switch tube S4, the drain of the switch tube S4 is connected to the source of the switch tube S3; a direct current inductor L m is connected between the source of the switch tube Q1 and the source of the switch tube S1;

[0071] The drain of the switch tube S1 is connected to one end of a capacitor C 11 , the other end of the capacitor C 11 is connected to one end of a capacitor C 12 , the other end of the capacitor C 12 is connected to the source of the switch tube S2; the source of the switch tube S1 is connected to one end of a direct current inductor L1, the other end of the direct current inductor L1 is connected to one end of a primary side of a center-tapped transformer, the other end of the primary side of the center-tapped transformer is connected to one end of a direct current inductor L2, the other end of the direct current inductor L2 is connected to the drain of the switch tube S4, and the middle tap of the primary side of the center-tapped transformer is connected to the other end of the capacitor C 11 .

[0072] The lagging bridge includes a switch tube S5, a switch tube S6, a switch tube S7 and a switch tube S8, the drain of the switch tube S5 is connected to the drain of the switch tube S7, the source of the switch tube S5 is connected to the drain of the switch tube S6, the source of the switch tube S6 is connected to the source of the switch tube S8, and the drain of the switch tube S8 is connected to the source of the switch tube S7; one end of a secondary side of a center-tapped transformer is connected to the source of the switch tube S5, and the other end of the secondary side of the center-tapped transformer is connected to the drain of the switch tube S8; the drain of the switch tube S7 is connected to one end of a capacitor C 21 , the other end of the capacitor C 21 is connected to one end of a capacitor C 22 , and the other end of the capacitor C 22The other end of the switch tube S8 is connected to the source; the middle tap of the secondary side of the transformer is connected to the capacitor C 21 The other end of the capacitor C 21 The one end of the capacitor C 22 The other end of the capacitor C L .

[0073] Specific implementation two, as shown in the combination Figures 1 to 8 The application also provides a control method of a fault-tolerant dual active bridge converter based on half-bridge multiplexing, which controls the fault-tolerant dual active bridge converter based on half-bridge multiplexing described in the specific implementation one, and one control period includes five modes.

[0074] Mode one, in the time period [t0, t1], the switch tube Q2 is turned off before the gate drive signal of the switch tube Q1 arrives; due to the freewheeling effect of the inductor current, the reverse current discharges the parasitic capacitor of the body diode of the switch tube Q1, so that the voltage across the switch tube Q2 is clamped to zero; when the gate drive signal of the switch tube Q1 arrives, the switch tube Q1 is turned on at zero voltage; wherein the time t0 is the starting time of the turn-on of the switch tube Q1, the switch tube S1 and the switch tube S4, at this time, the complementary conduction switch tubes Q2, S2 and S3 are in the off state; the time t1 is the starting time of the turn-on of the switch tube S5 and the switch tube S8, at this time, the complementary conduction switch tubes S6 and S7 are in the off state; the complementary conduction switch states are opposite.

[0075] Mode two, in the time period [t1, t2], the switch tube S6 and the switch tube S7 are turned off; due to the freewheeling effect of the inductor current, the reverse current discharges the parasitic capacitor of the body diode of the switch tube S5 and S8, so that the voltage across the switch tube S5 and the switch tube S8 is clamped to zero; when the gate drive signal of the switch tube S1 and the switch tube S8 arrives at the time t1, the switch tube S5 and the switch tube S8 are turned on at zero voltage; the time t2 is the starting time of the turn-off of the switch tube Q1.

[0076] Mode three, in the time period [t2, t3], the switch tube Q1 is turned off, the reverse current discharges the parasitic capacitor of the body diode of the switch tube Q2, and the voltage across the switch tube Q2 is clamped to zero; when the gate drive signal of the switch tube Q2 arrives at the time t2, the switch tube Q2 is turned on at zero voltage; the time t3 is the starting time of the turn-off of the switch tube S1 and the switch tube S4.

[0077] In mode four, during the time interval [t3, t4], switches S1 and S4 are turned off, and the inductor current discharges the parasitic capacitance of the body diodes of switches S2 and S3, clamping the voltage across switches S2 and S3 to zero. When the gate drive signal for switches S2 and S3 arrives at time t4, switches S2 and S3 achieve zero-voltage turn-on. Time t4 is the starting time for switches S5 and S8 to turn off.

[0078] In mode 5, during the time interval [t4, t5], switches S5 and S8 are turned off to compensate for the parasitic capacitance of the body diodes of switches S6 and S7 caused by the inductor current, and the voltage across switches S6 and S7 is clamped to zero. At time t5, when the gate drive signal for switches S6 and S7 arrives, switches S6 and S7 achieve zero-voltage turn-on. Time t5 is the starting time for switches Q1, S1, and S4 to turn on again.

[0079] Furthermore, Figure 1 The outputs of the upper and lower conduction paths of the primary side full-bridge converter shown are transmitted via AC square waves, respectively, in the form of v priH and v priL This design, through its symmetrical structure, achieves more efficient power transmission and stability under open-circuit fault conditions. Simultaneously, the AC output square wave of the primary full-bridge is labeled as v. pri The secondary output square wave is denoted as v. secH v secL and v sec The converter employs a phase-shift control strategy, and its waveform under normal operating conditions is shown in the figure below. Figure 2 and Figure 3 As shown, there are five working modes, and the working process of each mode is analyzed as follows:

[0080] In mode one, the DC inductor L m current i Lm (t) is:

[0081]

[0082] In the formula, t represents time.

[0083] C 11 =C 12 , making C k =C 11 =C 12 V Ck C represents k The voltage across the two ends;

[0084] Since S1 / S4, S2 / S3, S5 / S8, S6 / S7 are always on / off simultaneously, the relationship between the primary side AC output upper and lower voltages can be expressed as:

[0085]

[0086] where v priL represents the primary side AC square wave lower voltage, v priH represents the primary side AC square wave upper voltage, v pri represents the primary side AC square wave, v secL represents the secondary side AC square wave lower voltage, v secH represents the secondary side AC square wave upper voltage, v sec represents the secondary side AC square wave;

[0087] The voltage between inductors L1 and L2 can be calculated as:

[0088]

[0089] where v L1 is the DC voltage across inductor L1, v L2 is the DC voltage across inductor L2;

[0090]

[0091] where i Lp1 is the inductor current on the primary side of the center tapped transformer, V2 is the voltage across load R L ; i Lp2 is the inductor current on the primary side of the center tapped transformer; i Lp1 (t0) is the initial inductor current at time t0, L Lp2 (t0) is the initial inductor current at time t0, L k is the inductance of L1 and L2,

[0092] L k = L1 = L2.

[0093] In mode two,

[0094]

[0095] In mode three,

[0096]

[0097] In mode four,

[0098] i Lm (t) = i Lm (t3),

[0099]

[0100] In the fifth mode,

[0101] i Lm (t) = i Lm (t3),

[0102]

[0103] From the above, the inductance current i Lp1 and i Lp2 at the time t0 and t2 can be calculated as follows:

[0104]

[0105] i L1 = i Lp1 - i Lp2 = 0.

[0106] Where k is the input-output voltage ratio of the transformer, f s is the switching frequency, D is the duty ratio of the switch Q1 and Q2, d D is the phase shift ratio of the switch S1 and S5, and i L1 is the current of the intermediate tap of the transformer.

[0107] This shows that the upper inductance current i Lp1 and the lower inductance current i Lp2 are always equal.

[0108] In this embodiment, when the switch fails in the transformer, if the fault is in the primary side S3 / S4 switch, this case is called fault case 2, the structure diagram is shown in Figure 9 , and the circuit waveform diagram is shown in Figure 10 .

[0109] The gate signals of S3 and S4 are disabled to block the faulty device. After that, the conduction path of the inductance current is naturally switched to S1, S2 and the midpoint path, while the faulty switch S3 is completely passed through. Due to the change of the conduction path, the auxiliary inductance L2 and half of the transformer winding are disabled. At the same time, the secondary side operating conditions remain unchanged.

[0110] According to Kirchhoff's voltage law, the voltage condition of the conduction path of the circuit in fault-tolerant operation mode 2 is written as:

[0111] v L1 + n v secL - v priH = 0.

[0112] The relationship between the upper and lower voltages of the primary alternating current output can be expressed as:

[0113]

[0114] The voltage across the auxiliary inductor L1 can be calculated as follows:

[0115]

[0116] The alternating voltage V at different time intervals pri and secondary AC voltage v sec The amplitude of the inductor current i can be obtained from the value of the inductor current i. Lp2 :

[0117]

[0118] At the same time, due to the inductor current i L2 Due to symmetry, the inductor current i at times t0 and t2 is obtained by recalculation. Lp1 and i Lp2 The expression:

[0119]

[0120] It can be seen that the primary side AC voltage v priL The amplitude is only half that of mode one. Because the secondary side maintains four switches on, v sec The amplitude remains the same as V2. Furthermore, the inductor voltage v in mode two... L1 and primary inductor current i Lp1 The normal operating conditions are the same as those in the modal mode, while the midpoint branch i L1 Increment from 0 to the same i Lp1 This indicates that the primary inductor current remains constant under fault-tolerant mode two operating conditions. This is consistent with the constant primary inductor current i. L1 Unlike other transformers, the secondary inductor current i in mode two is smaller due to the smaller number of turns. Ls1 It is significantly lower than mode one.

[0121] When an open-circuit fault occurs on a secondary switch such as S5, the condition of a fault in the secondary-side switch transistor is defined as fault condition 3. Fault condition 3 can isolate and maintain power transmission capability. Fault condition 3 is an OCF fault in the secondary-side switch transistor, and its circuit diagram is as follows. Figure 11 As shown, the waveform is as follows Figure 12 As shown.

[0122] Case 3 is similar to Case 2, but the gate signals of S5 and S6 are disabled to isolate the faulty component S5. Then, the midpoint redundancy circuit operates naturally, and the secondary side's operating state shifts from a full-bridge to a half-bridge. Simultaneously, the primary side of the DAB converter continues to operate normally. Similarly, based on the above analysis, the inductor current i... L1 and i L2 Due to its symmetry, the inductor current i at times t0 and t2 can be calculated.Lp1 and i Lp2 The expression is:

[0123]

[0124] According to the analysis of the inductor current, the RMS value of the inductor current in the primary and secondary sides in the normal operating condition can be expressed as:

[0125]

[0126]

[0127] where I RMS1 and I RMS2 are the RMS currents of the primary and secondary sides.

[0128] Therefore, the expression of the transmission power in the normal operating condition can be calculated as:

[0129]

[0130] According to the previous analysis, the steady-state performance of the proposed fault-tolerant half-bridge multiplexed DAB converter can be controlled by the phase shift. If one of the switches has an open-circuit fault, the normal operation will be disturbed. The ocf on the semiconductor switch will generate a large current stress and a DC bias current.

[0131] Similarly, the inductor current and transmission power in fault conditions two and three can be calculated as follows:

[0132]

[0133] In the formula, case 1 is the normal operating condition.

[0134] The transmission power analysis of the fault-tolerant half-bridge multiplexed DAB converter can also be integrated as:

[0135]

[0136] The mathematical expression of the primary inductor current effective value I RMS1 is the same in the fault condition and the normal condition. Therefore, under the same phase shift condition, I RMS1 in different operating conditions is a constant value. This also proves that the primary effective value current is not affected by different operating modes. Based on the normal operating condition 1, I RMS2 in fault condition 3 is obviously greater than condition 1, which is twice the normal operating condition. On the contrary, fault condition 2 can ensure the same or lower I RMS2The transmission power of normal case 1 is equal to that of fault case 3, and the transmission power of fault case 2 is only half of that in the normal working case.

[0137] Experimental verification:

[0138] Based on the above analysis, the fault-tolerant half-bridge multiplexing DAB converter of the application is comprehensively simulated and verified to evaluate its performance and fault tolerance under various working conditions. During the simulation, a series of different working conditions are set, including normal operation state, open circuit fault (OCF) state under each mode, to test the response and performance of the fault-tolerant converter under these conditions. The selection of simulation parameters is shown in Table 1, and the parameters are set according to the expected indicators to follow the typical working conditions in actual applications, to ensure the reliability and referenceability of the simulation results.

[0139] Table 1 Simulation experiment parameters

[0140]

[0141] Based on the parameters in Table 1, a simulation circuit is built, which details the actual design of the fault-tolerant half-bridge multiplexing DAB converter, including the connection mode of each inductor, capacitor and switch, and the implementation of the control strategy. During the simulation, the performance of the circuit in the normal working mode is first tested. Then, the fault tolerance of the circuit is verified one by one for different open circuit fault modes.

[0142] The experimental waveforms under each mode are shown in Figures 13-15 Under fault-tolerant operation mode, although the rated power is reduced, the current stress and conduction loss on the secondary side are significantly reduced, which is of great significance to prolong the service life of the equipment and improve the reliability of the system. It can be seen that the input and output voltages under each mode can be stably output according to the expected requirements, without obvious fluctuations or deviations, proving the reliability and stability of the circuit. The inductor current waveform is highly consistent with the theoretical analysis results, indicating that the circuit design is reasonable, and the switch tube can realize zero voltage switching (ZVS) under various modes, effectively reducing the switching loss and improving the efficiency and performance of the circuit.

[0143] The above simulation verification results not only fully demonstrate the fault tolerance of the half-bridge multiplexing fault-tolerant DAB converter proposed in the application under various fault conditions, but also show that the circuit can maintain stable power transmission under various working conditions. In addition, the simulation verification also shows the current distribution and voltage waveform variation law under different fault conditions, proving that the application has stable and reliable performance. The application can still have stable output under wide range of voltage input and partial device fault conditions, can maintain stable grid voltage and improve the power quality of the direct current grid. It has wide application prospects in the field of photovoltaic power generation in high-latitude cold regions.

[0144] While the application has been described with reference to particular embodiments thereof, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present application. It will be apparent to those skilled in the art that numerous modifications can be made within the scope of the present application as defined by the appended claims. It is intended that all such modification fall within the spirit and scope of the present application. It will be understood that the features described in connection with one embodiment can be used in connection with another embodiment.

Claims

1. A fault-tolerant dual active bridge converter based on half-bridge multiplexing, characterized in that, Including multiplexed half-bridge, DC inductor L m Lead bridge, capacitor C 11 Capacitor C 12 A center-tapped transformer with a turns ratio of n:1, DC inductor L1, DC inductor L2, a hysteresis bridge, and capacitor C. 21 and capacitor C 22 , Multiplexed half-bridge through DC inductor L m Connected to the advance bridge, capacitor C 11 and capacitor C 12 After being connected in series, it is connected in parallel with the bridge. The two ends of the primary side of the center-tapped transformer are connected to DC inductors L1 and L2 respectively, and then connected to the bridge. The center tap of the primary side of the center-tapped transformer is connected to capacitor C. 11 and capacitor C 12 between; The secondary side of the center-tapped transformer is connected to the hysteresis bridge, and capacitor C... 21 and capacitor C 22 After being connected in series, it is connected in parallel with the lag bridge. The center tap of the secondary side of the center-tapped transformer is connected to capacitor C. 21 and capacitor C 22 between.

2. The fault-tolerant dual active bridge converter based on half-bridge multiplexing according to claim 1, characterized in that, The multiplexed half-bridge includes a switch Q1 and a switch Q2. The drain of switch Q1 is connected to the positive terminal of power supply V1, the source of switch Q1 is connected to the drain of switch Q2, and the source of switch Q2 is connected to the negative terminal of power supply V1. A capacitor C1 is connected between the drain of switch Q1 and the source of switch Q2. The lead bridge includes switching transistors S1, S2, S3, and S4. The drain of switching transistor S1 is connected to the drain of switching transistor S3, the source of switching transistor S1 is connected to the drain of switching transistor S2, the source of switching transistor S2 is connected to the source of switching transistor S4, and the drain of switching transistor S4 is connected to the source of switching transistor S3; DC inductor L m It is connected between the source of switch Q1 and the source of switch S1; The drain capacitor C of the switching transistor S1 11 One end of the capacitor C 11 The other end is connected to capacitor C 12 One end of the capacitor C 12 The other end is connected to the source of switching transistor S2; the source of switching transistor S1 is connected to one end of DC inductor L1, the other end of DC inductor L1 is connected to one end of the primary winding of the center-tapped transformer, the other end of the primary winding of the center-tapped transformer is connected to one end of DC inductor L2, the other end of DC inductor L2 is connected to the drain of switching transistor S4, and the center tap of the primary winding of the center-tapped transformer is connected to capacitor C. 11 The other end.

3. The fault-tolerant dual active bridge converter based on half-bridge multiplexing according to claim 2, characterized in that, The hysteresis bridge includes switching transistors S5, S6, S7, and S8. The drain of switching transistor S5 is connected to the drain of switching transistor S7, the source of switching transistor S5 is connected to the drain of switching transistor S6, the source of switching transistor S6 is connected to the source of switching transistor S8, and the drain of switching transistor S8 is connected to the source of switching transistor S7. One end of the secondary winding of the center-tapped transformer is connected to the source of switching transistor S5, and the other end is connected to the drain of switching transistor S8; the drain of switching transistor S7 is connected to capacitor C. 21 One end of the capacitor C 21 The other end is connected to capacitor C 22 One end of the capacitor C 22 The other end is connected to the source of the switching transistor S8; The center tap of the secondary side of the center-tapped transformer is connected to capacitor C. 21 The other end; capacitor C 21 one end and capacitor C 22 The other end is connected to the load R L .

4. A control method for a fault-tolerant dual active bridge converter based on half-bridge multiplexing, wherein the fault-tolerant dual active bridge converter based on half-bridge multiplexing as described in claim 3 is characterized in that, One control cycle includes five modes; In mode 1, during the time interval [t0, t1], before the gate drive signal of switch Q1 arrives, switch Q2 is turned off; when the gate drive signal of switch Q1 arrives, switch Q1 achieves zero-voltage turn-on; where t0 is the start time for switch Q1, switch S1 and switch S4 to turn on, and t1 is the start time for switch S5 and switch S8 to turn on. In mode 2, during the time interval [t1, t2], switches S6 and S7 are turned off, and the voltages across switches S5 and S8 are clamped to zero. When the gate drive signal for switches S1 and S8 arrives at time t1, switches S5 and S8 are turned on with zero voltage. Time t2 is the start time when switch Q1 is turned off. In mode 3, during the time interval [t2, t3], switch Q1 is turned off, and the voltage across switch Q2 is clamped to zero; when the gate drive signal for switch Q2 arrives at time t2, switch Q2 achieves zero-voltage turn-on; time t3 is the start time when switches S1 and S4 are turned off. In mode four, during the time interval [t3, t4], switches S1 and S4 are turned off, and the voltages across switches S2 and S3 are clamped to zero. When the gate drive signal for switches S2 and S3 arrives at time t4, switches S2 and S3 achieve zero-voltage turn-on. Time t4 is the start time for switches S5 and S8 to be turned off. In mode 5, during the time interval [t4, t5], switches S5 and S8 are turned off, and the voltages across switches S6 and S7 are clamped to zero. At time t5, when the gate drive signal for switches S6 and S7 arrives, switches S6 and S7 achieve zero-voltage turn-on. Time t5 is the starting time for switches Q1, S1, and S4 to turn on again.

5. The control method for a fault-tolerant dual active bridge converter based on half-bridge multiplexing according to claim 4, characterized in that, In mode one, the DC inductor L m current i Lm (t) is: In the formula, t represents time and V1 is the input voltage; C 11 =C 12 , making C k =C 11 =C 12 V Ck Indicate C k The voltage across the two ends; In the formula v priL This represents the voltage under a primary side AC square wave, v priH This represents the voltage on the primary side AC square wave, v pri This represents a primary-side AC square wave, v secL This represents the voltage on the secondary side under an AC square wave, v secH This represents the voltage on the secondary side AC square wave, v sec This represents a secondary-side AC square wave; n is the transformer turns ratio. In the formula v L1 V is the voltage across the DC inductor L1. L2 The voltage across DC inductor L2; In the formula i Lp1 V2 is the inductor current on the primary side of the center-tapped transformer, and R is the load current. L Voltage across terminals; i Lp2 This refers to the inductance current on the primary side of the center-tapped transformer. L k =L1=L2; L k Let L1 and L2 be the inductors.

6. The control method for a fault-tolerant dual active bridge converter based on half-bridge multiplexing according to claim 5, characterized in that, In mode two, 7. The control method for a fault-tolerant dual active bridge converter based on half-bridge multiplexing according to claim 6, characterized in that, In mode three, 8. The control method for a fault-tolerant dual active bridge converter based on half-bridge multiplexing according to claim 7, characterized in that, In mode four, i Lm (t)=i Lm (t3), 9. The control method for a fault-tolerant dual active bridge converter based on half-bridge multiplexing according to claim 8, characterized in that, In Modal 5, i Lm (t)=i Lm (t3), 10. The control method for a fault-tolerant dual active bridge converter based on half-bridge multiplexing according to claim 9, characterized in that, In Modal 5, i L1 =i Lp1 -i Lp2 =0; In the formula, k is the input-output voltage ratio of the converter, and f s d is the switching frequency, D is the duty cycle of switching transistors Q1 and Q2, and d is the switching frequency. D Compared to the shift of switching transistors S1 and S5, i L1 This refers to the current in the intermediate tap branch of the intermediate tap transformer.

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