Reconfigurable logic unit, control method and reconfigurable logic system for implementing complete boolean logic

Abstract

The application discloses a reconfigurable logic unit, a control method and a reconfigurable logic system for implementing complete Boolean logic, and belongs to the technical field of integrated circuit design. The reconfigurable logic unit comprises one P-type MOSFET and four N-type FeFETs. In the four N-FeFETs, two N-FeFETs are connected in parallel, the drain thereof is connected with the drain of the P-MOSFET, and the source thereof is connected in series with the drain of another set of two N-FeFETs connected in parallel. The reconfigurable logic unit takes the gate of the N-FeFET as an input terminal, and can realize logic reconfiguration under the control of the polarization voltage applied to the gate by fully utilizing the polarization characteristics of the ferroelectric device. The reconfigurable logic unit can support the dynamic reconfiguration of 16 complete Boolean logics by only using one P-type MOSFET and four N-type FeFETs, has the advantages of small layout area, low computing power consumption, strong reconfiguration capability, compatibility with CMOS and easy process integration, and the like.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of integrated circuit design, and more particularly, relates to a reconfigurable logic unit for implementing complete Boolean logic, a control method and a reconfigurable logic system. BACKGROUND

[0002] The "memory wall" of the Von Neumann architecture limits the improvement of chip computing performance. The existing VLSI chips are facing the bottlenecks of computing power and energy efficiency. The energy efficiency demand of high-performance computing chips and the energy efficiency computing power provided by the existing Von Neumann architecture differ by 2-3 orders of magnitude. Therefore, it is urgent to develop large-capacity, non-volatile memory devices and non-Von architecture technology to improve the chip computing power and energy efficiency. Research shows that among many new types of non-volatile memories, ferroelectric transistor FeFET has a potential advantage in power consumption and can realize a structure similar to 3D NAND Flash, which has a potential advantage of high integration. Therefore, the hafnium-based ferroelectric transistor with short access time, low power consumption and compatibility with advanced manufacturing has become the most potential candidate in new non-volatile memories.

[0003] In recent years, research on ferroelectric material devices and chips has been an important high-tech field of microelectronics research. There are many research reports on FeFET in the fields of non-volatile memory, neural network, reconfigurable device, etc. In particular, since the first hafnium-based ferroelectric transistor compatible with CMOS process was proposed in 2011, research on ferroelectric logic units and logic reconfiguration has been continuously deepened. For example, Sourav Dutta et al. published an article entitled Experimental Demonstration of Gate-Level Logic Camouflaging and Run-Time Reconfigurability Using Ferroelectric FET for Hardware Security in IEEE Transactions on Electron Devices, which first proposed a circuit module based on 8 FeFETs and implemented a reconfigurable NOR / NAND / XNOR logic gate using threshold voltage programming of FeFET. Although this design considers logic reconfiguration, the layout area and power consumption cost are large, the reconfiguration capability of the designed structure unit is not strong, and only three kinds of logic reconfiguration are supported, which does not maximize the flexibility advantage of the circuit brought by reconfiguration. SUMMARY

[0004] In view of the above defects or improvement needs of the prior art, the present application provides a reconfigurable logic unit for implementing complete Boolean logic, a control method and a reconfigurable logic system, which aims to provide a reconfigurable logic unit with small layout area, low computing power consumption and strong reconfiguration capability.

[0005] In order to achieve the above-mentioned purpose, the first aspect of the present application provides a reconfigurable logic unit for implementing complete Boolean logic, comprising: a P-type MOSFET, a first N-type FeFET, a second N-type FeFET, a third N-type FeFET and a fourth N-type FeFET;

[0006] The first N-type FeFET and the second N-type FeFET are connected in parallel; the third N-type FeFET and the fourth N-type FeFET are connected in parallel; the drains of the first N-type FeFET and the second N-type FeFET are connected to the drain of the P-type MOSFET, and the sources are connected to the drains of the third N-type FeFET and the fourth N-type FeFET; the sources of the third N-type FeFET and the fourth N-type FeFET are grounded;

[0007] The gates of the P-type MOSFET and each N-type FeFET are used to receive control signals to control the on-off state of the P-type MOSFET, the polarization state of each N-type FeFET and the on-off state under the polarization state, so that the reconfigurable logic unit performs a target logic operation; the drain of the P-type MOSFET serves as the output terminal of the reconfigurable logic unit.

[0008] The second aspect of the present application provides a control method of the above-mentioned reconfigurable logic unit, comprising: controlling the on-off state of the P-type MOSFET in the reconfigurable logic unit, the polarization state of each N-type FeFET and the on-off state under the polarization state, so that the reconfigurable logic unit performs a target logic operation.

[0009] Further preferably, the type of the target logic operation includes: a true logic operation, a false logic operation and a logic operation on input logic values; wherein the input logic values include: a logic value p and / or a logic value q;

[0010] Let the source and gate of the P-type MOSFET in the reconfigurable logic unit be S terminal and G terminal; let the gate of any one of the first N-type FeFET and the second N-type FeFET in the reconfigurable logic unit be A terminal, and the gate of the other N-type FeFET be B terminal; let the gate of any one of the third N-type FeFET and the fourth N-type FeFET in the reconfigurable logic unit be C terminal, and the gate of the other N-type FeFET be D terminal; the drain of the P-type MOSFET is the output terminal of the reconfigurable logic unit;

[0011] The above-mentioned control method includes:

[0012] When the target logic operation is a true logic operation, a positive power voltage VDD is connected to the S terminal, and a low-level voltage is applied to the G terminal;

[0013] When the target logic operation is a false logic operation, the S terminal is grounded;

[0014] When the target logic operation is p logic operation, the positive supply voltage VDD is connected to the S terminal in advance, and the positive polarization voltage is applied to the A terminal and the C terminal respectively, and the negative polarization voltage is applied to the B terminal; then the logic voltage signal is applied to the A terminal the high level voltage or the low level voltage is applied to the B terminal, the high level voltage is applied to the C terminal, and the high level voltage is applied to the G terminal;

[0015] When the target logic operation is q logic operation, the positive supply voltage VDD is connected to the S terminal in advance, and the positive polarization voltage is applied to the B terminal and the C terminal respectively, and the negative polarization voltage is applied to the A terminal; then the high level voltage or the low level voltage is applied to the A terminal, and the logic voltage signal is applied to the B terminal the high level voltage is applied to the C terminal, and the high level voltage is applied to the G terminal;

[0016] When the target logic operation is logic operation, the positive supply voltage VDD is connected to the S terminal in advance, and the positive polarization voltage is applied to the A terminal and the C terminal respectively, and the negative polarization voltage is applied to the B terminal; then the logic voltage signal p is applied to the A terminal, the high level voltage or the low level voltage is applied to the B terminal, the high level voltage is applied to the C terminal, and the high level voltage is applied to the G terminal;

[0017] When the target logic operation is logic operation, the positive supply voltage VDD is connected to the S terminal in advance, and the positive polarization voltage is applied to the B terminal and the C terminal respectively, and the negative polarization voltage is applied to the A terminal; then the high level voltage or the low level voltage is applied to the A terminal, and the logic voltage signal q is applied to the B terminal, the high level voltage is applied to the C terminal, and the high level voltage is applied to the G terminal;

[0018] When the target logic operation is logic operation, the positive supply voltage VDD is connected to the S terminal in advance, and the positive polarization voltage is applied to the A terminal, the B terminal and the C terminal respectively; then the logic voltage signal p is applied to the A terminal, the logic voltage signal q is applied to the B terminal, the high level voltage is applied to the C terminal, and the high level voltage is applied to the G terminal;

[0019] When the target logic operation is p·q logic operation, the positive supply voltage VDD is connected to the S terminal in advance, and the positive polarization voltage is applied to the A terminal, the B terminal and the C terminal respectively; then the logic voltage signal the logic voltage signal the high level voltage is applied to the C terminal, and the high level voltage is applied to the G terminal;

[0020] When the target logic operation is logic operation, the positive supply voltage VDD is connected to the S terminal in advance, and the positive polarization voltage is applied to the A terminal, the B terminal and the C terminal respectively; then the logic voltage signal A terminal is applied with a logic voltage signal p, B terminal is applied with a logic voltage signal q, C terminal is applied with a high level voltage, and G terminal is applied with a high level voltage.

[0021] When the target logic operation is logic operation, a positive supply voltage VDD is connected to S terminal in advance, and positive polarization voltage is applied to A terminal and C terminal respectively, and negative polarization voltage is applied to B terminal; then A terminal is applied with a logic voltage signal p, B terminal is applied with a low level voltage, C terminal is applied with a logic voltage signal q, and G terminal is applied with a high level voltage.

[0022] When the target logic operation is logic operation, a positive supply voltage VDD is connected to S terminal in advance, and positive polarization voltage is applied to A terminal and C terminal respectively, and negative polarization voltage is applied to B terminal; then A terminal is applied with a logic voltage signal p, B terminal is applied with a low level voltage, C terminal is applied with a logic voltage signal q, and G terminal is applied with a high level voltage.

[0023] When the target logic operation is p+q logic operation, a positive supply voltage VDD is connected to S terminal in advance, and positive polarization voltage is applied to A terminal and C terminal respectively, and negative polarization voltage is applied to B terminal; then A terminal is applied with a logic voltage signal p, B terminal is applied with a low level voltage, C terminal is applied with a logic voltage signal q, and G terminal is applied with a high level voltage.

[0024] When the target logic operation is logic operation, a positive supply voltage VDD is connected to S terminal in advance, and positive polarization voltage is applied to A terminal and C terminal respectively, and negative polarization voltage is applied to B terminal; then A terminal is applied with a logic voltage signal p, B terminal is applied with a low level voltage, C terminal is applied with a logic voltage signal q, and G terminal is applied with a high level voltage.

[0025] When the target logic operation is logic operation, a positive supply voltage VDD is connected to S terminal in advance, and positive polarization voltage is applied to A terminal and C terminal respectively, and negative polarization voltage is applied to B terminal; then A terminal is applied with a logic voltage signal p, B terminal is applied with a low level voltage, C terminal is applied with a logic voltage signal q, and G terminal is applied with a high level voltage.

[0026] When the target logic operation is exclusive or logic operation, a positive supply voltage VDD is connected to S terminal in advance, and positive polarization voltage is applied to A terminal, B terminal, C terminal and D terminal respectively; then A terminal is applied with a logic voltage signal p, B terminal is applied with a logic voltage signal q, C terminal is applied with a logic voltage signal p, and D terminal is applied with a logic voltage signal q. ​​​​​​​

[0027] When the target logic operation is an exclusive-OR operation, a positive power voltage VDD is connected to the S terminal in advance, and a positive polarization voltage is applied to the A terminal, the B terminal, the C terminal and the D terminal respectively; then a logic voltage signal is applied to the A terminal A logic voltage signal is applied to the B terminal A logic voltage signal p is applied to the C terminal, a logic voltage signal q is applied to the D terminal, and a high-level voltage is applied to the G terminal.

[0028] Further preferably, when the logic value p is 1, the logic voltage signal p is a high-level voltage, and the logic voltage signal is a low-level voltage; when the logic value p is 0, the logic voltage signal p is a low-level voltage, and the logic voltage signal is a high-level voltage.

[0029] When the logic value q is 1, the logic voltage signal q is a high-level voltage, and the logic voltage signal is a low-level voltage; when the logic value q is 0, the logic voltage signal q is a low-level voltage, and the logic voltage signal is a high-level voltage.

[0030] Further preferably, in each logic operation, after the operation of applying corresponding polarization voltages to different terminals is performed, the operation of applying corresponding level voltages to different terminals is performed in parallel.

[0031] Further preferably, in each logic operation, the operation of applying corresponding polarization voltages to different terminals is performed in parallel.

[0032] Further preferably, when the output signal of the reconfigurable logic unit is a high-level voltage, the result of the target logic operation is 1; when the output signal of the reconfigurable logic unit is a low-level voltage, the result of the target logic operation is 0.

[0033] In a third aspect, the present application provides a reconfigurable logic system, comprising: a controller and the reconfigurable logic unit provided in the first aspect of the present application.

[0034] The controller is configured to perform the control method provided in the second aspect of the present application.

[0035] In general, the above technical solutions conceived by the present application can achieve the following beneficial effects:

[0036] 1. The application provides a reconfigurable logic unit for implementing complete Boolean logic, comprising a P-type MOSFET and four N-type FeFETs; among the four N-FeFETs, two N-FeFETs are connected in parallel, the drain thereof is connected with the drain of the P-MOSFET, and the source thereof is connected in series with the drain of another set of two N-FeFETs connected in parallel. The reconfigurable logic unit takes the gate of the N-FeFET as a logic input terminal, and by making full use of the polarization characteristics of the ferroelectric device, can dynamically reconfigure 16 complete Boolean logics by only using one P-type MOSFET and four N-type FeFETs under the control of the polarization voltage applied at the gate, and has the advantages of small layout area, low computing power consumption, strong reconfiguration capability, CMOS compatibility, easy process integration and the like.

[0037] 2. The application provides a control method of the reconfigurable logic unit, which can flexibly input corresponding voltage signals at the gates of the P-type MOSFET and each N-type FeFET according to the type of the logic operation to be implemented, so as to realize 16 complete logic reconfigurations, and can effectively solve the problems of device circuit solidification and insufficient flexibility.

[0038] 3. Further, the control method of the reconfigurable logic unit provided by the application can, in each logic operation, perform the operation of applying corresponding polarization voltage at different terminals in parallel, and then perform the operation of applying corresponding level voltage at different terminals in parallel, so that one logic reconfiguration and logic calculation can be completed in two steps, and a separate calculation result reading step is not needed, thereby greatly shortening the time spent for the entire logic operation. BRIEF DESCRIPTION OF DRAWINGS

[0039] Figure 1 A structural schematic diagram of a reconfigurable logic unit for implementing complete Boolean logic provided by an embodiment of the application;

[0040] Figure 2 A separation schematic diagram of high state and low state threshold voltages of an N-FeFET provided by an embodiment of the application;

[0041] Figure 3 An example of a simulation waveform diagram of the reconfigurable logic unit provided by an embodiment of the application. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical scheme and advantages of the application more clear, the application is further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the application, and are not used to limit the application. In addition, the technical features involved in each embodiment of the application described below can be combined with each other as long as they do not conflict with each other.

[0043] To achieve the above object, in a first aspect, as shown in the accompanying drawings, Figure 1 The application provides a reconfigurable logic unit for implementing complete Boolean logic, comprising a P-type MOSFET, a first N-type FeFET, a second N-type FeFET, a third N-type FeFET and a fourth N-type FeFET.

[0044] The first N-type FeFET and the second N-type FeFET are connected in parallel; the third N-type FeFET and the fourth N-type FeFET are connected in parallel; the drains of the first N-type FeFET and the second N-type FeFET are connected to the drain of the P-type MOSFET, and the sources are connected to the drains of the third N-type FeFET and the fourth N-type FeFET; the sources of the third N-type FeFET and the fourth N-type FeFET are grounded.

[0045] The gates of the P-type MOSFET and each N-type FeFET serve as the input end of the reconfigurable logic unit (the gate of the ferroelectric transistor serves as the logic signal input end), for receiving a control signal to adjust the on-off state of the P-type MOSFET, and the polarization state and on-off state under the polarization state of each N-type FeFET, so that the reconfigurable logic unit performs a target logic operation; the drain of the P-type MOSFET serves as the output end of the reconfigurable logic unit.

[0046] The reconfigurable logic unit uses a direct current voltage as a logic input signal. When the direct current voltage applied to the gate of the N-FeFET is a voltage greater than 0V, it corresponds to a logic input of "1"; when the direct current voltage applied to the gate of the N-FeFET is 0V, it corresponds to a logic input of "0".

[0047] The logic unit uses the voltage V out of the drain of the P-MOSFET as a logic output signal. When V out is a high-level voltage, it corresponds to a logic output of "1"; when V out is a low-level voltage, it corresponds to a logic output of "0".

[0048] The P-MOSFET serves as a pull-up device of the logic unit, and its on or off state is determined according to the voltage applied to its gate. Specifically, when the voltage applied to the gate of the P-MOSFET is a high-level voltage, the P-MOSFET works in an off state; when the voltage applied to the gate of the P-MOSFET is a low-level voltage, the P-MOSFET works in an on state.

[0049] The on or off state of the N-FeFET is determined by the polarization voltage and the logic signal voltage applied to the gate of the N-FeFET in sequence. Specifically, when the polarization voltage applied to the gate of the N-FeFET is a positive voltage: if the direct current voltage continuously applied to the gate of the N-FeFET is high, the N-FeFET works in the on state; if the direct current voltage continuously applied to the gate of the N-FeFET is low, the N-FeFET works in the off state; when the polarization voltage applied to the gate of the N-FeFET is a negative voltage: if the direct current voltage continuously applied to the gate of the N-FeFET is high, the N-FeFET works in the off state; if the direct current voltage continuously applied to the gate of the N-FeFET is low, the N-FeFET works in the off state.

[0050] This is because the polarization voltage can change the polarization state of the ferroelectric layer inside the transistor, so that the threshold voltage of the N-FeFET transistor is shifted, and the separation of the high state and low state threshold voltages occurs, as shown in FIG. 2. Figure 2 Specifically, when the polarization voltage applied to the gate of the N-FeFET is a positive voltage, the threshold voltage of the N-FeFET is shifted to the left, forming a low threshold voltage V TL ; when the polarization voltage applied to the gate of the N-FeFET is a negative voltage, the threshold voltage of the N-FeFET is shifted to the right, forming a high threshold voltage V TH The shift of the threshold voltage will make the N-FeFET have two possible states of on or off when the logic input signal is applied, thereby producing different logic calculation results. The above-mentioned reconfigurable logic unit utilizes this to complete the logic reconfiguration design.

[0051] When performing a logic operation, the logic unit needs to be configured according to the logic function first, including applying a voltage to the gate of the P-MOSFET to determine its working state and applying a polarization voltage to the gate of the N-FeFET to determine its polarization state. Then according to the logic function, select the logic input terminal in the four N-FeFETs, and apply a direct current voltage signal to complete the logic calculation.

[0052] The configuration and logic signal input terminals corresponding to the 16 kinds of logic that can be realized by the reconfigurable logic unit provided by the present application are given in Table 1. Among them, "A", "B", "C", "D" represent optional logic input terminals, specifically, "A" represents the gate of any one of the first N-type FeFET and the second N-type FeFET, "B" represents the gate of the other one of the first N-type FeFET and the second N-type FeFET, "C" represents the gate of any one of the third N-type FeFET and the fourth N-type FeFET, and "D" represents the gate of the other one of the first N-type FeFET and the second N-type FeFET. "p", "q", "r", "s" represent logic input signals, "1" in the "A", "B", "C", "V" columns represents applying a high-level voltage, and "0" represents applying a low-level voltage. "E", "F", "G", "H" represent the direction of the polarization voltage applied by the N-FeFET, "1" in the "E", "F", "G", and "H" columns represents applying a positive polarization voltage, and "0" represents applying a negative polarization voltage. p p represents the gate bias voltage of the P-MOSFET, that is, the signal applied to the gate (G terminal) of the P-type MOSFET.

[0053] Table 1

[0054]

[0055] When the gates of the two parallel N-FeFETs connected to the drain of the P-MOSFET in the reconfigurable logic unit are selected as input terminals, the logic unit can realize 10 kinds of reconfigurable Boolean logic: logic "1", logic "0", logic "p", logic "q", logic logic logic (i.e. logic "NOR"), logic "p·q" (i.e. logic "AND"), logic (i.e. logic "NIMP"), logic (i.e. logic "RNIMP"). At this time, the N-FeFET in series with it always maintains the on state with the polarization upwards.

[0056] When the gates of the two series N-FeFETs in the reconfigurable logic unit are selected as input terminals, the logic unit can realize 4 kinds of reconfigurable Boolean logic: logic (i.e. logic "NAND"), logic "p+q" (i.e. logic "OR"), logic (i.e. logic "RIMP"), logic ​​(i.e. the logical "IMP"). At this time, the N-FeFET in parallel with it always maintains the blocking state of polarization downward.

[0057] When four gate electrodes of the N-FeFETs are selected as input terminals in the reconfigurable logic unit, the logic unit realizes two kinds of reconfigurable Boolean logic through logical combination: the logical "XOR", the logical "XNOR". Specifically, for the logical "XOR", the logic can be realized by combining the logical "RNIMP" and the logical "NIMP"; for the logical "XNOR", the logic can be realized by combining two groups of logical "AND".

[0058] It should be noted that the above logical "1" is a true logical operation, the logical "0" is a false logical operation, the logical "p" is a p logical operation, the logical "q" is a q logical operation, the logical is a logical operation, the logical is a logical operation, the logical is a logical operation, the logical "p·q" is a p·q logical operation, the logical is a logical operation, the logical is a logical operation, the logical is a logical operation, the logical "p+q" is a p+q logical operation, the logical is a logical operation, the logical is a logical operation, the logical "XOR" is an exclusive or operation of the logical p and the logical q, and the logical "XNOR" is an inclusive or operation of the logical p and the logical q.

[0059] When the reconfigurable logic unit performs the logical "1" operation, the P-MOSFET is in the on state, and the P-MOSFET remains in the blocking state when performing other logical operations.

[0060] The second aspect of the present application provides a control method of the reconfigurable logic unit provided in the first aspect, comprising: controlling the on-off state of the P-type MOSFET, the polarization state of each N-type FeFET and the on-off state under the polarization state in the reconfigurable logic unit, so that the reconfigurable logic unit performs a target logical operation. Wherein, the type of the target logical operation includes: a true logical operation, a false logical operation and a logical operation on an input logical value; the input logical value includes: a logical value p and / or a logical value q.

[0061] In an optional embodiment, the control method specifically comprises:

[0062] When the target logic operation is a true logic operation, a positive supply voltage VDD is connected to the S terminal, and a low-level voltage is applied to the G terminal;

[0063] When the target logic operation is a false logic operation, the S terminal is grounded;

[0064] When the target logic operation is a p logic operation, a positive supply voltage VDD is connected to the S terminal in advance, and a positive polarization voltage is applied to the A terminal and the C terminal respectively, and a negative polarization voltage is applied to the B terminal; then a logic voltage signal p is applied to the A terminal a high-level voltage or a low-level voltage is applied to the B terminal, a high-level voltage is applied to the C terminal, and a high-level voltage is applied to the G terminal;

[0065] When the target logic operation is a q logic operation, a positive supply voltage VDD is connected to the S terminal in advance, and a positive polarization voltage is applied to the B terminal and the C terminal respectively, and a negative polarization voltage is applied to the A terminal; then a high-level voltage or a low-level voltage is applied to the A terminal, a logic voltage signal q is applied to the B terminal, and a high-level voltage is applied to the C terminal, and a high-level voltage is applied to the G terminal;

[0066] When the target logic operation is a logic operation, a positive supply voltage VDD is connected to the S terminal in advance, and a positive polarization voltage is applied to the A terminal and the C terminal respectively, and a negative polarization voltage is applied to the B terminal; then a logic voltage signal p is applied to the A terminal, a high-level voltage or a low-level voltage is applied to the B terminal, a high-level voltage is applied to the C terminal, and a high-level voltage is applied to the G terminal;

[0067] When the target logic operation is a logic operation, a positive supply voltage VDD is connected to the S terminal in advance, and a positive polarization voltage is applied to the B terminal and the C terminal respectively, and a negative polarization voltage is applied to the A terminal; then a high-level voltage or a low-level voltage is applied to the A terminal, a logic voltage signal q is applied to the B terminal, a high-level voltage is applied to the C terminal, and a high-level voltage is applied to the G terminal;

[0068] When the target logic operation is a logic operation, a positive supply voltage VDD is connected to the S terminal in advance, and a positive polarization voltage is applied to the A terminal, the B terminal and the C terminal respectively; then a logic voltage signal p is applied to the A terminal, a logic voltage signal q is applied to the B terminal, a high-level voltage is applied to the C terminal, and a high-level voltage is applied to the G terminal;

[0069] When the target logic operation is a p·q logic operation, a positive supply voltage VDD is connected to the S terminal in advance, and a positive polarization voltage is applied to the A terminal, the B terminal and the C terminal respectively; then a logic voltage signal p is applied to the A terminal a logic voltage signal q is applied to the B terminal a high-level voltage is applied to the C terminal, and a high-level voltage is applied to the G terminal;​

[0070] When the target logic operation is logic operation, the positive supply voltage VDD is connected to the S terminal in advance, and positive polarization voltages are applied to the A terminal, the B terminal, and the C terminal respectively; then a logic voltage signal is applied to the A terminal, a logic voltage signal q is applied to the B terminal, a high-level voltage is applied to the C terminal, and a high-level voltage is applied to the G terminal;

[0071] When the target logic operation is logic operation, the positive supply voltage VDD is connected to the S terminal in advance, and positive polarization voltages are applied to the A terminal, the B terminal, and the C terminal respectively; then a logic voltage signal p is applied to the A terminal, a logic voltage signal is applied to the B terminal, a high-level voltage is applied to the C terminal, and a high-level voltage is applied to the G terminal;

[0072] When the target logic operation is logic operation, the positive supply voltage VDD is connected to the S terminal in advance, and positive polarization voltages are applied to the A terminal and the C terminal, and a negative polarization voltage is applied to the B terminal; then a logic voltage signal p is applied to the A terminal, a low-level voltage is applied to the B terminal, a logic voltage signal q is applied to the C terminal, and a high-level voltage is applied to the G terminal;

[0073] When the target logic operation is p+q logic operation, the positive supply voltage VDD is connected to the S terminal in advance, and positive polarization voltages are applied to the A terminal and the C terminal, and a negative polarization voltage is applied to the B terminal; then a logic voltage signal is applied to the A terminal, a low-level voltage is applied to the B terminal, a logic voltage signal q is applied to the C terminal, and a high-level voltage is applied to the G terminal;

[0074] When the target logic operation is logic operation, the positive supply voltage VDD is connected to the S terminal in advance, and positive polarization voltages are applied to the A terminal and the C terminal, and a negative polarization voltage is applied to the B terminal; then a logic voltage signal p is applied to the A terminal, a low-level voltage is applied to the B terminal, a logic voltage signal q is applied to the C terminal, and a high-level voltage is applied to the G terminal;

[0075] When the target logic operation is logic operation, the positive supply voltage VDD is connected to the S terminal in advance, and positive polarization voltages are applied to the A terminal and the C terminal, and a negative polarization voltage is applied to the B terminal; then a logic voltage signal p is applied to the A terminal, a low-level voltage is applied to the B terminal, a logic voltage signal q is applied to the C terminal, and a high-level voltage is applied to the G terminal;

[0076] ​​​When the target logic operation is an XOR logic operation, a positive power supply voltage VDD is connected to the S terminal in advance, and positive polarization voltages are applied to the A, B, C and D terminals respectively; then a logic voltage signal is applied to the A terminal a logic voltage signal q is applied to the B terminal, a logic voltage signal p is applied to the C terminal, and a logic voltage signal is applied to the D terminal a high-level voltage is applied to the G terminal

[0077] When the target logic operation is an XOR logic operation, a positive power supply voltage VDD is connected to the S terminal in advance, and positive polarization voltages are applied to the A, B, C and D terminals respectively; then a logic voltage signal is applied to the A terminal a logic voltage signal q is applied to the B terminal, a logic voltage signal p is applied to the C terminal, and a logic voltage signal is applied to the D terminal a high-level voltage is applied to the G terminal

[0078] In an optional embodiment, when the logic value p is 1, the logic voltage signal p is a high-level voltage, and the logic voltage signal is a low-level voltage; when the logic value p is 0, the logic voltage signal p is a low-level voltage, and the logic voltage signal is a high-level voltage

[0079] In an optional embodiment, when the logic value q is 1, the logic voltage signal q is a high-level voltage, and the logic voltage signal is a low-level voltage; when the logic value q is 0, the logic voltage signal q is a low-level voltage, and the logic voltage signal is a high-level voltage

[0080] In an optional embodiment, when the output signal of the reconfigurable logic unit is a high-level voltage, the result of the logic operation is 1; when the output signal of the reconfigurable logic unit is a low-level voltage, the result of the logic operation is 0.

[0081] Preferably, the polarization voltage applied to the N-FeFET gate and the logic voltage signal are serially input, and the voltage applied to the P-MOSFET gate and the logic voltage signal applied to the N-FeFET gate are parallelly input, so that only two steps are needed to perform a logic reconfiguration and a logic calculation. Specifically, in an optional embodiment, in each logic operation, after the operation of applying corresponding polarization voltages to different terminals is performed, the operation of applying corresponding level voltages to different terminals is performed in parallel. In an optional embodiment, in each logic operation, the operation of applying corresponding polarization voltages to different terminals is performed in parallel.

[0082] In an optional embodiment, the high-level voltage is 1-1.2V, and the low-level voltage is 0-0.2V. Preferably, the high-level voltage is set to 1V, and the low-level voltage is set to 0V.

[0083] In an alternative embodiment, the positive polarization voltage is 3-5V and the negative polarization voltage is -5--3V. Preferably, the positive polarization voltage is 4V and the negative polarization voltage is -4V.

[0084] In an alternative embodiment, the positive power supply voltage VDD is 1.5V.

[0085] To further illustrate the reconfigurable logic unit and the control method thereof provided by the second aspect of the present application, the following embodiment realizes the functional verification of the reconfigurable logic unit, transient simulation of the reconfigurable logic unit is performed by using SPICE software, polarization voltage and logic signal are applied to the gate of the N-FeFET by using segmented linear voltage sources, accurate simulation of 16 complete reconfigurable logic computing functions of the logic unit is realized, and the specific process is as follows:

[0086] The circuit building work of the reconfigurable logic unit provided by the first aspect of the present application is completed by using SPICE software, the source of the P-MOSFET is connected to the voltage source VDD, the gate is connected to the independent voltage source Vp, the four gates of the N-FeFET are connected to the four segmented linear voltage sources VinA, VinB, VinC and VinD in turn, and the drain of the P-MOSFET is set as the output terminal Vout. p

[0087] Among them, the voltage source VDD connected to the source of the P-MOSFET is set as 1.5V, the independent voltage source Vp connected to the gate is set as 1V or 0V according to the need of logic function, and the four segmented linear voltage sources VinA, VinB, VinC and VinD are set as +4V or -4V when applying polarization voltage, and are set as 1V or 0V when applying logic signal voltage. p

[0088] Transient simulation is used to complete the logic function test of the reconfigurable logic unit. A complete logic operation is completed in two steps, including logic reconfiguration and logic calculation.

[0089] Among them, the logic reconfiguration is completed by setting the four segmented linear voltage sources VinA, VinB, VinC and VinD as polarization voltage +4V or -4V and setting the independent voltage source Vp as direct current voltage 1V or 0V; the logic calculation is completed by setting the four segmented linear voltage sources VinA, VinB, VinC and VinD as logic signal voltage 0V or 1V; the logic voltage signal 0V and 1V correspond to logic input "0" and logic input "1" respectively.

[0090] ​​In the transient simulation process, the polarization voltage of the four segmented linear voltage sources and the logic voltage signal are serially inputted. The direct current voltage of the independent voltage source Vp and the logic voltage signal of the segmented linear voltage source are parallelly inputted. After the logic function configuration is completed, the logic input signal is set to be '00', '01', '10' and '11' in sequence, and whether the voltage at the logic output end Vout meets the logic calculation result is observed. If the voltage at Vout is high voltage, the logic calculation result is '1'; if the voltage at Vout is low voltage, the logic calculation result is '0'.

[0091] An example of simulating a logic operation is shown in the figure, which shows the logic input signal and the logic output signal corresponding to the transient simulation waveform diagram in the logic operation process from logic Figure 3 to logic .

[0092] In the logic operation, VinA and VinB are first set to be polarization voltage +4V and -4V, and then VinA and VinB are set to be logic input signals '00', '01', '10' and '11' in sequence. In the logic operation, VinA and VinB are first set to be polarization voltage -4V and +4V, and then VinA and VinB are set to be logic input signals '00', '01', '10' and '11' in sequence. It can be seen from the output voltage waveform of Vout that the logic unit realizes accurate switching of the logic function and accurate simulation of the logic calculation.

[0093] The reconfigurable logic unit provided by the application for realizing complete Boolean logic adopts the gate of the FeFET as an input terminal, realizes logic reconfiguration and logic calculation by applying polarization voltage and logic signal voltage to the gate, and can complete a logic reconfiguration and logic calculation in two steps without the need of adding a separate calculation result reading step, thereby greatly shortening the time spent in the whole logic operation. Compared with the traditional CMOS logic gate, the reconfigurable logic unit provided by the application has the advantages of small area, low power consumption, easy process integration and strong dynamic reconfiguration capability, and can effectively solve the problems of device circuit solidification and insufficient flexibility, thereby providing technical support for the development of low-power reconfigurable logic circuit system.

[0094] In a third aspect, the application provides a reconfigurable logic system, comprising: a controller and the reconfigurable logic unit provided by the first aspect of the application.

[0095] The controller is used for executing the control method provided by the second aspect of the application.

[0096] ​The related technical solutions are the reconfigurable logic unit provided by the first aspect of the present application and the control method provided by the second aspect of the present application, which are not described herein again.

[0097] Those skilled in the art can understand that the above description is only the preferred embodiment of the present application, and is not used to limit the present application, and any modification, equivalent replacement and improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A control method for a reconfigurable logic unit, characterized in that, The reconfigurable logic unit includes: a P-type MOSFET, a first N-type FeFET, a second N-type FeFET, a third N-type FeFET, and a fourth N-type FeFET; Among them, the first N-type FeFET and the second N-type FeFET are connected in parallel; the third N-type FeFET and the fourth N-type FeFET are connected in parallel; the drains of the first N-type FeFET and the second N-type FeFET are both connected to the drains of the P-type MOSFET, and the sources of the first N-type FeFET and the second N-type FeFET are both connected to the drains of the third N-type FeFET and the fourth N-type FeFET; the sources of the third N-type FeFET and the fourth N-type FeFET are both grounded. The drain of the P-type MOSFET serves as the output terminal of the reconfigurable logic unit; The control method includes: controlling the on / off state of the P-type MOSFET, the polarization state of each N-type FeFET, and the on / off state under the polarization state in the reconfigurable logic unit, so that the reconfigurable logic unit performs the target logic operation; The types of the target logical operation include: true logical operation, false logical operation, and logical operation performed on the input logical value; the input logical value includes: logical value p and / or logical value q; The control method includes: When the target logic operation is a true logic operation, a positive power supply voltage VDD is connected to the S terminal, and a low-level voltage is applied to the G terminal; When the target logic operation is a false logic operation, the S terminal is grounded; When the target logic operation is a p logic operation, a positive power supply voltage VDD is pre-connected to the S terminal, and positive polarization voltages are applied to the A and C terminals respectively, while a negative polarization voltage is applied to the B terminal; then, a logic voltage signal is applied to the A terminal. A high-level voltage or a low-level voltage is applied to terminal B, a high-level voltage is applied to terminal C, and a high-level voltage is applied to terminal G. When the target logic operation is a q logic operation, a positive power supply voltage VDD is pre-connected to the S terminal, and positive polarization voltages are applied to the B and C terminals respectively, while a negative polarization voltage is applied to the A terminal; then, a high-level voltage or a low-level voltage is applied to the A terminal, and a logic voltage signal is applied to the B terminal. A high-level voltage is applied to terminal C, and a high-level voltage is applied to terminal G. When the target logical operation is During logic operations, a positive power supply voltage VDD is first connected to the S terminal, and positive polarization voltages are applied to the A and C terminals respectively, while a negative polarization voltage is applied to the B terminal. Then, a logic voltage signal p is applied to the A terminal, a high-level voltage or a low-level voltage is applied to the B terminal, a high-level voltage is applied to the C terminal, and a high-level voltage is applied to the G terminal. When the target logical operation is During logic operations, a positive power supply voltage VDD is first connected to the S terminal, and positive polarization voltages are applied to the B and C terminals respectively, while a negative polarization voltage is applied to the A terminal. Then, a high-level voltage or a low-level voltage is applied to the A terminal, a logic voltage signal q is applied to the B terminal, a high-level voltage is applied to the C terminal, and a high-level voltage is applied to the G terminal. When the target logical operation is During logic operations, a positive power supply voltage VDD is first connected to the S terminal, and positive polarization voltages are applied to the A terminal, the B terminal, and the C terminal respectively; then, a logic voltage signal p is applied to the A terminal, a logic voltage signal q is applied to the B terminal, a high-level voltage is applied to the C terminal, and a high-level voltage is applied to the G terminal; When the target logic operation is a p·q logic operation, a positive power supply voltage VDD is pre-connected to the S terminal, and positive polarization voltages are applied to the A, B, and C terminals respectively; then, a logic voltage signal is applied to the A terminal. A logic voltage signal is applied to terminal B. A high-level voltage is applied to terminal C, and a high-level voltage is applied to terminal G. When the target logical operation is p· During logic operations, a positive power supply voltage VDD is pre-connected to the S terminal, and positive polarization voltages are applied to the A, B, and C terminals respectively; then a logic voltage signal is applied to the A terminal. A logic voltage signal q is applied to terminal B, a high-level voltage is applied to terminal C, and a high-level voltage is applied to terminal G. When the target logical operation is During logic operations, a positive power supply voltage VDD is pre-connected to the S terminal, and positive polarization voltages are applied to the A, B, and C terminals respectively; then, a logic voltage signal p is applied to the A terminal, and a logic voltage signal p is applied to the B terminal. A high-level voltage is applied to terminal C, and a high-level voltage is applied to terminal G. When the target logical operation is During logic operations, a positive power supply voltage VDD is first connected to the S terminal, and positive polarization voltages are applied to the A and C terminals respectively, while a negative polarization voltage is applied to the B terminal. Then, a logic voltage signal p is applied to the A terminal, a low-level voltage is applied to the B terminal, a logic voltage signal q is applied to the C terminal, and a high-level voltage is applied to the G terminal. When the target logic operation is a p+q logic operation, a positive power supply voltage VDD is pre-connected to the S terminal, and positive polarization voltages are applied to the A and C terminals respectively, while a negative polarization voltage is applied to the B terminal; then, a logic voltage signal is applied to the A terminal. A low-level voltage is applied to terminal B, and a logic voltage signal is applied to terminal C. A high-level voltage is applied to the G terminal; When the target logical operation is p During logic operations, a positive power supply voltage VDD is pre-connected to the S terminal, and positive polarization voltages are applied to the A and C terminals respectively, while a negative polarization voltage is applied to the B terminal; then, a logic voltage signal is applied to the A terminal. A low-level voltage is applied to terminal B, a logic voltage signal q is applied to terminal C, and a high-level voltage is applied to terminal G. When the target logical operation is During the +q logic operation, a positive power supply voltage VDD is first connected to the S terminal, and positive polarization voltages are applied to the A and C terminals respectively, while a negative polarization voltage is applied to the B terminal. Then, a logic voltage signal p is applied to the A terminal, a low-level voltage is applied to the B terminal, and a logic voltage signal p is applied to the C terminal. A high-level voltage is applied to the G terminal; When the target logic operation is an XOR logic operation, a positive power supply voltage VDD is pre-connected to the S terminal, and positive polarization voltages are applied to the A, B, C, and D terminals respectively; then a logic voltage signal is applied to the A terminal. A logic voltage signal q is applied to terminal B, a logic voltage signal p is applied to terminal C, and a logic voltage signal p is applied to terminal D. A high-level voltage is applied to the G terminal; When the target logic operation is an XNOR logic operation, a positive power supply voltage VDD is pre-connected to the S terminal, and positive polarization voltages are applied to the A, B, C, and D terminals respectively; then a logic voltage signal is applied to the A terminal. A logic voltage signal is applied to terminal B. A logic voltage signal p is applied to terminal C, a logic voltage signal q is applied to terminal D, and a high-level voltage is applied to terminal G. The S terminal and the G terminal correspond to the source and gate of the P-type MOSFET, respectively; the A terminal is the gate of one of the first N-type FeFET and the second N-type FeFET; the B terminal is the gate of the other N-type FeFET; the C terminal is the gate of one of the third N-type FeFET and the fourth N-type FeFET; and the D terminal is the gate of the other N-type FeFET.

2. The control method according to claim 1, characterized in that, When the logic value p is 1, the logic voltage signal p is a high-level voltage. When the logic value p is 0, the logic voltage signal p is a low-level voltage. It is a high-level voltage; When the logic value q is 1, the logic voltage signal q is a high-level voltage. When the logic value q is 0, the logic voltage signal q is a low-level voltage. This is a high-level voltage.

3. The control method according to claim 2, characterized in that, In each logical operation, after the operation of applying the corresponding polarization voltage to different terminals is completed, the operation of applying the corresponding level voltage to different terminals is performed in parallel.

4. The control method according to claim 3, characterized in that, In each logical operation, the operation of applying the corresponding polarization voltage at different terminals is performed in parallel.

5. The control method according to any one of claims 1-4, characterized in that, When the output signal of the reconfigurable logic unit is a high-level voltage, the result of the target logic operation is 1; when the output signal of the reconfigurable logic unit is a low-level voltage, the result of the target logic operation is 0.

6. A reconfigurable logic system, characterized in that, include: Controllers and reconfigurable logic units; The reconfigurable logic unit includes: a P-type MOSFET, a first N-type FeFET, a second N-type FeFET, a third N-type FeFET, and a fourth N-type FeFET; Among them, the first N-type FeFET and the second N-type FeFET are connected in parallel; the third N-type FeFET and the fourth N-type FeFET are connected in parallel; the drains of the first N-type FeFET and the second N-type FeFET are both connected to the drains of the P-type MOSFET, and the sources of the first N-type FeFET and the second N-type FeFET are both connected to the drains of the third N-type FeFET and the fourth N-type FeFET; the sources of the third N-type FeFET and the fourth N-type FeFET are both grounded. The drain of the P-type MOSFET serves as the output terminal of the reconfigurable logic unit; The controller is used to execute the control method according to any one of claims 1-5.

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