A ferroelectric transistor-based reconfigurable logic cell, control method and reconfigurable logic system

Abstract

The application discloses a reconfigurable logic unit based on a ferroelectric transistor, a control method and a reconfigurable logic system, and belongs to the technical field of integrated circuit design; the reconfigurable logic unit comprises a P-type MOSFET, a first N-type FeFET, a second N-type FeFET and a third N-type FeFET; wherein the first N-type FeFET and the second N-type FeFET are connected in parallel, the drains of the two are connected with the drain of the P-type MOSFET, and the sources of the two are connected with the drain of the third N-type FeFET; the source of the third N-type FeFET is grounded; the reconfigurable logic unit takes the gate of the N-FeFET as an input terminal, and by fully utilizing the polarization characteristics of the ferroelectric device, the separation of high and low state threshold voltages can be realized under the control of a polarization voltage, so that logic reconfiguration is realized, and the reconfigurable logic unit has the advantages of small layout area, low computing power consumption, strong reconfiguration capability, compatibility with CMOS and easy process integration and the like.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of integrated circuit design, and more particularly, relates to a reconfigurable logic unit based on a ferroelectric transistor, a control method and a reconfigurable logic system. BACKGROUND

[0002] The "memory wall" of the Von Neumann architecture limits the improvement of chip computing performance, and the existing VLSI chip faces the bottleneck of computing power and energy efficiency. The energy efficiency demand of high-performance computing chips and the energy efficiency computing power provided by the existing Von Neumann architecture differ by 2-3 orders of magnitude, so it is urgent to use large-capacity, non-volatile memory devices and non-Von architecture technology to improve chip computing power and energy efficiency. Research shows that among many new types of non-volatile memories, ferroelectric transistor FeFET has a potential advantage in power consumption and can realize a structure similar to 3D NAND Flash, which has a potential advantage of high integration, so the ferroelectric transistor with short access time, low power consumption and compatibility with advanced manufacturing has become the most potential candidate in new non-volatile memories.

[0003] In recent years, research on ferroelectric material devices and chips has been an important high-tech field of microelectronics research, and there have been many research reports on FeFET in the fields of non-volatile memories, neural networks, reconfigurable devices, etc. In particular, since the first hafnium-based ferroelectric transistor compatible with CMOS technology was proposed in 2011, research on ferroelectric logic units and logic reconfiguration has been continuously deepened. For example, Sourav Dutta et al. published an article entitled Experimental Demonstration of Gate-Level Logic Camouflaging and Run-Time Reconfigurability Using Ferroelectric FET for Hardware Security in IEEE Transactions on Electron Devices, which first proposed a circuit module based on 8 FeFETs and used the threshold voltage programming of FeFET to realize a reconfigurable NOR / NAND / XNOR logic gate. Although this design takes into account logic reconfiguration, the layout area and power consumption cost are large, the reconfiguration capability of the designed structure unit is not strong, and only supports the reconfiguration of 3 kinds of logic, without maximizing the flexibility advantage of the circuit brought by reconfiguration. SUMMARY

[0004] In view of the above defects or improvement needs of the prior art, the application provides a reconfigurable logic unit based on a ferroelectric transistor, a control method and a reconfigurable logic system, which aims to provide a reconfigurable logic unit with small layout area, low computing power consumption and strong reconfiguration capability.

[0005] To achieve the above object, in a first aspect, the application provides a reconfigurable logic unit based on ferroelectric transistors, comprising a P-type MOSFET, a first N-type FeFET, a second N-type FeFET and a third N-type FeFET;

[0006] The first N-type FeFET and the second N-type FeFET are connected in parallel, and the drains of both are connected to the drain of the P-type MOSFET, and the sources of both are connected to the drain of the third N-type FeFET; the source of the third N-type FeFET is grounded;

[0007] The gates of the P-type MOSFET and each N-type FeFET serve as the input end of the reconfigurable logic unit, for receiving control signals to control the on-off state of the P-type MOSFET, and the polarization state and the on-off state under the polarization state of each N-type FeFET, so that the reconfigurable logic unit performs a target logic operation; the drain of the P-type MOSFET serves as the output end of the reconfigurable logic unit.

[0008] In a second aspect, the application provides a control method for the reconfigurable logic unit, comprising: controlling the on-off state of the P-type MOSFET, the polarization state and the on-off state under the polarization state of each N-type FeFET in the reconfigurable logic unit, so that the reconfigurable logic unit performs a target logic operation.

[0009] Further preferably, the type of the target logic operation includes: a true logic operation, a false logic operation and a logic operation on input logic values; wherein the input logic values include: a logic value p and / or a logic value q;

[0010] Let the source and gate of the P-type MOSFET be S end and G end; let the gate of any one of the first N-type FeFET and the second N-type FeFET be A end, and the gate of the other N-type FeFET be B end; let the gate of the third N-type FeFET be E end; the drain of the P-type MOSFET is the output end of the reconfigurable logic unit;

[0011] The above control method includes:

[0012] When the target logic operation is a true logic operation, a positive power voltage VDD is connected to the S end, and a low-level voltage is applied to the G end;

[0013] When the target logic operation is a false logic operation, the S end is grounded;

[0014] When the target logic operation is a p logic operation, a positive power voltage VDD is connected to the S end in advance, a positive polarization voltage is applied to the A end and the E end respectively, and a negative polarization voltage is applied to the B end; then a logic voltage signal A high level voltage or a low level voltage is applied at the B terminal, a high level voltage is applied at the E terminal, and a high level voltage is applied at the G terminal;

[0015] When the target logic operation is a q logic operation, a positive supply voltage VDD is connected to the S terminal in advance, a positive polarization voltage is applied at the A terminal and the E terminal, and a negative polarization voltage is applied at the B terminal. Then, a high level voltage or a low level voltage is applied at the A terminal, a logic voltage signal q is applied at the B terminal, a high level voltage is applied at the E terminal, and a high level voltage is applied at the G terminal. A high level voltage is applied at the E terminal, and a high level voltage is applied at the G terminal.

[0016] When the target logic operation is a logic operation, a positive supply voltage VDD is connected to the S terminal in advance, a positive polarization voltage is applied at the A terminal and the E terminal, and a negative polarization voltage is applied at the B terminal. Then, a logic voltage signal p is applied at the A terminal, a high level voltage or a low level voltage is applied at the B terminal, a high level voltage is applied at the E terminal, and a high level voltage is applied at the G terminal.

[0017] When the target logic operation is a logic operation, a positive supply voltage VDD is connected to the S terminal in advance, a positive polarization voltage is applied at the B terminal and the E terminal, and a negative polarization voltage is applied at the A terminal. Then, a high level voltage or a low level voltage is applied at the A terminal, a logic voltage signal q is applied at the B terminal, a high level voltage is applied at the E terminal, and a high level voltage is applied at the G terminal.

[0018] When the target logic operation is a logic operation, a positive supply voltage VDD is connected to the S terminal in advance, a positive polarization voltage is applied at the A terminal, the B terminal, and the E terminal. Then, a logic voltage signal p is applied at the A terminal, a logic voltage signal q is applied at the B terminal, a high level voltage is applied at the E terminal, and a high level voltage is applied at the G terminal.

[0019] When the target logic operation is a p·q logic operation, a positive supply voltage VDD is connected to the S terminal in advance, and a positive polarization voltage is applied at the A terminal, the B terminal, and the E terminal. Then, a logic voltage signal a logic voltage signal q is applied at the B terminal a high level voltage is applied at the E terminal, and a high level voltage is applied at the G terminal.

[0020] When the target logic operation is a logic operation, a positive supply voltage VDD is connected to the S terminal in advance, a positive polarization voltage is applied at the A terminal, the B terminal, and the E terminal. Then, a logic voltage signal a logic voltage signal q is applied at the B terminal, a high level voltage is applied at the E terminal, and a high level voltage is applied at the G terminal.

[0021] When the target logic operation is a In the logic operation, the positive supply voltage VDD is connected to the S terminal in advance, and the positive polarization voltage is applied to the A terminal and the E terminal respectively, and the negative polarization voltage is applied to the B terminal. Then the logic voltage signal p is applied to the A terminal, the low level voltage is applied to the B terminal, the logic voltage signal q is applied to the E terminal, and the high level voltage is applied to the G terminal. The high level voltage is applied to the E terminal, and the high level voltage is applied to the G terminal.

[0022] When the target logic operation is In the logic operation, the positive supply voltage VDD is connected to the S terminal in advance, and the positive polarization voltage is applied to the A terminal and the E terminal respectively, and the negative polarization voltage is applied to the B terminal. Then the logic voltage signal p is applied to the A terminal, the low level voltage is applied to the B terminal, the logic voltage signal q is applied to the E terminal, and the high level voltage is applied to the G terminal.

[0023] When the target logic operation is p+q logic operation, the positive supply voltage VDD is connected to the S terminal in advance, and the positive polarization voltage is applied to the A terminal and the E terminal respectively, and the negative polarization voltage is applied to the B terminal. Then the logic voltage signal p is applied to the A terminal, the low level voltage is applied to the B terminal, the logic voltage signal q is applied to the E terminal, and the high level voltage is applied to the G terminal. The low level voltage is applied to the B terminal, and the logic voltage signal q is applied to the E terminal. The high level voltage is applied to the G terminal.

[0024] When the target logic operation is In the logic operation, the positive supply voltage VDD is connected to the S terminal in advance, and the positive polarization voltage is applied to the A terminal and the E terminal respectively, and the negative polarization voltage is applied to the B terminal. Then the logic voltage signal p is applied to the A terminal, the low level voltage is applied to the B terminal, the logic voltage signal q is applied to the E terminal, and the high level voltage is applied to the G terminal. The low level voltage is applied to the B terminal, the logic voltage signal q is applied to the E terminal, and the high level voltage is applied to the G terminal.

[0025] When the target logic operation is In the logic operation, the positive supply voltage VDD is connected to the S terminal in advance, and the positive polarization voltage is applied to the A terminal and the E terminal respectively, and the negative polarization voltage is applied to the B terminal. Then the logic voltage signal p is applied to the A terminal, the low level voltage is applied to the B terminal, the logic voltage signal q is applied to the E terminal, and the high level voltage is applied to the G terminal. The high level voltage is applied to the G terminal.

[0026] Further preferably, when the logic value p is 1, the logic voltage signal p is a high level voltage, and the logic voltage signal is a low level voltage; when the logic value p is 0, the logic voltage signal p is a low level voltage, and the logic voltage signal is a high level voltage.

[0027] When the logic value q is 1, the logic voltage signal q is a high level voltage, and the logic voltage signal is a low level voltage; when the logic value q is 0, the logic voltage signal q is a low level voltage, and the logic voltage signal is a high level voltage.

[0028] Further preferably, in each logic operation, the operation of applying corresponding polarization voltage to different terminals is performed in parallel with the operation of applying corresponding level voltage to different terminals.

[0029] Further preferably, in each logic operation, the operation of applying corresponding polarization voltage to different terminals is performed in parallel.

[0030] Further preferably, when the output signal of the reconfigurable logic unit is a high level voltage, the result of the target logic operation is 1; when the output signal of the reconfigurable logic unit is a low level voltage, the result of the target logic operation is 0.

[0031] In a third aspect, the present application provides a reconfigurable logic system, comprising a controller and the reconfigurable logic unit provided in the first aspect of the present application.

[0032] The controller is configured to perform the control method provided in the second aspect of the present application.

[0033] In general, the above technical solutions conceived by the present application can achieve the following beneficial effects:

[0034] 1. The present application provides a reconfigurable logic unit based on ferroelectric transistors, comprising a P-type MOSFET and three N-type FeFETs. Among the three N-FeFETs, two N-FeFETs are connected in parallel, with their drain connected to the drain of the P-MOSFET and their source connected to the drain of the other N-FeFET. The reconfigurable logic unit uses the gate of the N-FeFET as a logic input terminal. By fully utilizing the polarization characteristics of ferroelectric devices, it can separate the high and low state threshold voltages under the control of polarization voltage. Only one P-type MOSFET and three N-type FeFETs are needed to realize dynamic reconfiguration of 14 Boolean logic, with the advantages of small layout area, low computing power consumption, strong reconfiguration ability, CMOS compatibility, and easy process integration.

[0035] 2. The present application provides a control method for a reconfigurable logic unit, which can flexibly input corresponding voltage signals to the gates of the P-type MOSFET and each N-type FeFET according to the type of logic operation to be implemented, realizing up to 14 kinds of logic reconfiguration and effectively solving the problems of device circuit solidification and lack of flexibility.

[0036] 3. Further, the control method for the reconfigurable logic unit provided by the present application performs the operation of applying corresponding polarization voltage to different terminals in parallel, and then performs the operation of applying corresponding level voltage to different terminals in parallel, which can complete a logic reconfiguration and logic calculation in two steps without the need to add a separate calculation result reading step, greatly shortening the time spent on the entire logic operation. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 A structure schematic diagram of a reconfigurable logic unit based on a ferroelectric transistor is provided for an embodiment of the present application.

[0038] Figure 2 An N-FeFET high state and low state threshold voltage separation schematic diagram is provided for an embodiment of the present application. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical scheme and advantages of the present application clearer, the present application is further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application. In addition, the technical features involved in each embodiment of the present application described below can be combined with each other as long as they do not conflict with each other.

[0040] In order to achieve the above-mentioned purpose, in a first aspect, as shown in the present application provides a reconfigurable logic unit based on a ferroelectric transistor, comprising: a P-type MOSFET, a first N-type FeFET, a second N-type FeFET and a third N-type FeFET. Figure 1

[0041] The first N-type FeFET and the second N-type FeFET are connected in parallel, and the drains of both are connected to the drain of the P-type MOSFET, and the sources of both are connected to the drain of the third N-type FeFET; the source of the third N-type FeFET is grounded.

[0042] Among them, the gate of the P-type MOSFET and each N-type FeFET is used as the input end of the reconfigurable logic unit (wherein the gate of the ferroelectric transistor is used as the logic signal input end), for receiving control signals, to adjust the on-off state of the P-type MOSFET, and the polarization state and on-off state under the polarization state of each N-type FeFET, so that the reconfigurable logic unit performs target logic operation; the drain of the P-type MOSFET is used as the output end of the reconfigurable logic unit.

[0043] The reconfigurable logic unit uses a direct current voltage as a logic input signal. When the direct current voltage applied to the gate of the N-FeFET is a voltage greater than 0V, it corresponds to logic input "1"; when the direct current voltage applied to the gate of the N-FeFET is 0V, it corresponds to logic input "0".

[0044] The logic unit uses the voltage V out of the P-MOSFET drain as a logic output signal. When V out is a high level voltage, it corresponds to logic output "1"; when V out is a low level voltage, it corresponds to logic output "0".​

[0045] As a pull-up device in a logic cell, the P-MOSFET's on or off state is determined by the voltage applied to its gate. Specifically, when the voltage applied to the P-MOSFET gate is high, the P-MOSFET operates in the off state; when the voltage applied to the P-MOSFET gate is low, the P-MOSFET operates in the on state.

[0046] Due to the unique polarization characteristics of the ferroelectric layer, the conduction or blocking state of an N-FeFET is determined by the polarization voltage and logic signal voltage applied sequentially to its gate. Specifically, when the polarization voltage applied to the gate of an N-FeFET is a positive voltage: if the DC voltage subsequently applied to its gate is high, the N-FeFET operates in the conduction state; if the DC voltage subsequently applied to its gate is low, the N-FeFET operates in the blocking state. When the polarization voltage applied to the gate of an N-FeFET is a negative voltage: if the DC voltage subsequently applied to its gate is high, the N-FeFET operates in the blocking state; if the DC voltage subsequently applied to its gate is low, the N-FeFET operates in the blocking state.

[0047] This is because the polarization voltage can change the polarization state of the ferroelectric layer inside the transistor, causing a shift in the threshold voltage of the N-FeFET transistor, resulting in a separation between the high-state and low-state threshold voltages, such as... Figure 2 As shown. Specifically, when the polarization voltage applied to the N-FeFET gate is a positive voltage, the N-FeFET threshold voltage shifts to the left, forming a low threshold voltage V. TL When the polarization voltage applied to the gate of an N-FeFET is negative, the N-FeFET threshold voltage shifts to the right, forming a high threshold voltage V. TH The shift in threshold voltage causes the N-FeFET to exist in either a conducting or blocking state when a logic input signal is applied, resulting in different logic calculation results. The aforementioned reconfigurable logic unit utilizes this to complete the logic reconfiguration design.

[0048] When performing a logic calculation, the logic unit must first be configured according to the logic function, including applying a voltage to the gate of the P-MOSFET to determine its operating state and applying a polarization voltage to the gate of the N-FeFET to determine its polarization state. Then, according to the logic function, the gates of two N-FeFETs are selected as selection logic signal input terminals, and a DC voltage signal is applied to complete the logic calculation.

[0049] The 14 possible logic configurations and logic signal input terminals of the reconfigurable logic unit provided by this invention are given in Table 1. Here, "A", "B", and "E" represent selectable logic input terminals. Specifically, "A" represents the gate of any N-type FeFET selected from the first N-type FeFET and the second N-type FeFET; "B" represents the gate of the other N-type FeFET among the first and second N-type FeFETs; and "E" represents the gate of the third N-type FeFET. "p", "q", Represents the logic input signals, "A", "B", "V". p In the column, "1" indicates a high-level voltage is applied, and "0" indicates a low-level voltage is applied. "C", "D", and "F" indicate the polarization voltage direction applied to the N-FeFET; "1" in columns "C", "D", and "F" indicates a positive polarization voltage is applied, and "0" indicates a negative polarization voltage is applied. V p This indicates the gate bias voltage of the P-MOSFET, which is the signal applied to the gate (G terminal) of the P-type MOSFET.

[0050] Table 1

[0051]

[0052]

[0053] When the gates of two parallel N-FeFETs are selected as input terminals, the reconfigurable logic unit can implement 10 reconfigurable Boolean logic operations: logic "1", logic "0", logic "p", logic "q", and logic "q". logic logic Logical "p·q", logical logic At this time, the N-FeFET connected in series with it remains in the on state.

[0054] When the reconfigurable logic unit selects the gates of two N-FeFETs connected in series as input terminals, it can implement the remaining four types of reconfigurable Boolean logic: logic... Logical "p+q", logical logic At this time, the N-FeFET connected in parallel remains in a blocked state.

[0055] It should be noted that, in the above logic, "1" represents a true logical operation, "0" represents a false logical operation, "p" represents a p logical operation, and "q" represents a q logical operation. That is Logical operations, logic That is Logical operations, logic That is Logical operations, the logical "p·q" is the p·q logical operation, logical... That is Logical operations, logic That is Logical operations, logic That is Logical operations, the logical "p+q" is the same as the p+q logical operation. That is Logical operations, logic That is Logical operations.

[0056] When the reconfigurable logic unit performs a logic "1" operation, the P-MOSFET is in the on state, and when performing other logic operations, the P-MOSFET remains in the blocked state.

[0057] Regarding the reconfigurable logic unit provided in the first aspect, the second aspect of the present invention provides a control method thereof, comprising: controlling the on / off state of the P-type MOSFET, the polarization state of each N-type FeFET, and the on / off state under the polarization state in the reconfigurable logic unit, so that the reconfigurable logic unit performs a target logic operation. The types of the target logic operation include: true logic operation, false logic operation, and logic operation performed on input logic values; the input logic values ​​include: logic value p and / or logic value q;

[0058] In one optional implementation, the above control method specifically includes:

[0059] When the target logic operation is a true logic operation, a positive power supply voltage VDD is connected to the S terminal, and a low-level voltage is applied to the G terminal;

[0060] When the target logic operation is a false logic operation, ground the S terminal;

[0061] When the target logic operation is a p logic operation, a positive power supply voltage VDD is pre-connected to the S terminal, and positive polarization voltages are applied to the A and E terminals respectively, while a negative polarization voltage is applied to the B terminal; then, a logic voltage signal is applied to the A terminal. Apply a high-level voltage or a low-level voltage to terminal B, apply a high-level voltage to terminal E, and apply a high-level voltage to terminal G.

[0062] When the target logic operation is a q logic operation, a positive power supply voltage VDD is pre-connected to the S terminal, and positive polarization voltages are applied to the B and E terminals respectively, while a negative polarization voltage is applied to the A terminal. Then, a high-level voltage or a low-level voltage is applied to the A terminal, and a logic voltage signal is applied to the B terminal. Apply a high-level voltage to terminal E and a high-level voltage to terminal G;

[0063] When the target logical operation is During logic operations, a positive power supply voltage VDD is first connected to the S terminal, and positive polarization voltages are applied to the A and E terminals respectively, and a negative polarization voltage is applied to the B terminal; then, a logic voltage signal p is applied to the A terminal, a high-level voltage or a low-level voltage is applied to the B terminal, a high-level voltage is applied to the E terminal, and a high-level voltage is applied to the G terminal.

[0064] When the target logical operation is During logic operations, a positive power supply voltage VDD is first connected to the S terminal, and positive polarization voltages are applied to the B and E terminals respectively, while a negative polarization voltage is applied to the A terminal. Then, a high-level voltage or a low-level voltage is applied to the A terminal, a logic voltage signal q is applied to the B terminal, a high-level voltage is applied to the E terminal, and a high-level voltage is applied to the G terminal.

[0065] When the target logical operation is During logic operations, a positive power supply voltage VDD is first connected to the S terminal, and positive polarization voltages are applied to the A, B, and E terminals respectively; then, a logic voltage signal p is applied to the A terminal, a logic voltage signal q is applied to the B terminal, a high-level voltage is applied to the E terminal, and a high-level voltage is applied to the G terminal.

[0066] When the target logic operation is a p·q logic operation, a positive power supply voltage VDD is pre-connected to the S terminal, and positive polarization voltages are applied to the A, B, and E terminals respectively; then, a logic voltage signal is applied to the A terminal. Apply a logic voltage signal to terminal B. Apply a high-level voltage to terminal E and a high-level voltage to terminal G;

[0067] When the target logical operation is During logic operations, a positive power supply voltage VDD is first connected to the S terminal, and positive polarization voltages are applied to the A, B, and E terminals respectively; then, a logic voltage signal is applied to the A terminal. Apply a logic voltage signal q to terminal B, apply a high-level voltage to terminal E, and apply a high-level voltage to terminal G.

[0068] When the target logical operation is During logic operations, a positive power supply voltage VDD is first connected to the S terminal, and positive polarization voltages are applied to the A, B, and E terminals respectively; then, a logic voltage signal p is applied to the A terminal, and a logic voltage signal p is applied to the B terminal. Apply a high-level voltage to terminal E and a high-level voltage to terminal G;

[0069] When the target logical operation is During logic operations, a positive power supply voltage VDD is first connected to the S terminal, and positive polarization voltages are applied to the A and E terminals respectively, and a negative polarization voltage is applied to the B terminal; then, a logic voltage signal p is applied to the A terminal, a low-level voltage is applied to the B terminal, a logic voltage signal q is applied to the E terminal, and a high-level voltage is applied to the G terminal.

[0070] When the target logic operation is a p+q logic operation, a positive power supply voltage VDD is pre-connected to the S terminal, and positive polarization voltages are applied to the A and E terminals respectively, while a negative polarization voltage is applied to the B terminal; then, a logic voltage signal is applied to the A terminal. Apply a low-level voltage to terminal B and a logic voltage signal to terminal E. Apply a high-level voltage to the G terminal;

[0071] When the target logical operation is During logic operations, a positive power supply voltage VDD is first connected to the S terminal, and positive polarization voltages are applied to the A and E terminals respectively, while a negative polarization voltage is applied to the B terminal; then, a logic voltage signal is applied to the A terminal. Apply a low-level voltage to terminal B, apply a logic voltage signal q to terminal E, and apply a high-level voltage to terminal G.

[0072] When the target logical operation is During logic operations, a positive power supply voltage VDD is first connected to the S terminal, and positive polarization voltages are applied to the A and E terminals respectively, while a negative polarization voltage is applied to the B terminal. Then, a logic voltage signal p is applied to the A terminal, a low-level voltage is applied to the B terminal, and a logic voltage signal p is applied to the E terminal. Apply a high-level voltage to the G terminal.

[0073] In one optional implementation, when the logic value p is 1, the logic voltage signal p is a high-level voltage. The logic voltage signal p is a low-level voltage; when the logic value p is 0, the logic voltage signal p is a low-level voltage. It is a high-level voltage;

[0074] When the logic value q is 1, the logic voltage signal q is a high-level voltage. When the logic value q is 0, the logic voltage signal q is a low-level voltage. This is a high-level voltage.

[0075] In one optional implementation, when the output signal of the reconfigurable logic unit is a high-level voltage, the result of the logic operation is 1; when the output signal of the reconfigurable logic unit is a low-level voltage, the result of the logic operation is 0.

[0076] Preferably, the polarization voltage applied to the N-FeFET gate and the logic voltage signal are serial inputs, while the voltage applied to the P-MOSFET gate and the logic voltage signal applied to the N-FeFET gate are parallel inputs, allowing for logic reconstruction and logic calculation to be performed in only two steps. Specifically, in one optional embodiment, after performing the operation of applying the corresponding polarization voltage to different terminals in each logic operation, the operation of applying the corresponding level voltage to different terminals is performed in parallel. In another optional embodiment, the operation of applying the corresponding polarization voltage to different terminals is performed in parallel in each logic operation.

[0077] In one optional embodiment, the high-level voltage is 1 to 1.2V, and the low-level voltage is 0 to 0.2V. Preferably, the high-level voltage is set to 1V, and the low-level voltage is set to 0V.

[0078] In one optional embodiment, the positive polarization voltage is 3 to 5V, and the negative polarization voltage is -5 to -3V. Preferably, the positive polarization voltage is 4V, and the negative polarization voltage is -4V.

[0079] In one alternative implementation, the positive power supply voltage VDD is 1.5V.

[0080] Thirdly, the present invention provides a reconfigurable logic system, including: a controller, and the reconfigurable logic unit provided in the first aspect of the present invention;

[0081] The controller is used to execute the control method provided in the second aspect of the present invention.

[0082] The related technical solutions are the same as the reconfigurable logic unit provided in the first aspect of the present invention and the control method provided in the second aspect of the present invention, and will not be described in detail here.

[0083] The present invention provides a reconfigurable logic unit design based on ferroelectric transistors, which flexibly uses the gate of the ferroelectric transistor as the input terminal, makes full use of the polarization characteristics of ferroelectric devices, and realizes logic reconfiguration by applying polarization voltage to control the separation of high-state and low-state threshold voltages.

[0084] Compared with traditional CMOS logic gates, the reconfigurable logic unit provided by this invention has advantages such as small area, low power consumption, easy process integration and dynamic reconfigurability, providing technical support for the development of low-power reconfigurable logic circuit system.

[0085] Compared to other reconfigurable logic gates, the reconfigurable logic unit provided by this invention can complete a logic reconfiguration and logic calculation in two steps, without the need for a separate calculation result reading step, greatly shortening the time spent on the entire logic operation. It also possesses strong reconfiguration capabilities, capable of performing up to 14 different logic reconfigurations, effectively solving the problems of fixed device circuits and insufficient flexibility.

[0086] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A control method for a reconfigurable logic unit, characterized in that, The reconfigurable logic unit includes: a P-type MOSFET, a first N-type FeFET, a second N-type FeFET, and a third N-type FeFET; The first N-type FeFET and the second N-type FeFET are connected in parallel, and their drains are both connected to the drain of the P-type MOSFET. Their sources are both connected to the drain of the third N-type FeFET. The source of the third N-type FeFET is grounded. The drain of the P-type MOSFET serves as the output terminal of the reconfigurable logic unit; The control method includes: controlling the on / off state of the P-type MOSFET, the polarization state of each N-type FeFET, and the on / off state under the polarization state in the reconfigurable logic unit, so that the reconfigurable logic unit performs the target logic operation; The types of the target logical operation include: true logical operation, false logical operation, and logical operation performed on the input logical value; the input logical value includes: logical value p and / or logical value q; The control method includes: When the target logic operation is a true logic operation, a positive power supply voltage VDD is connected to the S terminal, and a low-level voltage is applied to the G terminal; When the target logic operation is a false logic operation, the S terminal is grounded; When the target logic operation is a p logic operation, a positive power supply voltage VDD is pre-connected to the S terminal, and positive polarization voltages are applied to the A and E terminals respectively, while a negative polarization voltage is applied to the B terminal; then, a logic voltage signal is applied to the A terminal. A high-level voltage or a low-level voltage is applied to terminal B, a high-level voltage is applied to terminal E, and a high-level voltage is applied to terminal G. When the target logic operation is a q logic operation, a positive power supply voltage VDD is pre-connected to the S terminal, and positive polarization voltages are applied to the B and E terminals respectively, while a negative polarization voltage is applied to the A terminal; then, a high-level voltage or a low-level voltage is applied to the A terminal, and a logic voltage signal is applied to the B terminal. A high-level voltage is applied to terminal E, and a high-level voltage is applied to terminal G. When the target logical operation is During logic operations, a positive power supply voltage VDD is first connected to the S terminal, and positive polarization voltages are applied to the A and E terminals respectively, while a negative polarization voltage is applied to the B terminal. Then, a logic voltage signal p is applied to the A terminal, a high-level voltage or a low-level voltage is applied to the B terminal, a high-level voltage is applied to the E terminal, and a high-level voltage is applied to the G terminal. When the target logical operation is During logic operations, a positive power supply voltage VDD is first connected to the S terminal, and positive polarization voltages are applied to the B and E terminals respectively, while a negative polarization voltage is applied to the A terminal. Then, a high-level voltage or a low-level voltage is applied to the A terminal, a logic voltage signal q is applied to the B terminal, a high-level voltage is applied to the E terminal, and a high-level voltage is applied to the G terminal. When the target logical operation is During logic operations, a positive power supply voltage VDD is first connected to the S terminal, and positive polarization voltages are applied to the A terminal, the B terminal, and the E terminal respectively; then, a logic voltage signal p is applied to the A terminal, a logic voltage signal q is applied to the B terminal, a high-level voltage is applied to the E terminal, and a high-level voltage is applied to the G terminal. When the target logic operation is a p·q logic operation, a positive power supply voltage VDD is pre-connected to the S terminal, and positive polarization voltages are applied to the A, B, and E terminals respectively; then a logic voltage signal is applied to the A terminal. A logic voltage signal is applied to terminal B. A high-level voltage is applied to terminal E, and a high-level voltage is applied to terminal G. When the target logical operation is p· During logic operations, a positive power supply voltage VDD is pre-connected to the S terminal, and positive polarization voltages are applied to the A, B, and E terminals respectively; then a logic voltage signal is applied to the A terminal. A logic voltage signal q is applied to terminal B, a high-level voltage is applied to terminal E, and a high-level voltage is applied to terminal G. When the target logical operation is During logic operations, a positive power supply voltage VDD is pre-connected to the S terminal, and positive polarization voltages are applied to the A, B, and E terminals respectively; then, a logic voltage signal p is applied to the A terminal, and a logic voltage signal p is applied to the B terminal. A high-level voltage is applied to terminal E, and a high-level voltage is applied to terminal G. When the target logical operation is During logic operations, a positive power supply voltage VDD is first connected to the S terminal, and positive polarization voltages are applied to the A and E terminals respectively, while a negative polarization voltage is applied to the B terminal. Then, a logic voltage signal p is applied to the A terminal, a low-level voltage is applied to the B terminal, a logic voltage signal q is applied to the E terminal, and a high-level voltage is applied to the G terminal. When the target logic operation is a p+q logic operation, a positive power supply voltage VDD is pre-connected to the S terminal, and positive polarization voltages are applied to the A and E terminals respectively, while a negative polarization voltage is applied to the B terminal; then, a logic voltage signal is applied to the A terminal. A low-level voltage is applied to terminal B, and a logic voltage signal is applied to terminal E. A high-level voltage is applied to the G terminal; When the target logical operation is p During logic operations, a positive power supply voltage VDD is pre-connected to the S terminal, and positive polarization voltages are applied to the A and E terminals respectively, while a negative polarization voltage is applied to the B terminal; then, a logic voltage signal is applied to the A terminal. A low-level voltage is applied to terminal B, a logic voltage signal q is applied to terminal E, and a high-level voltage is applied to terminal G. When the target logical operation is During the +q logic operation, a positive power supply voltage VDD is first connected to the S terminal, and positive polarization voltages are applied to the A and E terminals respectively, while a negative polarization voltage is applied to the B terminal. Then, a logic voltage signal p is applied to the A terminal, a low-level voltage is applied to the B terminal, and a logic voltage signal p is applied to the E terminal. A high-level voltage is applied to the G terminal; The S terminal and the G terminal correspond to the source and gate of the P-type MOSFET, respectively; the A terminal is the gate of one of the first N-type FeFET and the second N-type FeFET; the B terminal is the gate of the other N-type FeFET, which is either the first N-type FeFET or the second N-type FeFET; and the E terminal is the gate of the third N-type FeFET in the reconfigurable logic unit.

2. The control method according to claim 1, characterized in that, When the logic value p is 1, the logic voltage signal p is a high-level voltage. When the logic value p is 0, the logic voltage signal p is a low-level voltage. It is a high-level voltage; When the logic value q is 1, the logic voltage signal q is a high-level voltage. When the logic value q is 0, the logic voltage signal q is a low-level voltage. This is a high-level voltage.

3. The control method according to any one of claims 2, characterized in that, In each logical operation, after the operation of applying the corresponding polarization voltage to different terminals is completed, the operation of applying the corresponding level voltage to different terminals is performed in parallel.

4. The control method according to claim 3, characterized in that, In each logical operation, the operation of applying the corresponding polarization voltage at different terminals is performed in parallel.

5. The control method according to any one of claims 1-4, characterized in that, When the output signal of the reconfigurable logic unit is a high-level voltage, the result of the target logic operation is 1; when the output signal of the reconfigurable logic unit is a low-level voltage, the result of the target logic operation is 0.

6. A reconfigurable logic system, characterized in that, include: Controller and reconfigurable logic unit; The reconfigurable logic unit includes: a P-type MOSFET, a first N-type FeFET, a second N-type FeFET, and a third N-type FeFET; The first N-type FeFET and the second N-type FeFET are connected in parallel, and their drains are both connected to the drain of the P-type MOSFET. Their sources are both connected to the drain of the third N-type FeFET. The source of the third N-type FeFET is grounded. The drain of the P-type MOSFET serves as the output terminal of the reconfigurable logic unit; The controller is used to execute the control method according to any one of claims 1-5.

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