Transmitter equalization drive circuit and method of processing a signal to be transmitted

Abstract

This invention discloses a transmitter equalization drive circuit and a method for processing the signal to be transmitted. The circuit includes: a serialization and retiming module for generating multiple parallel data streams based on the signal to be transmitted; a data selector module connected to the serialization and retiming module for receiving a clock signal corresponding to each parallel data stream and generating process data including front-tap data, main-tap data, first back-tap data, and second back-tap data based on the parallel data and the clock signal; a pulse generation module connected to the data selector module for receiving the process data and generating front-tap equalization pulses and first back-tap equalization pulses; and a hybrid equalization drive module connected to the pulse generation module and the data selector module for receiving the front-tap data, front-tap equalization pulses, main-tap data, first back-tap equalization pulses, and second back-tap data to generate the output signal of the signal to be transmitted. This circuit improves the signal quality of the output signal.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a transmitter equalization drive circuit and a method for processing the signal to be transmitted. Background Technology

[0002] With the rapid development of communication technology and the significant increase in data transmission volume between communication devices, achieving fast data transmission between communication components has become increasingly important. However, limited by the number of chip pins and the strict timing requirements between parallel lines, traditional parallel data transmission cannot meet the ever-growing demand for high-speed bandwidth data transmission, posing a serious challenge to parallel data transmission. To address these issues, the SerDes (serializer / deserializer) system emerged, rapidly developing and gradually replacing parallel data transmission.

[0003] Currently, a SerDes system consists of three parts: a transmitter, a wired channel, and a receiver. However, due to non-ideal factors such as the skin effect, dielectric loss, and signal reflection in the wired channel, the signal transmission quality is severely affected, causing the eye diagram of the received signal to shrink or even close. Furthermore, with the rapid increase in signal transmission rates, signal quality attenuation becomes even more severe, further impacting the operating range and signal transmission rate of the SerDes system.

[0004] To address the aforementioned issues, SerDes systems typically employ feedforward equalizers (FFE), decision feedback equalizers (DFE), and continuous-time linear equalizers (CTLE). However, these solutions are still limited by fixed compensation ranges and equalization capabilities. For instance, traditional FFE and DFE are essentially high-pass FIR filters with a fixed peak compensation frequency at the Nyquist frequency. CTLE primarily compensates for channel attenuation by increasing the high-frequency components of the signal; its zero-pole pair enhancement technique inevitably leads to noise amplification and a fixed compensation slope. Furthermore, FFE in SerDes transmitters often employs de-emphasis equalization of the low-frequency components of the attenuated signal, exhibiting high-pass filter characteristics to compensate for low-pass attenuation. However, this approach reduces the signal output amplitude, resulting in a decrease in the transmitter output swing. Furthermore, in existing related technologies, the interval between two adjacent taps of FFE is an integer interval (i.e., one UI, a unit symbol interval). Equalization based on integer intervals can eliminate inter-symbol interference of the signal through pre-decision, but this method does not have flexible and adjustable equalization capabilities to cope with the complex and ever-changing working environment of the SerDes system, resulting in excessively low signal quality of the transmitter signal of the SerDes system. Summary of the Invention

[0005] In view of this, this application provides a transmitter equalization drive circuit and a method for processing the signal to be transmitted, the main purpose of which is to solve the technical problem of low signal quality of the transmitter signal in the existing SerDes system.

[0006] According to a first aspect of the invention, a transmitter equalization drive circuit is provided for use in a SerDes transmitter, the circuit comprising:

[0007] A serialization and retiming module is used to receive the signal to be transmitted and generate multiple parallel data corresponding to the signal to be transmitted.

[0008] A data selector module, which is connected to the serialization and retiming module, is used to receive a clock signal corresponding to each of the parallel data streams, and generate front tap data, main tap data, first back tap data, and second back tap data based on the multiple parallel data streams and the clock signal corresponding to each of the parallel data streams.

[0009] The code interval between the front tap data and the main tap data, and between the first back tap data and the main tap data, is a preset fraction of a code interval.

[0010] A pulse generation module, connected to the data selector module, is used to receive the front tap data, the main tap data, and the first back tap data, and generate a front tap equalization pulse and a first back tap equalization pulse.

[0011] A hybrid equalization driving module, which is connected to the pulse generation module and the data selector module, is used to receive the front tap equalization pulse, the main tap data, the first back tap equalization pulse and the second back tap data, and generate the output signal of the signal to be transmitted.

[0012] According to a second aspect of the present invention, a method for processing a signal to be transmitted is provided, applied in the above-described transmitter equalization drive circuit, the method comprising:

[0013] The signal to be transmitted is acquired, and the signal to be transmitted is delayed to obtain the front tap data, main tap data, first back tap data and second back tap data corresponding to the signal to be transmitted, respectively.

[0014] Wherein, the difference between the front tap data and the main tap data and between the main tap data and the first back tap data is a preset fraction of symbol interval, and the difference between the main tap data and the second back tap data is an integer of symbol interval.

[0015] Based on the phase difference between the front tap data and the main tap data, a pre-emphasis pulse for the front tap data is generated; based on the phase difference between the main tap data and the first rear tap data, a pre-emphasis pulse for the first rear tap data is generated; and based on the second rear tap data, a second rear tap deemphasis data is generated.

[0016] The output signal is obtained by superimposing the pre-emphasis pulse of the front tap data, the pre-emphasis pulse of the first rear tap data, the deemphasis data of the second rear tap, and the main tap data.

[0017] This invention provides a transmitter equalization drive circuit and a method for processing the signal to be transmitted. Based on a serialization and retiming module, the received signal to be transmitted is aligned and synchronized to obtain multiple parallel data streams. Each parallel data stream is then sent to a data selector module. Simultaneously, a pre-set clock signal corresponding to each parallel data stream is sent to the data selector module, causing the data selector module to generate front-tap data, main-tap data, first back-tap data, and second back-tap data. Here, the phase difference between the clock signals corresponding to adjacent parallel data streams can be between 0° and 90°, and the specific phase difference value can be predetermined. Multiple clock signals are input to the data selector module. By adjusting the phase difference between the clock signals corresponding to the parallel data streams, the front-tap data, main-tap data, first back-tap data, and second back-tap data generated from the parallel data can be synchronized. There is a specific phase difference between the tap data and the second post-tap data. Further, the front tap data, main tap data, first post-tap data, and second post-tap data with the specific phase difference are input into the pulse generation module. Based on the phase difference between the front tap data and the main tap data, a front tap equalization pulse for pre-emphasing the main tap data is generated. Similarly, based on the phase difference between the main tap data and the first post-tap data, a first post-tap equalization pulse for pre-emphasing the main tap data is generated. Further, the front tap equalization pulse, main tap data, first post-tap equalization pulse, and second post-tap data are input into the hybrid equalization drive module, enabling the hybrid equalization drive module to obtain an output signal that optimizes the signal swing and the output eye diagram, thus solving the problem of low signal quality at the transmitter of the existing SerDes system.

[0018] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0019] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this application, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings:

[0020] Figure 1 This figure shows one of the structural schematic diagrams of a transmitter equalization drive circuit provided in an embodiment of the present invention;

[0021] Figure 2 This diagram illustrates the principle of de-emphasis equalization based on tap data with integer symbol intervals, according to an embodiment of the present invention.

[0022] Figure 3 This diagram illustrates the principle of pre-emphasis equalization based on tap data with fractional symbol intervals, as provided in an embodiment of the present invention.

[0023] Figure 4 This is a second schematic diagram of a transmitter equalization drive circuit provided in an embodiment of the present invention;

[0024] Figure 5 This diagram illustrates the structure of a clock module according to an embodiment of the present invention.

[0025] Figure 6 A schematic diagram of an equalized pulse width control circuit provided in an embodiment of the present invention is shown;

[0026] Figure 7 This diagram illustrates the structure of a front-tap equalization pulse generation unit according to an embodiment of the present invention.

[0027] Figure 8 This diagram illustrates the structure of a first back-tap equalization pulse generation unit according to an embodiment of the present invention.

[0028] Figure 9 This diagram illustrates an AND and OR gate structure constituting a front-tap equalization pulse generation unit and a first rear-tap equalization pulse generation unit according to an embodiment of the present invention.

[0029] Figure 10 The diagram illustrates the waveforms of a front-tap equalization pulse and a first rear-tap equalization pulse provided in an embodiment of the present invention.

[0030] Figure 11 This is shown as a third schematic diagram of a transmitter equalization drive circuit according to an embodiment of the present invention;

[0031] Figure 12 This diagram illustrates a structural schematic of a forward drive circuit provided in an embodiment of the present invention.

[0032] Figure 13This diagram illustrates a structural schematic of a negative drive circuit provided in an embodiment of the present invention.

[0033] Figure 14 The diagram shows an equivalent circuit diagram of a conventional main tap driving circuit and a conventional first back tap driving circuit for integer interval de-emphasis equalization provided by an embodiment of the present invention, as well as an equivalent circuit diagram of a main tap driving circuit and a first back tap driving circuit for fractional interval pre-emphasis equalization.

[0034] Figure 15 An amplitude analysis diagram provided by an embodiment of the present invention is shown;

[0035] Figure 16 A comparative analysis chart of normalized power consumption provided by an embodiment of the present invention is shown;

[0036] Figure 17 This diagram illustrates the frequency response curve of a first back-tap drive circuit according to an embodiment of the present invention.

[0037] Figure 18 A flowchart illustrating a method for processing a signal to be transmitted according to an embodiment of the present invention is shown;

[0038] Figure 19 The diagram illustrates a processing method based on a signal to be transmitted, according to an embodiment of the present invention, which performs signal quality enhancement processing on the signal to be transmitted. Detailed Implementation

[0039] The present invention will be described in detail below with reference to the accompanying drawings and embodiments. It should be noted that, unless otherwise specified, the embodiments and features described in the present application can be combined with each other.

[0040] Existing SerDes systems consist of three parts: a transmitter, a wired channel, and a receiver. However, non-ideal factors in the wired channel, such as the skin effect, dielectric loss, and signal reflection, severely impact signal transmission quality, causing the eye diagram of the received signal to shrink or even close. Simultaneously, the rapid increase in signal transmission rates exacerbates signal quality attenuation, significantly affecting the operating range and transmission rate of the SerDes system. To address these issues, feedforward equalizers (FFEs), decision feedback equalizers (DFEs), and continuous-time linear equalizers (CTLEs) are typically incorporated into SerDes systems. However, these solutions are still limited by fixed compensation ranges and equalization capabilities, lacking the flexible and adjustable equalization capabilities to cope with the complex and ever-changing operating environment of SerDes systems, resulting in excessively low signal quality at the transmitter end.

[0041] To address the above problems, in one embodiment, such as Figure 1 As shown, a transmitter equalization drive circuit is provided. Taking its application in a SerDes transmitter as an example, the circuit includes a serialization and retiming module 1000, a data selector module 2000, a pulse generation module 3000, and a hybrid equalization drive module. Here, the transmitter equalization drive circuit can transmit four-level pulse amplitude modulation (PAM4) signals and non-return-to-zero (NRZ) signals. This embodiment uses the transmission of PAM4 signals as an example; other similar signal types are also applicable to this embodiment.

[0042] Specifically, the serialization and retiming module 1000 is used to receive the signal to be transmitted and generate multiple parallel data corresponding to the signal to be transmitted. The serialization and retiming module 1000 can be an integrated serialization circuit and a retiming circuit. The signal to be transmitted can be a PAM4 signal, which is 64 parallel data channels, divided into 32 high-order parallel data channels and 32 low-order parallel data channels. The high-order parallel data and the low-order parallel data can be processed based on two identical transmitter equalization drive circuits, and the signal processing principles are the same for both. In this embodiment, the transmitter equalization drive circuit for processing the high-order parallel data is used as an example for explanation. The workflow for processing the low-order parallel data can refer to the workflow for processing the high-order parallel data, and will not be repeated here.

[0043] Specifically, the signal to be transmitted is input into the serialization circuit in the serialization and retiming module 1000 to obtain four parallel data corresponding to the signal to be transmitted. These four parallel data are then input into the retiming circuit for signal alignment and synchronization to obtain four parallel data with a rate one-quarter of the final transmitted signal rate. Here, these four parallel data can be sequentially delayed and timed to obtain four parallel data with a preset unit symbol interval (UI) between adjacent parallel data. In this embodiment, the preset symbol interval can be 1UI.

[0044] Furthermore, the data selector module 2000 is connected to the serialization and retiming module 1000, and is used to receive a clock signal corresponding to each of the parallel data streams, and generate front tap data, main tap data, first back tap data and second back tap data based on the multiple parallel data streams and the clock signal corresponding to each of the parallel data streams.

[0045] The clock signals are pre-configured by relevant personnel, and the phase difference between each clock signal can be pre-selected and input into the data selector module 2000. Here, the clock signals can be four-phase clocks, with each clock signal corresponding to one parallel data stream, used to adjust the phase difference between the parallel data streams. When the phase difference between the first clock signal and the second clock signal, the second clock signal and the third clock signal, and the third clock signal and the fourth clock signal received by the data selector module 2000 is 90°, the data output by the data selector module 2000 is 1UI between the front tap data and the main tap data, the main tap data and the first rear tap data, and the first rear tap data and the second rear tap data. At this time, the interval between the front tap data and the main tap data, the main tap data and the first rear tap data, and the first rear tap data and the second rear tap data is an integer UI. In the embodiments of this application, the phase difference between the first clock signal corresponding to the first parallel data and the second clock signal corresponding to the second parallel data received by the data selector module 2000 can be pre-selected within the range of 0° to 90°, for adjusting the phase difference between the front tap data and the main tap data. UI, among which As a tap delay factor, its value ranges from 0 to 1. The value range is determined by the phase difference between the first clock signal and the second clock signal. The closer the phase difference is to 0°, the better. The closer the phase difference is to 0, the closer it is to 90°. The closer it is to 1.

[0046] Furthermore, the phase difference between the second clock signal corresponding to the second parallel data and the third clock signal corresponding to the third parallel data received by the data selector module 2000 can be pre-selected within the range of 0° to 90°, and is used to adjust the phase difference between the main tap data and the first post-tap data. UI, among which As a tap delay factor, its value ranges from 0 to 1. The value range is determined by the phase difference between the second and third clock signals. The closer the phase difference is to 0°, the better. The closer the phase difference is to 0, the closer it is to 90°. The closer it is to 1. Furthermore, the second clock signal received by the data selector module 2000 corresponding to the second parallel data and the fourth clock signal corresponding to the fourth parallel data can be the same. Based on the above method, it is possible to ensure that the pre-tap data and main tap data generated by the data selector module are spaced by a preset fraction of a symbol interval, the first post-tap data and the main tap data are spaced by a preset fraction of a symbol interval, and the pre-tap data and the second post-tap data are spaced by a preset integer of a symbol interval.

[0047] Furthermore, the pulse generation module 3000 is connected to the data selector module 2000, and is used to receive the front tap data, the main tap data, and the first back tap data, and generate a front tap equalization pulse and a first back tap equalization pulse. Furthermore, Figure 2 The principle diagram of existing de-emphasis equalization based on tap data with integer symbol intervals is given, such as... Figure 2 As shown, the FFE in the SerDes transmitter often adopts the following... Figure 2 The low-frequency component de-emphasis equalization method of the attenuated signal shown is as follows: input data reaches the main tap element 2 through buffer 1, and simultaneously reaches the back tap element 4 through buffer 1 and a 1UI delay unit 3. The un-equalized main tap pre-equalization data (i.e., the un-equalized input data reaching the back tap) is subtracted from the un-equalized main tap pre-equalization data (i.e., the un-equalized input data reaching the back tap), thus achieving de-emphasis equalization. In this case, FFE exhibits high-pass filter characteristics to compensate for the high-frequency attenuation of the channel, but this method causes a decrease in the signal output amplitude (from -1 to 1 to -1+G to 1-G, where G is the equalization strength of the back tap), resulting in a reduction in transmitter swing. Based on this, in this embodiment, the main tap data and the second back tap data are spaced by an integer symbol interval. Based on the above principle, back tap pre-equalization data can be generated from the second back tap data to achieve de-emphasis on the output signal, resulting in an integer-interval de-emphasis transmitter equalization drive circuit.

[0048] Furthermore, Figure 3 A schematic diagram of pre-emphasis equalization based on tap data with fractional symbol intervals is presented, solving the output swing reduction caused by traditional deemphasis equalization methods. Figure 3The pre-emphasis equalization method shown here enhances the high-frequency components of the signal. Input data passes through buffer 1 to the main tap element 2 and the back tap element 4. Simultaneously, input data passes through buffer 1 and the αUI (α, the tap delay coefficient, ranging from 0 to 1) delay unit 5 to the back tap element 4. The two data streams arriving at the back tap element 4 are processed to generate a pre-emphasis equalization pulse with a width of αUI. Pre-emphasis equalization is achieved by superimposing the pre-emphasis equalization pulse generated in the back tap element 4 onto the data before main tap equalization. In this case, FFE also exhibits high-pass filter characteristics to compensate for the attenuation of the high-frequency components of the channel. This pre-emphasis equalization method does not cause a reduction in output swing; instead, it increases the output swing and reduces power consumption. Furthermore, by adjusting the tap delay coefficient α, an scalable compensation range and flexible equalization can be achieved. Based on this, in this embodiment, the symbol interval between the front tap data and the first back tap data and the main tap data is a fraction. According to the above principle, the front tap equalization pulse and the first back tap equalization pulse are generated as pre-emphasis equalization pulses based on the front tap data, the first back tap data and the main tap data, so as to pre-emphasize the output signal and obtain the transmitter equalization drive circuit with fractional interval pre-emphasis.

[0049] Specifically, because the difference between the front tap data and the main tap data output by the data selector module 2000 is... In the UI, the difference between the first tap data and the main tap data is... UI and The values ​​are all between 0 and 1, and can be generated by the pulse generation module 3000 with widths of... UI and The UI's front tap equalization pulse and first back tap equalization pulse serve as pre-emphasis equalization pulses for pre-emphasing the data signal.

[0050] Furthermore, the hybrid equalization driver module 4000 is connected to the pulse generation module 3000 and the data selector module 2000, and is used to receive the front-tap equalization pulse, the main tap data, the first back-tap equalization pulse, and the second back-tap data to generate the output signal of the signal to be transmitted. Specifically, the hybrid equalization driver module 4000 can receive the front-tap equalization pulse and the first back-tap equalization pulse from the pulse generation module 3000, and the main tap data and the second back-tap data from the data selector module 2000. A buffer (not shown in the figure) can be provided on the data path between the hybrid equalization driver module 4000 and the data selector module 2000 to optimize the transmission rate of the main tap data and the second back-tap data. Furthermore, the hybrid equalization driver module 4000 can generate back-tap equalization pre-data based on the second back-tap data, and superimpose the main tap data based on the front-tap equalization pulse, the first back-tap equalization pulse, and the back-tap equalization pre-data to obtain an optimized output signal, which is then transmitted based on the channel.

[0051] The transmitter equalization drive circuit provided in this embodiment can align and synchronize the received transmitted signal based on the serialization and retiming module to obtain multiple parallel data streams. Each parallel data stream is then sent to a data selector module. Simultaneously, a pre-set clock signal corresponding to each parallel data stream is sent to the data selector module, causing the data selector module to generate front-tap data, main-tap data, first back-tap data, and second back-tap data. Here, the phase difference between the clock signals corresponding to adjacent parallel data streams can be between 0° and 90°, and the specific phase difference value can be predetermined. Multiple clock signals are input to the data selector module. At this time, by adjusting the phase difference between the clock signals corresponding to the parallel data streams, the front-tap data, main-tap data, first back-tap data, and second back-tap data generated based on the parallel data can be... The second back tap data has a specific phase difference. Further, the front tap data, main tap data, first back tap data, and second back tap data with the specific phase difference are input into the pulse generation module. Based on the phase difference between the front tap data and the main tap data, a front tap equalization pulse for pre-emphasing the main tap data is generated. Similarly, based on the phase difference between the main tap data and the first back tap data, a first back tap equalization pulse for pre-emphasing the main tap data is generated. Further, the front tap equalization pulse, main tap data, first back tap equalization pulse, and second back tap data are input into the hybrid equalization drive module, enabling the hybrid equalization drive module to obtain an output signal that optimizes the signal swing and the output eye diagram, thus solving the problem of low signal quality at the transmitter of the existing SerDes system.

[0052] In one embodiment, such as Figure 4As shown, the data selector module 2000 includes multiple data selectors, each connected to the serialization and retiming module 1000. Each data selector receives one channel of parallel data and the corresponding clock signal. The data selector can be a 4:1 data selector, used to convert the received parallel data into serial data. The multiple data selectors include a front-tap data selector 2100, a main-tap data selector 2200, a first back-tap data selector 2300, and a second back-tap data selector 2400. The parallel data includes first parallel data, second parallel data, third parallel data, and fourth parallel data. Specifically, the front-tap data selector 2100 receives the first parallel data, the main-tap data selector 2200 receives the second parallel data, the first back-tap data selector 2300 receives the third parallel data, and the second back-tap data selector 2400 receives the fourth parallel data.

[0053] Furthermore, the front-tap data selector 2100 is also connected to the pulse generation module 3000, for receiving the first parallel data and a first clock signal corresponding to the first parallel data, generating the front-tap data, and sending the front-tap data to the pulse generation module 3000; the main-tap data selector 2200 can also be connected to the hybrid equalization driving module 4000 through the first buffer 6000, and is also connected to the pulse generation module 3000, for receiving the second parallel data and a second clock signal corresponding to the second parallel data, generating the main-tap data, and sending the main-tap data to the hybrid equalization driving module 4000 and the pulse generation module 3000. The pulse generation module 3000 is described above; the first post-tap data selector 2300 is also connected to the pulse generation module 3000, and is used to receive the third parallel data and the third clock signal corresponding to the third parallel data, generate the first post-tap data, and send the first post-tap data to the pulse generation module 3000; the second post-tap data selector 2400 can also be connected to the hybrid equalization driving module 4000 through the second buffer 7000, and is used to receive the fourth parallel data and the fourth clock signal corresponding to the fourth parallel data, generate the second post-tap data, and send the second post-tap data to the hybrid equalization driving module 4000.

[0054] Furthermore, each set of serial data passes through a single-ended to differential circuit in the data selector, so that the generated front-tap data includes front-tap positive differential data DPpre and front-tap negative differential data DNpre; the generated main-tap data includes main-tap positive differential data DPmain and main-tap negative differential data DNmain; the generated first back-tap data includes first back-tap positive differential data DPPST1 and first back-tap negative differential data DNPSST1; and the generated second back-tap data includes second back-tap positive differential data DPPST2 and second back-tap negative differential data DNPSST2. The embodiments provided in this application enable multiple data selectors, each of which can generate serial data corresponding to the received parallel data and the corresponding clock data, and ensure that the serial data have a specific phase difference to facilitate subsequent signal processing.

[0055] In one embodiment, such as Figure 4 As shown, the transmitter equalization drive circuit also includes a clock module 5000, which is connected to the data selector module 2000. The clock module 5000 receives the original clock signal and, in response to a received clock adjustment command, generates a clock signal corresponding to each of the parallel data streams. It then sends the clock signals to the corresponding data selector modules 2000. Specifically, as... Figure 5 As shown, the clock module 5000 includes a buffer 5100, a four-phase clock generation circuit 5200, and an equalized pulse width control circuit 5300 connected in series. The buffer 5100 receives the original clock signal and sends it to the four-phase clock generation circuit 5200 to generate four-phase clock signals. Further, the four-phase clock generation circuit 5200 sends the four-phase clock signals to the equalized pulse width control circuit 5300. Based on a preset phase difference between the clock signals sent to each data selector, the equalized pulse width control circuit 5300 adjusts the phase of the four-phase clock signals, generating four clock signals with specific phase differences between them. These clock signals are then sent to the corresponding data selectors, ensuring that the front-tap data output by the front-tap data selector 2100 and the main-tap data selector 2200 have a fractional symbol interval between their front-tap data and main-tap data, and that the main-tap data output by the main-tap data selector 2200 and the first rear-tap data selector 2300 have a fractional symbol interval between their main-tap data and first rear-tap data.

[0056] Furthermore, when the equalized pulse width control circuit is in operation, it generates three sets of four-phase clocks with a certain phase difference based on the received four-phase clock signals. Specifically, the four-phase clock corresponding to the first tap data is PH0-90-180-270PRE, the four-phase clock for the main tap data and the second rear tap is PH0-90-180-270MAIN, and the four-phase clock for the first rear tap data is PH0-90-180-270PST1. Further, the four-phase clock for the main tap data can be the same as the four-phase clock for the second rear tap data. Here, PH0, PH90, PH180, and PH270 represent the four phases of the four-phase clock, respectively. The generated three sets of four-phase clocks serve as the sampling clocks for the data selector. Further, based on... Figure 6 The principle of the equalized pulse width control circuit is explained, such as... Figure 6 As shown in (a), when using traditional integer interval equalization, under the action of the equalization pulse width control circuit, the phase difference between two adjacent sets of four-phase clocks, PH0-90-180-270PRE, PH0-90-180-270MAIN, and PH0-90-180-270PST1, is 90°. Figure 6 In the first phase PH0PRE of the first parallel data, the first phase PH0MAIN of the second parallel data, and the first phase PH0PST1 of the third parallel data, the phase difference between two adjacent clocks is 90°, and the clock principle is the same for the other four phases. After parallel-to-serial conversion by a 4:1 data selector, the resulting front-tap data DPRE, main-tap data DMAIN, and first rear-tap data DPST1 are each 1UI apart, i.e., an integer interval. For example... Figure 6 As shown in (b), when fractional interval equalization is used, under the action of the equalization pulse width control circuit, the phase difference between two adjacent sets of four-phase clocks can be adjusted between the four-phase clocks PH0-90-180-270PRE corresponding to the front tap data, PH0-90-180-270MAIN corresponding to the main tap data, and PH0-90-180-270PST1 corresponding to the first rear tap data. The adjustment range is 0~90°. After the parallel-to-serial conversion by the data selector, the phase difference between the front tap data DPRE and the main tap data DMAIN is... UI, among which The variation range is 0~1, and the difference between the main tap data DMAIN and the first post-tap data DPST1 is... UI, among which The variation range is 0~1. The above data, after being processed by the equalization pulse generation circuit, can generate pulses with widths of... UI and UI pre-emphasis equalization pulse.

[0057] Furthermore, the clock corresponding to the serialization and retiming module can be obtained by further frequency division based on the clock corresponding to the data selector. The embodiments provided in this application can adjust the phase difference between clocks based on the clock module, sending clock signals with a preset phase difference to the data selector, so that there is a fractional symbol interval between the front tap data and the main tap data, and a fractional symbol interval between the main tap data and the first rear tap data. This allows for the generation of pre-emphasis pulses based on the fractional symbol interval between the tap data, improving the output swing and output signal quality.

[0058] In one embodiment, such as Figure 4 As shown, the pulse generation module 3000 includes a front-tap equalization pulse generation unit 3100 and a first rear-tap equalization pulse generation unit 3200. The front-tap equalization pulse generation unit 3100 is connected to both the front-tap data selector 2100 and the main-tap data selector 2200, and is used to receive the front-tap data and the main-tap data, generate the front-tap equalization pulse, and send the front-tap equalization pulse to the hybrid equalization drive module 4000.

[0059] Specifically, the front-tap data includes front-tap positive differential data DPpre and front-tap negative differential data DNpre; the main-tap data includes main-tap positive differential data DPmain and main-tap negative differential data DNmain; the front-tap equalization pulses include: a first positive front-tap equalization pulse ENPpre, a first negative front-tap equalization pulse ENNpre, a second positive front-tap equalization pulse EPPpre, and a second negative front-tap equalization pulse EPNpre. The front-tap positive differential data DPpre and the front-tap negative differential data DNpre form a set of differential signals, generated by the front-tap data selector.

[0060] Furthermore, the pre-tap equalization pulse generation unit includes a first AND gate and a first OR gate, such as... Figure 7As shown, the first input terminal of the first AND gate 3110 and the first input terminal of the first OR gate 3120 are respectively connected to the first output terminal of the front tap data selector, for receiving the front tap positive differential data DPpre. The second input terminal of the first AND gate 3110 and the second input terminal of the first OR gate 3120 are respectively connected to the first output terminal of the main tap data selector, for receiving the main tap negative differential data DNmain. The output terminal of the first AND gate 3110 is connected to the hybrid equalization driving module, for sending the first positive front tap equalization pulse ENPpre to the hybrid equalization driving module. The output terminal of the first OR gate 3120 is connected to the hybrid equalization driving module, for sending the first negative front tap equalization pulse ENNpre to the hybrid equalization driving module.

[0061] Furthermore, the front-tap equalization pulse generation unit also includes a second AND gate and a second OR gate, such as... Figure 7 As shown, the first input terminal of the second AND gate 3130 and the first input terminal of the second OR gate 3140 are respectively connected to the second output terminal of the front tap data selector, for receiving the front tap negative differential data DNpre. The second input terminal of the second AND gate 3130 and the second input terminal of the second OR gate 3140 are respectively connected to the second output terminal of the main tap data selector, for receiving the main tap positive differential data DPmain. The output terminal of the second AND gate 3130 is connected to the hybrid equalization driving module, for sending the second positive front tap equalization pulse EPPpre to the hybrid equalization driving module. The output terminal of the second OR gate 3140 is connected to the hybrid equalization driving module, for sending the second negative front tap equalization pulse EPNpre to the hybrid equalization driving module.

[0062] Furthermore, such as Figure 4As shown, the first back-tap equalization pulse generation unit 3300 is connected to both the main tap data selector 2200 and the first back-tap data selector 2300, and is used to receive the main tap data and the first back-tap data, generate the first back-tap equalization pulse, and send the first back-tap equalization pulse to the hybrid equalization drive module 4000. Further, the first back-tap data includes first back-tap positive differential data DPPST1 and first back-tap negative differential data DNpst1; the second back-tap data includes second back-tap positive differential data DPPST2 and second back-tap negative differential data DNpst2; the first back-tap equalization pulse includes: a first positive first back-tap equalization pulse ENPpst1, a first negative first back-tap equalization pulse ENNpst1, a second positive first back-tap equalization pulse EPPpst1, and a second negative first back-tap equalization pulse EPNpst1.

[0063] The first post-tap equalization pulse generation unit 3300 includes a third AND gate and a third OR gate, such as... Figure 8 As shown, the first input terminal of the third AND gate 3310 and the first input terminal of the third OR gate 3320 are respectively connected to the first output terminal of the first back tap data selector, for receiving the first back tap positive differential data DPpst1. The second input terminal of the third AND gate 3310 and the second input terminal of the third OR gate 3320 are respectively connected to the first output terminal of the main tap data selector, for receiving the main tap negative differential data DNmain. The output terminal of the third AND gate 3310 is connected to the hybrid equalization driving module, for sending the first positive first back tap equalization pulse ENPpst1 to the hybrid equalization driving module. The output terminal of the third OR gate 3320 is connected to the hybrid equalization driving module, for sending the first negative first back tap equalization pulse ENNpst1 to the hybrid equalization driving module.

[0064] Furthermore, the first post-tap equalization pulse generation unit also includes a fourth AND gate and a fourth OR gate, such as... Figure 8As shown, the first input terminal of the fourth AND gate 3330 and the first input terminal of the fourth OR gate 3340 are respectively connected to the second output terminal of the first back tap data selector, for receiving the first back tap negative differential data DNpst1. The second input terminal of the fourth AND gate 3330 and the second input terminal of the fourth OR gate 3340 are respectively connected to the second output terminal of the main tap data selector, for receiving the main tap positive differential data DPmain. The output terminal of the fourth AND gate 3330 is connected to the hybrid equalization driving module, for sending the second positive first back tap equalization pulse EPPpst1 to the hybrid equalization driving module. The output terminal of the fourth OR gate 3340 is connected to the hybrid equalization driving module, for sending the second negative first back tap equalization pulse EPNpst1 to the hybrid equalization driving module.

[0065] The transistor sizes constituting the first AND gate, second AND gate, third AND gate, fourth AND gate, first OR gate, second OR gate, third OR gate, and fourth OR gate are optimized to minimize parasitics and improve operating speed; the sizes of each of the above AND gates and OR gates are optimized based on the waveform characteristics of their corresponding input signals.

[0066] Furthermore, in combination Figure 9 , Figure 10 The principles of the front-tap equalization pulse generation unit in generating the first positive forward-tap equalization pulse ENPpre, the first negative forward-tap equalization pulse ENNpre, the second positive forward-tap equalization pulse EPPpre, and the second negative forward-tap equalization pulse EPNpre, as well as the principles of the first rear-tap equalization pulse generation unit in generating the first positive first rear-tap equalization pulse ENPpst1, the first negative first rear-tap equalization pulse ENNpst1, the second positive first rear-tap equalization pulse EPPpst1, and the second negative first rear-tap equalization pulse EPNpst1, are explained. Taking the generation process of the first positive forward-tap equalization pulse ENPpre as an example, as follows... Figure 9 As shown, only when Figure 9 (a) The first AND gate and Figure 9 (b) The rising edge of the first positive forward-tap equalization pulse ENPpre is generated only when the two input signals of the first OR gate, the front-tap positive differential data DPpre and the main-tap negative differential data DNmain, transition from logic low to logic high. The front-tap positive differential data DPpre is input through interface A, and the main-tap negative differential data DNmain is input through interface B. Since the rising edge of the front-tap positive differential data DPpre always occurs after the rising edge of the main-tap negative differential data DNmain, the rising edge of the first positive forward-tap equalization pulse ENPpre is determined by the rising edge of the front-tap positive differential data DPpre. Therefore, Figure 9In (a), the pull-up transistor M1, controlled by the main tap negative differential data DNmain, can be set to a small size to reduce parasitic capacitance, while the pull-down transistor M2 can be set to a large size to achieve low transmission impedance. These transistor size optimizations in a two-input AND gate also apply to the transistors in a two-input OR gate, because they have opposite push-pull structures (the pull-up network of an AND gate is the same as the pull-down network of an OR gate, and the pull-down network of an AND gate is the same as the pull-up network of an OR gate). Therefore, Figure 9 In (a), transistors M1 and M3 can be set to small size, while transistors M2 and M4 can be set to large size, thereby minimizing parasitics and improving the operating speed of the equalization pulse generation circuit.

[0067] Furthermore, such as Figure 10 (a) An example is shown of the waveforms of the front-tap equalization pulses generated by the front-tap equalization pulse generation unit, including the waveforms of the front-tap positive differential data DPpre and front-tap negative differential data DNpre used to generate the front-tap equalization pulses, as well as the main-tap data, the main-tap positive differential data DPmain and the main-tap negative differential data DNmain, and the waveforms of the generated first positive front-tap equalization pulse ENPpre, first negative front-tap equalization pulse ENNpre, second positive front-tap equalization pulse EPPpre, and second negative front-tap equalization pulse EPNpre. From Figure 10 As can be seen from this, by adjusting the delay between the positive differential data DPpre and the negative differential data DNpre of the front tap, and between the positive differential data DPmain and the negative differential data DNmain of the main tap ( In the picture =1), which can adjust the width of the generated first positive forward tap equalization pulse ENPpre, first negative forward tap equalization pulse ENNpre, second positive forward tap equalization pulse EPPpre, and second negative forward tap equalization pulse EPNpre, which are used as pre-emphasis equalization pulses. Figure 10(b) An example is shown of the waveform of the first back-tap equalization pulse generated by the first back-tap equalization pulse generation unit, including the waveforms of the main tap positive differential data DPmain, the main tap negative differential data DNmain, the first back-tap positive differential data DPPst1, and the first back-tap negative differential data DNpst1, as well as the waveforms of the generated first positive first back-tap equalization pulse ENPpst1, the first negative first back-tap equalization pulse ENNpst1, the second positive first back-tap equalization pulse EPPpst1, and the second negative first back-tap equalization pulse EPNpst1. It can be seen from the figure that by adjusting the delay between the main tap positive differential data DPmain and the main tap negative differential data DNmain and the first back-tap positive differential data DPpst1 or the first back-tap negative differential data DNpst1 (…), the first back-tap equalization pulse can be effectively generated. In the picture =0.5), the widths of the generated first positive first back-tap equalization pulse ENPpst1, first negative first back-tap equalization pulse ENNpst1, second positive first back-tap equalization pulse EPPpst1, and second negative first back-tap equalization pulse EPNpst1, which serve as pre-emphasis equalization pulses, can be adjusted. In the embodiments provided in this application, the front-tap pre-emphasis equalization pulse and the first back-tap pre-emphasis equalization pulse are generated before and after the main tap data edge, respectively, and the pulse widths can be flexibly adjusted due to tap delay. UI and The UI can be flexibly adjusted under the action of the equalization pulse width control circuit. Therefore, based on the front tap and the first back tap, flexible fractional interval pre-emphasis equalization can be achieved.

[0068] In one embodiment, such as Figure 11As shown, the hybrid equalization drive module 4000 includes a hybrid equalization drive unit 4100 and a bias circuit unit 4200. Specifically, the hybrid equalization drive unit 4100 is connected to the pulse generation module 3000 and the data selector module 2000, and is used to receive the front-tap equalization pulse, the main tap data, the first back-tap equalization pulse, and the second back-tap data, and generate the output signal of the signal to be transmitted. Further, the bias circuit unit 4200 is connected to the hybrid equalization drive unit 4100, and is used to generate and send a bias signal to the hybrid equalization drive unit 4100 to control the amplitude of the output signal in response to the received signal amplitude command. The bias signals include a positive forward tap bias signal VPpre, a negative forward tap bias signal VNpre, a positive main tap bias signal VPmain, a negative main tap bias signal VNmain, a positive first rear tap bias signal VPpst1, a negative first rear tap bias signal VNpst1, a positive second rear tap bias signal VPpst2, and a negative second rear tap bias signal VNpst2. The embodiments provided in this application can generate bias signals based on the bias circuit unit to control the magnitude of the pre-emphasis on the signal, thereby improving the controllability of the output signal amplitude.

[0069] In one embodiment, such as Figure 11As shown, the hybrid equalization driving unit 4100 includes a positive driving circuit 4110, a negative driving circuit 4120, and a signal output circuit 4130. The positive driving circuit 4110 is used to receive the first positive forward tap equalization pulse ENPpre, the main tap negative differential data DNmain, the first positive first back tap equalization pulse ENPpst1, the second back tap positive differential data DPpst2, the positive forward tap bias signal VPpre, the negative forward tap bias signal VNpre, the negative main tap bias signal VNmain, the positive first back tap bias signal VPpst1, the negative first back tap bias signal VNpst1, the negative second back tap bias signal VNpst2, the first negative first back tap equalization pulse ENNpst1, and the first... A negative forward tap equalization pulse ENNpre is generated to produce positive mixed output data. The negative drive circuit 4120 is used to receive the second positive forward tap equalization pulse EPPpre, the main tap positive differential data DPmain, the second positive first back tap equalization pulse EPPpst1, the second back tap negative differential data DNpst2, the positive forward tap bias signal VPpre, the negative forward tap bias signal VNpre, the negative main tap bias signal VNmain, the positive first back tap bias signal VPpst1, the negative first back tap bias signal VNpst1, the negative second back tap bias signal VNpst2, the second negative first back tap equalization pulse EPNpst1, and the second negative forward tap equalization pulse EPNpre to generate negative mixed output data. Furthermore, the signal output circuit 4130 is connected to the positive driving circuit 4110 and the negative driving circuit 4120 to acquire the positive mixed output data and the negative mixed output data, and to generate the output signal based on the positive mixed output data and the negative mixed output data.

[0070] Furthermore, such as Figure 12 As shown, the forward drive circuit includes multiple forward sub-circuits, and each forward sub-circuit is connected to the others through a forward circuit connection point C1 provided on each forward sub-circuit. The forward sub-circuit includes a forward front tap drive circuit 4111, a forward main tap drive circuit 4112, a forward first rear tap drive circuit 4113, and a forward second rear tap drive circuit 4114. The forward main tap drive circuit is provided with a forward signal output terminal TXP.

[0071] Furthermore, such as Figure 12As shown, the forward tap driving circuit 4111 adopts an SST structure, including a first resistor R1 and a first current bias transistor P1, a first control pulse transistor P2, a second current bias transistor N3, and a second control pulse transistor N4 connected in series. The first current bias transistor P1 can be a PMOS current bias transistor, the first control pulse transistor P2 can be a PMOS control pulse transistor, the second current bias transistor N3 can be an NMOS current bias transistor, and the second control pulse transistor N4 can be an NMOS control pulse transistor. The source of the first current bias transistor P1 is connected to a first power supply (not shown in the figure), and the drain of the first current bias transistor P1 is connected to the source of the first control pulse transistor P2. The drain of a control pulse transistor P2 is connected to the drain of a second current bias transistor N3. The source of the second current bias transistor N3 is connected to the drain of a second control pulse transistor N4. A first resistor R1 is connected in parallel between the source and drain of the second control pulse transistor N4. The source of the second control pulse transistor N4 is grounded. The forward circuit connection point C1 is located between the first control pulse transistor P2 and the second current bias transistor N3. The forward tap driving circuit 4111 is used to connect the forward tap bias signal VPpre, the negative forward tap bias signal VNpre, the first negative forward tap equalization pulse ENNpre, and the first forward tap equalization pulse ENPpre to the forward driving circuit.

[0072] Specifically, the gate of the first current bias transistor P1 is connected to the first output terminal of the bias circuit unit to receive the positive forward tap bias signal VPpre; the gate of the first control pulse transistor P2 is connected to the output terminal of the first OR gate to receive the first negative forward tap equalization pulse ENNpre; the gate of the second current bias transistor N3 is connected to the second output terminal of the bias circuit unit to receive the negative forward tap bias signal VNpre; and the gate of the second control pulse transistor N4 is connected to the output terminal of the first AND gate to receive the first positive forward tap equalization pulse ENPpre.

[0073] Furthermore, the forward main tap drive circuit 4112 includes a second resistor R2, a first terminating resistor Rt1, and a third current bias transistor N5 and a first switching transistor S1 connected in series. The forward main tap drive circuit 4112 adopts a tailless CML structure. The third current bias transistor N5 can be an NMOS current bias transistor, and the first switching transistor S1 can be an NMOS switching transistor, used to achieve integer intervals to enhance equalization while ensuring the driving capability of the hybrid equalization drive circuit. The first terminal of the first terminating resistor Rt1 is connected to a second power supply (not shown in the figure), and the second terminal of the first terminating resistor Rt1 is connected to the third current bias transistor. The drain of the body transistor N5, the source of the third current bias transistor N5 is connected to the drain of the first switching transistor S1, the second resistor R2 is connected in parallel between the source and drain of the first switching transistor S1, the source of the first switching transistor S1 is grounded, the positive signal output terminal TXP is set at the second end of the first terminating resistor Rt1, the positive circuit connection point C1 is set between the positive signal output terminal TXP and the third current bias transistor N5, and the positive main tap drive circuit 4112 is used to connect the negative main tap bias signal VNmain and the main tap negative differential data DNmain into the positive drive circuit.

[0074] The gate of the third current bias transistor N5 is connected to the third output terminal of the bias circuit unit to receive the negative main tap bias signal VNmain. The gate of the first switching transistor S1 is connected to the first output terminal of the main tap data selector to receive the main tap negative differential data DNmain.

[0075] Furthermore, the forward first back-tap driving circuit 4113 includes a third resistor R3 and a fourth current bias transistor P5, a third control pulse transistor P6, a fifth current bias transistor N7, and a fourth control pulse transistor N8 connected in series. The forward first back-tap driving circuit 4113 adopts an SST structure. The fourth current bias transistor P5 can be a PMOS current bias transistor, the third control pulse transistor P6 can be a PMOS control pulse transistor, the fifth current bias transistor N7 can be an NMOS current bias transistor, and the fourth control pulse transistor N8 can be an NMOS control pulse transistor. The source of the fourth current bias transistor P5 is connected to a third power supply (not shown in the figure), and the drain of the fourth current bias transistor P5 is connected to the source of the third control pulse transistor P6. The drain of the third control pulse transistor P6 is connected to the drain of the fifth current bias transistor N7, the source of the fifth current bias transistor N7 is connected to the drain of the fourth control pulse transistor N8, the third resistor R3 is connected in parallel between the source and drain of the fourth control pulse transistor N8, the source of the fourth control pulse transistor N8 is grounded, the positive circuit connection point C1 is located between the third control pulse transistor P6 and the fifth current bias transistor N7, and the positive first back tap drive circuit 4113 is used to connect the positive first back tap bias signal VPpst1, the negative first back tap bias signal VNpst1, the first negative first back tap equalization pulse ENNpst1, and the first positive first back tap equalization pulse ENPpst1 to the positive drive circuit.

[0076] Specifically, the gate of the fourth current bias transistor P5 is connected to the fourth output terminal of the bias circuit unit to receive the positive first back-tap bias signal VPpst1; the gate of the third control pulse transistor P6 is connected to the output terminal of the third OR gate to receive the first negative first back-tap equalization pulse ENNpst1; the gate of the fifth current bias transistor N7 is connected to the fifth output terminal of the bias circuit unit to receive the negative first back-tap bias signal VNpst1; and the gate of the fourth control pulse transistor N8 is connected to the output terminal of the third AND gate to receive the first positive first back-tap equalization pulse ENPpst1.

[0077] Furthermore, the positive second back-tap driving circuit 4114 includes a fourth resistor R4 and a sixth current bias transistor N9 and a second switch S2 connected in series. The positive circuit connection point C1 is located at the drain of the sixth current bias transistor N9. The source of the sixth current bias transistor N9 is connected to the drain of the second switch S2. The fourth resistor R4 is connected in parallel between the source and drain of the second switch S2. The source of the second switch S2 is grounded. The positive second back-tap driving circuit 4114 is used to input the negative second back-tap bias signal VNpst2 and the second back-tap positive differential data DPpst2 into the positive driving circuit. The gate of the sixth current bias transistor N9 is connected to the sixth output terminal of the bias circuit unit to receive the negative second back-tap bias signal VNpst2. The gate of the second switch S2 is connected to the first output terminal of the second back-tap data selector to receive the second back-tap positive differential data DPpst2.

[0078] Here, the PMOS and NMOS current bias transistors can adjust the pre-emphasis equalization intensity by regulating the current flowing through them. The PMOS and NMOS control pulse transistors can intermittently switch under the control of the first positive forward tap equalization pulse ENPpre, the first negative forward tap equalization pulse ENNpre, the first positive first back tap equalization pulse ENPpst1, and the first negative first back tap equalization pulse ENNpst1 included in the pre-emphasis equalization pulse. Furthermore, the first terminating resistor RT1 is used to achieve impedance matching and reduce signal reflection. The product of the output drive current of the hybrid equalization drive unit and the first terminating resistor RT1 determines the swing of the output signal. When equalization is not enabled, this output drive current is determined by the NMOS current bias transistor (main tap current) of the positive main tap drive circuit. After equalization is enabled, the pre-emphasis equalization of the front tap equalization pulse and the first back tap equalization pulse, as well as the deemphasis equalization of the second back tap data, generate the front tap current, the first back tap current, and the second back tap current under the control of the pre-emphasis equalization pulse and the deemphasis equalization, respectively, thereby increasing or decreasing the output drive current.

[0079] Furthermore, the negative differential data DNmain and the negative main tap bias signal VNmain from the main tap enter the forward tap driving circuit 4111 with a tailless CML structure, resulting in an unequalized output signal at the positive signal output terminal TXP. The first positive forward tap equalization pulse ENPpre, the first negative forward tap equalization pulse ENNpre, the positive forward tap bias signal VPpre, and the negative forward tap bias signal VNpre from the forward tap drive circuit 4111 with an SST structure are superimposed on the unequalized output signal at the positive signal output terminal TXP, thus achieving pre-emphasis equalization. The first positive first back tap equalization pulse ENPpst1, the first negative first back tap equalization pulse ENNpst1, the positive first back tap bias signal VPpst1, and the negative first back tap bias signal VNpst1 from the forward first back tap drive circuit 4113 with an SST structure are superimposed on the unequalized output signal at the positive signal output terminal TXP, thus achieving pre-emphasis equalization. The positive differential data DPpst2 and the negative bias signal VNpst2 from the second back tap enter the positive second back tap drive circuit 4114, which employs a tailless CML structure. At the positive signal output terminal TXP, they cancel each other out with the unequalized output signal, thus achieving de-emphasis equalization. The pre-equalization data is driven by the combined action of the positive front tap drive circuit 4111, the positive main tap drive circuit 4112, the positive first back tap drive circuit 4113, and the positive second back tap drive circuit, achieving hybrid equalization drive.

[0080] Furthermore, such as Figure 13 As shown, the negative driving circuit includes multiple negative sub-circuits, each of which is connected via a negative circuit connection point C2. Further, each negative sub-circuit includes a negative forward tap driving circuit 4121, a negative main tap driving circuit 4122, a negative first rear tap driving circuit 4123, and a negative second rear tap driving circuit 4124, wherein the negative main tap driving circuit is provided with a negative signal output terminal TXN. Further, a signal output circuit is connected to both the positive signal output terminal and the negative signal output terminal, used to combine the positive mixed output data and the negative mixed output data to generate the output signal.

[0081] Furthermore, the negative forward tap drive circuit 4121 includes a fifth resistor R5 and a seventh current bias transistor P10, a fifth control pulse transistor P11, an eighth current bias transistor N12, and a sixth control pulse transistor N13 connected in series. The source of the seventh current bias transistor P10 is connected to a fourth power supply (not shown in the figure), the drain of the seventh current bias transistor P10 is connected to the source of the fifth control pulse transistor P11, the drain of the fifth control pulse transistor P11 is connected to the drain of the eighth current bias transistor N12, and the source of the eighth current bias transistor N12 is connected to the source of the fifth control pulse transistor P11. The drain of the sixth control pulse transistor N13 is connected, and the fifth resistor R5 is connected in parallel between the source and drain of the sixth control pulse transistor N13. The source of the sixth control pulse transistor N13 is grounded. The negative circuit connection point C2 is located between the fifth control pulse transistor P11 and the eighth current bias transistor N12. The negative forward tap drive circuit is used to connect the positive forward tap bias signal VPpre, the negative forward tap bias signal VNpre, the second negative forward tap equalization pulse EPNpre, and the second negative forward tap equalization pulse EPNpre to the negative drive circuit.

[0082] Among them, the gate of the seventh current bias transistor P10 is connected to the seventh output terminal of the bias circuit unit and is used to receive the negative forward tap bias signal VNpre; the gate of the fifth control pulse transistor P11 is connected to the output terminal of the second OR gate and is used to receive the second negative forward tap equalization pulse EPNpre; the gate of the eighth current bias transistor N12 is connected to the eighth output terminal of the bias circuit unit and is used to receive the positive forward tap bias signal VPpre; and the gate of the sixth control pulse transistor N13 is connected to the output terminal of the second AND gate and is used to receive the second positive forward tap equalization pulse EPPpre.

[0083] Furthermore, the negative main tap drive circuit includes a sixth resistor R6, a second terminating resistor Rt2, and a ninth current bias transistor N14 and a third switch S3 connected in series. The first end of the second terminating resistor Rt2 is connected to a sixth power supply (not shown in the figure), and the second end of the second terminating resistor Rt2 is connected to the drain of the ninth current bias transistor N14. The source of the ninth current bias transistor N14 is connected to the drain of the third switch S3. The sixth resistor R6 is connected in parallel between the source and drain of the third switch S3. The source of the third switch S3 is grounded. Circuit connection point C2 is located between the ninth current bias transistor N14 and the second terminating resistor Rt2. The negative main tap driving circuit 4122 is used to connect the positive main tap bias signal VPmain and the main tap positive differential data DPmain into the negative driving circuit. The gate of the ninth current bias transistor N14 is connected to the ninth output terminal of the bias circuit unit to receive the positive main tap bias signal VPmain. The gate of the third switching transistor S3 is connected to the second output terminal of the main tap data selector to receive the main tap positive differential data DPmain.

[0084] Furthermore, the negative first back-tap drive circuit 4123 includes a seventh resistor R7 and a tenth current bias transistor P15, a seventh control pulse transistor P16, an eleventh current bias transistor N17, and an eighth control pulse transistor N18 connected in series. The source of the tenth current bias transistor P15 is connected to a sixth power supply (not shown in the figure), the drain of the tenth current bias transistor P15 is connected to the source of the seventh control pulse transistor P16, the drain of the seventh control pulse transistor P16 is connected to the drain of the eleventh current bias transistor N17, and the source of the eleventh current bias transistor N17 is connected to the eighth control pulse transistor. The drain of transistor N18 is connected, and the source and drain of the eighth control pulse transistor N18 are connected in parallel with the seventh resistor R7. The source of the eighth control pulse transistor N18 is grounded. The negative circuit connection point C2 is located between the seventh control pulse transistor P16 and the eleventh current bias transistor N17. The negative first back tap drive circuit 4123 is used to connect the second negative first back tap equalization pulse EPNpst1, the second positive first back tap equalization pulse EPPpst1, the positive first back tap bias signal VPpst1, and the negative first back tap bias signal VNpst1 to the negative drive circuit.

[0085] Specifically, the gate of the tenth current bias transistor P15 is connected to the tenth output terminal of the bias circuit unit to receive the negative first back tap bias signal VNpst1; the gate of the seventh control pulse transistor P16 is connected to the output terminal of the fourth OR gate to receive the second negative first back tap equalization pulse EPNpst1; the gate of the eleventh current bias transistor N17 is connected to the eleventh output terminal of the bias circuit unit to receive the positive first back tap bias signal VPpst1; and the gate of the eighth control pulse transistor N18 is connected to the output terminal of the fourth AND gate to receive the second negative first back tap equalization pulse EPNpst1.

[0086] Furthermore, the negative second tap drive circuit 4124 includes an eighth resistor R8 and a twelfth current bias transistor N19 and a fourth switch S4 connected in series. The negative circuit connection point C2 is located at the drain of the twelfth current bias transistor N19. The source of the twelfth current bias transistor N19 is connected to the drain of the fourth switch S4. The eighth resistor R8 is connected in parallel between the source and drain of the fourth switch S4. The source of the fourth switch S4 is grounded. The second-back-tap drive circuit 4124 is used to connect the negative second-back-tap bias signal VNpst2 and the second-back-tap negative differential data DNpst2 into the negative drive circuit; wherein, the gate of the twelfth current bias transistor N19 is connected to the twelfth output terminal of the bias circuit unit, and is used to receive the positive second-back-tap bias signal VPpst2, and the gate of the fourth switch S4 is connected to the second output terminal of the second-back-tap data selector, and is used to receive the second-back-tap negative differential data DNpst2.

[0087] Furthermore, the seventh current bias transistor P10 and the tenth current bias transistor P15 can be PMOS current bias transistors; the fifth control pulse transistor P11 and the seventh control pulse transistor P16 can be PMOS control pulse transistors; the eighth current bias transistor N12 and the eleventh current bias transistor N17 can be NMOS current bias transistors; the sixth control pulse transistor N13 and the eighth control pulse transistor N18 can be NMOS control pulse transistors; the ninth current bias transistor N14 and the twelfth current bias transistor N19 can be NMOS current bias transistors; and the third switch S3 and the fourth switch S4 can be NMOS switches. Furthermore, the negative forward tap drive circuit 4121 and the negative first backward tap drive circuit 4123 can be SST structures; and the negative main tap drive circuit 4122 and the negative second backward tap drive circuit 4124 can be tailless CML structures. Furthermore, the process of the negative drive circuit generating negative mixed output data is similar to the process of the positive drive circuit generating positive mixed output data, and will not be elaborated here.

[0088] The embodiments provided in this application can acquire various signals generated by the data selector module and the pulse generation module based on the positive drive circuit and the negative drive circuit, respectively. The main tap data is pre-emphasized based on the front tap equalization pulse and the first back tap equalization pulse with a symbol interval of fractional interval to the main tap data. The main tap data is de-emphasized based on the second back tap data with a symbol interval of integer interval to the main tap data. Finally, the signals are superimposed to obtain the output signal, which optimizes the swing of the output signal and significantly improves the signal quality of the output signal. Compared with the traditional integer interval de-emphasis equalization, the fractional interval pre-emphasis equalization can achieve an expandable compensation range and flexible equalization, reducing the power consumption of the driver while ensuring a high output swing of the signal.

[0089] Furthermore, Figure 14 (a) shows the circuit diagram of the traditional main tap driving circuit and the traditional first back tap driving circuit for weighted equalization with integer intervals. The main tap driving circuit and the first back tap driving circuit adopt a tailless CML structure. Figure 14 (b) An equivalent circuit diagram of the main tap driving circuit and the first back tap driving circuit of the fractional interval pre-emphasis equalization used in this invention is shown. The main tap driving circuit can refer to the positive main tap driving circuit and the negative main tap driving circuit in this application, and the first back tap driving circuit can refer to the positive first back tap driving circuit and the negative first back tap driving circuit in this application. Specifically, the main tap driving circuit adopts a tailless CML structure, and the first back tap driving circuit adopts an SST structure. The following analysis... Figure 14 (a) shows the conventional main tap drive circuit and the conventional integer interval first post-tap drive circuit for weighted equalization, and Figure 14 (b) illustrates the circuit operation principle of the main tap drive circuit and the first post-tap drive circuit of the fractional interval pre-emphasis equalization used in this invention, thereby obtaining... Figure 14 (a) and Figure 14 (b) provides a comparison of the output swing and power consumption of the two circuits shown.

[0090] Furthermore, Figure 15 (a) gives Figure 14 (a) shows the swing analysis diagram of the circuit output corresponding to the circuit. Figure 15 (b) gives Figure 14 (b) shows the swing analysis diagram of the corresponding circuit output. Specifically, Figure 14 (a) shows a traditional integer interval de-emphasis circuit that outputs a common-mode voltage. and single-ended output swing The calculation method is shown in formula (1):

[0091] (1)

[0092] in, This is the power supply voltage. and These represent the current of the main tap drive circuit and the current of the first rear tap drive circuit, respectively. Indicates the terminating resistance. Minimum output voltage. It can be obtained through formula (2):

[0093] (2)

[0094] To ensure Figure 14 Transistor M1 operates in the saturation region, and the aforementioned minimum output voltage... The conditions to be met are shown in formula (3):

[0095] (3)

[0096] in, and These represent the gate voltage and threshold voltage of transistor M1, respectively. Substituting equation (2) into equation (3) yields equation (4):

[0097] (4)

[0098] Conversely, for Figure 14 (b) Example fractional interval pre-emphasis circuit, output common-mode voltage V CM,PE and single-ended output swing The calculation methods are shown in formula (5):

[0099] (5)

[0100] Comparing formula (1) with formula (5), it can be found that the first back-tap drive circuit with integer interval de-emphasis, due to its tailless CML structure, directly causes a decrease in the output common-mode voltage. However, the first back-tap drive circuit with fractional interval pre-emphasis, due to its SST structure, has no effect on the output common-mode voltage because its pull-up current and pull-down current are statistically equal. Figure 14 (b) The single-ended output swing of the example circuit can be expressed as shown in formula (6):

[0101]

[0102] Combining formulas (5) and (6), we can obtain Figure 14 (b) Example of fractional interval pre-emphasis circuit ratio Figure 14(a) The integer-interval de-emphasis circuit in the example has a larger output swing, a conclusion that... Figure 15 The comparative analysis of the output swing amplitude shown in the diagram further illustrates this. The above conclusions can be further extended to... Figure 12 and forward drive circuit and Figure 13 In the negative drive circuit shown, by employing a pre-tap drive circuit with fractional interval pre-emphasis and a first back tap drive circuit, the hybrid equalization drive circuit can obtain a larger output swing.

[0103] Furthermore, such as Figure 16 A comparative analysis chart is shown, illustrating the normalized power consumption of the pre-emphasis equalization used in this embodiment versus the traditional de-emphasis equalization. Figure 14 (a) The example integer interval de-emphasis circuit uses a tailless CML structure for its main tap drive circuit and first post-tap drive circuit, which continuously draw power from the power supply. The current is drawn from the middle, where the power consumption is reduced. It can be represented by formula (7):

[0104]

[0105] in, The current of the main tap drive circuit. This is the current of the first post-tap drive circuit.

[0106] As can be seen from the above formula (1), when the output swing and power supply voltage of the circuit are fixed, the total current IMAIN+IPST1 is also fixed. Therefore, under different equalization intensities, the power consumption of the circuit is fixed when increasing the intensity of the circuit at integer intervals.

[0107] Conversely, for Figure 14 (b) Example fractional interval pre-emphasis circuit, which employs a tailless CML structure master tap drive circuit that continuously draws power from the power supply. The current is extracted from the middle. The first back-tap drive circuit, employing an SST structure, achieves intermittent switching under the control of the first negative first back-tap equalization pulse ENNpst1, the first positive first back-tap equalization pulse ENPpst1, the second negative first back-tap equalization pulse EPNpst1, and the second positive first back-tap equalization pulse EPPpst1, which serve as pre-emphasis equalization pulses. Mathematical statistical analysis shows that the edge density of the pseudo-random binary sequence is around 50%, meaning that the generated pre-emphasis equalization pulses occupy 50% of the number of symbols in the input sequence. Since the width of the pre-emphasis equalization pulse is... The UI can be freely adjusted, and the first post-tap drive circuit only draws current from the power supply when the pre-emphasis equalization pulse arrives, thus reducing pre-emphasis power consumption. It can be represented by formula (8):

[0108]

[0109] in, The power supply voltage for the front tap drive circuit and the first rear tap drive circuit can be further defined as a coefficient. Then the equilibrium intensity G can be expressed as shown in formula (9):

[0110]

[0111] By changing Meanwhile, the total current IMAIN+IPST1 is kept constant, and PPE is normalized relative to PDE. The normalized power consumption under different equilibrium intensities can be represented by formula (10):

[0112]

[0113] visible, Figure 16 Examples of different score coefficients obtained based on the test The normalized power consumption curve of the pre-emphasized equalization. It can be seen that when the equalization intensity and fractional coefficient... When set to 6 dB and 0.5 dB respectively, fractional interval pre-emphasis equalization can save 18% of power consumption. The above conclusions can be further extended to... Figure 12 and Figure 13 In the shown positive and negative drive circuits, the front tap drive circuit and the first rear tap drive circuit with fractional interval pre-emphasis have advantages in terms of power consumption. Furthermore, this low-power advantage becomes more pronounced as the equalization intensity increases, and can be further enhanced by appropriately reducing the fractional coefficient. It can also reduce power consumption.

[0114] Furthermore, in Figure 14 (b) Based on the example fractional interval pre-emphasis circuit, this invention further analyzes the frequency response characteristics of fractional interval equalization. Here, the first post-tap drive circuit is used as an example for illustration: Figure 14 (b) The transfer function expression of the example circuit is shown in formula (11):

[0115]

[0116] in, , For the fractional coefficients, the amplitude-frequency response function can be further obtained as shown in formula (12):

[0117]

[0118] when When ωT=π, the amplitude reaches its maximum value, thus obtaining the corresponding frequency compensation range as shown in formula (13):

[0119]

[0120] From formula (13), it can be seen that reducing the fractional coefficient It can effectively improve the frequency compensation range. Figure 17 Examples are shown with different fraction coefficients The frequency response curve of the first back tap drive circuit is shown below. The value is 1 / 4, which shows that as the fraction coefficient increases... As the frequency of the first tap driver circuit decreases, the frequency compensation range of the first tap continuously expands. The above conclusion can be further extended to... Figure 12 and Figure 13 In the driving circuit shown, both the front tap driving circuit and the first rear tap driving circuit, which employ fractional interval pre-emphasis, can be adjusted by changing the corresponding fractional coefficients. and This enables scalable frequency compensation range that extends beyond the Nyquist frequency compensation range, and flexible, adjustable equalization.

[0121] This invention provides a transmitter equalization drive circuit that aligns and synchronizes received transmit signals based on a serialization and retiming module to obtain multiple parallel data streams. Each parallel data stream is then sent to multiple data selector modules. A clock module containing an equalization pulse width control circuit sends a pre-set clock signal corresponding to each parallel data stream to the data selector modules, causing the data selector modules to generate front-tap data, main-tap data, first back-tap data, and second back-tap data. Here, the phase difference between the clock signals corresponding to adjacent parallel data streams can be between 0° and 90°, and the specific phase difference value can be predetermined. Multiple clock signals are input to the data selector modules. By adjusting the phase difference between the clock signals corresponding to the parallel data streams, the front-tap data, main-tap data, and second back-tap data generated from the parallel data can be... The data, the first back tap data, and the second back tap data have a specific phase difference. Further, the front tap data, main tap data, first back tap data, and second back tap data with the specific phase difference are input into the pulse generation module. Based on the phase difference between the front tap data and the main tap data, a front tap equalization pulse for pre-emphasing the main tap data is generated. Similarly, based on the phase difference between the main tap data and the first back tap data, a first back tap equalization pulse for pre-emphasing the main tap data is generated. Further, the front tap equalization pulse, main tap data, first back tap equalization pulse, and second back tap data are input into the hybrid equalization drive module, enabling the hybrid equalization drive module to obtain an output signal that optimizes the signal swing and the output eye diagram, thus solving the problem of low signal quality at the transmitter of the existing SerDes system.

[0122] Furthermore, such as Figure 18 As shown, this application provides a method for processing a signal to be transmitted, applied in the aforementioned transmitter equalization drive circuit, the method comprising:

[0123] 101. Acquire the signal to be transmitted, perform delay processing on the signal to be transmitted, and obtain the front tap data, main tap data, first back tap data and second back tap data corresponding to the signal to be transmitted, respectively.

[0124] The difference between the front tap data and the main tap data, and between the main tap data and the first back tap data, is a preset fractional symbol interval; the difference between the main tap data and the second back tap data is an integer symbol interval; furthermore, the fractional symbol interval is a non-integer symbol interval.

[0125] Specifically, the signal to be transmitted can be buffered and then delayed based on clock signals with different phase differences. For example, a 2UI delay unit can be used to delay the signal to be transmitted to obtain the main tap data. Then, a 2UI delay unit can be used to delay the main tap data to obtain the second post-tap data, ensuring that the main tap data and the second post-tap data are spaced by an integer symbol interval. The delay effect of the delay unit can be implemented based on the clock signal. Furthermore, it can be achieved through (2- The UI's delay unit performs delay processing on the signal to be transmitted, obtaining the pre-tap data, where... Not an integer, so that the UI is a fractional interval between the front tap data and the main tap data; further, by (2- The UI's delay unit performs delay processing on the main tap data to obtain the first subsequent tap data, where... The value is not an integer, and is a symbol interval of a fraction between the main tap data and the first post-tap data. Here, the front tap data, main tap data, first post-tap data, and second post-tap data can be obtained based on the data selector module.

[0126] 102. Based on the phase difference between the front tap data and the main tap data, a pre-emphasis pulse for the front tap data is generated, and based on the phase difference between the main tap data and the first rear tap data, a pre-emphasis pulse for the first rear tap data is generated, and a second rear tap deemphasis data is generated based on the second rear tap data.

[0127] Specifically, the front tap data and the main tap data can be input into the pulse generation module, and a pre-emphasis pulse for the front tap data can be generated based on the phase difference between the front tap data and the main tap data. Further, the main tap data and the first rear tap data can be input into the pulse generation module, and a pre-emphasis pulse for the first rear tap data can be generated based on the phase difference between the first rear tap data and the main tap data. Further, the second rear tap data can be input into the hybrid equalization driving module to generate second rear tap deemphasis data.

[0128] 103. The pre-emphasis pulse of the front tap data, the pre-emphasis pulse of the first rear tap data, the deemphasis data of the second rear tap, and the main tap data are superimposed to obtain the output signal.

[0129] Specifically, further, the second back tap data, the front tap data pre-emphasis pulse, the first back tap data pre-emphasis pulse, and the main tap data can be superimposed through a hybrid equalization drive module to obtain the output signal.

[0130] Furthermore, such as Figure 19 The schematic diagram shown is based on the signal processing method for the signal to be transmitted provided in this embodiment, which performs signal quality enhancement processing on the signal to be transmitted. It involves a main tap element 30, a front tap element 20 and a first rear tap element 40 that pre-emphasize using fractional intervals, and a second rear tap element 50 that de-emphasizes using integer intervals. Figure 19 (a) shows the pre-equalization data to be transmitted after passing through buffer 10 and (2- The UI receives the front-tap data after a delay of 60 seconds, such as... Figure 19 (a) The data to be transmitted before equalization, after passing through buffer 10 and the delay unit 70 of the first 2UI, becomes the main tap data, as shown. Figure 19 (a) The data to be transmitted before equalization, as shown, passes through buffer 10, the first 2UI delay unit 70, and (2+ The UI receives the first tap data after a delay of 80 seconds, such as... Figure 19 (a) The pre-equalization data to be transmitted passes through buffer 10, the first 2UI delay unit 70, and the second 2UI delay unit 90 to obtain the second post-tap data. The pre-tap data and the main tap data are then passed through the equalization pulse generation circuit to obtain the following... Figure 19 (b) shows the pre-emphasis pulse PRE of the pre-emphasis equalization pulse for the front tap. The main tap data and the first back tap data are obtained after passing through the equalization pulse generation circuit as shown. Figure 19 (b) shows the first back-tap data pre-emphasis pulse PST1 as the first back-tap pre-emphasis equalization pulse. The second back-tap data is obtained after passing through buffer 10 as follows: Figure 19(b) shows the second post-tap de-emphasis data PST2. Under the combined action of the pre-emphasis pulse PRE of the pre-tap data, the first post-tap data pre-emphasis pulse PST1, and the second post-tap de-emphasis data PST2, Figure 19 (b) The master tap data MAIN shown as the data before balancing is finally superimposed into... Figure 19 (b) shows the output data OUT as the driver output. Here, the front tap element 20 corresponds to the positive forward tap drive circuit and the negative forward tap drive circuit described above, the main tap element 30 corresponds to the positive main tap drive circuit and the negative main tap drive circuit described above, the first rear tap element 40 corresponds to the positive first rear tap drive circuit and the negative first rear tap drive circuit described above, and the second rear tap element 50 corresponds to the positive second rear tap drive circuit and the negative second rear tap drive circuit described above.

[0131] from Figure 19 The waveform diagram in (b) shows that the width of the pre-emphasis equalization pulse in the pre-emphasis pulse PRE of the front-tap data is UI, among which The delay between the front tap data and the main tap data is determined, and the range is 0~1. As shown in 19(b), the width of the pre-emphasis equalization pulse in the first back tap data pre-emphasis pulse PST1 is... UI, among which The pre-emphasis equalization pulse width is determined by the delay between the main tap data and the first post-tap data, and varies from 0 to 1. By adjusting the delay between the front tap element 20 or the first post-tap element 40 and the main tap element 30, the pre-emphasis equalization pulse width can be flexibly adjusted. In this embodiment, the positive forward tap drive circuit, negative forward tap drive circuit, positive first post-tap drive circuit, and negative first post-tap drive circuit of the hybrid equalization drive module use pre-emphasis equalization to enhance the high-frequency components of the signal, while the positive second post-tap drive circuit and negative second post-tap drive circuit use de-emphasis equalization to attenuate the low-frequency components of the signal. The combination of pre-emphasis and de-emphasis equalization methods can compensate for the low-frequency and high-frequency components of the signal from multiple aspects. At the same time, pre-emphasis equalization can compensate for the reduction in signal output swing caused by de-emphasis equalization. The pre-emphasis equalization used in the positive forward tap drive circuit, the negative forward tap drive circuit, the positive first back tap drive circuit, and the negative first back tap drive circuit is based on fractional intervals. By flexibly adjusting the width of the pre-emphasis equalization pulse (width range is 0-1UI), an expandable compensation range can be achieved, that is, a compensation range beyond the Nyquist frequency, and a flexibly adjustable equalization.

[0132] The signal processing method provided in this embodiment can be based on a combination of fractional interval pre-emphasis equalization and integer interval de-emphasis equalization. This method can achieve compensation beyond the Nyquist frequency range and comprehensive compensation for low-frequency and high-frequency components of the transmitted signal. At the same time, pre-emphasis equalization can effectively compensate for the reduction in output swing caused by de-emphasis equalization. Furthermore, pre-emphasis equalization controlled by adjustable-width pulses can further reduce the power consumption of the driver by operating intermittently.

[0133] Through the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware platform, or it can be implemented by hardware. By applying the technical solution of this application, firstly, the signal to be transmitted is acquired, and the signal to be transmitted is delayed to obtain front tap data, main tap data, first back tap data, and second back tap data corresponding to the signal to be transmitted; wherein, the phase difference between the front tap data and the main tap data, and between the main tap data and the first back tap data, is a preset fraction of symbol interval, and the phase difference between the main tap data and the second back tap data is an integer bit of symbol interval; then, based on the phase difference between the front tap data and the main tap data, a front tap data pre-emphasis pulse is generated, and based on the phase difference between the main tap data and the first back tap data, a first back tap data pre-emphasis pulse is generated, and based on the second back tap data, a second back tap deemphasis data is generated; finally, the front tap data pre-emphasis pulse, the first back tap data pre-emphasis pulse, the second back tap deemphasis data, and the main tap data are superimposed to obtain the output signal. Compared with existing technologies, it can improve the signal quality of the output signal.

[0134] Those skilled in the art will understand that the accompanying drawings are merely schematic diagrams of a preferred embodiment, and the modules or processes shown in the drawings are not necessarily essential for implementing this application. Those skilled in the art will understand that the modules in the apparatus of the embodiment can be distributed within the apparatus of the embodiment as described, or can be modified to be located in one or more apparatuses different from this embodiment. The modules of the above-described embodiment can be combined into one module, or further divided into multiple sub-modules.

[0135] The serial numbers in this application are for descriptive purposes only and do not represent the superiority or inferiority of any particular implementation scenario. The above disclosures are merely a few specific implementation scenarios of this application; however, this application is not limited thereto, and any variations conceived by those skilled in the art should fall within the protection scope of this application.

Claims

1. A transmitter equalization drive circuit, applied to a SerDes transmitter, characterized in that, The circuit includes: A serialization and retiming module is used to receive the signal to be transmitted and generate multiple parallel data corresponding to the signal to be transmitted. A data selector module, which is connected to the serialization and retiming module, is used to receive a clock signal corresponding to each of the parallel data streams, and generate front tap data, main tap data, first back tap data, and second back tap data based on the multiple parallel data streams and the clock signal corresponding to each of the parallel data streams. The code interval between the front tap data and the main tap data, and between the first back tap data and the main tap data, is a preset fraction of a code interval. A pulse generation module, connected to the data selector module, is used to receive the front tap data, the main tap data, and the first back tap data, and generate a front tap equalization pulse and a first back tap equalization pulse. A hybrid equalization driving module, which is connected to the pulse generation module and the data selector module, is used to receive the front tap equalization pulse, the main tap data, the first back tap equalization pulse and the second back tap data, and generate the output signal of the signal to be transmitted.

2. The transmitter equalization drive circuit according to claim 1, characterized in that, The data selector module includes: Multiple data selectors, each of which is connected to the serialization and retiming module, and each of which is used to receive one channel of parallel data and the clock signal corresponding to the parallel data; The plurality of data selectors include a front tap data selector, a main tap data selector, a first back tap data selector, and a second back tap data selector, and the parallel data includes first parallel data, second parallel data, third parallel data, and fourth parallel data. The front-tap data selector is also connected to the pulse generation module, and is used to receive the first parallel data and the first clock signal corresponding to the first parallel data, generate the front-tap data, and send the front-tap data to the pulse generation module. The main tap data selector is also connected to the hybrid equalization drive module and the pulse generation module, and is used to receive the second parallel data and the second clock signal corresponding to the second parallel data, generate the main tap data, and send the main tap data to the hybrid equalization drive module. The first post-tap data selector is also connected to the pulse generation module, and is used to receive the third parallel data and the third clock signal corresponding to the third parallel data, generate the first post-tap data, and send the first post-tap data to the pulse generation module. The second back-tap data selector is also connected to the hybrid equalization driver module, and is used to receive the fourth parallel data and the fourth clock signal corresponding to the fourth parallel data, generate the second back-tap data, and send the second back-tap data to the hybrid equalization driver module.

3. The transmitter equalization drive circuit according to claim 2, characterized in that, The transmitter equalization drive circuit also includes: A clock module, connected to the data selector, is used to receive a raw clock signal, generate a clock signal corresponding to each of the parallel data streams in response to a received clock adjustment command, and send the clock signals to the data selectors corresponding to the clock signals respectively.

4. The transmitter equalization drive circuit according to claim 2, characterized in that, The pulse generation module includes: A front-tap equalization pulse generation unit is connected to the front-tap data selector and the main-tap data selector respectively. It is used to receive the front-tap data and the main-tap data, generate the front-tap equalization pulse, and send the front-tap equalization pulse to the hybrid equalization drive module. The first back-tap equalization pulse generation unit is connected to the main tap data selector and the first back-tap data selector respectively. It is used to receive the main tap data and the first back-tap data, generate the first back-tap equalization pulse, and send the first back-tap equalization pulse to the hybrid equalization driving module.

5. The transmitter equalization drive circuit according to claim 3, characterized in that, The front tap data includes front tap positive differential data and front tap negative differential data, and the main tap data includes main tap positive differential data and main tap negative differential data; The forward tap equalization pulse includes: a first positive forward tap equalization pulse, a first negative forward tap equalization pulse, a second positive forward tap equalization pulse, and a second negative forward tap equalization pulse. The front-tap equalization pulse generation unit includes a first AND gate and a first OR gate. The first input terminals of the first AND gate and the first OR gate are respectively connected to the first output terminal of the front-tap data selector for receiving the front-tap positive differential data. The second input terminals of the first AND gate and the first OR gate are respectively connected to the first output terminal of the main-tap data selector for receiving the main-tap negative differential data. The output terminal of the first AND gate is connected to the hybrid equalization driving module for sending the first positive front-tap equalization pulse to the hybrid equalization driving module. The output terminal of the first OR gate is connected to the hybrid equalization driving module for sending the first negative front-tap equalization pulse to the hybrid equalization driving module. The front-tap equalization pulse generation unit further includes a second AND gate and a second OR gate. The first input terminals of the second AND gate and the second OR gate are respectively connected to the second output terminal of the front-tap data selector for receiving the front-tap negative differential data. The second input terminals of the second AND gate and the second OR gate are respectively connected to the second output terminal of the main-tap data selector for receiving the main-tap positive differential data. The output terminal of the second AND gate is connected to the hybrid equalization driving module for sending the second positive front-tap equalization pulse to the hybrid equalization driving module. The output terminal of the second OR gate is connected to the hybrid equalization driving module for sending the second negative front-tap equalization pulse to the hybrid equalization driving module.

6. The transmitter equalization drive circuit according to claim 5, characterized in that, The first post-tap data includes positive difference data and negative difference data of the first post-tap. The second post-tap data includes the positive difference data and the negative difference data of the second post-tap. The first back-tap equalization pulse includes: a first positive first back-tap equalization pulse (ENPpst1), a first negative first back-tap equalization pulse, a second positive first back-tap equalization pulse, and a second negative first back-tap equalization pulse; The first back-tap equalization pulse generation unit includes a third AND gate and a third OR gate. The first input terminals of the third AND gate and the third OR gate are respectively connected to the first output terminal of the first back-tap data selector to receive the first back-tap positive differential data. The second input terminals of the third AND gate and the third OR gate are respectively connected to the first output terminal of the main tap data selector to receive the main tap negative differential data. The output terminal of the third AND gate is connected to the hybrid equalization driving module to send the first positive first back-tap equalization pulse to the hybrid equalization driving module. The output terminal of the third OR gate is connected to the hybrid equalization driving module to send the first negative first back-tap equalization pulse to the hybrid equalization driving module. The first back-tap equalization pulse generation unit further includes a fourth AND gate and a fourth OR gate. The first input terminals of the fourth AND gate and the fourth OR gate are respectively connected to the second output terminals of the first back-tap data selector to receive the first back-tap negative differential data. The second input terminals of the fourth AND gate and the fourth OR gate are respectively connected to the second output terminals of the main tap data selector to receive the main tap positive differential data. The output terminal of the fourth AND gate is connected to the hybrid equalization driving module to send the second positive first back-tap equalization pulse to the hybrid equalization driving module. The output terminal of the fourth OR gate is connected to the hybrid equalization driving module to send the second negative first back-tap equalization pulse to the hybrid equalization driving module.

7. The transmitter equalization drive circuit according to claim 6, characterized in that, The hybrid equalization driving module includes: A hybrid equalization driving unit, which is connected to the pulse generation module and the data selector module, is used to receive the front tap equalization pulse, the main tap data, the first back tap equalization pulse and the second back tap data, and generate the output signal of the signal to be transmitted. A bias circuit unit, connected to the hybrid equalization drive unit, is used to generate and send a bias signal to the hybrid equalization drive unit in response to a received signal amplitude command, for controlling the amplitude of the output signal.

8. The transmitter equalization drive circuit according to claim 7, characterized in that, The bias signals include a positive forward tap bias signal, a negative forward tap bias signal, a positive main tap bias signal, a negative main tap bias signal, a positive first back tap bias signal, a negative first back tap bias signal, a positive second back tap bias signal, and a negative second back tap bias signal. The hybrid equalization drive unit includes: A forward drive circuit includes multiple forward sub-circuits, each of which is connected to the others via a forward circuit connection point. Each forward sub-circuit includes a forward front tap drive circuit, a forward main tap drive circuit, a forward first rear tap drive circuit, and a forward second rear tap drive circuit. The forward main tap drive circuit is provided with a forward signal output terminal. The forward driving circuit is used to receive the first positive forward tap equalization pulse, the main tap negative differential data, the first positive first back tap equalization pulse, the second back tap positive differential data, the positive forward tap bias signal, the negative forward tap bias signal, the negative main tap bias signal, the positive first back tap bias signal, the negative first back tap bias signal, the negative second back tap bias signal, the first negative first back tap equalization pulse, and the first negative forward tap equalization pulse, and generate positive mixed output data; The hybrid equalization drive unit also includes: A negative driving circuit includes multiple negative sub-circuits, each of which is connected to the others via a negative circuit connection point. Each negative sub-circuit includes a negative front tap driving circuit, a negative main tap driving circuit, a negative first rear tap driving circuit, and a negative second rear tap driving circuit. The negative main tap driving circuit is provided with a negative signal output terminal. The negative driving circuit is used to receive the second positive forward tap equalization pulse, the main tap positive differential data, the second positive first back tap equalization pulse, the second back tap negative differential data, the positive forward tap bias signal, the negative forward tap bias signal, the positive main tap bias signal, the positive first back tap bias signal, the negative first back tap bias signal, the positive second back tap bias signal, the second negative first back tap equalization pulse, and the second negative forward tap equalization pulse, and generate negative mixed output data; The hybrid equalization drive unit also includes: A signal output circuit, connected to the positive signal output terminal and the negative signal output terminal, is used to generate the output signal based on the positive mixed output data and the negative mixed output data.

9. The transmitter equalization drive circuit according to claim 8, characterized in that, The forward tap driving circuit includes a first resistor and a first current bias transistor, a first control pulse transistor, a second current bias transistor, and a second control pulse transistor connected in series. The source of the first current bias transistor is connected to a first power supply, the drain of the first current bias transistor is connected to the source of the first control pulse transistor, the drain of the first control pulse transistor is connected to the drain of the second current bias transistor, the source of the second current bias transistor is connected to the drain of the second control pulse transistor, the first resistor is connected in parallel between the source and drain of the second control pulse transistor, and the source of the second control pulse transistor is grounded. The forward circuit connection point is located between the first control pulse transistor and the second current bias transistor. The forward tap driving circuit is used to input the forward tap bias signal, the negative forward tap bias signal, the first negative forward tap equalization pulse, and the first forward tap equalization pulse into the forward driving circuit. The positive main tap driving circuit includes a second resistor, a first terminating resistor, and a third current bias transistor and a first switching transistor connected in series. The first end of the first terminating resistor is connected to a second power supply, and the second end of the first terminating resistor is connected to the drain of the third current bias transistor. The source of the third current bias transistor is connected to the drain of the first switching transistor. The second resistor is connected in parallel between the source and drain of the first switching transistor. The source of the first switching transistor is grounded. The positive signal output terminal is located at the second end of the first terminating resistor. The positive circuit connection point is located between the positive signal output terminal and the third current bias transistor. The positive main tap driving circuit is used to input the negative main tap bias signal and the negative differential data of the main tap into the positive driving circuit. The positive first back-tap driving circuit includes a third resistor and a fourth current bias transistor, a third control pulse transistor, a fifth current bias transistor, and a fourth control pulse transistor connected in series. The source of the fourth current bias transistor is connected to a third power supply. The drain of the fourth current bias transistor is connected to the source of the third control pulse transistor. The drain of the third control pulse transistor is connected to the drain of the fifth current bias transistor. The source of the fifth current bias transistor is connected to the drain of the fourth control pulse transistor. The third resistor is connected in parallel between the source and drain of the fourth control pulse transistor. The source of the fourth control pulse transistor is grounded. The positive circuit connection point is located between the third control pulse transistor and the fifth current bias transistor. The positive first back-tap driving circuit is used to input the positive first back-tap bias signal, the negative first back-tap bias signal, the first negative first back-tap equalization pulse, and the first positive first back-tap equalization pulse into the positive driving circuit. The positive second back tap driving circuit includes a fourth resistor and a sixth current bias transistor and a second switching transistor connected in series. The positive circuit connection point is located at the drain of the sixth current bias transistor. The source of the sixth current bias transistor is connected to the drain of the second switching transistor. The fourth resistor is connected in parallel between the source and drain of the second switching transistor. The source of the second switching transistor is grounded. The positive second back tap driving circuit is used to input the negative second back tap bias signal and the positive differential data of the second back tap into the positive driving circuit.

10. The transmitter equalization drive circuit according to claim 8, characterized in that, The negative forward tap driving circuit includes a fifth resistor and a seventh current bias transistor, a fifth control pulse transistor, an eighth current bias transistor, and a sixth control pulse transistor connected in series. The source of the seventh current bias transistor is connected to a fourth power supply. The drain of the seventh current bias transistor is connected to the source of the fifth control pulse transistor. The drain of the fifth control pulse transistor is connected to the drain of the eighth current bias transistor. The source of the eighth current bias transistor is connected to the drain of the sixth control pulse transistor. The fifth resistor is connected in parallel between the source and drain of the sixth control pulse transistor. The source of the sixth control pulse transistor is grounded. The negative circuit connection point is located between the fifth control pulse transistor and the eighth current bias transistor. The negative forward tap driving circuit is used to input the positive forward tap bias signal, the negative forward tap bias signal, the second negative forward tap equalization pulse, and the second negative forward tap equalization pulse into the negative driving circuit. The negative main tap driving circuit includes a sixth resistor, a second terminating resistor, and a ninth current bias transistor and a third switching transistor connected in series. The first end of the second terminating resistor is connected to the sixth power supply, and the second end of the second terminating resistor is connected to the drain of the ninth current bias transistor. The source of the ninth current bias transistor is connected to the drain of the third switching transistor. The sixth resistor is connected in parallel between the source and drain of the third switching transistor. The source of the third switching transistor is grounded. The negative circuit connection point is located between the ninth current bias transistor and the second terminating resistor. The negative main tap driving circuit is used to input the positive main tap bias signal and the positive differential data of the main tap into the negative driving circuit. The negative first back-tap driving circuit includes a seventh resistor and a tenth current bias transistor, a seventh control pulse transistor, an eleventh current bias transistor, and an eighth control pulse transistor connected in series. The source of the tenth current bias transistor is connected to a sixth power supply. The drain of the tenth current bias transistor is connected to the source of the seventh control pulse transistor. The drain of the seventh control pulse transistor is connected to the drain of the eleventh current bias transistor. The source of the eleventh current bias transistor is connected to the drain of the eighth control pulse transistor. The seventh resistor is connected in parallel between the source and drain of the eighth control pulse transistor. The source of the eighth control pulse transistor is grounded. The negative circuit connection point is located between the seventh control pulse transistor and the eleventh current bias transistor. The negative first back-tap driving circuit is used to input the second negative first back-tap equalization pulse, the second positive first back-tap equalization pulse, the positive first back-tap bias signal, and the negative first back-tap bias signal into the negative driving circuit. The negative second back-tap driving circuit includes an eighth resistor and a twelfth current bias transistor and a fourth switch connected in series. The negative circuit connection point is located at the drain of the twelfth current bias transistor. The source of the twelfth current bias transistor is connected to the drain of the fourth switch. The eighth resistor is connected in parallel between the source and drain of the fourth switch. The source of the fourth switch is grounded. The negative second back-tap driving circuit is used to input the positive second back-tap bias signal and the negative differential data of the second back-tap into the negative driving circuit.

11. A method for processing a signal to be transmitted, characterized in that, The method is applied to the transmitter equalization drive circuit according to any one of claims 1 to 10, and the method includes: The signal to be transmitted is acquired, and the signal to be transmitted is delayed to obtain the front tap data, main tap data, first back tap data and second back tap data corresponding to the signal to be transmitted, respectively. Wherein, the difference between the front tap data and the main tap data and between the main tap data and the first back tap data is a preset fraction of symbol interval, and the difference between the main tap data and the second back tap data is an integer of symbol interval. Based on the phase difference between the front tap data and the main tap data, a pre-emphasis pulse for the front tap data is generated; based on the phase difference between the main tap data and the first rear tap data, a pre-emphasis pulse for the first rear tap data is generated; and based on the second rear tap data, a second rear tap deemphasis data is generated. The output signal is obtained by superimposing the pre-emphasis pulse of the front tap data, the pre-emphasis pulse of the first rear tap data, the deemphasis data of the second rear tap, and the main tap data.

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