Satellite terminal automatic test system and application method

Abstract

The embodiment of the invention provides a satellite terminal automatic test system and an application method, and the system comprises a system main body, a first synchronous transmission board card, and a second synchronous transmission board card. Wherein the system main body is used for sending a test data sending instruction carrying original data to the first synchronous transmission board card; the first synchronous transmission board card is used for extracting the original data from the test data sending instruction and sending the original data to an accompanying test satellite terminal; the second synchronous transmission board card is used for receiving loopback data from a satellite terminal to be tested and sending the loopback data to the system main body; and the system main body is also used for comparing the loopback data with the original data and calculating an automatic test result of synchronous data transmission, so that the automatic test of the synchronous data service of the satellite terminal is realized, and the problem of low test efficiency caused by adopting a manual test scheme for testing in the prior art is avoided.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of satellite communication testing technology, and in particular to an automated testing system and application method for synchronous data services of satellite terminals. Background Art

[0002] At present, there are some automated testing solutions for satellite terminal RF and protocol performance indicators on the market, but the performance indicators of synchronous data services are still tested manually. The manual testing solution uses a bit error meter to send and receive random bit streams for bit error comparison, and the tester then records the test results, which has high labor costs and low testing efficiency. Summary of the invention

[0003] The main purpose of the embodiments of the present application is to propose a satellite terminal automatic testing system and application method, aiming to achieve performance indicators for synchronous data services and to conduct testing in an automated manner.

[0004] In a first aspect, a satellite terminal automated test system is provided, comprising: a system body, a first synchronous transmission board and a second synchronous transmission board; wherein:

[0005] The system body is used to send a test data sending instruction carrying original data to the first synchronous transmission board;

[0006] The first synchronous transmission board is used to extract the original data from the test data sending instruction and send the original data to the accompanying test satellite terminal;

[0007] The second synchronous transmission board is used to receive loopback data from the satellite terminal to be tested, and send the loopback data to the system body, wherein the loopback data is the data obtained by loopback transmission of the original data through the satellite terminal to be tested, the satellite communication system radio frequency, and the satellite terminal to be tested;

[0008] The system body is also used to compare the loopback data with the original data and calculate the synchronous data transmission automatic test result.

[0009] Through the system provided in the first aspect, automated testing of the synchronous data service of the satellite terminal can be achieved, thus avoiding the problem of low testing efficiency caused by the manual testing scheme still used in the prior art to test the performance indicators of the synchronous data service.

[0010] In a possible implementation, the system body includes: a data management module, a test execution module and a front-end display module; wherein,

[0011] The data management module is used to process system data and provide a unified encapsulated data management interface to other modules. The data management module can integrate data from different sources and formats to achieve centralized storage and management of data, thereby facilitating data sharing and access, improving data utilization and processing efficiency, reducing manual intervention, reducing error rates, and improving data processing speed and accuracy;

[0012] The test execution module is used to complete the automatic test of synchronous data transmission. It can configure the synchronous transmission rate of the first synchronous transmission board and the second synchronous transmission board according to the test parameters, read the system data sample, send the system data sample to the first synchronous transmission board, and receive the test data looped back by the external satellite communication system from the second synchronous transmission board, compare it with the original data, and calculate the automatic test result of synchronous transmission. The test execution module can realize the automatic test of the synchronous data service of the satellite terminal, improve the efficiency and accuracy of the test process, reduce the dependence on manual operation and the risk of human error, and avoid the problem of low test efficiency in the prior art that the manual test solution is still used to test the performance indicators of the synchronous data service;

[0013] The front-end display module is used to provide users with a visual front-end display interface to manage the system data, monitor and control the test process, and view the test process, test log and test results. The front-end display module can display key information in the system to users in an intuitive manner, helping users to quickly obtain required information and improve work efficiency.

[0014] In a possible implementation, the system data includes operation data and test data;

[0015] The operation data includes the local IP address and port, the synchronous transmission board IP address and port, and the test data includes the synchronous transmission rate, the test data sample source, the number of test packets, the number of sent bits, the number of received bits, the number of bit errors and the bit error rate.

[0016] In a possible implementation, the composition structure of the first synchronous transmission board and the second synchronous transmission board includes:

[0017] Instruction interaction module, shared memory module and synchronous transmission module; wherein,

[0018] The instruction interaction module is used to interact with the system body in test control instructions and test data receiving and sending instructions, and can complete efficient data processing and control through simplified instructions when processing complex computing tasks;

[0019] The shared memory module is used for data caching and cyclic reading and writing by other modules. The shared memory module can transmit data at both the rising and falling edges of each clock cycle, thereby achieving double the data transmission rate, improving the bandwidth of the memory, and enabling the processor to access and process data faster;

[0020] The synchronous transmission module is used to send test data to the outside in a synchronous manner, and also supports receiving data sent from the outside in a synchronous manner from the synchronous serial port;

[0021] The data block pointed to by the synchronous transmission module pointer is syncCnt, the data block pointed to by the instruction interaction module pointer is orderCnt, the length of a single data block is BlockLength, and the maximum count of data blocks is Max.

[0022] In one possible implementation, the system body communicates with the first synchronous transmission board and the second synchronous transmission board via a LAN connection line, and the first synchronous transmission board and the second synchronous transmission board both communicate with the satellite terminal to be tested and the accompanying satellite terminal via a synchronous serial port line.

[0023] In a second aspect, an application method of a satellite terminal automated test system is provided, which is applied to a system main body, a first synchronous transmission board and a second synchronous transmission board, and the method comprises the following steps:

[0024] The system body is connected to the first synchronous transmission board and the second synchronous transmission board;

[0025] The first synchronous transmission board is connected to the companion satellite terminal, the second synchronous transmission board is connected to the satellite terminal to be tested, and all devices are powered on;

[0026] The system main body configures test parameters and starts automated testing;

[0027] The system main body sends a test data sending instruction carrying original data to the first synchronous transmission board;

[0028] The first synchronous transmission board extracts the original data from the test data sending instruction, and sends the original data to the accompanying test satellite terminal;

[0029] The second synchronous transmission board receives loopback data from the satellite terminal to be tested;

[0030] The second synchronous transmission board converts the loopback data into a test data receiving instruction form;

[0031] The second synchronous transmission board sends the test data receiving instruction carrying the loopback data to the system main body, where the loopback data is the data obtained by loopback transmission of the original data through the companion satellite terminal, the satellite communication system radio frequency, and the satellite terminal to be tested;

[0032] The system body is also used to compare the loopback data with the original data and calculate the synchronous data transmission automatic test result.

[0033] Through the method provided in the second aspect, automated testing of the synchronous data service of the satellite terminal can be achieved, thus avoiding the problem of low testing efficiency caused by the manual testing scheme still used in the prior art to test the performance indicators of the synchronous data service.

[0034] In a possible implementation, the first synchronous transmission board extracts the original data from the test data sending instruction and applies it to the instruction interaction module, the shared memory module and the synchronous transmission module;

[0035] The data block count syncCnt pointed to by the synchronous transmission module pointer is set to zero;

[0036] Set the data block orderCnt pointed to by the instruction interaction module pointer to syncCnt+10;

[0037] The first synchronous transmission board waits to receive a synchronous rate configuration instruction, and the instruction interaction module parses and sets the synchronous transmission rate, tests the frame length and the synchronous transmission interval;

[0038] The first synchronous transmission board waits to receive a synchronous transmission side configuration instruction, and the working mode is switched to a data transmission mode;

[0039] The synchronous transmission module reads the test data from the syncCnt position of the shared memory module, and sends the test data outward through the synchronous serial port. When the length of the test data reaches the length of a single data block BlockLength, the syncCnt of the shared memory module moves backward 1 bit in a loop, and this step is repeated;

[0040] The instruction interaction module monitors the test data sending instruction, parses the test data and writes it into the buffer. If the data length of the buffer exceeds 10*FrameLength, and the first synchronous transmission board meets the following conditions:

[0041] (orderCnt + 10 * FrameLength / BlockLength) mod Max < syncCnt, then read the test data with a length of 10 * FrameLength from the buffer, circularly write the test data into the shared memory module from the orderCnt position, the orderCnt circularly moves backward by 10 * FrameLength / BlockLength bits, wait for a time of SendInterval length, and repeat this step.

[0042] In a possible implementation manner, the second synchronous transmission board converts the loopback data into a test data reception instruction form and applies it to the instruction interaction module, the shared memory module, and the synchronous transmission module;

[0043] Set the data block count syncCnt pointed to by the synchronous transmission module pointer to zero;

[0044] Set the data block orderCnt pointed to by the instruction interaction module pointer to zero;

[0045] The second synchronous transmission board waits to receive a synchronous rate configuration instruction, and the instruction interaction module parses and sets the synchronous transmission rate, the test frame length, and the synchronous send interval;

[0046] The second synchronous transmission board waits for a synchronous receiving side configuration instruction, and the working mode is switched to the data receiving mode;

[0047] The synchronous transmission module obtains synchronous data from the synchronous serial port, writes the synchronous data into the shared memory module from the syncCnt position, when the length of the synchronous data reaches the length of a single data block BlockLength, the syncCnt circularly moves backward by 1 bit, and repeat this step;

[0048] If the second synchronous transmission board meets the following conditions:

[0049] (orderCnt + FrameLength / BlockLength) mod Max < syncCnt, then the instruction interaction module reads the synchronous data with a length of FrameLength from the orderCnt position of the shared memory module, encapsulates it as the test data reception instruction, and sends it to the system main body, the orderCnt of the shared memory module circularly moves backward by FrameLength / BlockLength bits, and repeat this step.

[0050] In a third aspect, an electronic device is provided, including:

[0051] One or more processors;

[0052] A memory having one or more programs stored thereon, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the application method of the satellite terminal automatic testing system as described in any possible implementation method in the second aspect.

[0053] In a fourth aspect, a computer-readable storage medium is provided, on which a computer program is stored, and when the program is executed by a processor, an application method of a satellite terminal automatic test system as described in any possible implementation method in the second aspect is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] The accompanying drawings are used to provide a further understanding of the technical solution of the present invention and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present invention and do not constitute a limitation on the technical solution of the present invention.

[0055] Figure 1 A diagram of the structure of a satellite terminal automated test system provided in an embodiment of the present application;

[0056] Figure 2 A composition architecture diagram of a synchronous transmission board of a satellite terminal automated test system provided in an embodiment of the present application;

[0057] Figure 3 A schematic diagram of a flow chart of an application method of a satellite terminal automatic test system provided in an embodiment of the present application;

[0058] Figure 4 A schematic diagram of a flow chart of a first synchronous transmission board converting test data from an instruction form to a synchronous form in an application method of a satellite terminal automatic test system provided in an embodiment of the present application;

[0059] Figure 5 A schematic diagram of a flow chart of a second synchronous transmission board converting test data from a synchronous form to an instruction form in an application method of a satellite terminal automatic test system provided in an embodiment of the present application;

[0060] Figure 6 This is a structural block diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0061] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0062] It should be noted that, although the functional modules are divided in the device schematic diagram and the logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart. The terms "first", "second", etc. in the specification, claims and the above drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0063] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0064] In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other. The embodiments of the present invention are further described below in conjunction with the accompanying drawings.

[0065] Please refer to Figure 1 , Figure 1 A diagram of the composition architecture of a satellite terminal automated testing system provided in an embodiment of the present invention.

[0066] First, as Figure 1 As shown, a satellite terminal automatic test system is provided, comprising: a system main body, a first synchronous transmission board card and a second synchronous transmission board card;

[0067] The system body is used to send a test data sending instruction carrying original data to the first synchronous transmission board.

[0068] It should be noted that the first synchronous transmission board is used to extract the original data from the test data sending instruction and send the original data to the accompanying test satellite terminal.

[0069] The second synchronous transmission board is used to receive loopback data from the satellite terminal to be tested and send the loopback data to the system body. The loopback data is the data obtained by loopback transmission of the original data through the companion satellite terminal, the satellite communication system radio frequency, and the satellite terminal to be tested.

[0070] The system body is also used to compare the loopback data with the original data and calculate the synchronous data transmission automatic test result.

[0071] Through the system provided in the first aspect, automated testing of satellite terminal synchronous data services can be implemented, test content can be customized, and there is no need to rely on a bit error meter, thereby improving test efficiency and avoiding the manual testing scheme used in the prior art to test the performance indicators of synchronous data services, where a bit error meter is used to send and receive random bit streams for bit error comparison, and the test results are recorded by the tester, resulting in high labor costs, low test efficiency, and an inability to customize test content.

[0072] like Figure 1 As shown, in a possible implementation, the system body includes: a data management module, a test execution module and a front-end display module;

[0073] The data management module is used to process system data and provide a unified encapsulated data management interface to other modules. The data management module can integrate data from different sources and formats, realize centralized storage and management of data, thereby facilitating data sharing and access, improving data utilization and processing efficiency, and through the data management module, automatic data processing, such as data cleaning, conversion, loading, etc., can be realized, reducing manual intervention, reducing error rates, and improving data processing speed and accuracy.

[0074] The test execution module is used to complete the automatic test of synchronous data transmission. It can configure the synchronous transmission rate of the first synchronous transmission board and the second synchronous transmission board according to the test parameters, read the system data sample, send the system data sample to the first synchronous transmission board, and receive the test data looped back by the external satellite communication system from the second synchronous transmission board, compare it with the original data, and calculate the automatic test result of synchronous transmission. The test execution module can realize the automatic test of the synchronous data service of the satellite terminal, improve the efficiency and accuracy of the test process, reduce the dependence on manual operation and the risk of human error, and avoid the problem of low test efficiency caused by the manual test scheme used in the prior art to test the performance indicators of the synchronous data service.

[0075] The front-end display module is used to provide users with a visual front-end display interface to manage the system data, monitor and control the test process, and view the test process, test log and test results. The front-end display module can display key information in the system to users in an intuitive way, helping users to quickly obtain required information, improve work efficiency, and provide strong support for the interaction between users and computer systems.

[0076] In a possible implementation manner, the system data includes operation data and test data.

[0077] In one embodiment, the operating data includes but is not limited to: local IP address and port, synchronous transmission board IP address and port, and the test data includes but is not limited to: synchronous transmission rate, test data sample source, number of test packets, number of sent bits, number of received bits, number of bit errors and bit error rate.

[0078] Those skilled in the art will understand that Figure 1 The structure shown in the figure is merely a component architecture diagram of a partial structure related to the embodiment of the present invention, and does not constitute a limitation on the satellite terminal automatic test system to which the embodiment of the present invention is applied. A specific satellite terminal automatic test system may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0079] In one possible implementation, Figure 2 As shown, the composition structure of the first synchronous transmission board and the second synchronous transmission board includes:

[0080] ARM-based instruction interaction module, DDR-based shared memory module and FPGA-based synchronous transmission module.

[0081] The ARM-based instruction interaction module is used to interact with the system body in test control instructions and test data receiving and sending instructions. The ARM-based instruction interaction module can complete efficient data processing and control through simplified instructions when processing complex computing tasks.

[0082] The DDR-based shared memory module is used for data caching and cyclic reading and writing by other modules. The core advantage of the DDR-based shared memory module is that it can transmit data at both the rising and falling edges of each clock cycle, thereby achieving a double data transmission rate. This greatly improves the bandwidth of the memory, allowing the processor to access and process data faster, and the access delay of the DDR-based shared memory module is relatively low, allowing the processor to respond to memory requests faster, improving the overall response speed and performance of the system.

[0083] The FPGA-based synchronous transmission module is used to send test data to the outside in a synchronous manner according to the current synchronization rate, and also supports receiving data sent from the outside in a synchronous form from the synchronous serial port. Due to the parallel processing characteristics of FPGA, the FPGA-based synchronous transmission module can complete data synchronization and transmission with extremely low latency.

[0084] It should be noted that the data block pointed to by the synchronous transmission module pointer is syncCnt, the data block pointed to by the instruction interaction module pointer is orderCnt, the length of a single data block is BlockLength, and the maximum count of data blocks is Max.

[0085] like Figure 1 and Figure 2 As shown, in one possible implementation, the system body communicates with the first synchronous transmission board and the second synchronous transmission board via a LAN connection line, and the first synchronous transmission board and the second synchronous transmission board both communicate with the satellite terminal to be tested and the companion satellite terminal via a synchronous serial port line.

[0086] Second, as Figure 3 As shown, an application method of a satellite terminal automatic test system is provided, which is applied to a system main body, a first synchronous transmission board and a second synchronous transmission board, and the method comprises the following steps:

[0087] S100: The system body is connected to a first synchronous transmission board and a second synchronous transmission board.

[0088] S200, the first synchronous transmission board is connected to the companion satellite terminal, the second synchronous transmission board is connected to the satellite terminal to be tested, and all devices are powered on.

[0089] S300. Configure test parameters on the front-end display interface in the system body.

[0090] It should be noted that the test parameters are configured on the front-end display interface, including but not limited to: test times, test packets, synchronous transmission rate and synchronous transmission test sample source, and the synchronous data transmission test automation test is started.

[0091] S400: The test execution module in the system body starts to execute the automated test based on the test parameter information sent from the front-end display interface.

[0092] S500, load the test times, and set the current test times to 0.

[0093] S600: The system body sends a synchronous transmission rate configuration instruction and a synchronous transmission side configuration instruction to the first synchronous transmission board, and sends a synchronous transmission rate configuration instruction and a synchronous reception side configuration instruction to the second synchronous transmission board.

[0094] It should be noted that the system body starts a test sending thread and a test receiving thread, binds the communication objects to the first synchronous transmission board and the second synchronous transmission board respectively, sends synchronous transmission rate configuration instructions and synchronous sending side configuration instructions to the first synchronous transmission board, and sends synchronous transmission rate configuration instructions and synchronous receiving side configuration instructions to the second synchronous transmission board.

[0095] S700: The system body sends a test data sending instruction carrying original data to the first synchronous transmission board.

[0096] The test sending thread continuously sends test data sending instructions to the first synchronous transmission board, and records the number of sent bits and the number of sent packets at the same time.

[0097] S800. The first synchronous transmission board extracts original data from the test data sending instruction.

[0098] The first synchronous transmission board parses the test data sending instruction, converts it into a synchronous form and sends the test data through the synchronous serial port.

[0099] S900. The first synchronous transmission board sends original data to the companion satellite terminal.

[0100] S1000. The second synchronous transmission board receives loopback data from the satellite terminal to be tested.

[0101] S1100. The second synchronous transmission board converts the loopback data into a test data receiving instruction format.

[0102] S1200. The second synchronous transmission board sends a test data receiving instruction carrying the loopback data to the system body. The loopback data is the data obtained by loopback transmission of the original data through the companion satellite terminal, the satellite communication system radio frequency, and the satellite terminal to be tested.

[0103] The second synchronous transmission board receives the test loopback data sent by the satellite terminal through the synchronous serial port, converts it into the form of test data receiving instructions, and sends it to the system body, and the test receiving thread parses the instructions.

[0104] S1300, the system body compares the loopback data with the original data, and calculates test results such as the number of received bits and the number of error bits in the synchronous data transmission automation.

[0105] S1400: If the test data packet is sent completely and the number of received bits does not change within a certain period of time, the test is terminated and the current test count is increased by 1.

[0106] S1500, determine whether the current test number has reached the preset test number, if so, execute step S1600, if not, jump to step S600.

[0107] S1600: Calculate the test bit error rate as the final test result, where bit error rate = number of error bits / number of transmitted bits.

[0108] Through the method provided in the second aspect, automated testing of satellite terminal synchronous data services can be achieved, test content can be customized, and there is no need to rely on a bit error meter, thereby improving test efficiency and avoiding the manual testing scheme used in the prior art to test the performance indicators of synchronous data services, where a bit error meter is used to send and receive random bit streams for bit error comparison, and the test results are recorded by the tester, resulting in high labor costs, low test efficiency, and the inability to customize test content.

[0109] In one possible implementation, Figure 4 As shown, for step S800, the first synchronous transmission board extracts raw data from the test data sending instruction and applies it to the instruction interaction module, the shared memory module and the synchronous transmission module, which may specifically include:

[0110] S810: The first synchronous transmission board is powered on and initialized.

[0111] S820. Set the data block count syncCnt pointed to by the synchronous transmission module pointer to zero.

[0112] S830. Set orderCnt of the data block pointed to by the instruction interaction module pointer to syncCnt+10.

[0113] S840: The first synchronous transmission board waits to receive a synchronous rate configuration instruction, and the instruction interaction module parses and sets the synchronous transmission rate, and tests the frame length and the synchronous transmission interval.

[0114] S850: The first synchronous transmission board waits to receive a synchronous transmission side configuration instruction, and the working mode is switched to a data transmission mode.

[0115] S860, the synchronous transmission module executes step S861, and the instruction interaction module executes step S862.

[0116] S861. The synchronous transmission module reads the test data from the syncCnt position of the shared memory module and sends the test data outward through the synchronous serial port. When the length of the test data reaches the length of a single data block BlockLength, the syncCnt of the shared memory module moves backward 1 bit in a loop and repeats this step.

[0117] S862, the command interaction module listens to the test data sending command, parses the test data and writes it into the buffer. If the data length of the buffer exceeds 10*FrameLength, and the first synchronous transmission board meets the following conditions:

[0118] (orderCnt + 10 * FrameLength / BlockLength) mod Max < syncCnt, then read test data with a length of 10 * FrameLength from the buffer, circularly write the test data into the shared memory module starting from the orderCnt position, and orderCnt circularly moves backward by 10 * FrameLength / BlockLength bits, wait for a time of SendInterval length, and repeat this step.

[0119] In a possible implementation, as Figure 5 shown, for step S1100, the second synchronous transmission board converts the loopback data into the form of a test data reception instruction and applies it to the instruction interaction module, the shared memory module, and the synchronous transmission module, which may specifically include:

[0120] S1110. The second synchronous transmission board is powered on and initialization is performed.

[0121] S1120. Set the data block count syncCnt pointed to by the pointer of the synchronous transmission module to zero.

[0122] S1130. Set the data block orderCnt pointed to by the pointer of the instruction interaction module to zero.

[0123] S1140. The second synchronous transmission board waits to receive a synchronous rate configuration instruction, and the instruction interaction module parses and sets the synchronous transmission rate, the test frame length, and the synchronous send interval.

[0124] S1150. The second synchronous transmission board waits for a synchronous reception side configuration instruction, and the working mode is switched to the data reception mode.

[0125] S1160. The synchronous transmission module executes step S1161, and the instruction interaction module executes step S1162.

[0126] S1161. The synchronous transmission module obtains synchronous data from the synchronous serial port, writes the synchronous data into the shared memory module starting from the syncCnt position. When the length of the synchronous data reaches the length of a single data block BlockLength, syncCnt circularly moves backward by 1 bit, and repeat this step.

[0127] S1162. If the second synchronous transmission board meets the following conditions:

[0128] (orderCnt + FrameLength / BlockLength) mod Max < syncCnt, the instruction interaction module reads the synchronization data with a length of FrameLength from the orderCnt position of the shared memory module, encapsulates it into a test data reception instruction, and sends it to the system main body. The orderCnt of the shared memory module loops backward by FrameLength / BlockLength bits, and this step is repeated.

[0129] The embodiment of the present application also provides an electronic device, such as Figure 6 shown, the electronic device 1400 includes:

[0130] One or more processors 1410;

[0131] A memory 1420, on which one or more programs are stored. When the one or more programs are executed by the one or more processors 1410, the one or more processors 1410 implement the application method of the satellite terminal automation test system provided in any embodiment of the present application.

[0132] The memory 1420, as a non-transitory network system, can be used to store non-transitory software programs and non-transitory computer-executable programs. In addition, the memory 1420 may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state storage devices. In some embodiments, the memory 1420 may optionally include a memory 1420 remotely disposed relative to the processor 1410, and these remote memories 1420 may be connected to the processor 1410 through a network. Examples of the above networks include but are not limited to the Internet, an enterprise intranet, a local area network, a mobile communication network, and combinations thereof.

[0133] The memory 1420 can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM), etc. The memory 1420 can store an operating system and other application programs. When implementing the technical solutions provided in the embodiments of this specification through software or firmware, the relevant program codes are stored in the memory 1420 and are called by the processor 1410 to execute the methods of the embodiments of the present application.

[0134] The processor 1410 can be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present application.

[0135] In some embodiments, the electronic device further comprises:

[0136] Input / output interface, used to realize information input and output;

[0137] Communication interface, used to realize communication interaction between this device and other devices, which can be realized through wired mode (such as USB, network cable, etc.) or wireless mode (such as mobile network, WIFI, Bluetooth, etc.);

[0138] A bus that transmits information between various components of the device (e.g., processor 1410, memory 1420, input / output interface, and communication interface);

[0139] The processor 1410 , the memory 1420 , the input / output interface and the communication interface can be connected to each other in communication within the device via a bus.

[0140] An embodiment of the present application also provides a computer-readable storage medium storing computer-executable instructions, which are used to execute an application method of a satellite terminal automatic test system provided by any embodiment of the present application.

[0141] An embodiment of the present application also provides a computer program product, including a computer program or computer instructions, which are stored in a computer-readable storage medium. A processor of a computer device reads the computer program or computer instructions from the computer-readable storage medium, and the processor executes the computer program or computer instructions, so that the computer device executes the application method of the satellite terminal automatic test system provided in any embodiment of the present application.

[0142] The system architecture and application scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that with the evolution of the system architecture and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are equally applicable to similar technical problems.

[0143] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0144] It will be appreciated by those skilled in the art that all or some of the steps and systems in the disclosed method above may be implemented as software, firmware, hardware and appropriate combinations thereof. Some physical components or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor or a microprocessor, or may be implemented as hardware, or may be implemented as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or a non-transitory medium) and a communication medium (or a temporary medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that may be used to store desired information and may be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0145] The above describes some embodiments of the present application with reference to the accompanying drawings, but does not limit the scope of the present invention. Any modification, equivalent substitution and improvement made by those skilled in the art without departing from the scope and essence of the present invention shall be within the scope of the present application.

[0146] Those skilled in the art will appreciate that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0147] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0148] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0149] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of the rights of the present invention is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present invention should be within the scope of the rights of the present invention.

Claims

1. A satellite terminal automatic test system, characterized in that: include: System main body, a first synchronous transmission board and a second synchronous transmission board; wherein, The system body is used to send a test data sending instruction carrying original data to the first synchronous transmission board; The first synchronous transmission board is used to extract the original data from the test data sending instruction and send the original data to the accompanying test satellite terminal; The second synchronous transmission board is used to receive loopback data from the satellite terminal to be tested, and send the loopback data to the system body, wherein the loopback data is the data obtained by loopback transmission of the original data through the satellite terminal to be tested, the satellite communication system radio frequency, and the satellite terminal to be tested; The system body is also used to compare the loopback data with the original data and calculate the synchronous data transmission automatic test result.

2. The satellite terminal automatic test system according to claim 1, characterized in that: The system body includes: a data management module, a test execution module and a front-end display module; wherein, The data management module is used to process system data and provide a uniformly encapsulated data management interface to other modules; The test execution module is used to complete the synchronous data transmission automation test; The front-end display module is used to provide a visual front-end display interface to manage the system data, monitor and control the test process, and view the test process, test logs and test results.

3. The satellite terminal automatic test system according to claim 2, characterized in that: The system data includes operation data and test data; The operation data includes the local IP address and port, the synchronous transmission board IP address and port, and the test data includes the synchronous transmission rate, the test data sample source, the number of test packets, the number of sent bits, the number of received bits, the number of bit errors and the bit error rate.

4. The satellite terminal automatic test system according to claim 1, characterized in that: The composition structure of the first synchronous transmission board and the second synchronous transmission board includes: Instruction interaction module, shared memory module and synchronous transmission module; wherein, The instruction interaction module is used to interact with the system body to perform test control instruction interaction and test data receiving and sending instruction interaction; The shared memory module is used for data caching and cyclic reading and writing by other modules; The synchronous transmission module is used to send test data to the outside in a synchronous manner, and also supports receiving data sent from the outside in a synchronous manner from the synchronous serial port.

5. The satellite terminal automatic test system according to claim 1, characterized in that: The system body communicates with the first synchronous transmission board and the second synchronous transmission board via a LAN connection line, and the first synchronous transmission board and the second synchronous transmission board both communicate with the satellite terminal to be tested and the accompanying satellite terminal via a synchronous serial port line.

6. An application method of a satellite terminal automatic test system, characterized in that: Applied to a system main body, a first synchronous transmission board and a second synchronous transmission board, the method comprises the following steps: The system body is connected to the first synchronous transmission board and the second synchronous transmission board; The first synchronous transmission board is connected to the satellite terminal to be tested, and the second synchronous transmission board is connected to the satellite terminal to be tested; The system main body configures test parameters and starts automated testing; The system main body sends a test data sending instruction carrying original data to the first synchronous transmission board; The first synchronous transmission board extracts the original data from the test data sending instruction, and sends the original data to the accompanying test satellite terminal; The second synchronous transmission board card receives loopback data from the satellite terminal to be tested; The second synchronous transmission board card converts the loopback data into the form of a test data reception instruction; The second synchronous transmission board card sends the test data reception instruction carrying the loopback data to the system main body, and the loopback data is the data obtained by the original data through loopback transmission by the accompanying satellite terminal, the satellite communication system radio frequency, and the satellite terminal to be tested; The system main body is further configured to compare the loopback data with the original data and calculate the automated test result of synchronous data transmission.

7. The application method of the satellite terminal automatic test system according to claim 6 is characterized in that: The first synchronous transmission board card extracts the original data from the test data sending instruction and applies it to the instruction interaction module, the shared memory module, and the synchronous transmission module, specifically including the following steps: Set the data block count syncCnt pointed to by the pointer of the synchronous transmission module to zero; Set the data block orderCnt pointed to by the pointer of the instruction interaction module to syncCnt + 10; The first synchronous transmission board card waits to receive a synchronous rate configuration instruction, and the instruction interaction module parses and sets the synchronous transmission rate, test frame length, and synchronous sending interval; The first synchronous transmission board card waits to receive a synchronous sending side configuration instruction, and the working mode is switched to the data sending mode; The synchronous transmission module reads the test data from the syncCnt position of the shared memory module and sends the test data outward through the synchronous serial port. When the length of the test data reaches the length of a single data block BlockLength, the syncCnt of the shared memory module moves backward by 1 bit in a loop, and this step is repeated; The instruction interaction module listens to the test data sending instruction, parses the test data and writes it into the buffer. If the data length in the buffer exceeds 10 * FrameLength, and the first synchronous transmission board card meets the following conditions: (orderCnt + 10 × FrameLength / BlockLength) mod Max < syncCnt, then read the test data with a length of 10 * FrameLength from the buffer, circularly write the test data into the shared memory module from the orderCnt position, and the orderCnt moves backward by 10 * FrameLength / BlockLength bits in a loop, and wait for the time of SendInterval length, and repeat this step.

8. The application method of the satellite terminal automatic test system according to claim 6, characterized in that: The second synchronous transmission board card converts the loopback data into the form of a test data reception instruction and applies it to the instruction interaction module, the shared memory module, and the synchronous transmission module, specifically including the following steps: Set the data block count syncCnt pointed to by the pointer of the synchronous transmission module to zero; Set the data block orderCnt pointed to by the pointer of the instruction interaction module to zero; The second synchronous transmission board card waits to receive a synchronous rate configuration instruction, and the instruction interaction module parses and sets the synchronous transmission rate, test frame length, and synchronous sending interval; The second synchronous transmission board waits for the configuration instruction on the synchronous receiving side, and the working mode is switched to the data receiving mode; The synchronous transmission module obtains synchronous data from the synchronous serial port, writes the synchronous data into the shared memory module from the syncCnt position. When the length of the synchronous data reaches the length of a single data block BlockLength, the syncCnt moves backward by 1 bit in a loop, and this step is repeated; If the second synchronous transmission board meets the following conditions: (orderCnt + FrameLength / BlockLength) mod Max < syncCnt, then the instruction interaction module reads the synchronous data with a length of FrameLength from the orderCnt position of the shared memory module, encapsulates it as the test data receiving instruction, and sends it to the system main body. The orderCnt of the shared memory module moves backward by FrameLength / BlockLength bits in a loop, and this step is repeated.

9. An electronic device, comprising: One or more processors; A memory, on which one or more programs are stored. When the one or more programs are executed by the one or more processors, the one or more processors implement the application method of the satellite terminal automatic test system as described in any one of claims 6-8.

10. A computer-readable storage medium, on which a computer program is stored. When the program is executed by a processor, it implements the application method of the satellite terminal automatic test system as described in any one of claims 6-8.

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