Scrambling and descrambling in passive optical networks

Abstract

The invention relates to scrambling and descrambling in a passive optical network. Example embodiments describe an optical network unit (ONU) configured to transmit data to an optical line terminal (OLT) during an upstream time slot within a passive optical network; wherein the ONU comprises: a scrambler circuit configured to scramble at least one data stream according to a periodic scrambling pattern; and a descrambler circuit configured to descramble the at least one scrambled data stream according to a periodic scrambling pattern; and wherein the ONU further comprises: at least one data channel for exchanging at least one scrambled data stream between the scrambler circuit and the descrambler circuit; and wherein the scrambler circuit is further configured to perform, during a period between the upstream time slots: scrambling a predetermined reference sequence according to a periodic scrambling pattern, thereby obtaining a scrambled reference sequence; and transmitting the scrambled reference sequence to the descrambler circuit over the at least one data channel.

Description

Technical Field

[0001] Various example embodiments relate to passive optical networks and, more particularly, to scrambling and descrambling of upstream data in a passive optical network. Background Art

[0002] In a passive optical network PON, at least one optical line terminal OLT on the network side is connected to one or more optical network units ONU on the user side. It is desirable to physically separate some signal processing functions of the ONU and / or OLT by providing them on different interconnected circuits. This allows implementing or combining different circuits in advantageous physical locations, depending on the signal processing functions they include.

[0003] For emerging PON systems with increased line rates (e.g., 50G-PON according to the ITU-T G.9804 standard), this physical separation of signal processing functions is a challenge because the increased line rates require the connections between the different circuits to have high bandwidth, which significantly increases the cost. To this end, a demultiplexing interface can be used to exchange data streams between interconnected circuits at a lower baud rate than the full-rate PON signal.

[0004] The characteristics of these demultiplexed data streams (e.g., allowed consecutive identical bits and DC balance) are not controlled because the demultiplexed data streams of full-rate PON signals are not standardized. For some full-rate data sequences, the corresponding demultiplexed data streams may therefore include undesirable bit sequences, which may cause malfunctions or poor performance of signal processing functions included in the circuits receiving the demultiplexed data streams, for example, long bit sequences with consecutive identical bits may cause clock recovery failures at the receiving circuits. Summary of the invention

[0005] The scope of protection sought by various embodiments of the present invention is set out in the independent claims. Embodiments and features described in this specification that do not fall within the scope of the independent claims, if any, should be interpreted as examples that aid in understanding the various embodiments of the present invention.

[0006] Among other objects, embodiments of the present invention aim to limit the probability of occurrence of undesired bit sequences affecting signal processing functions when upstream data is exchanged between different circuits of an optical network unit or optical line terminal.

[0007] According to a first exemplary aspect of the present disclosure, the object is achieved by an optical network unit ONU, which is configured to transmit data to an optical line terminal OLT during an upstream time slot in a passive optical network. The ONU includes: a scrambler circuit, which is configured to scramble at least one data stream according to a periodic scrambling pattern; and a descrambler circuit, which is configured to descramble at least one scrambled data stream according to the periodic scrambling pattern. The ONU also includes: at least one data channel, which is used to exchange the at least one scrambled data stream between the scrambler circuit and the descrambler circuit. The scrambler circuit is also configured to perform during the period between the upstream time slots: scrambling a predetermined reference sequence according to the periodic scrambling pattern to obtain a scrambled reference sequence; and sending the scrambled reference sequence to the descrambler circuit through the at least one data channel.

[0008] The scrambler circuit may be included in a first circuit of the ONU, and the descrambler circuit may be included in a second circuit of the ONU. The first circuit and the second circuit may each perform a portion of the signal processing functions of the ONU, such as electro-optical conversion of signals, clock and data recovery, equalization and data processing. The first circuit and the second circuit may also be located in different physical locations. The scrambler circuit and the descrambler circuit and therefore the first circuit and the second circuit are interconnected by means of the at least one data channel providing an interface between the circuits.

[0009] The baud rate of at least one data stream exchanged through the at least one data channel may be significantly lower than the baud rate of data transmitted from the ONU to the OLT (i.e., the upstream line rate of the PON). For example, a 50G non-return-to-zero NRZ upstream signal may be exchanged between the circuits as two demultiplexed 25G NRZ data streams on two data channels, as five demultiplexed 10G NRZ data streams on five data channels, or as a single 50G pulse amplitude modulation 4-level PAM4 data stream on one data channel. Alternatively, the baud rate of the at least one data stream exchanged through the at least one data channel may have substantially the same baud rate as the data transmitted from the ONU to the OLT.

[0010] The predetermined reference sequence is a fixed bit sequence provided to both the scrambler circuit and the descrambler circuit, for example, during ONU configuration or at design time. The scrambler circuit is configured to send the predetermined reference sequence scrambled according to the periodic scrambling pattern to the descrambler circuit. This allows the descrambler circuit to determine the periodic scrambling pattern because the descrambler circuit knows the unscrambled predetermined reference sequence and the descrambler circuit receives the scrambled predetermined reference sequence.

[0011] The scrambled reference sequence is sent to the descrambler circuit via the at least one data channel (i.e. not the at least one data stream). The at least one data stream comprises data received by the ONU, for example from a connected service, which data should be forwarded to the OLT within an upstream burst. The ONU can transmit only upstream bursts during the upstream time slots allocated to the ONU. By sending the scrambled reference sequence to the descrambler circuit via the at least one data channel during the period between consecutive upstream time slots allocated to the ONU, interference with the upstream burst data can be avoided, since no optical signal is transmitted from the ONU to the OLT in this period. The advantage is that the same connection (i.e. at least one data channel) can be used for exchanging burst data and for exchanging scrambled reference sequences.

[0012] Sending the scrambled reference sequence to the descrambler circuit also allows scrambling at least one data stream with different periodic scrambling patterns in time, i.e., the periodic scrambling patterns can be adaptive. This has the advantage that the periodic scrambling pattern can be dynamically adapted to avoid generating undesirable bit sequences that cause failure or poor performance of signal processing functions included in the circuit receiving at least one scrambled data stream, also known as killer modes. For example, a killer mode can be a scrambled data stream with an excessive number of consecutive identical bits, resulting in a clock recovery failure at the receiving circuit (i.e., the descrambler circuit). Another advantage is the ability to use shorter periodic scrambling patterns that are less complex to implement, since the increased probability of occurrence of the killer mode associated with the shorter periodic scrambling pattern can be controlled by dynamically adapting the periodic scrambling pattern.

[0013] Sending the scrambled reference sequence to the descrambler circuit also allows restoring the alignment of the periodic scrambling pattern between upstream time slots (ie between upstream bursts transmitted by the ONU). This has the further advantage that it makes scrambling and descrambling more robust to the occurrence of bit slips.

[0014] According to example embodiments, the predetermined reference sequence may be a bit sequence having the same logic value.

[0015] Thus, the predetermined reference sequence may be a sequence or string of bits in which all bits have a logic value of 0 or all bits have a logic value of 1. In doing so, the periodic scrambling pattern itself or an inverted version of the periodic scrambling pattern appears on at least one data channel. This has the advantage that the periodic scrambling pattern can be determined with only limited or even no processing of the bits received by the descrambler circuit. Another advantage is that no alignment of the predetermined reference sequence has to be performed. The bit length of the predetermined reference sequence may be fixed. The bit length may be provided to the scrambler circuit and the descrambler circuit.

[0016] According to an example embodiment, the descrambler circuit may be further configured to perform: determining the periodic scrambling pattern for descrambling the at least one scrambled data stream based on the scrambled reference sequence and the predetermined reference sequence.

[0017] The descrambler circuit receives a reference sequence scrambled according to the periodic scrambling pattern from the scrambler circuit. Since the predetermined reference sequence is known to the descrambler circuit (e.g., provided in a memory), the descrambling circuit can determine the periodic scrambling pattern used by the scrambling circuit to scramble the reference sequence. Determining the periodic scrambling pattern can be performed during a period between upstream time slots.

[0018] According to an example embodiment, the descrambler circuit may be further configured to perform: capturing at least a portion of the scrambled reference sequence within at least one acquisition buffer.

[0019] Thus, the descrambler circuit may include at least one capture buffer that captures and stores a bit sequence received by the descrambler circuit (i.e., sent by the scrambler circuit). The portion of the scrambled reference sequence that may be captured within the at least one capture buffer is determined by the size of the at least one capture buffer. The capture buffer size may be at least large enough to extract or determine the periodic scrambling pattern from the captured bit sequence. Thus, the capture buffer size may be less than the pattern length of the periodic scrambling pattern, equal to the pattern length of the periodic scrambling pattern, or greater than the pattern length of the periodic scrambling pattern.

[0020] The descrambler circuit may include a plurality of capture buffers associated with a plurality of data channels between the scrambler circuit and the descrambler circuit, respectively. Thus, the corresponding capture buffers may capture received bits sent via the corresponding data channels. An advantage of the capture buffers is that they have low complexity, and the capture buffers are typically available within the ONU (e.g., within a serializer / deserializer SerDes device).

[0021] According to an example embodiment, determining the periodic scrambling pattern may be based on a captured portion of the scrambled reference sequence and the predetermined reference sequence.

[0022] To this end, the descrambler circuit may include a pattern extraction component or block configured to load the captured portion of the scrambled reference sequence from the at least one capture buffer. The pattern extraction component or block may also be configured to determine the periodic scrambling pattern from the loaded portion of the scrambled reference sequence and the predetermined reference sequence.

[0023] According to an example embodiment, the periodic scrambling pattern has a pattern length and the at least one acquisition buffer has a buffer size; and wherein the buffer size is an integer multiple of the pattern length.

[0024] This has the advantage that synchronization of the periodic scrambling pattern determined by the descrambler circuit with the scrambled data stream received by the descrambler circuit can be achieved automatically, since the descrambler circuit knows the internal time relationship between the capture event, the descrambling pattern memory, and the received scrambled data stream. This has the further advantage that, if the predetermined reference sequence is a bit sequence having all logical values ​​0 or 1, the periodic scrambling pattern at the descrambler circuit can be loaded directly from the at least one capture buffer, without having to perform additional operations other than bit inversion of the captured bit sequence, i.e., without additional logic or correlators.

[0025] According to an example embodiment, the scrambler circuit may further include a controller configured to perform: during the period between upstream time slots, sending a control signal to the descrambler circuit, the control signal indicating that the scrambler circuit is sending the scrambled reference sequence to the descrambler circuit through the at least one data channel.

[0026] In other words, a controller within the scrambler circuit can signal the descrambler circuit that the scrambled reference sequence is being sent through the at least one data channel instead of the at least one scrambled data stream. The control signal can be a dedicated signal generated by the controller. Alternatively, the control signal can be an existing signal or a bit sequence that is typically present in the PON, such as a burst enable signal. This allows the descrambler circuit to capture at least a portion of the scrambled reference sequence. The advantage is that sending a control signal to the descrambler circuit does not have to be precisely aligned with the start of sending the scrambled reference sequence through at least one data channel, because the scrambler-descrambler system is self-synchronizing, that is, no external time reference is required to achieve synchronization between the scrambler circuit and the descrambler circuit.

[0027] According to an example embodiment, the scrambler circuit may be further configured to perform: adjusting the periodic scrambling pattern during a period between an end of an upstream time slot and a control signal following the upstream time slot.

[0028] Therefore, it is possible to adapt or change the periodic scrambling pattern for scrambling at least one data stream and a predetermined reference sequence. This adaptation or change can be performed after the upstream time slot assigned to the ONU ends, but before the control signal after the upstream time slot indicating that the scrambler circuit is sending the scrambled reference sequence. In other words, the adaptation of the periodic scrambling pattern can be performed during the portion of the period between the upstream time slots before the controller sends the control signal. This allows the adaptability of the periodic scrambling pattern on a burst-by-burst basis (i.e., between consecutive upstream time slots). This has another advantage, namely, the probability of the killer mode is reduced. For example, adjusting the periodic scrambling pattern can be achieved by changing the seed of the pattern generator (e.g., linear feedback shift register LFSR). Alternatively or in addition, the adjustment can be triggered by the data stream in the upcoming upstream burst.

[0029] According to an example embodiment, the adjustment is based on data expected to be transmitted from the ONU to the OLT in a next upstream time slot.

[0030] If the scrambled data stream of the upstream burst data to be transmitted in the next upstream time slot is a killer pattern, the periodic scrambling pattern can be adjusted or changed, for example, between the end of the upstream time slot and the control signal. Thus, adjusting the periodic scrambling pattern can allow the probability of occurrence of undesirable bit sequences (i.e., killer patterns) that affect signal processing functions to be further limited.

[0031] The upstream burst data transmitted from the ONU to the OLT in an upstream timeslot may comprise a preamble and a payload.Preferably, the adjustment is based on the preamble of data expected to be transmitted by the ONU in a next upstream timeslot.

[0032] According to an example embodiment, the descrambler circuit may be further configured to perform: detecting bit errors by comparing the determined periodic scrambling pattern with one or more previously determined periodic scrambling patterns.

[0033] When the scrambler circuit is transmitting the scrambled reference sequence, a plurality of subsequent bit sequence captures may be performed. A periodic scrambling pattern may be determined for each of these subsequent captured bit sequences. Bit errors in the captured bit sequences may be detected based on deviations in the subsequently determined periodic scrambling patterns, since the determined periodic scrambling patterns should be the same for subsequent captures. For example, the correct periodic scrambling pattern may be identified by performing a majority vote on the captured bits in the subsequent captures.

[0034] According to an example embodiment, the descrambler circuit may be further configured to perform: detecting bit errors by descrambling the scrambled reference sequence according to the periodic scrambling pattern determined by the descrambler circuit.

[0035] To this end, the descrambler circuit may determine a periodic scrambling pattern for descrambling at least one scrambled data stream. Thereafter, while still receiving a scrambled reference sequence from the scrambler circuit, the descrambler circuit may descramble the received scrambled reference sequence according to the determined periodic scrambling pattern. If the descrambling does not produce the predetermined reference sequence, a bit error exists in determining the periodic scrambling pattern.

[0036] According to an example embodiment, the scrambler circuit may be included in a first circuit of the ONU configured to process the at least one data stream; and wherein the descrambler circuit is included in a second circuit of the ONU configured to interface with an optical fiber of the passive optical network to transmit the data to the optical line terminal.

[0037] The second circuit may also be sometimes referred to as "PHY", which implements the physical layer protocol of the PON system, such as optical-to-electrical conversion of signals, electrical-to-optical conversion of signals, clock and data recovery, and equalization. The first circuit may also be sometimes referred to as "HOST", which implements, among other items, the high-level protocol of the PON system.

[0038] According to a second exemplary aspect, an optical line terminal OLT is disclosed, configured to receive data from one or more optical network units ONU during corresponding upstream time slots within a passive optical network. The OLT includes: a scrambler circuit configured to scramble at least one data stream according to a periodic scrambling pattern; and a descrambler circuit configured to descramble at least one scrambled data stream according to the periodic scrambling pattern. The OLT also includes: at least one data channel for exchanging the at least one scrambled data stream between the scrambler circuit and the descrambler circuit. The scrambler circuit is also configured to perform during a period between corresponding upstream time slots: scrambling a predetermined reference sequence according to the periodic scrambling pattern to obtain a scrambled reference sequence; and sending the scrambled reference sequence to the descrambler circuit through the at least one data channel.

[0039] According to a third example aspect, a method is disclosed comprising: during a period between upstream time slots for transmitting data from an optical network unit, ONU, to an optical line terminal, OLT, within a passive optical network:

[0040] -scrambling a predetermined reference sequence according to a periodic scrambling pattern by a scrambler circuit in the ONU, thereby obtaining a scrambled reference sequence; wherein the scrambler circuit is configured to scramble at least one data stream according to the periodic scrambling pattern; and

[0041] - sending the scrambled reference sequence to a descrambler circuit within the ONU via at least one data channel, the at least one data channel being used to exchange the at least one scrambled data stream between the scrambler circuit and the descrambler circuit; wherein the descrambler circuit is configured to descramble the at least one data stream according to the periodic scrambling pattern.

[0042] According to a fourth example aspect, a method is disclosed comprising: during a period between respective upstream time slots for receiving data from one or more optical network units ONU by an optical line terminal OLT within a passive optical network:

[0043] - scrambling a predetermined reference sequence according to a periodic scrambling pattern by a scrambler circuit within the OLT, thereby obtaining a scrambled reference sequence; wherein the scrambler circuit is configured to scramble at least one data stream according to the periodic scrambling pattern; and

[0044] -sending the scrambled reference sequence to a descrambler circuit within the OLT via at least one data channel, the at least one data channel being used to exchange at least one scrambled data stream between the scrambler circuit and the descrambler circuit; wherein the descrambler circuit is configured to descramble the at least one data stream according to the periodic scrambling pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 A schematic block diagram illustrating an example passive optical network;

[0046] Figure 2 An example embodiment of an optical network unit ONU including a scrambler circuit and a descrambler circuit for scrambling and descrambling upstream data in a passive optical network is shown;

[0047] Figure 3 An example embodiment of an optical line terminal OLT comprising a scrambler circuit and a descrambler circuit for scrambling and descrambling upstream data in a passive optical network is shown; and

[0048] Figure 4 An example embodiment of a scrambler circuit and a descrambler circuit for an optical network unit or an optical line terminal according to an embodiment is shown. DETAILED DESCRIPTION

[0049] Figure 1A schematic block diagram of an example point-to-multipoint optical network 100, in particular a passive optical network PON, is shown. The optical network 100 comprises an optical line terminal OLT 110 and a plurality of optical network units ONUs 131, 132, 133, 134 connected via an optical distribution network ODN 120. In this example, the OLT 110 is connected to four ONUs 131, 132, 133, 134, however the OLT 110 may be connected to fewer or more endpoints. The ODN 120 has a tree structure comprising an optical feeder fibre 121, one or more passive optical splitters / multiplexers 123, and a plurality of drop fibres or drop fibres 124, 125, 126, 127 connecting the splitter / multiplexer 123 to the respective ONUs 131, 132, 133, 134. In the downstream direction, the passive optical splitter / multiplexer 123 splits the optical signal from the OLT 110 into low-power optical signals for the connected ONUs 131, 132, 133, 134, while in the upstream direction, the passive optical splitter / multiplexer 123 multiplexes the optical signals from the connected ONUs 131, 132, 133, 134 into burst signals for the OLT 110.

[0050] The passive optical network 100 may be a Gigabit passive optical network GPON according to the ITU-T G.984 standard, a 10x Gigabit passive optical network 10G-PON according to the ITU-T G.987 standard, a 10G symmetric XGS-PON according to the ITU-T G.9807 standard, a four-channel 10G symmetric NG-PON2, 25GS-PON according to the ITU-T G.989 standard, a 50G-PON according to the ITU-T G.9804 standard, or a next generation passive optical network NG-PON. The passive optical network 100 may implement time division multiplexing (TDM) or time and wavelength division multiplexing (TWDM).

[0051] The ONUs 131, 132, 133, 134 typically include multiple components that perform various signal processing functions, such as: optoelectronic transceivers for converting electrical signals into optical signals and vice versa, laser diodes for transmitting optical signals, photodiodes for receiving optical signals, and signal processing units for modulation, demodulation, error correction, and protocol processing.

[0052] The OLT 110 also typically includes multiple components that perform various signal processing functions, such as: optoelectronic transceivers for converting electrical signals into optical signals and vice versa, laser diodes for transmitting optical signals, photodiodes for receiving optical signals, and signal processing units for modulation, demodulation, error correction, and protocol processing.

[0053] These components in both ONU 131,132,133,134 and OLT 110 are usually interconnected to form a sequence or pipeline, so that each component contributes to the processing of signals for transmission or reception. It is desirable to physically separate some signal processing functions of ONU 131,132,133,134 and / or OLT 110 by providing signal processing functions on different interconnected circuits. Therefore, physically separating signal processing functions refers to arranging some components of ONU 131,132,133,134 or OLT 110 on different interconnected circuits, so that different circuits can perform a part of signal processing functions of ONU or OLT respectively. In other words, the sequence or pipeline of signal processing components is distributed across different interconnected circuits. This allows the corresponding signal processing functions of the corresponding circuits to be implemented or combined in a favorable physical location or in combination with the corresponding circuits, for example, the "PHY" layer function can be placed close to the optical connection, and the "HOST" layer function can be placed on the line card.

[0054] For emerging PON systems with increased line rates (e.g., 50G-PON according to the ITU-T G.9804 standard), this physical separation of signal processing functions is a challenge because the increased line rates require the connections between the different circuits to have high bandwidth, thereby significantly increasing costs. To this end, the demultiplexing interface 140 can be used to exchange data streams 144, 145 between the interconnected circuits 141, 142 at a lower baud rate than the full-rate PON signal.

[0055] For example, downstream, a 50G downstream signal 143 modulated according to a non-return-to-zero NRZ modulation format may be received by a first circuit 141 of the ONU 131 configured to receive an optical signal and convert it into an electrical signal. The 50G NRZ downstream signal 143 may be demultiplexed into two 25G NRZ signals 144 for exchanging the 50G NRZ downstream signal 143 using a second circuit 142 of the ONU 131. For example, the second circuit 142 may be configured to further process the signal. In this way, two low-bandwidth connections 144 may be used between the circuits 141, 142, rather than a single high-bandwidth connection.

[0056] In the upstream of this example, data to be transmitted from the ONU 131 to the OLT 110 may be exchanged by the second circuit 142 with the first circuit 141 as two 25G NRZ signals 145. The 25G NRZ signal 145 may be multiplexed into a single 50G NRZ signal 146, which is then transmitted as an optical signal to the OLT 110. Likewise, two low-bandwidth connections 145 may be used between the circuits 141, 142 instead of a single high-bandwidth connection.

[0057] However, such demultiplexed data streams 144, 145 of full-rate PON signals 143, 146 are not standardized. Therefore, the characteristics of these demultiplexed data streams 144, 145 (e.g., allowed consecutive identical bits and DC balance) are not controlled. For some full-rate data sequences 143, 146, the corresponding demultiplexed data streams 144, 145 may therefore include undesirable bit sequences or symbol sequences that cause signal processing functions included in the circuits 141, 142 that receive the demultiplexed data streams 144, 145 to malfunction or perform poorly, for example, long sequences with consecutive identical bits or symbols may cause clock recovery failure at the receiving circuit. This can cause ONUs 131, 132, 133, 134 or OLT 110 to malfunction or perform poorly. Such data streams including undesirable bit sequences that cause signal processing functions to malfunction or perform poorly may be referred to as killer patterns or killer bit sequences. It is therefore desirable to avoid or at least limit the probability of killer mode occurring when providing a demultiplexed connection or interface between circuits of an OLT or ONU.

[0058] This can be achieved by scrambling the demultiplexed data streams 144, 145 by means of a scrambling circuit before the demultiplexed data streams 144, 145 are exchanged or sent to the receiving circuit. The scrambling circuit usually manipulates the data stream before sending it to the receiving circuit. The manipulation (i.e., scrambling) is usually determined by a scrambling pattern. The descrambler circuit within the receiving circuit reverses the manipulation based on the scrambling pattern used, thereby obtaining the original data stream. This allows the bit sequence to be replaced with other bit sequences (i.e., scrambled bit sequences), which changes the probability of the occurrence of killer patterns (i.e., annoying bit sequences). In this way, scrambling the demultiplexed data streams 144, 145 can avoid the generation of killer patterns, for example by avoiding long bit sequences with the same value.

[0059] The problem with scrambling and descrambling a data stream is that some input sequences still result in undesired output sequences, i.e., killer patterns. Another challenge is that longer scrambling patterns generally reduce the probability of killer patterns occurring, but greatly increase implementation complexity. Another problem is that, regardless of the length of the scrambling pattern, at least one input data sequence will result in the occurrence of a killer pattern. Another problem is that the scrambling pattern must generally be provided to the descrambler circuit before the scrambled data is exchanged over the data channel.

[0060] Figure 2An example embodiment of an optical network unit ONU 210 is shown, which includes a scrambler circuit 220 and a descrambler circuit 240 for scrambling and descrambling upstream data 232 to be transmitted by the ONU 210 in the PON, which solves or at least alleviates the above challenges and problems. The scrambler circuit 220 is configured to scramble 226, 227 at least one data stream 222, 223. The data stream 222, 223 may include data from a network connected to the ONU 210 ( Figure 2 The data streams 222, 223 may be data of a service or application (not shown) to be transmitted upstream to the OLT 110. For example, the data streams 222, 223 may be low-level data streams including data packets encapsulated by the PON protocol. The corresponding data streams 222, 223 may be obtained by demultiplexing (demultiplexing) the data streams received from the connected services or applications. Figure 2 The scrambler circuit 220 is configured to scramble 226, 227 the data streams 222, 223 according to a periodic scrambling pattern 228, thereby obtaining corresponding scrambled data streams 230, 231.

[0061] The descrambler circuit 240 is configured to descramble 243, 244 at least one scrambled data stream 230, 231. The scrambler circuit 220 is connected to the descrambler circuit 240 by means of at least one data channel 251, 252. The scrambled data streams 230, 231 are exchanged between the circuits 220, 240 via the respective data channels 251, 252. Thus, the data channels 251, 252 provide a demultiplexing interface between the scrambler circuit 220 and the descrambler circuit 240.

[0062] After descrambling 243, 244 the scrambled data streams 230, 231, the descrambled data streams are multiplexed 230 into upstream signals 232 that can be transmitted from the ONU 210 to the OLT 110 via the PON. The baud rate of the data streams 230, 231 exchanged through the data channels 251, 252 can be significantly lower than the baud rate of the upstream signal 232 transmitted from the ONU to the OLT (i.e., the upstream line rate of the PON).

[0063] Obviously, the number of data lanes 251, 252 can vary depending on how the data streams received from the connected services or applications are demultiplexed into the data streams 222, 223 and how the descrambled data streams are multiplexed into the upstream signal 232 transmitted from the ONU to the OLT. For example, two demultiplexed 25G NRZ data streams 222, 223 can be exchanged through two data lanes 251, 252; five demultiplexed 10G NRZ data streams can be exchanged through five data lanes; or a single 50G pulse amplitude modulation 4-level PAM4 data stream can be exchanged through one data lane. Alternatively, the baud rate of the data streams 230, 231 exchanged through the data lanes 251, 252 can have substantially the same baud rate as the upstream signal 232. For example, this can occur when the data 222, 223 is exchanged between the circuits 220, 240 through a single data lane 251, 252 without demultiplexing.

[0064] It is also apparent that the scrambled data streams 230, 231 exchanged through the respective data channels 251, 252 can be scrambled according to different periodic scrambling patterns 228. For example, scrambled data 230 may be obtained by scrambling 226 data 222 according to a first periodic scrambling pattern, and scrambled data 231 may be obtained by scrambling 227 data 223 according to a second periodic scrambling pattern.

[0065] The upstream signal 232 (i.e., optical signal or burst) is transmitted to the OLT 110 during the upstream time slots 201, 204, 206 assigned to the ONU 210. Such time slots 201, 204, 206 or transmission opportunities are generally assigned to corresponding ONUs in the PON during which the corresponding ONUs are allowed to transmit data to the OLT 110. The upstream time slots 201, 204, 206 assigned to the ONU 210 are cyclic in time. Successive cyclic upstream time slots 201, 204, 206 assigned to the same ONU 210 are separated in time by time periods 203, 205 during which the ONU 210 cannot transmit upstream bursts.

[0066] During the time periods 203, 205 between the upstream time slots 201, 204, 206 allocated to the ONU 210, the scrambler circuit 220 is configured to perform scrambling of the predetermined reference sequences 221a, 221b according to the periodic scrambling pattern 228, thereby obtaining a scrambled reference sequence. In other words, during the time periods 203, 205, the scrambler circuit 220 may scramble the predetermined reference sequences 221a, 221b instead of the data streams 222, 223. This is achieved by Figure 2224, 225 in the ONU. The predetermined reference sequences 221a, 221b are fixed bit sequences provided to both the scrambler circuit 220 and the descrambler circuit 240, for example, during ONU configuration or at design time. Obviously, the corresponding predetermined reference sequences 221a, 221b can be the same sequence, or can be different sequences. For example, the predetermined reference sequences 221a and 221b can both be bit sequences with all logic values ​​0. Alternatively, the predetermined reference sequence 221a can be, for example, a bit sequence with all logic values ​​0, and the predetermined reference sequence 221b can be, for example, a bit sequence with all logic values ​​1.

[0067] The scrambler circuit 220 is also configured to perform sending the scrambled reference sequence to the descrambler circuit 240 via the data channels 251, 252. Thus, the descrambler circuit 240 receives the scrambled version of the reference sequence 221a, 221b. The descrambler circuit 240 may also include components 241, 242 configured to perform determining a periodic scrambling pattern 228 from the received scrambled reference sequence based on the predetermined reference sequence 221a, 221b. Thus, the descrambler circuit 240 may determine the periodic scrambling pattern 228 currently used by the scrambling circuit 220. This allows the scrambled data received from the scrambling circuit 220, e.g., the scrambled data stream 230, 231 of the next upstream burst, to be descrambled 243, 244 using the determined periodic scrambling pattern 228.

[0068] By sending the scrambled reference sequence to the descrambler circuit 240 during the periods 203, 205 between consecutive upstream time slots 201, 204, 206 allocated to the ONU 210, interference with the upstream burst data can be avoided, since no optical signal will be transmitted from the ONU to the OLT during this period 203, 205. An advantage is that the same connection (i.e. at least one data channel 251, 252) can be used for exchanging burst data and for exchanging scrambled reference sequences.

[0069] Sending the scrambled reference sequence to the descrambler circuit 240 also allows scrambling 226, 227 of at least one data stream 222, 223 with different periodic scrambling patterns 228 in time, i.e., the periodic scrambling pattern 228 may be adaptive. For example, a first periodic scrambling pattern may be used to scramble the data streams 222, 223 during the upstream time slot 201. During the period 203, the periodic scrambling pattern may be changed or adapted to a second scrambling pattern. According to the above-described example embodiment, the second scrambling pattern may be provided to the descrambler circuit 240 during the period 203. Then, the second periodic scrambling pattern may be used to scramble the data streams 222, 223 during the upstream time slot 204.

[0070] This has the advantage that the periodic scrambling pattern 228 can be dynamically adapted to avoid generating killer patterns, i.e., scrambled data streams 230, 231 that would cause failure or poor performance of one or more signal processing functions within the ONU 210. Another advantage is that shorter periodic scrambling patterns that are less complex to implement can be used, since the increased probability of occurrence of killer patterns associated with shorter periodic scrambling patterns can be controlled by dynamically adapting the periodic scrambling pattern.

[0071] Sending the scrambled reference sequence to the descrambler circuit 240 also allows restoring the alignment of the periodic scrambling pattern 228 between upstream time slots 201, 204, 206 (i.e., between upstream bursts transmitted by the ONU 210). This has the further advantage of making scrambling and descrambling more robust to the occurrence of bit slips.

[0072] The predetermined reference sequence 221a, 221b may be a sequence of bits having the same logic value. Thus, the predetermined reference sequence 221a, 221b may be a sequence of bits or a bit string of a certain length, in which all bits have a logic value of 0 or all bits have a logic value of 1. In doing so, the periodic scrambling pattern 228 itself appears on the data channels 251, 252, or an inverted version of the periodic scrambling pattern appears on the data channels 251, 252. This has the advantage that, for example, by means of components 241, 242, only limited processing or even no processing needs to be performed on the bits received by the descrambler circuit 240 to determine the periodic scrambling pattern 228. The bit length of the predetermined reference sequence 228 may be fixed. The bit length may be provided to the scrambler circuit 220 and the descrambler circuit 240.

[0073] The scrambler circuit 220 may also be included in a first circuit of the ONU 210, and the descrambler circuit 240 may be included in a second circuit of the ONU 210. The first circuit and the second circuit may each perform a portion of the signal processing functions of the ONU 210, such as electrical-optical conversion of signals, clock and data recovery, equalization, and data processing.

[0074] The first circuit including the scrambler circuit 220 may be configured to process the data streams 222, 223, for example, the "HOST" layer of the ONU 210 implementing the high-level protocol of the PON system. The second circuit including the descrambler circuit 240 may be configured to interface with the optical fiber of the PON to transmit the data to the OLT 110, for example, the "PHY" layer of the ONU 210, which implements the physical layer protocol of the PON system, such as optical-electrical conversion of signals, electrical-optical conversion of signals, clock and data recovery, and equalization.

[0075] Figure 3An example embodiment of an optical line terminal OLT 300 is shown, which includes a scrambler circuit 220 and a descrambler circuit 240 for scrambling and descrambling upstream data 302 received by the OLT 300. The scrambler circuit 220 can be configured to scramble at least one data stream 304, 305. The data streams 304, 305 include burst data originating from ONUs 131, 132, 133, 134 within the PON. The respective data streams 304, 305 can be obtained by demultiplexing 303 the upstream signals or bursts 302 received from the respective ONUs 131, 132, 133. The scrambler circuit 220 is configured to scramble 226, 227 the data streams 304, 305 according to a periodic scrambling pattern 228, thereby obtaining respective scrambled data streams 230, 231.

[0076] The descrambler circuit 240 may be configured to descramble 243, 244 at least one scrambled data stream 230, 231. The scrambler circuit 220 is connected to the descrambler circuit 240 by means of at least one data channel 251, 252. The scrambled data streams 230, 231 are exchanged between the circuits 220, 240 via the respective data channels 251, 252. Thus, the data channels 251, 252 provide a demultiplexing interface between the scrambler circuit 220 and the descrambler circuit 240.

[0077] After descrambling 243, 244 the scrambled data streams 230, 231, the descrambled data streams 306, 307 may be multiplexed ( Figure 3 ) to obtain the burst data 302 received by the OLT 300. The baud rate of the data streams 230, 231 exchanged on the data channels 251, 252 is much lower than the baud rate of the upstream signal 302 received from the ONUs 131, 132, 133, 134, that is, the upstream line rate of the PON.

[0078] The OLT 300 receives the upstream signal or burst 302 during the respective upstream time slots 311, 312, 313, 314 assigned to the respective ONUs 131, 132, 133, 134. During the time slots 311, 312, 313, 314, the respective ONUs 131, 133, 134 are allowed to transmit data to the OLT 300. For example, time slot 311 may be assigned to ONU 131, thereby allowing ONU 131 to transmit an upstream burst during time slot 311. Time slot 312 may be assigned to ONU 132, time slot 313 may be assigned to ONU 133, and time slot 314 may be assigned to ONU 134. Consecutive upstream time slots assigned to the respective ONUs 131, 132, 133, 134 may be separated by periods 315, 316, 317 (sometimes also referred to as guard times). During these periods 315 , 316 , 317 , the OLT 300 does not expect to receive any valuable data, ie, upstream bursts 302 .

[0079] During the time periods 315, 316, 317 between the upstream time slots 311, 312, 313, 314 allocated to the respective ONUs 131, 132, 133, 134, the scrambler circuit 220 is configured to perform scrambling of the predetermined reference sequence 221a, 221b according to the periodic scrambling pattern 228, thereby obtaining a scrambled reference sequence. In other words, during the time periods 315, 316, 317, the scrambler circuit 220 may scramble the predetermined reference sequence instead of the data streams 304, 305. This is achieved by Figure 3 The predetermined reference sequences 221a, 221b are fixed bit sequences provided to both the scrambler circuit 220 and the descrambler circuit 240, for example, during OLT configuration or at design time.

[0080] The scrambler circuit 220 is also configured to perform sending the scrambled reference sequence to the descrambler circuit 240 via the data channels 251, 252. The descrambler circuit 240 thus receives the scrambled version of the reference sequence 221a, 221b. The descrambler circuit 240 may also include components 241, 242 configured to perform determining a periodic scrambling pattern 228 from the received scrambled reference sequence based on the predetermined reference sequence 221a, 221b. Thus, the descrambler circuit 240 may determine the periodic scrambling pattern 228 currently used by the scrambling circuit 220. This allows the scrambled data received from the scrambling circuit 220, for example, the scrambled data stream 230, 231 of the next upstream burst, to be descrambled 243, 244 using the determined periodic scrambling pattern 228.

[0081] By sending the scrambled reference sequence to the descrambler circuit 240 during the periods 315, 316, 317 between consecutive upstream time slots 311, 312, 313, 314 allocated to the respective ONUs 131, 132, 133, 134, interference with the upstream burst data 302 can be avoided, since during these periods no burst data will be received at the OLT 300. An advantage is that the same connection (i.e. at least one data channel 251, 252) can be used for exchanging burst data and for exchanging scrambled reference sequences.

[0082] Sending the scrambled reference sequence to the descrambler circuit 240 also allows to scramble 226, 227 at least one data stream 304, 305 with different periodic scrambling patterns 228 in time, i.e. the periodic scrambling pattern 228 can be adaptive. This has the advantage that the periodic scrambling pattern 228 can be dynamically adapted to avoid killer modes, i.e. scrambled data streams 230, 231 that would cause one or more signal processing functions within the OLT 300 to fail. Another advantage is that shorter periodic scrambling patterns that are less complex to implement can be used, since the increased probability of killer modes associated with shorter periodic scrambling patterns can be controlled by dynamically adapting the periodic scrambling pattern.

[0083] Sending the scrambled reference sequence to the descrambler circuit 240 also allows the alignment of the periodic scrambling pattern 228 between upstream time slots 311, 312, 313, 314 (i.e., between upstream bursts received by the OLT 300) to be restored. This has the further advantage that it makes the scrambling and descrambling more robust to the occurrence of bit slips.

[0084] The scrambler circuit 220 may also be included in a first circuit of the OLT 300, and the descrambler circuit 240 may be included in a second circuit of the OLT 300. The first circuit and the second circuit may each perform a portion of the signal processing functions of the OLT 300, such as optical-electrical conversion of a signal, electrical-optical conversion of a signal, clock and data recovery, equalization, and data processing.

[0085] The first circuit including the scrambler circuit 220 can be configured to interface with the optical fiber of the PON to receive the upstream burst 302 from the corresponding ONU 131, 132, 133, 134, such as the "PHY" layer of the OLT 300, which implements the physical layer protocol of the PON system, such as optical-electrical conversion of signals, electrical-optical conversion of signals, clock and data recovery, and equalization. The second circuit including the descrambler circuit 240 can be configured to process the data stream 304, 305, that is, the received upstream data 302. For example, the "HOST" layer of the OLT 300 implements the high-layer protocol of the PON system.

[0086] Figure 4 An example embodiment 400 of a scrambler circuit and a descrambler circuit for an ONU or an OLT according to an embodiment of the present disclosure is shown. Obviously, the example embodiment 400 of the scrambler circuit and the descrambler circuit can be combined with the example embodiment 400 of the present disclosure. Figure 2 described in the ONU, or is incorporated in the Figure 3 The OLT described. Therefore, Figure 4 The consecutive upstream time slots 411, 416 shown in FIG. 4 may represent time slots allocated to corresponding ONUs when the embodiment 400 is implemented in an OLT; or may represent time slots allocated to a single ONU when the embodiment 400 is implemented in an ONU.

[0087] The descrambler circuit 240 may also be configured to perform capturing at least a portion of the scrambled reference sequence within at least one capture buffer 401, 403. Thus, the descrambler circuit 240 may include at least one capture buffer 401, 403 that captures and stores a sequence having a specific number of bits received by the descrambler circuit 240, i.e., the bits of the scrambled reference sequence sent by the scrambler circuit 220.

[0088] The descrambler circuit 240 may include a plurality of capture buffers 401, 403 associated with the plurality of data lanes 251, 252, respectively, between the scrambler circuit 220 and the descrambler circuit 240. Thus, the respective capture buffers 401, 403 may capture the received bits of the scrambled reference sequence transmitted on the respective data lanes 251, 252. An advantage is that the use of the capture buffers 401, 403 is associated with low complexity, and the capture buffers are typically incorporated in the serializer / deserializer SerDes devices typically available in ONUs and OLTs.

[0089] The descrambler circuit 240 may also include components 402, 404 configured to perform determining the periodic scrambling pattern 228 based on the captured portion of the scrambled reference sequence and the predetermined reference sequence 221a, 221b. For example, the components 402, 404 may be pattern extraction components or blocks that implement logic or correlators that load the captured portion of the scrambled reference sequence from the capture buffer 401, 403. The pattern extraction components or blocks 402, 404 may also be configured to determine the periodic scrambling pattern 228 based on the loaded portion of the scrambled reference sequence and the predetermined reference sequence 221a, 221b.

[0090] It will be further apparent that a single capture buffer and a single pattern extraction component or block may be used to determine a periodic scrambling pattern 228 for descrambling two or more scrambled data streams 230, 231. In this case, the scrambler circuit 220 is configured to scramble 226, 227 a single predetermined reference sequence 221a, 221b according to a single periodic scrambling pattern 228. For example, Figure 4 The descrambler circuit 240 shown in FIG. 2 may include only a capture buffer 401 and a pattern extraction block 402 to obtain the periodic scrambling pattern 228 for descrambling 243 the scrambled data stream 230 and for descrambling 244 the scrambled data stream 231 .

[0091] At least one capture buffer 401, 402 may be characterized by a buffer size, which is defined, for example, by the number of bits that may be captured within the buffer. Thus, the portion of the scrambled reference sequence that may be captured within the at least one capture buffer 401, 403 is determined by the buffer size. The capture buffer size may be at least large enough to extract or determine the periodic scrambling pattern 228 from the captured bit sequence. Thus, the capture buffer size may be less than the pattern length of the periodic scrambling pattern, equal to the pattern length of the periodic scrambling pattern, or greater than the pattern length of the periodic scrambling pattern.

[0092] Preferably, the buffer size of the capture buffer 401, 403 may be an integer multiple of the pattern length of the periodic scrambling pattern. This has the further advantage that synchronization of the periodic scrambling pattern 228 determined by the descrambler circuit with the scrambled data stream 230, 231 received by the descrambler circuit 240 can be achieved automatically, since the descrambler circuit 240 knows the internal time relationship between the capture event, the descrambling pattern memory, and the received scrambled data stream. This has the advantage that, if the predetermined reference sequence 221a, 221b is a bit sequence having all logic values ​​0 or 1, the periodic scrambling pattern 228 at the descrambler circuit 240 may be directly loaded from the capture buffer 401, 403 without performing other operations on the captured bit sequence except bit reversal, i.e., without the need for additional logic or correlators.

[0093] The scrambler circuit 220 may further include a controller 407 configured to send a control signal 405 to the descrambler circuit 240 during periods 412 , 417 between upstream time slots 411 , 416 . Figure 4An example embodiment of the timing 413, 418 of sending such a control signal 405 is shown. The control signal 405 may indicate that the scrambler circuit 220 is sending a scrambled reference sequence to the descrambler circuit 240 via the data channels 251, 252. In other words, the controller 407 within the scrambler circuit 220 may signal the descrambler circuit 240 that the scrambled reference sequence is being sent via at least one data channel 251, 252 instead of at least one scrambled data stream 230, 231. Alternatively, the controller 407 may be included in the descrambler circuit 240. Preferably, the controller 407 is included in a circuit of the ONU or OLT configured to process the data streams 222, 223, for example, a "HOST" layer of the ONU or a "HOST" layer of the OLT. As such, the controller 407 may preferably be included in a circuit such as Figure 2 In the scrambler circuit 220 of the ONU shown in FIG. 1 , or included in the Figure 3 In the descrambler circuit 240 of the OLT shown in FIG.

[0094] The control signal 405 may be a dedicated signal generated by the controller 407, i.e., a signal generated specifically for the purpose of signaling the presence of the scrambled reference sequence on the data channels 251, 252 between the circuits 220, 240. Alternatively, the control signal 405 may be an existing signal or a bit sequence that is typically present in a PON, such as a burst enable signal.

[0095] The control signal 405 allows the descrambler circuit 240 to capture at least a portion of the scrambled reference sequence sent by the scrambler circuit 220. Advantageously, the sending of the control signal 405 to the descrambler circuit 220 does not have to be precisely aligned with the start of sending the scrambled reference sequence over at least one data channel, because the scrambler-descrambler system is self-synchronizing, i.e., no external time reference is required to achieve synchronization between the scrambler circuit 220 and the descrambler circuit 240.

[0096] The controller 407 may also be configured to control sending the scrambled reference sequence to the descrambler circuit 240. This may be accomplished by providing a control signal to components 224, 225 configured to switch between providing the data stream 222, 223 as an input to the scramblers 226, 227 and providing a predetermined reference sequence as an input to the scramblers 226, 227.

[0097] The scrambler circuit may also be configured to perform an adjustment, change or adaptation of the periodic scrambling pattern 228 during the time periods 415, 419 (i.e., between the end of the upstream time slots 411, 416 and the subsequent control signals 413, 418). In other words, the adaptation or change of the periodic scrambling pattern 228 may be performed during the portions 415, 419 of the time periods 412, 417 before the controller sends the control signals 413, 418. This allows the periodic scrambling pattern 228 to be adapted on a burst-by-burst basis (i.e., between consecutive upstream time slots 411, 416). This has another advantage, namely, that the probability of occurrence of the killer mode is reduced. For example, adjusting the periodic scrambling pattern 228 can be achieved by changing the seed of the pattern generator (e.g., a linear feedback shift register LFSR).

[0098] Alternatively or additionally, the adjustment may be triggered by the data stream 222, 223 within the upcoming upstream burst. The adjustment may be based on the data expected to be transmitted during the upstream time slots 411, 416. The upstream burst data may include a preamble and a payload. Preferably, the adjustment is based on the preamble of the data. For example, if the system 400 is incorporated within an ONU, the adjustment may be based on the data expected to be transmitted from the ONU to the OLT within the next upstream time slot allocated to the ONU. If the system 400 is incorporated within an OLT, the adjustment may be, for example, based on the preamble data expected to be received by the OLT within the next upstream time slot allocated to the respective ONU.

[0099] If the scrambled data stream 230, 231 of the upstream burst data to be transmitted in the next upstream time slot 411, 416 is a killer pattern (e.g., a demultiplexed scrambled data stream 230, 231 having a long sequence of consecutive identical bits), the periodic scrambling pattern 228 can be adjusted or changed, for example. Thus, adjusting the periodic scrambling pattern can allow further limiting the probability of occurrence of undesired bit sequences (i.e., killer patterns) that affect signal processing functions.

[0100] The descrambler circuit 240 may also be configured to perform detection of bit errors within the scrambled reference sequence that may result in an erroneously determined scrambling pattern 228 at the descrambler circuit 240. This may be accomplished by comparing the determined periodic scrambling pattern 228 to one or more previously determined periodic scrambling patterns.

[0101] For example, when the scrambler circuit 220 is transmitting the scrambled reference sequence, the capture buffers 401, 403 may subsequently perform multiple bit sequence captures. Thus, components 402, 404 may subsequently determine multiple periodic scrambling patterns 228. In the absence of bit errors, the subsequently determined periodic scrambling patterns should be the same. Therefore, by the deviations in the subsequently determined periodic scrambling patterns, bit errors in one or more captured portions of the scrambled reference sequence can be detected. For example, the correct periodic scrambling pattern can be identified by performing a majority vote on the captured bits in the subsequent captures.

[0102] Alternatively, detecting bit errors within the scrambled reference sequence may be achieved by descrambling 243, 244 the scrambled reference sequence according to the periodic scrambling pattern 228 determined by the descrambler circuit 240. To this end, the descrambler circuit 240 may determine the periodic scrambling pattern 228. Thereafter, while still receiving the scrambled reference sequence from the scrambler circuit 220, the descrambler circuit 240 may descramble 243, 244 the received scrambled reference sequence according to the determined periodic scrambling pattern 228. If the descrambling 243, 244 does not produce the predetermined reference sequence 221a, 221b, then there is a bit error in determining the periodic scrambling pattern.

[0103] As used in this application, the term "circuitry" may refer to one or more or all of the following:

[0104] (a) pure hardware circuit implementations, such as implementations in analog and / or digital circuits only, and

[0105] (b) a combination of hardware circuitry and software such as (where applicable):

[0106] (i) a combination of analog and / or digital hardware circuitry and software / firmware, and

[0107] (ii) any portion of a hardware processor (including a digital signal processor) with software, software, and memory that work together to enable a device (such as a mobile phone or server) to perform various functions; and

[0108] (c) Hardware circuits and / or processors (such as a microprocessor or portion of a microprocessor) that require software (e.g., firmware) to operate, but the software may not be present when it is not required for operation.

[0109] This definition of circuitry applies to all uses of the term in this application, including in any claims. As another example, as used in this application, the term "circuitry" also covers a pure hardware circuit or processor (or multiple processors) or a portion of a hardware circuit or processor and its accompanying software and / or firmware implementation. For example, and if applicable to a particular claim element, the term "circuitry" also covers a baseband integrated circuit or processor integrated circuit for a mobile device, or a similar integrated circuit in a server, cellular network device, or other computing or network device.

[0110] Although the present invention has been described with reference to specific embodiments, it will be clear to those skilled in the art that the present invention is not limited to the details of the aforementioned illustrative embodiments, and the present invention can be implemented with various changes and modifications without departing from its scope. Therefore, the embodiments of the present invention should be considered to be illustrative and not restrictive in all aspects, and the scope of the present invention is indicated by the appended claims rather than the foregoing description, and therefore all changes falling within the meaning and equivalent range of the claims are intended to be included therein. In other words, it is intended to cover any and all modifications, variations or equivalents that fall within the scope of the basic principles and whose basic properties are claimed in this patent application.

[0111] The reader of this patent application should also understand that the words "comprise" or "include" do not exclude other elements or steps, the words "one" or "an" do not exclude multiple, and a single element such as a computer system, a processor, or another integrated unit can implement the functions of multiple components recorded in the claims. Any reference mark in the claims should not be interpreted as limiting the relevant corresponding claims. When used in the specification or claims, the terms "first", "second", "third", "a", "b", "c", etc. are introduced to distinguish similar elements or steps, rather than necessarily describing the order or time sequence. Similarly, the terms "top", "bottom", "above", "below", etc. are introduced for descriptive purposes and do not necessarily indicate relative positions. It should be understood that the terms used in this way are interchangeable where appropriate, and embodiments of the present invention can be operated according to the present invention in other orders or in directions different from those described or illustrated above.

Claims

1. An optical network unit ONU (210) configured to transmit data (232) to an optical line terminal OLT (110) during an upstream time slot (201, 204, 206) within a passive optical network; wherein: The ONU comprises: a scrambler circuit (220) configured to scramble (226, 227) at least one data stream (222, 223) according to a periodic scrambling pattern (228); and a descrambler circuit (240) configured to descramble (243, 244) at least one scrambled data stream (230, 231) according to the periodic scrambling pattern; and wherein the ONU further comprises: at least one data channel (251, 252) for exchanging the at least one scrambled data stream between the scrambler circuit and the descrambler circuit; and wherein the scrambler circuit is further configured to perform, during a period (203, 205) between the upstream time slots: - scrambling a predetermined reference sequence (221a, 221b) according to the periodic scrambling pattern, thereby obtaining a scrambled reference sequence; and - sending the scrambled reference sequence to the descrambler circuit over the at least one data channel.

2. The optical network unit (ONU) according to claim 1, wherein: The predetermined reference sequence (221a, 221b) is a bit sequence having the same logic value.

3. An optical network unit (ONU) according to any one of the preceding claims, wherein: The descrambler circuit (240) is further configured to perform: Based on the scrambled reference sequence and the predetermined reference sequence (221a, 221b), the periodic scrambling pattern (228) is determined for descrambling the at least one scrambled data stream (230, 231).

4. An optical network unit (ONU) according to any one of the preceding claims, wherein: The descrambler circuit (240) is further configured to perform: At least a portion of the scrambled reference sequence is captured in at least one capture buffer (401, 403).

5. The optical network unit (ONU) according to claim 3 or 4, wherein: Determining the periodic scrambling pattern (228) is based on the captured portion of the scrambled reference sequence and the predetermined reference sequence.

6. The optical network unit (ONU) according to claim 4, wherein: The periodic scrambling pattern (228) has a pattern length, and the at least one acquisition buffer (401, 403) has a buffer size; and wherein the buffer size is an integer multiple of the pattern length.

7. An optical network unit (ONU) according to any one of the preceding claims, wherein: The scrambler circuit (220) further comprises a controller (407) configured to perform: During the period (412, 417) between upstream time slots, a control signal (305) is sent to the descrambler circuit, the control signal indicating that the scrambler circuit is sending the scrambled reference sequence to the descrambler circuit over the at least one data lane.

8. The optical network unit (ONU) according to claim 7, wherein: The scrambler circuit is further configured to perform: The periodic scrambling pattern (228) is adjusted during a period (415, 419) between the end of an upstream time slot (411, 416) and a control signal (413, 418) following the upstream time slot.

9. The optical network unit (ONU) according to claim 8, wherein: The adjustment is based on data expected to be transmitted from the ONU to the OLT in the next upstream time slot (411, 416).

10. An optical network unit (ONU) according to any one of the preceding claims, wherein: The descrambler circuit (240) is further configured to perform: Bit errors are detected by comparing the determined periodic scrambling pattern to one or more previously determined periodic scrambling patterns.

11. The optical network unit (ONU) according to claim 3, wherein: The descrambler circuit (240) is further configured to perform: Bit errors are detected by descrambling the scrambled reference sequence according to the periodic scrambling pattern determined by the descrambler circuit.

12. An optical network unit (ONU) according to any one of the preceding claims, wherein: The scrambler circuit (220) is included in a first circuit of the ONU configured to process the at least one data stream; and wherein the descrambler circuit (240) is included in a second circuit of the ONU configured to interface with an optical fiber of the passive optical network to transmit the data to the optical line terminal.

13. An optical line terminal OLT (300) configured to receive data (302) from one or more optical network units ONU (131, 132, 133, 134) during corresponding upstream time slots (311, 312, 313, 314) within a passive optical network; wherein, The OLT comprises: a scrambler circuit (220) configured to scramble (226, 227) at least one data stream (304, 305) according to a periodic scrambling pattern (228); and a descrambler circuit (240) configured to descramble (243, 244) at least one scrambled data stream (230, 231) according to the periodic scrambling pattern; and wherein the OLT further comprises: at least one data channel (251, 252) for exchanging the at least one scrambled data stream between the scrambler circuit and the descrambler circuit; and wherein the scrambler circuit is further configured to perform, during a period (315, 316, 317) between corresponding upstream time slots (311, 312, 313, 314): - scrambling a predetermined reference sequence (221a, 221b) according to the periodic scrambling pattern, thereby obtaining a scrambled reference sequence; and - sending the scrambled reference sequence to the descrambler circuit over the at least one data channel.

14. A method comprising: During the period between upstream time slots used to transmit data from the optical network unit ONU to the optical line terminal OLT within the passive optical network: -scrambling a predetermined reference sequence according to a periodic scrambling pattern by a scrambler circuit in the ONU, thereby obtaining a scrambled reference sequence; wherein the scrambler circuit is configured to scramble at least one data stream according to the periodic scrambling pattern; and - sending the scrambled reference sequence to a descrambler circuit within the ONU via at least one data channel, the at least one data channel being used to exchange the at least one scrambled data stream between the scrambler circuit and the descrambler circuit; wherein the descrambler circuit is configured to descramble the at least one data stream according to the periodic scrambling pattern.

15. A method comprising: During the period between respective upstream time slots for receiving data from one or more optical network units ONU by the optical line terminal OLT within the passive optical network: - scrambling a predetermined reference sequence according to a periodic scrambling pattern by a scrambler circuit within the OLT, thereby obtaining a scrambled reference sequence; wherein the scrambler circuit is configured to scramble at least one data stream according to the periodic scrambling pattern; and -sending the scrambled reference sequence to a descrambler circuit within the OLT via at least one data channel, the at least one data channel being used to exchange at least one scrambled data stream between the scrambler circuit and the descrambler circuit; wherein the descrambler circuit is configured to descramble the at least one data stream according to the periodic scrambling pattern.

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