PAM4 Transmitter and Its Linearity Adjustment Method

Abstract

The present disclosure provides a PAM4 transmission device and a method for adjusting its linearity. The PAM4 generating device according to the present disclosure includes: a transmitting unit configured to receive a transmission signal and a linearity configuration signal and output a PAM4 output signal; a feedback reading unit configured to receive the PAM4 output signal and a threshold configuration signal and output a feedback reading signal; a comparison unit configured to receive the transmission signal and the feedback reading signal and compare the transmission signal and the feedback reading signal to output a comparison result; and a control unit configured to receive the comparison result and output the linearity configuration signal and the threshold configuration signal. According to the PAM4 transmission device and the method for adjusting its linearity of the present disclosure, regardless of how the environment and temperature change, the linearity of the PAM4 output signal can be adjusted in real time while outputting the PAM4 output signal to meet the linearity requirements of the PAM4 output signal.

Description

Technical Field

[0001] The present disclosure relates to the technical field of electronic circuits, and in particular, to a PAM4 transmitting device and a linearity adjustment method thereof. Background Art

[0002] Wired high-speed data transmission systems usually include a transmitter and a receiver. With the increase in transmission bandwidth, four-level pulse amplitude modulation (PAM4: Pulse-Amplitude Modulation 4-Level) technology has been widely used and adopted by multiple transmission standards. PAM4 technology uses four different voltage levels to transmit data, and can transmit 2 bits of information in each symbol cycle. Compared with the traditional non-return-to-zero (NRZ: Non-Return-to-Zero) signal, PAM4 signal can achieve twice the bit rate at the same baud rate.

[0003] In PAM4 technology, the linearity of the output signal is an important indicator of the PAM4 transmitter. Unsatisfactory linearity usually increases the bit error rate of the receiving device and affects the entire transmission system. However, it is difficult for existing PAM4 transmitters to meet the linearity requirements of the PAM4 output signal. Therefore, a PAM4 transmitter is needed that can optimize the PAM4 output signal to meet the linearity requirements of the PAM4 output signal.

[0004] The above information disclosed in this Background section is only for understanding the background of the present disclosure concept and therefore it may contain information that does not constitute prior art. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present disclosure proposes a novel PAM4 transmitting device and a linearity adjustment method thereof.

[0006] According to one aspect of the present disclosure, a four-level pulse amplitude modulation (PAM4) transmitting device is provided, which includes: a transmitting unit, configured to receive a transmitting signal and a linearity configuration signal, and output a PAM4 output signal; a readback unit, configured to receive the PAM4 output signal and a threshold configuration signal, and output the readback signal; a comparing unit, configured to receive the transmitting signal and the readback signal, and compare the transmitting signal and the readback signal to output a comparison result; and a control unit, configured to receive the comparison result, and output a linearity configuration signal and a threshold configuration signal.

[0007] According to another aspect of the present disclosure, a method for adjusting the linearity of a PAM4 transmission device is provided, which includes: a first step: a control unit outputs a linearity configuration signal, and a transmission unit adjusts the linearity of a PAM4 output signal according to the linearity configuration signal; a second step: the control unit outputs a threshold configuration signal, a readback unit outputs a readback signal according to the threshold configuration signal, a comparison unit compares the transmission signal and the readback signal and outputs the comparison result to the control unit, and the control unit records the current threshold configuration signal and the corresponding comparison result; a third step: repeat the second step multiple times, and the control unit records a series of threshold configuration signals and a series of corresponding comparison results; a fourth step: the control unit calculates the linearity of the PAM4 output signal, and when the linearity does not meet the target value, the control unit adjusts the linearity configuration signal; and a fifth step: repeat the first step to the fourth step until the linearity of the PAM4 output signal meets the target value.

[0008] The PAM4 transmission device according to the present disclosure can, during the transmission process, regardless of how the environment and temperature change, adjust the linearity of the PAM4 output signal in real time while outputting the PAM4 output signal to meet the requirements for the linearity of the PAM4 output signal.

[0009] However, the effects of the present disclosure are not limited to the above effects, and various expansions can be made without departing from the spirit and scope of the present disclosure. It should be understood that the foregoing general description and the following detailed description are both exemplary and explanatory, and are intended to provide further illustration of the claimed present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying drawings are included to provide a further understanding of the present disclosure, and the drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the present disclosure and, together with the specification, are used to explain the inventive concept of the present disclosure.

[0011] Figure 1 is a schematic block diagram showing a PAM4 wired data transmission system.

[0012] Figure 2 is a schematic eye diagram showing a PAM4 output signal.

[0013] Figure 3 is a schematic block diagram showing a PAM4 transmission device according to an embodiment of the present disclosure.

[0014] Figure 4 is a schematic block diagram showing a transmission unit according to an embodiment of the present disclosure.

[0015] Figure 5 is a schematic circuit diagram showing an output sub-unit according to an embodiment of the present disclosure.

[0016] Figure 6 is a schematic block diagram showing a read-back unit according to an embodiment of the present disclosure.

[0017] Figure 7 is a schematic circuit diagram showing an input sub-unit according to an embodiment of the present disclosure and an eye diagram schematic of a PAM4 output signal.

[0018] Figure 8 is a schematic flowchart showing a linearity adjustment method of a PAM4 transmission device according to an embodiment of the present disclosure. Detailed Embodiments

[0019] In the following description, for purposes of illustration, numerous specific details are set forth in order to provide a thorough understanding of the various exemplary embodiments of the present disclosure. As used herein, "embodiment" is a non-limiting example of a device or method that employs one or more of the inventive concepts disclosed herein. However, it will be apparent that the various exemplary embodiments may be practiced without these specific details or with one or more equivalent configurations. In addition, the various exemplary embodiments may be different, but not necessarily exclusive. For example, without departing from the inventive concept of the present disclosure, specific features of other exemplary embodiments may be used or implemented in some exemplary embodiments.

[0020] Unless otherwise stated, the described exemplary embodiments are to be understood as providing exemplary features of some ways in which the inventive concept of the present disclosure may be implemented in practice. Thus, unless otherwise stated, the features, components, units, regions, and / or aspects, etc. (hereinafter individually or collectively referred to as "elements") of the various embodiments may be combined, separated, interchanged, and / or reconfigured otherwise without departing from the inventive concept of the present disclosure.

[0021] For the purposes of the present disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be construed to mean only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0022] Although terms such as "first" and "second" may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0023] The terms used herein are for the purpose of describing particular embodiments and are not intended to be limiting. As used herein, the singular forms "a" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Further, when used in this specification, the terms "comprises" and / or "comprising" mean that the stated features, steps, operations, elements, components, and / or groups thereof are present, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof.

[0024] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0025] Embodiments of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings. However, the present disclosure may be implemented in many different ways and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Like reference numerals throughout the figures denote like elements.

[0026] Embodiments of the present disclosure will be described below in conjunction with the accompanying drawings.

[0027] Figure 1 A schematic block diagram of a four-level pulse amplitude modulation (PAM4) wired data transmission system 1 is shown.

[0028] As Figure 1 shown, the PAM4 wired data transmission system 1 generally may include a PAM4 transmitting device 10, a PAM4 receiving device 50, and a transmission cable connected between the PAM4 transmitting device 10 and the PAM4 receiving device 50. The PAM4 transmitting device 10 may receive a transmission signal 11 and output a PAM4 output signal 21. The PAM4 output signal 21 may be received by the PAM4 receiving device 50 via the transmission cable, and the PAM4 receiving device 50 may perform amplification or equalization processing on the PAM4 output signal 21.

[0029] The PAM4 transmitting device 10 may be configured to transmit the PAM4 output signal 21 in the form of a differential signal. In this case, the transmission cable may be a differential signal cable, such as a differential twisted pair cable. The PAM4 transmitting device 10 may also be configured to transmit the PAM4 output signal 21 in the form of a single-ended signal. In this case, the transmission cable may also be a single-ended signal cable such as a shielded coaxial cable.

[0030] Figure 2 shows a schematic eye diagram of a PAM4 output signal. In Figure 2 , (a) shows that the linearity of the PAM4 output signal is better, while (b) shows that the linearity of the PAM4 output signal is worse, which will be described in more detail below.

[0031] PAM4 technology converts binary logic signals into four different level signals according to a predetermined rule. Therefore, each period of the PAM4 output signal includes the logic information of two-bit data. The two-bit data can be represented by the most significant bit (MSB) data and the least significant bit (LSB) data.

[0032] In this article, when both the MSB data and the LSB data are logic low level 0, the two-bit data of PAM4 can be marked as "00", when the MSB data and the LSB data are logic low level 0 and logic high level 1 respectively, the two-bit data of PAM4 can be marked as "01", when the MSB data and the LSB data are logic high level 1 and logic low level 0 respectively, the two-bit data of PAM4 can be marked as "10", and when both the MSB data and the LSB data are logic high level 1, the two-bit data of PAM4 can be marked as "11".

[0033] It should be noted that "logic high level" and "logic low level" are used to describe the logic levels of signals. A signal with "logic high level" is different from a signal with "logic low level". For example, when a signal with a first voltage corresponds to a signal with "logic high level", a signal with a second voltage corresponds to a signal with "logic low level". According to the embodiment, the voltage of "logic high level" is higher than that of "logic low level". According to the embodiment, the logic levels of signals can be at different logic levels or opposite logic levels. For example, in some embodiments, a signal with logic high level can be at logic low level, while in other embodiments, a signal with logic low level can be at logic high level.

[0034] As Figure 2 shown, the voltage of the PAM4 output signal can include four level voltages. In this embodiment, the four level voltages of the PAM4 output signal can be respectively represented as level 0, level 1, level 2, and level 3.

[0035] In this article, level 0 is the PAM4 output signal when the two-bit data of PAM4 is "00", level 1 is the PAM4 output signal when the two-bit data of PAM4 is "01", level 2 is the PAM4 output signal when the two-bit data of PAM4 is "10", and level 3 is the PAM4 output signal when the two-bit data of PAM4 is "11".

[0036] As Figure 2 shown, the schematic eye diagram of the PAM4 output signal includes three eye heights, namely eye height A, eye height B, and eye height C. Among them, eye height A can be defined as the voltage amplitude difference between level 0 and level 1, eye height B can be defined as the voltage amplitude difference between level 1 and level 2, and eye height C can be defined as the voltage amplitude difference between level 2 and level 3.

[0037] The linearity (RLM) of the PAM4 output signal can be defined as: 3 × min(A, B, C) / sum(A, B, C), where min(A, B, C) is the minimum value of eye height A, eye height B, and eye height C, that is, the minimum value among the three eye heights, and sum(A, B, C) is the sum of eye height A, eye height B, and eye height C, that is, the total voltage amplitude of the PAM4 output signal.

[0038] It can be seen from the definition of the above linearity calculation formula that the smaller the difference between the three eye heights, the larger the calculation result of the linearity RLM, and the better the linearity of the PAM4 output signal. On the contrary, the larger the difference between the three eye heights, the smaller the calculation result of the linearity RLM, and the worse the linearity of the PAM4 output signal.

[0039] Specifically, when eye height A, eye height B, and eye height C are the same as each other, the calculated value of the linearity RLM is 1, which is the theoretical maximum value of RLM. When eye height A, eye height B, and eye height C are different from each other, RLM is less than 1. Therefore, in order to obtain a larger RLM value, that is, better linearity, eye height A, eye height B, and eye height C should be as close to each other as possible.

[0040] Return Figure 2 , in Figure 2 the schematic eye diagram shown in (a), eye height A, eye height B, and eye height C are the same as or close to each other, and the calculated result of the linearity RLM is approximately 1. Therefore, its linearity is better. On the contrary, in Figure 2 the schematic eye diagram shown in (b), eye height A is the smallest, eye height B is the second, and eye height C is the largest. The three are different from each other, and the calculated value of the linearity RLM is much less than 1. Therefore, its linearity is worse.

[0041] The PAM4 technology has been adopted by multiple transmission standards. Usually, the PAM4 technology defines relatively strict index requirements for the linearity of the output signal of the PAM4 transmitting device (that is, the PAM4 output signal). For example, the 56G optical communication protocol (OIF CEI-56G) stipulates that the minimum value of the linearity RLM of the PAM4 output signal is 0.95. In addition, although the 10G automotive Ethernet protocol (10G BASE-T1) does not stipulate the linearity RLM, it can be known through other calculation methods that it also has relatively strict requirements for the linearity of the PAM4 output signal.

[0042] However, existing PAM4 transmission devices are difficult to meet the linearity requirements of PAM4 output signals. The linearity of PAM4 output signals is usually achieved by optimizing design parameters during the design process of the transmission device. However, the linearity of PAM4 output signals is inevitably affected by factors such as semiconductor processes, power supply voltages, and temperatures. For example, environmental and temperature changes can affect the characteristics of semiconductor devices in the PAM4 transmission device, thereby changing the linearity of the PAM4 output signal. Therefore, a PAM4 transmission device is needed that can continuously optimize the linearity of the PAM4 output signal during operation to meet the linearity requirements of the system for the PAM4 output signal.

[0043] To solve the above problems, a PAM4 transmission device according to the present disclosure is proposed.

[0044] Figure 3 A schematic block diagram of a PAM4 transmission device 10 according to an embodiment of the present disclosure is shown.

[0045] As Figure 3 shown, according to an embodiment of the present disclosure, the PAM4 transmission device 10 may include a transmission unit 100, a feedback unit 200, a comparison unit 300, and a control unit 400.

[0046] As Figure 3 shown, according to an embodiment of the present disclosure, the transmission unit 100 may receive a transmission signal 11 and output a PAM4 output signal 21. According to an embodiment of the present disclosure, the transmission signal 11 may be an analog signal. According to an embodiment of the present disclosure, the transmission signal 11 may be a digital signal of one or more bits. According to an embodiment of the present disclosure, the PAM4 output signal 21 may be a differential signal, including a positive signal and a negative signal. According to an embodiment of the present disclosure, the PAM4 output signal 21 may be a single-ended signal, including only one polarity.

[0047] According to an embodiment of the present disclosure, the transmission unit 100 may further receive a linearity configuration signal 41 for adjusting the linearity of the PAM4 output signal 21. According to an embodiment of the present disclosure, the linearity configuration signal 41 may be a digital signal of one or more bits. According to an embodiment of the present disclosure, the linearity configuration signal 41 may be one or more analog signals.

[0048] As Figure 3As shown, according to an embodiment of the present disclosure, the readback unit 200 may receive the PAM4 output signal 21 and output a readback signal 31. According to an embodiment of the present disclosure, the readback unit 200 may receive a differential PAM4 output signal 21, which includes a positive signal and a negative signal. According to an embodiment of the present disclosure, the readback unit 200 may receive a single-ended PAM4 output signal 21, which includes only one polarity. According to an embodiment of the present disclosure, the readback signal 31 may be an analog signal. According to an embodiment of the present disclosure, the readback signal 31 may be a digital signal of one or more bits.

[0049] According to an embodiment of the present disclosure, the readback unit 200 may further receive a threshold configuration signal 42 for changing the readback signal 31 output by the readback unit 200. According to an embodiment of the present disclosure, the threshold configuration signal 42 may be a digital signal of one or more bits. According to an embodiment of the present disclosure, the threshold configuration signal 42 may also be one or more analog signals.

[0050] As Figure 3 shown, according to an embodiment of the present disclosure, the comparison unit 300 may receive the transmission signal 11 and the readback signal 31, and compare the transmission signal 11 and the readback signal 31 to output a comparison result 32.

[0051] Specifically, according to an embodiment of the present disclosure, when the transmission signal 11 and the readback signal 31 are exactly the same, the comparison result 32 output by the comparison unit 300 may be a logic high level 1, and when the transmission signal 11 and the readback signal 31 are not exactly the same, the comparison result 32 output by the comparison unit 300 may be a logic low level 0.

[0052] According to an embodiment of the present disclosure, when both the transmission signal 11 and the readback signal 31 are multi-bit digital signals, the comparison result 32 may be a one-bit voltage signal. For example, when each corresponding bit of the transmission signal 11 and the readback signal 31 is exactly the same, the comparison result 32 may be a logic high level 1, otherwise it may be a logic low level 0.

[0053] According to an embodiment of the present disclosure, when both the transmission signal 11 and the readback signal 31 are multi-bit digital signals, the comparison result 32 may be a multi-bit digital signal, where each bit of the comparison result 32 may represent the comparison result of each corresponding bit of the transmission signal 11 and the readback signal 31.

[0054] As Figure 3 shown, according to an embodiment of the present disclosure, the control unit 400 receives the comparison result 32 and outputs a linearity configuration signal 41 and a threshold configuration signal 42.

[0055] Figure 4FIG. 0 shows a schematic block diagram of a transmission unit 100 according to an embodiment of the present disclosure.

[0056] As Figure 4 shown, according to an embodiment of the present disclosure, the transmission unit 100 may include a serialization subunit 101, an encoding subunit 102, and an output subunit 103.

[0057] As Figure 4 shown, according to an embodiment of the present disclosure, the serialization subunit 101 may receive a transmission signal 11 and output a two-bit digital signal, including a transmission MSB signal 13 and a transmission LSB signal 12. According to an embodiment of the present disclosure, when the transmission signal 11 is a multi-bit digital signal, the serialization subunit 101 may perform a serialization operation on the transmission signal 11. Specifically, according to an embodiment of the present disclosure, when the transmission signal 11 is, for example, a 20-bit digital signal, the serialization subunit 101 may perform a 10:1 serialization operation on the transmission signal 11 to output the transmission MSB signal 13 and the transmission LSB signal 12.

[0058] As Figure 4 shown, according to an embodiment of the present disclosure, the encoding subunit 102 may receive the transmission MSB signal 13 and the transmission LSB signal 12, perform an encoding operation on them, and output an encoded transmission signal, including signal 16, signal 15, and signal 14.

[0059] Specifically, according to an embodiment of the present disclosure, the encoding subunit 102 may perform the following encoding operation on the transmission MSB signal 13 and the transmission LSB signal 12: when the transmission MSB signal 13 and the transmission LSB signal 12 are "00", the encoded transmission signal may be "000", that is, signal 16, signal 15, and signal 14 are all logic low level 0; when the transmission MSB signal 13 and the transmission LSB signal 12 are "01", the encoded transmission signal may be "001", that is, signal 16, signal 15, and signal 14 are logic low level 0, logic low level 0, and logic high level 1 respectively; when the transmission MSB signal 13 and the transmission LSB signal 12 are "10", the encoded transmission signal may be "011", that is, signal 16, signal 15, and signal 14 are logic low level 0, logic high level 1, and logic high level 1 respectively; when the transmission MSB signal 13 and the transmission LSB signal 12 are "11", the encoded transmission signal may be "111", that is, signal 16, signal 15, and signal 14 are all logic high level 1.

[0060] As Figure 4 shown, according to an embodiment of the present disclosure, the output subunit 103 may receive the encoded transmission signal (including signal 16, signal 15, and signal 14) and a linearity configuration signal 41, and output a PAM4 output signal 21.

[0061] In this document, according to an embodiment of the present disclosure, the voltage level of the PAM4 output signal 21 can be level 0, level 1, level 2, or level 3.

[0062] According to an embodiment of the present disclosure, when the encoded transmission signal is "000", the PAM4 output signal 21 can be level 0; when the encoded transmission signal is "001", the PAM4 output signal 21 can be level 1; when the encoded transmission signal is "011", the PAM4 output signal 21 can be level 2; and when the encoded transmission signal is "111", the PAM4 output signal 21 can be level 3.

[0063] According to an embodiment of the present disclosure, the linearity configuration signal 41 can adjust the linearity of the PAM4 output signal 21.

[0064] Specifically, according to an embodiment of the present disclosure, the linearity configuration signal 41 can adjust the linearity of the PAM4 output signal 21 by changing at least one of the eye height A, eye height B, and eye height C of the PAM4 output signal 21.

[0065] Figure 5 A schematic circuit diagram of the output sub-unit 103 according to an embodiment of the present disclosure is shown.

[0066] According to an embodiment of the present disclosure, the output sub-unit 103 can include one or more current source sub-units. For example, as Figure 5 shown, according to an embodiment of the present disclosure, the output sub-unit 103 can include a first current source sub-unit 104, a second current source sub-unit 105, and a third current source sub-unit 106.

[0067] According to an embodiment of the present disclosure, the linearity configuration signal 41 can change the output current value of one or more current source sub-units in the output sub-unit 103. Correspondingly, as Figure 5 shown, according to an embodiment of the present disclosure, the linearity configuration signal 41 can include a first linearity configuration signal 41_1, a second linearity configuration signal 41_2, and a third linearity configuration signal 41_3.

[0068] As Figure 5 shown, according to an embodiment of the present disclosure, the first current source sub-unit 104 can receive the first linearity configuration signal 41_1 for adjusting its output current value, the second current source sub-unit 105 can receive the second linearity configuration signal 41_2 for adjusting its output current value, and the third current source sub-unit 106 can receive the third linearity configuration signal 41_3 for adjusting its output current value.

[0069] According to an embodiment of the present disclosure, the output subunit 103 includes one or more switching transistors for controlling whether the current of the corresponding current source subunit is incorporated into the PAM4 output signal 21. As Figure 5 shown, according to an embodiment of the present disclosure, the output subunit 103 may include a first switching transistor M14, a second switching transistor M15, and a third switching transistor M16.

[0070] As Figure 5 shown, according to an embodiment of the present disclosure, the first switching transistor M14 is connected in series with the first current source subunit 104, and the gate of the first switching transistor M14 receives the encoded transmission signal 14, the source of the first switching transistor M14 is connected to the PAM4 output signal 21, and the drain of the first switching transistor M14 is connected to the first current source subunit 104.

[0071] According to an embodiment of the present disclosure, when the encoded transmission signal 14 is at a logic high level 1, the first switching transistor M14 is turned on, so that the first current source subunit 104 is connected to the PAM4 output signal 21 and provides an output current for the PAM4 output signal 21, and when the encoded transmission signal 14 is at a logic low level 0, the first switching transistor M14 is turned off, so that the first current source subunit 104 cannot provide an output current for the PAM4 output signal 21.

[0072] As Figure 5 shown, according to an embodiment of the present disclosure, the second switching transistor M15 is connected in series with the second current source subunit 105, and the gate of the second switching transistor M15 receives the encoded transmission signal 15, the source of the second switching transistor M15 is connected to the PAM4 output signal 21, and the drain of the second switching transistor M15 is connected to the second current source subunit 105.

[0073] According to an embodiment of the present disclosure, when the encoded transmission signal 15 is at a logic high level 1, the second switching transistor M15 is turned on, so that the second current source subunit 105 is connected to the PAM4 output signal 21 and provides an output current for the PAM4 output signal 21, and when the encoded transmission signal 15 is at a logic low level 0, the second switching transistor M15 is turned off, so that the second current source subunit 105 cannot provide an output current for the PAM4 output signal 21.

[0074] As Figure 5 shown, according to an embodiment of the present disclosure, the third switching transistor M16 is connected in series with the third current source subunit 106, and the gate of the third switching transistor M16 receives the encoded transmission signal 16, the source of the third switching transistor M16 is connected to the PAM4 output signal 21, and the drain of the third switching transistor M16 is connected to the third current source subunit 106.

[0075] According to an embodiment of the present disclosure, when the encoded transmission signal 16 is at a logic high level 1, the third switching transistor M16 is turned on, such that the third current source sub-unit 106 is connected to the PAM4 output signal 21 and provides an output current for the PAM4 output signal 21, and when the encoded transmission signal 16 is at a logic low level 0, the third switching transistor M16 is turned off, such that the third current source sub-unit 106 cannot provide an output current for the PAM4 output signal 21.

[0076] As Figure 5 shown, according to an embodiment of the present disclosure, the first current source sub-unit 104 and the first switching transistor M14 connected in series, the second current source sub-unit 105 and the second switching transistor M15 connected in series, and the third current source sub-unit 106 and the third switching transistor M16 connected in series are connected in parallel between the power supply voltage VDD and the PAM4 output signal 21. Therefore, the first current source sub-unit 104, the second current source sub-unit 105, and the third current source sub-unit 106 together provide a current for the PAM4 output signal 21.

[0077] As Figure 5 shown, according to an embodiment of the present disclosure, the output sub-unit 103 further includes a termination resistor unit 107 for providing a termination resistor. According to an embodiment of the present disclosure, the typical resistance value of the termination resistor unit 107 can be, for example, 50 ohms.

[0078] Therefore, according to an embodiment of the present disclosure, the output level of the PAM4 output signal 21 is the product of the sum of the current values output by all the first to third current source sub-units 104 to 106 and the resistance value provided by the termination resistor unit 107.

[0079] Specifically, according to an embodiment of the present disclosure, when the transmit MSB signal 13 and the transmit LSB signal 12 are "00", the encoded transmission signal is "000", that is, signals 16, 15, and 14 are all at a logic low level 0. Therefore, the third switching transistor M16, the second switching transistor M15, and the first switching transistor M14 are all turned off, such that the third current source sub-unit 106, the second current source sub-unit 105, and the first current source sub-unit 104 do not provide a current for the PAM4 output signal 21, and thus the voltage value of the PAM4 output signal 21 is 0, that is, at level 0.

[0080] Similarly, according to an embodiment of the present disclosure, when the transmitted MSB signal 13 and the transmitted LSB signal 12 are "01", the encoded transmitted signal is "001", that is, the signal 16, the signal 15, and the signal 14 are respectively a logic low level 0, a logic low level 0, and a logic high level 1. Therefore, the third switching transistor M16 and the second switching transistor M15 are turned off and the first switching transistor M14 is turned on, so that only the first current source sub-unit 104 provides current for the PAM4 output signal 21. Thus, the voltage value of the PAM4 output signal 21 can be calculated as the product of the current value of the first current source sub-unit 104 and the resistance value of the terminal resistance unit 107, that is, level 1. Therefore, by adjusting the current value of the first current source sub-unit 104, the voltage value of the PAM4 output signal 21 can be adjusted, that is, the size of the eye height A of the PAM4 output signal 21 can be adjusted.

[0081] Therefore, according to an embodiment of the present disclosure, adjusting the first linearity configuration signal 41_1 can adjust the size of the eye height A by adjusting the current value of the first current source sub-unit 104, so that the linearity of the PAM4 output signal 21 can be adjusted.

[0082] Similarly, according to an embodiment of the present disclosure, when the transmitted MSB signal 13 and the transmitted LSB signal 12 are "10", the encoded transmitted signal is "011", that is, the signal 16, the signal 15, and the signal 14 are respectively a logic low level 0, a logic high level 1, and a logic high level 1. Therefore, the third switching transistor M16 is turned off and the second switching transistor M15 and the first switching transistor M14 are turned on, so that the second current source sub-unit 105 and the first current source sub-unit 104 provide current for the PAM4 output signal 21. Thus, the voltage value of the PAM4 output signal 21 can be calculated as the product of the sum of the current values of the second current source sub-unit 105 and the first current source sub-unit 104 and the resistance value of the terminal resistance unit 107, that is, level 2. Since the eye height B is the voltage amplitude difference between the level 2 of the PAM4 output signal 21 and the level 1 of the PAM4 output signal 21, adjusting the current value of the second current source sub-unit 105 can adjust the size of the eye height B.

[0083] Therefore, according to an embodiment of the present disclosure, adjusting the second linearity configuration signal 41_2 can adjust the size of the eye height B by adjusting the current value of the second current source sub-unit 105, so that the linearity of the PAM4 output signal 21 can be adjusted.

[0084] Similarly, according to an embodiment of the present disclosure, when the two bits of the transmitted MSB signal and the transmitted LSB signal are "11", the encoded transmitted signal is "111", that is, signal 16, signal 15, and signal 14 are all logic high level 1. Therefore, the third switching transistor M16, the second switching transistor M15, and the first switching transistor M14 are all turned on, enabling the third current source sub-unit 106, the second current source sub-unit 105, and the first current source sub-unit 104 to all provide current for the PAM4 output signal 21. Thus, the voltage value of the PAM4 output signal 21 can be calculated as the product of the sum of the current values of the third current source sub-unit 106, the second current source sub-unit 105, and the first current source sub-unit 104 and the resistance value of the terminal resistance unit 107, that is, level 3. Since the eye height C is the voltage difference between level 3 and level 2 of the PAM4 output signal, adjusting the current value of the third current source sub-unit 106 can adjust the magnitude of the eye height C.

[0085] Therefore, according to an embodiment of the present disclosure, adjusting the third linearity configuration signal 41_3 can adjust the magnitude of the eye height C by adjusting the current value of the third current source sub-unit 106, so that the linearity of the PAM4 output signal 21 can be adjusted.

[0086] In summary, according to an embodiment of the present disclosure, by adjusting at least one of the first linearity configuration signal 41_1, the second linearity configuration signal 41_2, and the third linearity configuration signal 41_3, the linearity of the PAM4 output signal 21 can be adjusted.

[0087] Although Figure 5 the PAM4 output signal 21 of the output sub-unit 105 shown is a single-ended signal, those skilled in the art should recognize that when the PAM4 output signal 21 is a differential signal, the above-described working principle can equally apply. Therefore, for the sake of brevity, it will not be elaborated here.

[0088] Figure 6 Fig. shows a schematic block diagram of a readback unit 200 according to an embodiment of the present disclosure.

[0089] As Figure 6 shown, according to an embodiment of the present disclosure, the readback unit 200 may include a parallelization sub-unit 201, a decoding sub-unit 202, and an input sub-unit 203.

[0090] As Figure 6 shown, according to an embodiment of the present disclosure, the input sub-unit 203 may receive the PAM4 output signal 21 and the threshold configuration signal 42 and output an encoded readback signal, including signal 26, signal 25, and signal 24.

[0091] Specifically, according to an embodiment of the present disclosure, when the PAM4 input signal 21 is at level 0, the input subunit 203 can output an encoded read-back signal "000", that is, signals 26, 25, and 24 are all at logic low level 0. When the PAM4 input signal 21 is at level 1, the input subunit 203 can output an encoded read-back signal "001", that is, signals 26, 25, and 24 are at logic low level 0, logic low level 0, and logic high level 1 respectively. When the PAM4 input signal 21 is at level 2, the input subunit 203 can output an encoded read-back signal "011", that is, signals 26, 25, and 24 are at logic low level 0, logic high level 1, and logic high level 1 respectively. And when the PAM4 input signal 21 is at level 3, the input subunit 203 can output an encoded read-back signal "111", that is, signals 26, 25, and 24 are all at logic high level 1.

[0092] According to an embodiment of the present disclosure, the input subunit 203 receives a threshold configuration signal 42. According to an embodiment of the present disclosure, by adjusting the threshold configuration signal 42, the encoded read-back signal output by the input subunit 203 can be changed, including at least one of signals 26, 25, and 24.

[0093] As Figure 6 shown, the decoding subunit 202 receives the encoded read-back signal, including 26, signal 25, and signal 24 and performs a decoding operation on it, and outputs a read-back MSB signal 23 and a read-back LSB signal 22.

[0094] According to an embodiment of the present disclosure, the decoding subunit 202 may perform the following decoding operations on the encoded readback signals, including signal 26, signal 25, and signal 24: When the decoding subunit 202 receives the encoded readback signal "000", that is, when signal 26, signal 25, and signal 24 are all logic low level 0, the decoding subunit 202 may output a readback MSB signal 23 and a readback LSB signal 22 that are both logic low level 0, that is, "00". When the decoding subunit 202 receives the encoded readback signal "001", that is, when signal 26, signal 25, and signal 24 are logic low level 0, logic low level 0, and logic high level 1 respectively, the decoding subunit 202 may output a readback MSB signal 23 of logic low level 0 and a readback LSB signal 22 of logic high level 1, that is, "01". When the decoding subunit 202 receives the encoded readback signal "011", that is, when signal 26, signal 25, and signal 24 are logic low level 0, logic high level 1, and logic high level 1 respectively, the decoding subunit 202 may output a readback MSB signal 23 of logic high level 1 and a readback LSB signal 22 of logic low level 0, that is, "10". And when the decoding subunit 202 receives the encoded readback signal "111", that is, when signal 26, signal 25, and signal 24 are all logic high level 1, the decoding subunit 202 may output a readback MSB signal 23 and a readback LSB signal 22 that are both logic high level 1, that is, "11".

[0095] As Figure 6 shown, according to an embodiment of the present disclosure, the parallelization subunit 201 may receive the readback MSB signal 23 and the readback LSB signal 22 and perform a parallelization operation to output a readback signal 31.

[0096] According to an embodiment of the present disclosure, the parallelization subunit 201 may perform, for example, a 1:10 parallelization operation on the readback MSB signal 23 and the readback LSB signal 22 to output a readback signal 31 as a 20-bit digital signal.

[0097] Figure 7 shows a schematic circuit diagram of the input subunit 203 and a schematic eye diagram of the PAM4 output signal 21 according to an embodiment of the present disclosure.

[0098] According to an embodiment of the present disclosure, the input subunit 203 may include a plurality of comparator subunits. As Figure 7 shown in (a) of, according to an embodiment of the present disclosure, the input subunit 203 may include a first comparator subunit 204, a second comparator subunit 205, and a third comparator subunit 206.

[0099] As Figure 7As shown in (a) of, according to an embodiment of the present disclosure, the positive input terminal of the first comparator subunit 204 receives the PAM4 output signal 21, the negative input terminal of the first comparator subunit 204 receives the first threshold signal 27, and the output of the first comparator subunit 204 is connected to the encoded read-back signal 24.

[0100] According to an embodiment of the present disclosure, when the voltage of the PAM4 output signal 21 is greater than or equal to the voltage of the first threshold signal 27, the encoded read-back signal 24 output by the first comparator subunit 204 can be a logic high level 1, and when the voltage of the PAM4 output signal 21 is less than the voltage of the first threshold signal 27, the encoded read-back signal 24 output by the first comparator subunit 204 can be a logic low level 0.

[0101] As Figure 7 As shown in (a) of, according to an embodiment of the present disclosure, the positive input terminal of the second comparator subunit 205 receives the PAM4 output signal 21, the negative input terminal of the second comparator subunit 205 receives the second threshold signal 28, and the output of the second comparator subunit 205 is connected to the encoded read-back signal 25.

[0102] Similarly, according to an embodiment of the present disclosure, when the voltage of the PAM4 output signal 21 is greater than or equal to the voltage of the second threshold signal 28, the encoded read-back signal 25 output by the second comparator subunit 205 can be a logic high level 1, and when the voltage of the PAM4 output signal 21 is less than the voltage of the second threshold signal 28, the encoded read-back signal 25 output by the second comparator subunit 205 can be a logic low level 0.

[0103] As Figure 7 As shown in (a) of, according to an embodiment of the present disclosure, the positive input terminal of the third comparator subunit 206 receives the PAM4 output signal 21, the negative input terminal of the third comparator subunit 206 receives the third threshold signal 29, and the output of the third comparator subunit 204 is connected to the encoded read-back signal 26.

[0104] Similarly, according to an embodiment of the present disclosure, when the voltage of the PAM4 output signal 21 is greater than or equal to the voltage of the third threshold signal 29, the encoded read-back signal 26 output by the third comparator subunit 206 can be a logic high level 1, and when the voltage of the PAM4 output signal 21 is less than the voltage of the third threshold signal 29, the encoded read-back signal 26 output by the third comparator subunit 206 can be a logic low level 0.

[0105] In Figure 7In the schematic eye diagram of the PAM4 output signal 21 shown in (b) thereof, the voltage of the PAM4 output signal 21 can be level 0, level 1, level 2, or level 3. According to an embodiment of the present disclosure, the threshold voltage 1 can be set between level 0 and level 1, the threshold voltage 2 can be set between level 1 and level 2, and the threshold voltage 3 can be set between level 2 and level 3.

[0106] According to an embodiment of the present disclosure, the threshold voltage 1, the threshold voltage 2, and the threshold voltage 3 can be used as voltage determination conditions for the PAM4 output signal 21.

[0107] Specifically, according to an embodiment of the present disclosure, when the PAM4 output signal 21 is less than the threshold voltage 1, the PAM4 output signal 21 can be level 0. When the PAM4 output signal 21 is less than the threshold voltage 2 and greater than or equal to the threshold voltage 1, the PAM4 output signal 21 can be level 1. When the PAM4 output signal 21 is less than the threshold voltage 3 and greater than or equal to the threshold voltage 2, the PAM4 output signal 21 can be level 2. And when the PAM4 output signal 21 is greater than or equal to the threshold voltage 3, the PAM4 output signal 21 can be level 3.

[0108] According to an embodiment of the present disclosure, the voltage of the first threshold signal 27 can be set to the threshold voltage 1, the voltage of the second threshold signal 28 can be set to the threshold voltage 2, and the voltage of the third threshold signal 29 can be set to the threshold voltage 3.

[0109] Correspondingly, according to an embodiment of the present disclosure, when the PAM4 output signal 21 is less than the voltage of the first threshold signal 27, the PAM4 output signal 21 is level 0. Therefore, the encoded readback signal is "000", that is, the signals 26, 25, and 24 are all logic low level 0. When the PAM4 output signal 21 is less than the voltage of the second threshold signal 28 and greater than or equal to the voltage of the first threshold signal 27, the PAM4 output signal 21 is level 1. Therefore, the encoded readback signal is "001", that is, the signals 26, 25, and 24 are respectively logic low level 0, logic low level 0, and logic high level 1. When the PAM4 output signal 21 is less than the voltage of the third threshold signal 29 and greater than or equal to the voltage of the second threshold signal 28, the PAM4 output signal 21 is level 2. Therefore, the encoded readback signal is "011", that is, the signals 26, 25, and 24 are respectively logic low level 0, logic high level 1, and logic high level 1. And when the PAM4 output signal 21 is greater than or equal to the voltage of the third threshold signal 29, the PAM4 output signal 21 is level 3. Therefore, the encoded readback signal is "111", that is, the signals 26, 25, and 24 are all logic high level 1.

[0110] Thus, according to an embodiment of the present disclosure, by changing at least one of the voltage values of the first threshold signal 27, the voltage value of the second threshold signal 28, and the voltage value of the third threshold signal 29, the result of the encoded read-back signal of the PAM4 output signal 21 can be changed.

[0111] According to an embodiment of the present disclosure, the threshold configuration signal 42 output by the control unit 400 may be a plurality of analog signals, respectively serving as the first threshold signal 27, the second threshold signal 28, and the third threshold signal 29.

[0112] According to an embodiment of the present disclosure, the threshold configuration signal 42 output by the control unit 400 may be a digital signal, and the first threshold signal 27, the second threshold signal 28, and the third threshold signal 29 are respectively generated through digital-to-analog conversion.

[0113] As Figure 7 shown in (a) of , according to an embodiment of the present disclosure, the first threshold configuration signal 42_1 output by the control unit 400 is a digital signal. Correspondingly, the first digital-to-analog conversion unit 207 receives the first threshold configuration signal 42_1 and performs digital-to-analog conversion on it to output the first threshold signal 27.

[0114] As Figure 7 shown in (a) of , according to an embodiment of the present disclosure, the second threshold configuration signal 42_2 output by the control unit 400 is a digital signal. Correspondingly, the second digital-to-analog conversion unit 208 receives the second threshold configuration signal 42_2 and performs digital-to-analog conversion on it to output the second threshold signal 28.

[0115] As Figure 7 shown in (a) of , according to an embodiment of the present disclosure, the third threshold configuration signal 42_3 output by the control unit 400 is a digital signal. Correspondingly, the third digital-to-analog conversion unit 209 receives the third threshold configuration signal 42_3 and performs digital-to-analog conversion on it to output the third threshold signal 29.

[0116] Figure 8 shows a schematic flowchart of a linearity adjustment method 800 of the PAM4 transmission device 10 according to an embodiment of the present disclosure. As described above with reference to Figures 3 to 7 the above, the PAM4 transmission device 10 may include a transmission unit 100, a read-back unit 200, a comparison unit 300, and a control unit 400. According to an embodiment of the present disclosure, the linearity adjustment method 800 of the PAM4 transmission device 10 may include the following steps.

[0117] Step S801: The control unit 400 outputs a linearity configuration signal 41, and the transmission unit 100 adjusts the linearity of the PAM4 output signal 21 according to the linearity configuration signal 41.

[0118] As described above with reference to Figures 3 to 7 As described above, according to an embodiment of the present disclosure, the control unit 400 outputs a linearity configuration signal 41 to the transmission unit 100, and the transmission unit 100 receives a transmission signal 11 and adjusts the linearity of the PAM4 output signal 21 according to the received linearity configuration signal 41.

[0119] Specifically, as described above with reference to Figures 3 to 7 As described above, according to an embodiment of the present disclosure, the control unit 400 may output a first linearity configuration signal 41_1 to the first current source sub-unit 104, and the first current source sub-unit 104 may adjust its output current according to the received first linearity configuration signal 41_1 to adjust the linearity of the PAM4 output signal 21. Similarly, as described above with reference to Figures 3 to 7 As described above, according to an embodiment of the present disclosure, the control unit 400 may output a second linearity configuration signal 41_2 to the second current source sub-unit 105, and the second current source sub-unit 105 may adjust its output current according to the received second linearity configuration signal 41_2 to adjust the linearity of the PAM4 output signal 21. Similarly, as described above with reference to Figures 3 to 7 As described above, according to an embodiment of the present disclosure, the control unit 400 may output a third linearity configuration signal 41_3 to the third current source sub-unit 106, and the third current source sub-unit 106 may adjust its output current according to the received third linearity configuration signal 41_3 to adjust the linearity of the PAM4 output signal 21.

[0120] Step S802: The control unit 400 outputs a threshold configuration signal 42, the read-back unit 200 outputs a read-back signal 31 according to the received threshold configuration signal 42, the comparison unit 300 compares the transmission signal 11 and the read-back signal 31 and outputs a comparison result 32 to the control unit 400, and the control unit 400 records the current threshold configuration signal 42 and the corresponding comparison result.

[0121] As described above with reference to Figures 3 to 7 As described above, according to an embodiment of the present disclosure, the control unit 400 may output a threshold configuration signal 42, and the read-back unit 200 may receive the PAM4 output signal 21 and output a read-back signal 31 according to the received threshold configuration signal 42. As described above with reference to Figures 3 to 7 As described above, according to an embodiment of the present disclosure, the comparison unit 300 may compare the transmission signal 11 and the read-back signal 31 and output a comparison result 32 to the control unit 400. According to an embodiment of the present disclosure, the control unit 400 may record the current threshold configuration signal 42 and the corresponding comparison result 32.

[0122] Specifically, as described above with reference to Figures 3 to 7As described above, according to an embodiment of the present disclosure, the control unit 400 may output a first threshold configuration signal 42_1, a second threshold configuration signal 42_2, and a third threshold configuration signal 42_3 to generate a first threshold signal 27, a second threshold signal 28, and a third threshold signal 29, respectively. As described above with reference to Figures 3 to 7 As described above, according to an embodiment of the present disclosure, the readback unit 200 may output a readback signal 31 according to the voltage values of the first to third threshold signals 27 to 29.

[0123] As described above with reference to Figures 3 to 7 As described above, according to an embodiment of the present disclosure, the comparison unit 300 may receive the readback signal 31 to compare the transmission signal 11 and the readback signal 31, and output a comparison result 32 to the control unit 400. According to an embodiment of the present disclosure, the control unit 400 may record the current threshold configuration signal 42, including the first threshold configuration signal 42_1, the second threshold configuration signal 42_2, and the third threshold configuration signal 42_3, and the corresponding comparison result 32.

[0124] Step S803: Repeat step S802 multiple times, and the control unit 400 records a series of threshold configuration signals 42 and corresponding series of comparison results 32.

[0125] According to an embodiment of the present disclosure, the control unit 400 may change the threshold configuration signal 42 input to the readback unit 200. The readback unit 200 may output a readback signal 31 according to the received threshold configuration signal 42. The comparison unit 300 may output a comparison result 32 of the transmission signal 11 and the readback signal 31, and the control unit 400 may record the current threshold configuration signal 42 and the corresponding comparison result 32.

[0126] According to an embodiment of the present disclosure, whenever the control unit 400 changes the threshold configuration signal 42, the current threshold configuration signal 42 and the corresponding comparison result 32 are recorded. According to an embodiment of the present disclosure, the control unit 400 may repeat the above steps multiple times, that is, a series of threshold configuration signals 42 and corresponding series of comparison results 32 may be recorded.

[0127] According to an embodiment of the present disclosure, by adjusting the threshold configuration signal 42, the threshold voltages 1 to 3 in the eye diagram shown in (b) of Figure 7 can be adjusted so that the readback signal 31 output by the readback unit 200 changes to determine the eye height of the PAM4 output signal 21.

[0128] Specifically, according to an embodiment of the present disclosure, by adjusting the first threshold configuration signal 42_1, the voltage value of the first threshold signal 27, i.e., the threshold voltage 1, can be changed. By repeatedly adjusting the first threshold configuration signal 42_1, according to the corresponding comparison result 32, the control unit 400 can determine the size of the eye height A of the PAM4 output signal 21.

[0129] Similarly, according to an embodiment of the present disclosure, by adjusting the second threshold configuration signal 42_2, the voltage value of the second threshold signal 28, i.e., the threshold voltage 2, can be changed. By repeatedly adjusting the second threshold configuration signal 42_2, according to the corresponding comparison result 32, the control unit 400 can determine the size of the eye height B of the PAM4 output signal 21.

[0130] Similarly, according to an embodiment of the present disclosure, by adjusting the third threshold configuration signal 42_3, the voltage value of the third threshold signal 29, i.e., the threshold voltage 3, can be changed. By repeatedly adjusting the third threshold configuration signal 42_3, according to the corresponding comparison result 32, the control unit 400 can determine the size of the eye height C of the PAM4 output signal 21.

[0131] Step S804: The control unit 400 calculates the linearity of the PAM4 output signal 21. When the linearity does not meet the target value, the control unit 400 adjusts the linearity configuration signal 42 so that the linearity of the PAM4 output signal 21 approaches the target value.

[0132] Specifically, according to an embodiment of the present disclosure, the control unit 400 can determine the sizes of the eye height A, eye height B, and eye height C of the PAM4 output signal 21 based on a series of threshold configuration signals 42 and the corresponding series of comparison results 32 recorded in step S803.

[0133] According to an embodiment of the present disclosure, the control unit 400 can use the sizes of the eye height A, eye height B, and eye height C to calculate the linearity of the PAM4 output signal 21 according to the linearity calculation formula RLM = 3×min(A, B, C) / sum(A, B, C).

[0134] According to an embodiment of the present disclosure, the target value of the linearity can be preset. If the currently calculated linearity does not reach the linearity target value, the control unit 400 can adjust the linearity configuration signal 41 to adjust the linearity of the PAM4 output signal 21 output by the transmitting unit 100 so that the linearity of the PAM4 output signal 21 is closer to the target value.

[0135] Specifically, as described above with reference to Figures 3 to 7As described above, according to an embodiment of the present disclosure, when the eye height A is small, the control unit 400 can adjust the first linearity configuration signal 41_1 so that the output current of the first current source sub-unit 104 is larger, making the eye height A of the PAM4 output signal 21 larger, thereby improving the linearity of the PAM4 output signal 21.

[0136] Similarly, as referred to above Figures 3 to 7 As described above, according to an embodiment of the present disclosure, when the eye height C is large, the control unit 400 can adjust the third linearity configuration signal 41_3 so that the output current of the third current source sub-unit 106 is smaller, making the eye height C of the PAM4 output signal 21 smaller, thereby improving the linearity of the PAM4 output signal 21.

[0137] Step S805: Repeat steps S801 to S804 until the linearity of the PAM4 output signal 21 meets the target value.

[0138] According to an embodiment of the present disclosure, the control unit 400 can repeat steps S801 to S804 until the linearity of the PAM4 output signal 21 reaches a pre-set linearity target value.

[0139] According to an embodiment of the present disclosure, the PAM4 transmitter 10 can perform the linearity adjustment method 800 of the PAM4 transmitter once after power-on or during operation. According to an embodiment of the present disclosure, after the linearity of the PAM4 output signal 21 reaches the linearity target value, the feedback unit 200 and the comparison unit 300 can be turned off, thereby reducing the overall power consumption of the PAM4 transmitter 10.

[0140] According to an embodiment of the present disclosure, a time period can be pre-set for the PAM4 transmitter 10. According to this time period, the PAM4 transmitter 10 can periodically activate the feedback unit 200 and the comparison unit 300 and perform the linearity adjustment method 800 of the PAM4 transmitter 10. When the feedback unit 200 and the comparison unit 300 are not working, the feedback unit 200 and the comparison unit 300 are turned off to achieve the purpose of power saving. Therefore, the PAM4 transmitter 10 can continuously adjust the linearity of the PAM4 output signal 21 to reach the linearity target value according to the pre-set time period, thereby reducing the influence of changes in the external environment and temperature on the linearity of the PAM4 output signal 21.

[0141] According to the PAM4 transmitter and its linearity adjustment method of the present disclosure, regardless of how the environment and temperature change, the linearity of the PAM4 output signal can be adjusted in real time while outputting the PAM4 output signal, meeting the requirements for the linearity of the PAM4 output signal.

[0142] For illustrative purposes, a limited number of possible embodiments of the present disclosure have been presented above. Although the present disclosure has been described with reference to embodiments of the present disclosure, those skilled in the art will understand that various modifications and changes can be made to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure as disclosed in the appended claims.

[0143] Although the present disclosure contains many details, these details should not be construed as limitations on the present disclosure or on the scope that may be claimed, but rather as descriptions of features that may be specific to particular embodiments. Certain features described herein in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented separately in multiple embodiments or in any suitable sub-combination. In addition, although features may have been described above as acting in certain combinations and even initially so claimed, in some cases, one or more features in a claimed combination may be excluded from the combination, and the claimed combination may cover a sub-combination or a variation of a sub-combination.

Claims

1. A PAM4 transmitting device, comprising: A transmitting unit configured to receive a transmit signal and a linearity configuration signal, and output a PAM4 output signal; a readback unit configured to receive the PAM4 output signal and a threshold configuration signal, and output a readback signal; a comparison unit configured to receive the transmission signal and the readback signal, and compare the transmission signal and the readback signal to output a comparison result; as well as The control unit is configured to receive the comparison result and output the linearity configuration signal and the threshold configuration signal according to the comparison result.

2. The PAM4 transmitting device according to claim 1, wherein: The sending unit is configured to adjust the linearity of the PAM4 output signal according to the linearity configuration signal.

3. The PAM4 transmitting device according to claim 2, wherein: The transmitting unit includes one or more current source subunits, and The linearity configuration signal adjusts the linearity of the PAM4 output signal by adjusting the current value of the current source subunit.

4. The PAM4 transmitting device according to claim 1, wherein: The readback unit is configured to change the readback signal according to the threshold configuration signal.

5. The PAM4 transmitting device according to claim 4, wherein: The readback unit includes one or more comparator subunits, and The threshold configuration signal changes the readback signal by adjusting the threshold voltage of the comparator subunit.

6. The PAM4 transmitting device according to claim 1, wherein: The sending unit comprises: A serialization subunit, configured to receive the transmission signal and perform a serialization operation thereon, and output a transmission MSB signal and a transmission LSB signal; an encoding subunit configured to receive the transmit MSB signal and the transmit LSB signal and perform encoding operations thereon, and output an encoded transmit signal; and The output subunit is configured to receive the encoded transmit signal and the linearity configuration signal, and output the PAM4 output signal.

7. The PAM4 transmitting device according to claim 1, wherein: The readback unit comprises: An input subunit, configured to receive the PAM4 transmit signal and the threshold configuration signal, and output a coded readback signal; A decoding subunit, configured to receive the encoded readback signal and perform a decoding operation thereon, and output a readback MSB signal and a readback LSB signal; The parallelization subunit is configured to receive the readback MSB signal and the readback LSB signal, perform a parallelization operation thereon, and output the readback signal.

8. The PAM4 transmitting device according to claim 1, wherein: The PAM4 output signal is a single-ended output signal or a differential output signal.

9. The PAM4 transmitting device according to claim 1, wherein: The comparison unit is configured to output the comparison result indicating whether the transmission signal and the readback signal are identical.

10. The PAM4 transmitting device according to claim 1, wherein: The control unit is configured to record a series of threshold configuration signals and corresponding comparison results.

11. A linearity adjustment method for a PAM4 transmitting device according to any one of claims 1 to 10, comprising: Step 1: the control unit outputs the linearity configuration signal, and the sending unit adjusts the linearity of the PAM4 output signal according to the linearity configuration signal; Step 2: the control unit outputs the threshold configuration signal, the readback unit outputs the readback signal according to the threshold configuration signal, the comparison unit compares the transmission signal with the readback signal and outputs the comparison result to the control unit, and the control unit records the current threshold configuration signal and the corresponding comparison result; Step 3: Repeat the second step multiple times, and the control unit records a series of threshold configuration signals and a corresponding series of comparison results; Step 4: the control unit calculates the linearity of the PAM4 output signal, and when the linearity does not meet the target value, the control unit adjusts the linearity configuration signal; as well as Step 5: Repeat the first step to the fourth step until the linearity of the PAM4 output signal meets the target value.

12. The linearity adjustment method according to claim 11, wherein: The PAM4 transmitting device executes the linearity adjustment method once, and then turns off the readback unit and the comparison unit.

13. The linearity adjustment method according to claim 11, wherein: The PAM4 transmitting device periodically starts the readback unit and the comparison unit according to a time period to execute the linearity adjustment method.

14. The linearity adjustment method according to claim 11, wherein: The PAM4 output signal is a single-ended output signal or a differential output signal.

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