Apparatus, system and method for protected sensor data communication

Abstract

The invention relates to an apparatus, system and method for protected sensor data communication. The invention provides a network communication device (100) having: a signal input adapted to receive a signal derived from a sensor; an analog-to-digital converter, ADC, (118) having an input coupled to the signal input, and an output; a data scrambling circuit (120) having an input coupled to the output of the ADC, and an output; a watermark insertion circuit (122) having an input coupled to the output of the data scrambling circuit, and an output; and a signal output coupled to the output of the watermark insertion circuit.

Description

Technical Field

[0001] The described examples involve communication of sensor data. Background Art

[0002] In various applications, sensors are used to sense corresponding parameters, and values ​​associated with the sensed parameters can be communicated by a communication device that includes the sensor or communicates with the sensor. In some examples, the communication device includes an analog / digital converter (ADC) that converts analog outputs from the sensor into corresponding digital values ​​so that the sensor values ​​can be periodically converted by the ADC to provide a sequence of digital values ​​representing the sensed parameters. The communication device may also include a transmitter (or transceiver) circuit system and / or functionality to communicate the ADC values ​​to a remote location (e.g., wirelessly to a local or remote network). Such systems can be implemented in various forms, such as in Internet of Things (IoT) technology. IoT or other sensing / communication devices can be used in numerous sensing applications, such as in industrial environments, and a large number of sensors as part of or in combination with corresponding communication devices can be distributed to sense and communicate data about the environment.

[0003] Specific industries and applications for communication devices as described above illustrate an increased need to protect the value of sensed data. For example, while personal electronics may have lesser degrees of security issues, industrial sensing may contain highly private, confidential, or sensitive information. While such data requires restriction, it may also have considerable information and / or business value, for example, in applications involving machine learning and artificial intelligence. These values ​​can often be achieved by communicating the data to a remote network (e.g., to a cloud or the global Internet), from which other applications with access to the remote network can process the data. In addition, the processing may result in return control of the communication device that senses such data or other considerations regarding the industrial environment in which the sensor is located. In all cases, there is a trade-off between communicating such data and preventing it from being accessed in an unauthorized manner.

[0004] Examples are provided herein that may improve upon various of the above considerations as well as other concepts, as further detailed below. Summary of the invention

[0005] In one example, there is a network communication device comprising: a signal input adapted to receive a sensor-derived signal; an analog-to-digital converter (ADC) having an input coupled to the signal input, and an output; a data scrambling circuit having an input coupled to the output of the ADC, and an output; a watermark insertion circuit having an input coupled to the output of the data scrambling circuit, and an output; and a signal output coupled to the output of the watermark insertion circuit.

[0006] Other aspects are also disclosed and claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is an electrical block diagram of the communication device 100 .

[0008] Figure 2 For Figure 1 An electrical diagram of a communication device 200 of an example implementation of the communication device 100 .

[0009] Figure 3 for Figure 2 A partial diagram of scrambler configurator circuit 202 .

[0010] Figure 4 for Figure 2 The watermark insertion engine circuit 122 and a local map for inserting watermark information into a data stream.

[0011] Figure 5 For use Figure 1 An electrical diagram of another example implementation 500 of the communication device 100 .

[0012] Figure 6 The sequence of 16 bits B1 to B16 forming a single digital data block DBx is illustrated as a sequence from Figure 1 The output of ADC 118 is provided to a scrambler circuit 120 .

[0013] Figure 7 For use Figure 1 An electrical diagram of another example implementation 700 of the communication device 100 .

[0014] Figure 8 A sequence of N data blocks DB1 to DBN is illustrated, wherein selective scrambling is applied to selected ones of the data blocks. DETAILED DESCRIPTION

[0015] Figure 1 1 is an electrical block diagram of the communication device 100. The communication device 100 may be implemented as part of a variety of device applications, for example with particular advantage in commercial or industrial applications where sensor devices are prolific and there is an increased sensitivity to protecting data when the data is communicated remotely. The communication device 100 may be powered by a battery or a continuous or switched (e.g., line) power source. The communication device 100 is a network communication device and, as such, communicates with a network 102. A receive processor 104 is also coupled to the network 102 such that the receive processor 104 can receive and process information from the communication device 100 via the network 102. Bidirectionally, the receive processor 104 can also communicate back to the communication device 100 via the network 102.

[0016] The communication device 100 includes one or more circuits that may be separated or provided as one or more integrated circuits (ICs). The IC will be described and divided into three circuit domains for the purpose of introduction: (i) data sensing domain 106; (ii) digital data generation domain 108; and (iii) data transmission domain 110. The various blocks in the three circuit domains may be implemented by circuits having separable or overlapping boundaries, and may be implemented in part by sequential / processing / execution circuit systems, such as logic circuit systems, controllers, processors, etc. Such circuit systems may also include or access programming code that can be accessed from a readable memory, wherein access and execution of such programming code may implement some of the functions described herein. The data sensing domain 106 has an output connected to an input of the digital data generation domain 108. The digital data generation domain 108 has an output connected to an input of the data transmission domain 110. In general, the data sensing domain 106 senses data, such as that applicable to the functions of the communication device 100. The data sensing domain 106 outputs the sensed data to the digital data generation domain 108. The digital data generation domain 108 converts the sensed data into digital values ​​that are each communicated as data blocks, and it also performs additional data protection, for example, by scrambling the data within the data blocks (which may be selective for some blocks or applicable to all blocks) and by inserting watermarks into selected locations along the stream of data blocks. The digital data generation domain 108 also optionally reports data protection information about the scrambling or watermarking to the data transmission domain 110. The data transmission domain 110 wirelessly transmits the scrambled and watermarked data and the optional data protection information to the network 102 as long as the network 102 is within range of the communication device 100. Thereafter, the receive processor 104 may process the protected data by accessing the protected data from the network 102.

[0017] The data sensing domain 106 includes a sensor 112, a sample and hold circuit 114, and a sampling trigger logic circuit 116. The output of the sensor 112 is connected to the data input of the sample and hold circuit 114. The output of the sampling trigger logic circuit 116 is connected to the enable input of the sample and hold circuit 114. One or more trigger signals are provided to the input of the sampling trigger logic circuit 116. The sensor 112 includes a circuit system for sensing one or more attributes, for example, where the attribute is present and close to or within a configuration that includes the communication device 100. Examples of such attributes may include pressure, acoustics, temperature, or other attributes. The sensor 112 also generates an analog signal corresponding to or representing the sensed attribute. The analog signal is provided to the input of the sample and hold circuit 114, which, when instructed by the sampling trigger logic circuit 116, samples the analog signal from the sensor 112 and maintains the analog signal at a nearly constant voltage (and / or current) during the analog / digital conversion. Specifically, the one or more trigger signals may be provided by software or hardware or both. In response to asserting one or more of these trigger signals, the sampling trigger logic circuit 116 outputs an enable signal to the sample and hold circuit 114 enable input, and the sample and hold circuit 114 responds by sampling and holding the value (e.g., voltage) of the analog signal from the sensor 112 for a predetermined duration. Thus, if the analog output from the sensor 112 changes during a predetermined period, the output of the sample and hold circuit 114 remains unchanged.

[0018] The digital data generation domain 108 includes a data path having an ADC 118, a scrambler circuit 120, and a watermark insertion engine circuit 122. The input of the ADC 118 is connected to receive a sensor-derived (e.g., sampled) signal, herein received from the output of the data sensing domain 106. The ADC 118 operates (cycles) by a conversion clock signal. The data output of the ADC 118 is connected to the input of the scrambler circuit 120. The data output of the scrambler circuit 120 is connected to the input of the watermark insertion engine circuit 122. The output of the watermark insertion engine circuit 122 provides the output of the digital data generation domain 108.

[0019] The digital data generation domain 108 also includes various control circuit systems. The scrambler configurator circuit 124 has an output coupled to a control input of the scrambler circuit 120. The watermark configurator circuit 126 is bidirectionally coupled to a control port of the watermark insertion engine circuit 122. The various control circuit systems are appropriately synchronized for controlling the circuit systems within the digital data generation domain 108. For example, the SAMPLE_READY output can be connected from the ADC 118 to the enable input of the scrambler configurator circuit 124 to facilitate proper timing of the scrambler configurator circuit 124 and the scrambler circuit 120 when the ADC 118 provides each digital value output. As also described in detail below, the scrambler configurator circuit 124 receives a control signal input CTRL_S, and the watermark configurator circuit 126 receives a control signal input CTRL_W, where each control signal is used to provide a respective control, which in some cases may be user-configurable, to configure and / or select an alternative manner of scrambling data and inserting a watermark into a data stream that includes sensed data values ​​from the ADC 118. In addition, each of the scrambler configurator circuit 124 and the watermark configurator circuit 126 may include sufficient circuitry to implement the user selection, for example, as a programmable control register, a selection table, etc. Finally, the digital data generation domain 108 includes a data protection reporter circuit 128. A first input of the data protection reporter circuit 128 is coupled to receive the scrambling identification information S_ID from the scrambler configurator circuit 124, and a second input of the data protection reporter circuit 128 is coupled to receive the watermark identification information W_ID from the watermark configurator circuit 126. An output of the data protection reporter circuit 128 is connected to the data transmission domain 110.

[0020] The general operation of the digital data generation domain 108 is now described, with additional details provided later in conjunction with various alternative implementation examples. The ADC 118 samples the analog signal from the data sensing domain 106 synchronously and at a frequency set by the conversion clock, and in response outputs a corresponding digital data block of N bits (e.g., N=16) proportional to the voltage at the input of the ADC 118. Under the control of the scrambler configurator circuit 124, the N-bit data block continues along the data path from the ADC 118 to the scrambler circuit 120, where the data block may be scrambled. Thereafter, the data block, which may be scrambled, is output from the scrambler circuit 120 to the watermark insertion engine circuit 122. The watermark insertion engine circuit 122 is operable to insert a watermark into the data stream, or in some examples, insert one of a variety of different types of watermarks into the data stream containing the data block received from the scrambler circuit 120. In addition, options associated with the watermark insertion engine circuit 122 are provided under the control of the watermark configurator circuit 126.

[0021] The additional operation of the scrambler circuit 120 is now described. Whenever a digital sample value is ready from ADC 118, ADC 118 asserts the coupled SAMPLE_READY to the scrambler configurator circuit 124. The scrambler configurator circuit 124 then controls the scrambler circuit 120 to apply the scrambling technique when needed. As further described below, in one example, scrambling is applied to each M-bit data block, and in different examples, scrambling can be selectively applied, that is, scrambling is only applied to some M-bit data blocks, for example, depending on the value represented by the data block. Therefore, when scrambling is needed, the scrambler configurator circuit 124 outputs appropriate control to indicate that there are data blocks to be scrambled and also indicates the scrambling mode, and examples are provided below. On the contrary, when scrambling is not enabled, the scrambler circuit 120 can be prohibited from sampling the data block, for example, to save power. Additionally, in some examples, when scrambling data, the scrambler configurator circuit 124 provides identifying information, e.g., as a map, table, flag, or other indication from the ADC 118 of which data units are scrambled and how the scrambling is applied, wherein the information is provided in the Figure 1 The S_ID signal is provided to a data protection reporter circuit 128, which is coupled to provide this information to the transmission domain 110 at the appropriate time and in the appropriate form, so the S_ID may also be communicated to the network 102 and the receive processor 104. When the receive processor 104 receives the S_ID, it is thereby informed which data it receives from the communication device 100 is scrambled and how the scrambling is applied, and in response, the receive processor 104 may then appropriately descramble only those scrambled data blocks, while processing the remaining blocks received from the communication device 100 as unscrambled data.

[0022] Additional operation of the watermark engine circuit 122 is now described. Whenever the watermark insertion engine circuit 122 receives a data block from the scrambler circuit 120, the watermark configurator circuit 126 is informed of the data block reception event (e.g., via a bidirectional coupling between the two circuits). In response, the watermark configurator circuit 126 controls the watermark insertion engine circuit 122 to insert watermark information, which may be one or more bits inserted at various locations between specific ones of the received data blocks. The insertion locations from the watermark configurator circuit 126 may be user configurable, e.g., via CTRL_W configuration. Additionally, in some examples, the watermark configurator circuit 126 provides identification information, e.g., as a map, table, flag, or other indication of the location of the watermark information among the data blocks received by the watermark insertion engine circuit 122 from the scrambler circuit 120, wherein the information is provided in Figure 1The W_ID signal is provided to a data protection reporter circuit 128, which is coupled to provide this information to the transmission domain 110, so that the W_ID can also be communicated to the network 102 and the receiving processor 104. When the receiving processor 104 receives the W_ID, it is thereby informed of the location of the watermark information among the data it receives from the communication device 100, and in response, the receiving processor 104 can then appropriately determine whether the watermark information corresponds to expectations, such as whether the information matches the expected watermark of the recipient associated with the receiving processor 104.

[0023] The data transmission domain 110 includes a sample first-in-first-out (FIFO) circuit 130, a central processing unit (CPU) / direct memory access (DMA) circuit 132, and a transmitter 134. The input of the sample FIFO circuit 130 is connected to the output of the watermark insertion engine circuit 122. The output of the sample FIFO 130 is connected to the input of the CPU / DMA circuit 132. The output of the CPU / DMA circuit 132 is connected to the input of the transmitter 134. The output of the transmitter 134 is intended to indicate wireless transmission of the data, for example, to an appropriate radio frequency / antenna or other suitable interface for wireless communication.

[0024] The operation of the data transmission domain 110 is now described. As blocks of digital data, scrambled or unscrambled and interspersed with watermarks, are output by the watermark insertion engine circuit 122, those samples and watermark information are stored in the sample FIFO 130. The CPU / DMA circuit 132 represents one or more alternatives for retrieving data from a memory storage area, in this case the sample FIFO 130, and forwarding the retrieved data for transmission. In the illustrated example, the retrieved and forwarded data is provided to a transmitter 134, which transmits such data wirelessly to the network 102. Thus, the transmitter 134 provides a data gateway to the network 102 within range of the transmitter, for example using a WiFi implementation or other wireless protocol. Once the data arrives at the network 102, it may be processed by the appropriate device(s) that accesses the network 102 directly or through other intermediate paths or nodes to include the receiving processor 104.

[0025] Figure 2 For Figure 1 An electrical diagram of a communication device 200 of an example implementation of the communication device 100. Figure 2 In the following diagrams, use Figure 1 Common reference numerals are used to describe identical or comparable circuit blocks. Therefore, the following discussion focuses primarily on cases where specific blocks are modified or explained with respect to specific implementation details.

[0026] exist Figure 2In the digital data generation field 108, replace the corresponding Figure 1 1 and 2. The scrambler configurator circuit 124 and the watermark configurator circuit 126 of FIG. 1 show a scrambler configurator circuit 202 and a watermark configurator circuit 204. The scrambler configurator circuit 202 includes a lookup table (LUT) 206, which is optionally configurable by a user in accordance with CTRL_S. The output of the LUT 206 is connected to the scrambler circuit 120. The watermark configurator circuit 204 includes a comparator 208, a counter 210, a threshold storage circuit 212 for storing a threshold value THR1, and a watermark storage circuit 214 for storing a watermark WM. Each of THR1 (stored in the threshold storage circuit 212) and WM (stored in the watermark storage circuit 214) may be provided internally, or alternatively, may be configurable by a user, for example, via CTRL_W. THR1 is connected to a first input of the comparator 208. The output of the counter 210 is connected to a second input of the comparator 208. The output of the comparator 208 is connected to the enable (or trigger) input of the watermark insertion engine circuit 122, and is also connected to the clear input of the counter 210. The input of the counter 210 is connected to the watermark insertion engine circuit 122 for the purpose of incrementing the count in the counter 210. As described in detail below, the counter 210 counts the number of data blocks received by the watermark insertion engine circuit 122, and the watermark configurator circuit 204 can control the watermark insertion engine circuit 122 to selectively insert watermark information whenever the count reaches THR1.

[0027] Figure 3 for Figure 2 A partial diagram of the scrambler configurator circuit 202 is combined with example data values ​​to illustrate the operation of the scrambler configurator circuit 202. Figure 3 The bottom horizontal line shows a single digital data block DBx, which is obtained from Figure 1 ADC 118 output and provided to scrambler circuit 120. In the illustrated example, DBx has 16 bits, each bit is shown with an indicator Bz, where the reference z indicates the bit of its corresponding illustrated bit position. For example, bit B1 is at bit position 1, bit B2 is at bit position B2, and so on, up to bit B16 at bit position 16. Figure 3 Further illustrating, LUT 206 stores a data transposed coordinate pair, shown as (A:B). The values ​​of a and b are stored in LUT 206 and output to scrambler circuit 120 in order to control / indicate the data at the corresponding bit positions to be transposed by scrambler circuit 120. In the illustrated example, LUT 206 stores A=2 and B=12, and is coupled as a control to scrambler circuit 120. In response, scrambler circuit 120 transposes bit B2 at bit position A=2 indicated by the LUT with bit B12 at bit position B=12 indicated by the LUT. As a result, Figure 3 The upper horizontal line of illustrates a block of data DBSx, which is generated from the scrambler circuit 120 under control of the swap indicated by the LUT. Thus, in the illustrated example and where (A:B)=(2,12), then in DBSx, bit B12 appears at bit position B2, and bit B2 appears at bit position B12, with all other bits in DBSx matching the same values ​​and positions as in the original bit value of DBx. It should be noted that A and B may be provided, for example, by CTRL_S, or alternatively, from some other source (e.g., pre-programmed, periodically generated internally, etc.). Finally, in accordance with the previous figure, Figure 3 It is illustrated that the scrambled data block DBSx is output to the watermark insertion engine circuit 122.

[0028] Figure 3 The illustration and discussion of are by way of example. In other examples, other transpositions may be implemented. For example, for a data block of N>2 bits, more than two bits may be transposed. As another example, the manner in which more than two bits are transposed may be according to various methods or patterns. For example, a cyclic rotation of the transposed bits may be implemented, such as moving each designated transposed bit to the next most (or least) significant bit position, and rotating around the data block so that any bits moved beyond the most (or least) significant bit position are rotated to the least (or most) significant bit position for the transposition indication. In this scenario, assume that in Figure 3 In the example, the bit positions indicated by the LUT include three identifiers: A=2, B=12, and C=15, and the bits are swapped to the next most significant bit position in a rotational manner. In this case, the data value at position A=2 is moved to the B=12 position, the data value at position B=12 is moved to the C=15 position, and the data value at position C=15 is moved to the A=2 position. In yet another alternative, multiple bit pairs may be swapped. For example, in this scenario, assuming that Figure 3 , the bit positions indicated by the LUT include four identifiers, A=2, B=12, C=15, and D=16. These four indications can be divided into pairs, such as the first pair {A:B} indicating that the two positions are bit-swapped (the data value at position A=2 is swapped with the data value at position B=12), and the second pair {C:D} indicating that the two positions are also bit-swapped (the data value at position C=15 is swapped with the data value at position D=16). In another alternative, the aforementioned alternatives can also be combined, such as the paired indication that the first pair of bit positions (or other multiple bits of the bit positions) are all swapped to higher (or lower) significant bit positions.

[0029] Figure 4 for Figure 2 FIG. 1 is a partial diagram of the watermark insertion engine circuit 122 in combination with example data values ​​to illustrate the operation of the watermark insertion engine circuit 122. Figure 4The top horizontal line of FIG. 1 shows a single scrambled (or possibly scrambled) data block DBSx, which is obtained from Figure 1 The scrambler circuit 120 output is provided to the watermark insertion engine circuit 122. In the illustrated example, DBSx is a data block to be followed by an integer number M of data blocks, where Figure 4 A sequence of such blocks DB1, DB2, ..., DBM is described. Figure 4 In this example, the watermark configurator circuit 126 includes Figure 3 , but it is not repeated in detail, and THR1=4. Thus, the counter 210 is reset or initialized to a first value, such as zero, and it is advanced (e.g., incremented) for each data block DBSx received by the watermark insertion engine circuit 122. Additionally, THR1 is set in any of the above-described manners, where in the illustrated example, THR1=3. For each data block in the first received set of three data blocks (DB1, DB2, DB3), the counter is thereby incremented to three, at which time COUNT=THR1. The comparator 208 detects a match of COUNT and THR1, and signals or asserts a representative match (or other appropriate) signal to the watermark insertion engine circuit 122. In response, the watermark insertion engine circuit 122 inserts the watermark information WM1 into the data sequence after the most recently received data block DB3. The assertion signal from the comparator 208 also resets the counter 210. Thereafter, the above sequence is repeated until the next occurrence that the condition COUNT=THR1 is satisfied (which occurs in the illustrated sequence after receiving the next three data blocks (DB4, DB5, DB6)), at which time again the comparator 208 asserts its output and, in response, the watermark insertion engine circuit 122 inserts the watermark information WM2 into the data sequence and again resets the counter 210. This process may continue indefinitely, or until control is otherwise changed.

[0030] In different examples, the watermark information inserted by the watermark insertion engine 122 may be in various forms. In one example, the watermark is the same number of N bits in each data block, where N=16 in the previous example. In another example, the watermark is less than N bits, and in a specific example, may be a single bit (having a value of 0 or 1), which is sometimes referred to in other contexts as a padding bit between sets of blocks, where each set has THR1 blocks. Any one or more of the potential selections among the value, selection, and multiple selections may be user configurable and indicated via CTRL_W. Thus, the communication device 100 may be provided to a user, and the user may adapt his own watermark for use with the communication device 100. Similarly, where the user also has control over the operation of the receive processor 104, the user may detect an incoming signal stream of data blocks and determine whether the inserted watermark in the stream corresponds to the user's expectations, so as to identify whether the data is the user's data or data intended for the user.

[0031] Given that Figure 3 and 4 In an example of a communication device 100, a data sensing domain 106 may sense (e.g., using a sensor 112) a property and provide a corresponding analog signal for each of a series of sampled signals. A digital data generation domain 108 may convert each analog signal sample value into a corresponding digital value data block (e.g., using an ADC 118), while scrambling selected bits in those sample data blocks (e.g., every fourth sample) and interspersing watermark information between sets of those data blocks. A data transmission domain 110 transmits the stream of scrambled data blocks, as well as the watermarks interspersed among the data blocks, to the network 102 and thereby makes them available for processing (e.g., by a receive processor 104). The data transmission domain 110 may also transmit data protection information from a data protection reporter circuit 128, the data protection information representing one or both of the scrambling and watermarking associated with the data from the ADC 118. Furthermore, such data protection information may then be used by the receive processor 104 to accurately descramble the data and / or detect and / or verify the watermark. For example, for data scrambling, the LUT pair (A:B) may be provided as part of the S_ID, and THR1 of the threshold storage circuit 212 may be provided as part of the W_ID, both of which are transmitted by the data transmission domain 110 to the receiving processor 104. The receiving processor 104 may then descramble each data block DBx by again swapping the (A:B) pair, and it may similarly detect and or verify the watermark by referencing each data set that occurs immediately after the number THR1 data blocks DBx.

[0032] Figure 5 For use Figure 1 Another example embodiment of the communication device 100 is an electrical diagram of a communication device 500. Figure 5, the scrambler configurator circuit 124 of the communication device 100 is shown as a scrambler configurator circuit 502, which includes a pseudo-random (PN) sequence generator 504. Thus, in one example, a user-configurable CTRL_S signal may provide a random (including PN) sequence, or in an alternative example, the CTRL_S signal may enable (or disable) the PN sequence generator 504. The cost of the PN sequence generator 504 depends on the degree and quality of scrambling that needs to be achieved in a given application. The PN sequence may be seeded using different methods, such as by selecting from a set of orthogonal codes stored in the PN sequence generator 504 (e.g., stored in a LUT). For example, one method may address this LUT in a predictable and static manner to select the seed from different values ​​stored in the LUT. As another example, the PN may be used to select an address in the LUT, thereby randomly accessing the seed from the LUT. In either case, the seed is then used to generate the remaining PN sequences. Figure 6 Examples are shown in .

[0033] Figure 6 The sequence of 16 bits B1 to B16 forming a single digital data block DBx is illustrated as a sequence from Figure 1 The output of ADC 118 is provided to a scrambler circuit 120 . Figure 6 It is further illustrated that the PN sequence generator 504 generates a data transposed coordinate pair, shown as (C:D). The values ​​of C and D are generated in a random or pseudo-random manner and are provided or modified appropriately to identify (or otherwise process) two of the total N bits in DBx. In the illustrated example, the generated PN causes the generator 504 to provide C=5 and D=14 coupled to the scrambler circuit 120. In response, the scrambler circuit 120 transposes the bit B5 at the bit position C=5 with the bit B14 at the bit position D=14. As a result, Figure 6 The upper horizontal line of illustrates a data block DBSx, which is generated by scrambler circuit 120 under control of the transposition indicated by PN sequence generator circuit 504. Thus, in the illustrated example and where (C:D)=(5,14), then in DBSx, bit B14 appears at bit position B5, and bit B5 appears at bit position B14, with all other bits in DBSx matching the same values ​​and positions as in the original bit values ​​of DBx. The above description and Figure 6 Only the example of two PN identification bits being swapped is shown, but similar to Figure 3 , PN identification can be used to first identify multiple bits, where the transposition is achieved in some other way, such as by rotation, by pairing, or otherwise.

[0034] And, combined with Figure 5 and 6, S_ID provides an indication of the random or pseudo-random bit swap within the data block DBx to the data protection reporter circuit 128, for example, to provide (C:D) or an appropriate seed that can be used by the receiving processor 104 to equally generate (C:D) so that the receiving processor 104 can descramble each data block. For example, the generation key used to generate the PN at the communication device 100 can be provided and securely reported to the receiving processor 104 by and via the data protection reporter circuit 128 and the data transmission domain 110. Different reporting instances may include at least one of the two instances to securely provide this generation key. First, the key can be statically embedded for querying in a given register, where the register is protected by authorized access only based on a software authentication mechanism. For example, in order to protect the register, an application program interface (API) can be developed to provide register values ​​as well as key information, where the API can also be further protected by requiring authentication of an external component. Second, the generation key can be dynamically replaced by a public / private key challenge.

[0035] Figure 7 For use Figure 1 An electrical diagram of another example implementation of the communication device 100 of the communication device 700 is shown. Figure 7 , the scrambler configurator circuit 124 of the communication device 100 is shown as a scrambler configurator circuit 702, which includes a scramble position identifier circuit 704 and a comparator 706. The scramble position identifier circuit 704 has an output coupled to the scrambler circuit 120 to indicate at least two bit positions to the scrambler circuit 120, wherein those bit positions are swapped as described above. The scramble position identifier circuit 704 also has an enable input (shown as "EN") and a select input (shown as "SEL") coupled to the enable output of the comparator 706 to control the selection among the alternative ways of scrambling the data, such as previously described, to indicate the bit swap position. The comparator 706 has a first data input (shown as D1) connected to receive the data value output from the ADC 118, and a second data input (shown as THR2) connected to receive a threshold value, which may be provided as part of the user control signal CTRL_S.

[0036] The operation of the scrambler configurator circuit 702 causes the scrambler circuit 120 to scramble only selected data blocks among the data blocks output from the ADC 118, wherein the selection is based on the comparison of D1 and THR2 by the comparator 706. Specifically, the comparator 706 compares D1 and THR2 and asserts or deasserts EN to the scramble position identifier circuit 704 based on the comparison result. An example of a user providing USER_CONFIG=THR2 and responsive operation is shown below.

[0037] Figure 8 With the above Figure 4The sequence of M data blocks DB1 to DBM is described in the same manner as described in Figure 8 In addition to watermark insertion, selective scrambling is also described. Figure 8 Also describes the depiction in the horizontal line below the data block Figure 7 An example of an enabling sequence of logic values ​​of the EN signal that corresponds to or directs whether scrambling is applied to each corresponding data block DBx. Below the row of EN signals, Figure 8 The magnitude of each data block value DBx from ADC 118 is described. Finally, Figure 8 An example value of CTLR_S=THR2 is illustrated. In the illustrated example, some values ​​of DBx are lower than THR2 (i.e., values ​​DB1, DB2, DB5, DB6, and DB9), and some values ​​of DBx are higher than THR2 (i.e., values ​​DB3, DB4, DB7, and DB8). In addition, the EN signal is asserted when the DBx value is higher than THR2, and the EN signal is de-asserted when the DBx value is lower than THR2. Back to Figure 7 , and with Figure 8 118, it should be noted that for the first two data block values ​​output by the ADC 118, the comparator 706 will de-assert EN. Therefore, the de-asserted EN disables the scramble position identifier circuit 704, so that the data values ​​output by the ADC 118 pass through the scrambler circuit 120 without being scrambled (e.g., a switch circuit may be included in the data path to bypass, or otherwise prohibit scrambling from occurring). As a result, the first two data block values ​​output by the ADC 118 are not scrambled and passed to the watermark insertion engine circuit 122. However, for the third and fourth data block values ​​output by the ADC 118, the comparator 706 asserts the EN signal. In response to the asserted EN signal, the scramble position identifier circuit 704 applies the scrambling method indicated to it by the SEL signal to the third and fourth data block values ​​output from the ADC 118, and those scrambled data block values ​​are passed to the watermark insertion engine circuit 122. The same operation continues for the remaining data values, where DB5, DB6 and DB9 remain unscrambled by the digital data generation domain 108 and passed to the data transmission domain 110, and where values ​​DB7 and DB8 are scrambled by the digital data generation domain 108 and passed to the data transmission domain 110.

[0038] And, in conjunction with the communication device 100, the S_ID provides an indication of each data value that is scrambled to the data protection reporter circuit 128. Figure 8In the example of , therefore, S_ID identifies the values ​​DB3, DB4, DB7, and DB8 as being scrambled. This information may be encoded in various ways and then reported by the data protection reporter circuit 128 to the data transmission domain 110. In one example, S_ID may be a fixed number of bits that map correspondingly to the same number of data values ​​and have complementary values ​​that are set (e.g., logical one) or cleared (e.g., logical zero) to indicate whether the corresponding data value is scrambled. For example, in Figure 8 , S_ID may be, for example, an 8-bit value encoded in a circular buffer, corresponding to data values ​​DB1 to DB8, and for the example shown, then S_ID=00110011. The S_ID may also provide additional information related to scrambling, for example, for the various alternative scrambling methods described above (e.g., pair swapping; multi-bit rotation; multi-pair swapping), the S_ID may include an indication of the scrambling method. The data protection reporter circuit 128 provides the S_ID information to the data transmission domain 110 so that it can be communicated to the receive processor 104. It should be noted that additional security may be applied to this information, such as communicating the information along a secure channel or with its own encryption (e.g., an asymmetric key). As an alternative, it should be noted that the S_ID may be included as part of the data value, such as by including an additional bit stamp for each data value, and where the additional bit acts as a flag for the corresponding data value, again, indicating in one state that the data value is scrambled, or in another (e.g., complementary) state that the data value is not scrambled. There may be different trade-offs in the above approach, where the secure channel increases the communication complexity and the bit stamping involves storage requirements in the data transmission domain 110 .

[0039] In view of the foregoing, selective bit scrambling can be realized by the communication device 100 based on the comparison of the value of each digital sample with the threshold. In addition, the threshold can remain the same, or can be changed, for example, by user input. As an example, the threshold can be set based on the expected pattern in the data. For example, the communication device 700 or its sensor 112 can be used to sense data, which is expected to be low during some low-attention periods and has little effect on the sensed environment. In this case, THR2 can be set to a higher than expected value during the low-attention period so that all data are not scrambled during the period, and therefore more easily accessed, due to being from the low-attention time range, and less concerned. On the contrary, during the period of concern when the expected data exceeds THR2, the data will be scrambled and therefore less vulnerable to attack. As another example, the threshold can be changed based on the change of data, such as adjusting the threshold based on the moving average value of the data in a cycle. In all cases, selective scrambling provides some protection against illegal data attacks or access, but avoids the need for additional resources that will be needed for scrambling the complete data stream. For example, selective scrambling may reduce storage (eg, memory), power consumption (eg, battery), device size, complexity, and processing power.

[0040] As can be seen from the above, the described examples provide a network communication device that can sample signals, selectively scramble some of those signals, insert watermarks into the sample stream, and transmit the sampled / watermarked signals to a network and / or processing device. The selectivity can be controlled by the user, whereby the user can choose among the type of scrambling, the selectivity of the scrambling, and the type of watermarking. These alternatives can provide any one or more of various advantages. For example, the device can reduce or avoid attacks on ADC data sensing, and thereby permit secure sensing capabilities. Selective scrambling can free up resources that would otherwise be used if all data samples were scrambled. In the case where not all samples are scrambled, power and complexity can be reduced on both the transmission side and the receiving side of the sampling process. In addition, digital watermarking in conjunction with ADC data is heretofore unknown, and provides a way to protect against hackers or other data attacks at the hardware source end (e.g., the communication device 100). In addition, depending on the type and strength of the circuits and methods for scrambling the data, the number of unique combinations of scrambling can be increased to extend it to multiple end-user protections, where a relative consideration or balance is the potential cost if multiple different methods are implemented into the same IC where the combination is optional. In addition, one or more of the examples may be particularly beneficial in certain applications, such as in industrial environments. As a final example, with additional data protection, users can more freely delegate limited access or use of their data (including on a large scale) for a greatly increased number of applications in machine learning / artificial intelligence, where such data is extremely useful and increasingly valuable / profitable. As a result, data from different users can coexist in such applications while still providing customers with a certain degree of protection for each's corresponding data. Other benefits include changes and modifications to the structure, of which certain examples have been provided. Therefore, in the described embodiments, additional modifications are possible, and other examples are possible within the scope of the appended claims.

Claims

1. A network communication device, comprising: a signal input adapted to receive a signal derived from a sensor; an analog-to-digital converter ADC having an input coupled to said signal input, and an output; a data scrambling circuit having an input coupled to said output of said ADC, and an output; a watermark insertion circuit having an input coupled to said output of said data scrambling circuit, and an output; as well as A signal output is coupled to the output of the watermark insertion circuit.

2. A network communications device according to claim 1, and further comprising a user configurable circuit having an input adapted to receive a user configurable parameter and an output coupled to the data scrambling circuit.

3. The network communications device of claim 2, wherein the user configurable circuit is adapted to control the data scrambling circuit to select among a plurality of scrambling methods in response to the user configurable parameter.

4. The network communication device of claim 3, wherein the plurality of scrambling methods include transposing data at different bit positions within a data block in response to a stored value or a pseudo-randomly generated value. 5 . The network communication device of claim 4 , wherein the swapping of data comprises swapping data within the data block in a rotational manner. The network communication device according to claim 4 , wherein the swapping of data comprises swapping a plurality of pairs of data within the data block.

7. The network communication device of claim 3, wherein the plurality of scrambling methods include transposing data at more than two bit positions within a data block.

8. The network communication device of claim 3, wherein the plurality of scrambling methods include transposing data at more than two bit positions within a data block in response to a stored value or a pseudo-randomly generated value.

9. A network communications device according to claim 1, and further comprising a user configurable circuit having an input adapted to receive a user configurable parameter and an output coupled to the watermark insertion circuit.

10. A network communications device according to claim 9, wherein the user configurable circuitry is adapted to control the watermark insertion circuitry to select among a plurality of watermark insertion methods in response to the user configurable parameters.

11. The network communication device of claim 10, wherein the plurality of watermark insertion methods comprises inserting a single-bit watermark indicator between multi-bit ADC data values, and inserting a multi-bit watermark indicator between multi-bit ADC data values.

12. The network communication device according to claim 1: wherein the ADC is adapted to output a sequence of N-bit data values; and The watermark insertion circuit is adapted to insert an N-bit watermark into an N-bit value stream output by the ADC.

13. The network communications device of claim 12, and further comprising counting circuitry to determine the size of the stream of N-bit values.

14. A network communications device according to claim 13, and further comprising a user configurable circuit having an input adapted to receive a user configurable parameter and an output coupled to control the size of the N-bit value stream in response to the user configurable parameter.

15. A network communication device according to claim 1, and further comprising a user configurable circuit, the user configurable circuit having an input adapted to receive a first user configurable parameter and an output coupled to the data scrambling circuit, and an input adapted to receive a second user configurable parameter and an output coupled to the watermark insertion circuit.

16. A network communication device according to claim 15, wherein the user-configurable circuit is suitable for controlling the data scrambling circuit to select among multiple scrambling methods in response to the first user-configurable parameter, and controlling the watermark insertion circuit to select among multiple watermark insertion methods in response to the second user-configurable parameter.

17. A network communication device according to claim 1, and further comprising a comparison circuit, the comparison circuit having a first data input coupled to receive a data value from the output of the ADC and a second data input suitable for receiving a threshold level, the comparison circuit further comprising a control output suitable for selectively enabling the data scrambling circuit in response to a comparison of the data value and the threshold level.

18. The network communication device of claim 1 and further comprising a sensor having an output coupled to the signal input of the ADC.

19. The network communications device of claim 1 and further comprising a transmitter circuit coupled to the output of the ADC and to the output of the watermark insertion circuit.

20. A network system comprising: A first network communication device, which is adapted to be coupled to a network, the first network communication device comprising: a signal input adapted to receive a signal derived from a sensor; an analog-to-digital converter ADC having an input coupled to said signal input, and an output; a data scrambling circuit having an input coupled to said output of said ADC, and an output; a watermark insertion circuit having an input coupled to said output of said data scrambling circuit, and an output; and a signal output coupled to said output of said watermark insertion circuit; and A second network communication device adapted to be coupled to the network and comprising processing circuitry adapted to process scrambled data having watermark information coupled to the network through the first network communication device.

21. A method comprising: receiving an analog signal from a sensor; determining a first set of digital data associated with the analog signal using an analog-to-digital converter; determining whether to rearrange a subset of the first set of digital data to produce a second set of digital data or to provide the first set of digital data as the second set of digital data; determining whether to insert a watermark into the second digital data set to generate a third digital data set or to provide the second digital data set as the third digital data set; as well as The third set of digital data is provided for transmission via a network.

Images