A heterogeneous hybrid programmable switch fabric system and method

Abstract

The application provides a heterogeneous hybrid programmable switch structure system and method. The system comprises three target units of ASIC units, FPGA units and CPU units arranged in order of processing rate from high to low; the ASIC units are used for performing basic processing on received data packets to generate data packets in a preset format; the FPGA units are used for receiving data packets from the ASIC units, processing the received data packets according to rules and generating data packets in a preset format; and the CPU units are used for receiving data packets from the ASIC units and / or FPGA units, processing the received data packets according to rules and generating data packets in a preset format. The application can meet diversified data processing requirements.

Description

Technical Field

[0001] This invention relates to the field of programmable network technology, and in particular to a heterogeneous hybrid programmable switch architecture system and method. Background Technology

[0002] The internet has entered a new era of interconnectedness, with the emergence of new business applications such as autonomous driving, metaverse, and large-scale models accelerating the deep integration of industrial production, social life, and networks. These new business systems not only require networks to provide high-speed and stable data transmission capabilities, but also flexible computing and efficient storage capabilities to meet the diverse needs of various vertical industry applications for network storage-to-computing capabilities. Under current technological levels, a single device cannot simultaneously support both flexibility and high-performance processing, and relying on the performance of a single chip is no longer sufficient to cope with the rapidly growing storage and computing demands of network business development. Summary of the Invention

[0003] To meet the current network requirements for switches in terms of flexibility and throughput, this invention adopts a heterogeneous hardware and software collaborative approach to provide a heterogeneous hybrid programmable switch architecture system and method that can meet diverse data processing needs.

[0004] On one hand, the present invention provides a heterogeneous hybrid programmable switch structure system, comprising: a three-level target unit consisting of ASIC units, FPGA units, and CPU units arranged in descending order of processing speed;

[0005] The ASIC unit is used to perform basic processing on the received data packets to generate data packets in a preset format.

[0006] The FPGA unit is used to receive data packets from the ASIC unit, process the received data packets according to rules, and generate data packets in a preset format.

[0007] The CPU unit is used to receive data packets from the ASIC unit and / or FPGA unit, process the received data packets according to rules, and generate data packets in a preset format.

[0008] Furthermore, each target unit is obtained by combining three or more modules from the parser, matching action module, inverse parser, and traffic management module;

[0009] The parser is used to perform protocol parsing and extract key information from the arriving data packets; the matching action module is used to perform a matching lookup based on the key information extracted by the parser, and execute the corresponding action according to the lookup result; the inverse parser is used to encapsulate the data into data packets of a preset format; and the traffic management module is used to perform data packet switching scheduling and traffic shaping.

[0010] Furthermore, the ASIC unit includes a first-level parser, a first-level matching action module, a first-level inverse parser, a traffic management module, a second-level parser, a second-level matching action module, and a second-level inverse parser connected in sequence.

[0011] Furthermore, the FPGA unit includes an input queue module, a parser, a matching action module, an inverse parser, and an output queue module connected in sequence.

[0012] Furthermore, the CPU unit includes a parser, a first-level matching action module, a traffic management module, a second-level matching action module, and an inverse parser connected in sequence.

[0013] Furthermore, an external function module is also provided in the FPGA unit and / or the CPU unit, which is used to support user-defined operations; correspondingly, the FPGA unit and / or the CPU unit processes the received data packets according to the rules and / or the output of the external function module and generates data packets in a preset format.

[0014] Furthermore, the preset format data packet includes a data packet formed by encapsulating a custom Ethernet header outside the original data packet to encapsulate the original data packet and metadata together.

[0015] Furthermore, the custom Ethernet header includes a reserved field, a CAT field, a source / destination device physical interface number field, an ETHTYPE field, and a VALUE field;

[0016] The CAT field is used to indicate whether the lookup of the previous target unit is successful, whether there is a custom calculation, and to indicate the valid location of the custom calculation result.

[0017] The source and destination device physical interface number field is a multiplexed field. When a data packet is sent to each target unit for table matching, this field is used to indicate the source device physical interface number of the data packet; when the table matching of the data packet is successful, this field is used to indicate the destination device physical interface number of the data packet.

[0018] The ETHTYPE field is used in conjunction with the CAT field to indicate the internal encapsulation format;

[0019] The VALUE field is used to store the corresponding quintuple information and the result of the custom calculation when a table lookup is successful and / or a custom calculation exists.

[0020] On the other hand, the present invention provides a data processing method for a heterogeneous hybrid programmable switch architecture system as described in the first aspect, comprising:

[0021] The ASIC unit receives data packets from the external network, performs protocol parsing on the received data packets and extracts key information. It then performs a lookup table based on the extracted key information. If the lookup table matches, it executes the corresponding action according to the rules and encapsulates the preset metadata together with the original data packet. Next, it forwards the encapsulated data packet to the FPGA unit, CPU unit, or system output port based on the lookup result. If the lookup table does not match, it directly encapsulates the preset metadata together with the original data packet and forwards the encapsulated data packet to the CPU unit.

[0022] The FPGA unit extracts metadata from the received data packet, extracts the key from the metadata, and uses the key to perform a table lookup. If the lookup matches, the corresponding action is executed according to the rules, and the lookup result is filled into the metadata. Then, the metadata and the original data packet are encapsulated together, and the encapsulated data packet is forwarded to the ASIC unit according to the lookup result. If the lookup does not match, the metadata and the original data packet are directly encapsulated together, and the encapsulated data packet is forwarded to the CPU unit.

[0023] The CPU unit extracts metadata from the received data packets, extracts the key from the metadata, uses the key to perform a table lookup match, and if the table lookup match is found, it executes the corresponding action according to the rules and forwards the table lookup result to the ASIC unit.

[0024] The ASIC unit receives data packets from the FPGA unit or CPU unit and forwards the data packets directly according to the outgoing interface instructions in the metadata of the data packets.

[0025] The beneficial effects of this invention are:

[0026] This invention employs three programmable target units with different characteristics. By combining the features of different target units, a switch structure with high-performance processing speed, large-capacity flow table, and flexible and definable characteristics is created, which can meet diverse data processing needs. Attached Figure Description

[0027] Figure 1 A heterogeneous hybrid programmable switch structure system provided in this embodiment of the invention;

[0028] Figure 2This invention provides a custom Ethernet header metadata data frame format. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of the embodiments of this invention will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0030] like Figure 1 As shown, this embodiment of the invention provides a heterogeneous hybrid programmable switch structure system, including: three levels of target units: ASIC unit, FPGA unit, and CPU unit arranged in order of processing speed from high to low; that is, in the three-level pipeline structure, in order of processing speed from high to low and flexibility from low to high, the ASIC unit is the first level, and the FPGA unit and CPU unit are the second and third levels, respectively.

[0031] The ASIC unit performs basic processing on received data packets to generate data packets in a preset format; the FPGA unit receives data packets from the ASIC unit, processes the received data packets according to rules, and generates data packets in a preset format; the CPU unit receives data packets from the ASIC unit and / or the FPGA unit, processes the received data packets according to rules, and generates data packets in a preset format. All three target units are programmable.

[0032] It should be noted that in an ASIC unit, data packets may originate from packets arriving from an external network, or they may be data packets processed by the CPU unit or FPGA.

[0033] The heterogeneous hybrid programmable switch architecture provided in this invention provides a system where different target units are physically decoupled and interconnected using standard Ethernet. The front-end programmable ASIC unit is mainly used for basic data processing, while the FPGA unit and CPU unit can implement the functional definition of the external function unit in P4, supporting more flexible data processing and larger capacity flow tables. This overcomes the bottlenecks and shortcomings of existing programmable switches in complex function calculation, security functions, and state processing.

[0034] Based on the above embodiments, in this embodiment, each target unit is obtained by combining three or more modules from the parser, matching action module, inverse parser and traffic management module;

[0035] The parser is used to parse the protocol and extract key information (such as 5-tuple information) from the arriving data packets; the matching action module is used to perform matching lookups based on the key information extracted by the parser and execute corresponding actions according to the lookup results; the inverse parser is used to encapsulate the data into data packets of a preset format; and the traffic management module is used to perform data packet switching scheduling and traffic shaping. The matching lookup includes three types of matching lookup operations: longest match, exact match, and range match. The corresponding actions include adding, modifying, or deleting a specific protocol field.

[0036] like Figure 1 As shown, in one possible implementation, the ASIC unit includes a first-level parser, a first-level matching action module, a first-level inverse parser, a flow management module, a second-level parser, a second-level matching action module, and a second-level inverse parser connected in sequence. The FPGA unit includes an input queue module, a parser, a matching action module, an inverse parser, and an output queue module connected in sequence. The CPU unit includes a parser, a first-level matching action module, a flow management module, a second-level matching action module, and an inverse parser connected in sequence.

[0037] Building upon the aforementioned embodiments, external functional modules are further incorporated into the FPGA and CPU units. These external functional modules support user-defined operations, enabling functional expansion of the entire system. Specifically, within the CPU unit, the external functional modules interact with two matching action modules to process data packets based on their outputs. The FPGA unit also interacts with the parser, matching action modules, and inverse parser to process data packets according to the outputs of the external functional modules.

[0038] Based on the above embodiments, to better coordinate the performance of heterogeneous resources, this embodiment defines a data packet format. The three target units use this custom data packet format to transmit data packets and metadata. Specifically, based on the standard Ethernet Layer 2 frame construction transmission data frame format, a custom Ethernet header format is used to encapsulate metadata before the original Layer 2 frame, thereby passing information such as the interface, key, and matching structure of the previous level to the subsequent programmable unit. For example... Figure 2 As shown, the custom Ethernet header in this embodiment of the invention includes a reserved RSV field, a CAT field, a source / destination device physical interface number field, an ETHTYPE field, and a VALUE field.

[0039] This custom Ethernet header uses a total of 59 (6+6+2+45) bytes. Since this data is encapsulated and transmitted within the entire system, there is no issue of communication with external devices. Therefore, the definition of the protocol fields has been optimized. The specific format is as follows: In the standard DMAC field, the first two bytes are reserved, namely the two-byte RSV field, which defaults to all 0s; the middle two bytes of the CAT field are used for classification descriptions in the three-level target unit processing stage, respectively indicating whether the table lookup of the previous level target unit is successful, whether there is a custom calculation, and indicating the valid position of the custom calculation result; the last two bytes of the standard DMAC field plus the 6 bytes of SMAC form an 8-byte source and destination device physical interface number field. This field is a multiplexed field. When the data packet is sent to each target unit for table matching, this field is used to indicate the source device physical interface number of the data packet; when the table match of the data packet is successful, this field is used to indicate the destination device physical interface number of the data packet. This field is 8 bytes long and uses one-hot encoding to correspond to physical ports, supporting a maximum of 64 physical ports. When multiple ports need to forward data packets, the bit corresponding to that interface can be set to 1. The ETHTYPE field (Ethernet type field) is used in conjunction with the CAT field to indicate the internal encapsulation format. Specifically, this field inherits the usage of standard Ethernet and uses the undefined "0xAAAA" as the identifier for the internal encapsulation format. If the ETHTYPE field is "0xAAAA" and the CAT value is all 0, it means that the original data packet follows the ETHTYPE field, i.e., there is no VALUE field; otherwise, the VALUE field exists. The VALUE field is used to store the corresponding 5-tuple information and the custom calculation result when a table lookup hit occurs and / or a custom calculation exists. This field is 45 bytes long, with the first 13 bytes containing the 5-tuple information and the last 32 bytes containing the custom calculation result. The effective length of the custom calculation result can be obtained from the last byte of the CAT field, with a maximum of 256 bits.

[0040] Based on the above-described heterogeneous hybrid programmable switch architecture system, this embodiment of the invention also provides a data processing method for the system, which consists of three processing stages: ASIC processing, FPGA processing, and CPU processing. The specific processing flow is as follows:

[0041] The ASIC unit receives data packets arriving from the external network, performs protocol parsing on the received data packets, and extracts key information (such as source IP address, destination IP address, source port, destination port, etc.). Based on the extracted key information, it performs a lookup operation (such as longest match of destination IP, exact match of 5-tuple, or range match). If the lookup is successful, the corresponding action is executed according to the rules, and the preset metadata is encapsulated together with the original data packet. Then, based on the lookup result, the encapsulated data packet is forwarded to the FPGA unit, CPU unit, or system output port. If the lookup is unsuccessful, the preset metadata is directly encapsulated together with the original data packet, and the encapsulated data packet is forwarded to the CPU unit.

[0042] Specifically, after a data packet arrives, it first enters the first-level parser for protocol parsing. Then, keywords are extracted from the data packet. Based on the extracted keywords, a table lookup is performed in the first-level matching action module. The first-level reverse parser encapsulates the table lookup results and the data packet, and then the data packet is exchanged to the second-level parser through the traffic management module. After extracting the corresponding keywords, the table lookup operation is performed again in the second-level matching action module. The data packet is then edited and modified, and sent to the reverse parser to be encapsulated into a new data packet. The new data packet is then forwarded to the FPGA unit, CPU unit, or system output port.

[0043] The FPGA unit extracts metadata from the received data packet, extracts the key from the metadata, and uses the key to perform a table lookup (either on-chip TCAM or off-chip SDRAM HASH). If the lookup matches, the corresponding action is executed according to the rules (when there are external functional modules in the FPGA internal unit, the action here can include the action output by the external functional module), and the lookup result is filled into the metadata. Then, the metadata and the original data packet are encapsulated together, and the encapsulated data packet is forwarded to the ASIC unit according to the lookup result. If the lookup does not match, the metadata and the original data packet are directly encapsulated together, and the encapsulated data packet is forwarded to the CPU unit.

[0044] Specifically, in the FPGA unit, data packets sent from the ASIC unit are received. After the data packets arrive, they first enter the input queue module for pre-processing queuing, and then enter the parser to parse the internal data format. According to the definition of the internal format fields, a table lookup operation is performed in the matching action module. Data processing is performed based on the lookup results. This part of the processing can be performed in a user-defined external functional unit. Afterwards, the data packets are encapsulated by the reverse parser and sent to the next level target unit.

[0045] The CPU unit extracts metadata from the received data packets, extracts the key from the metadata, and uses the key to perform a table lookup. If the table lookup matches, the corresponding action is executed according to the rules (when there are external function modules in the CPU internal unit, the action here can include the action output by the external function modules), and the table lookup result is forwarded to the ASIC unit.

[0046] Specifically, in the CPU unit, data packets sent from the ASIC unit and FPGA unit are received. After the data packet arrives, it first enters the parser to parse the internal data format and performs a table lookup operation in the matching action module according to the definition of the internal format field. Data processing is performed based on the lookup result. This part of the processing can be performed in the user-defined external functional unit. Afterwards, the data packet is encapsulated by the reverse parser and sent to the next level target unit.

[0047] The ASIC unit receives data packets from the FPGA unit or the CPU unit and forwards them directly according to the outgoing interface indication in the metadata of the data packet. That is, for data packets that return from the CPU unit or the FPGA unit to the ASIC unit and need to be processed again in the ASIC unit, the ASIC unit directly forwards them to the ASIC unit according to the outgoing interface indication in the metadata of the data packet, without performing a second table lookup operation.

[0048] The heterogeneous hybrid programmable switch structure system and method provided by the present invention adopts three programmable target units with different characteristics. By combining the characteristics of different target units, a switch structure with high-performance processing speed, large-capacity flow table and flexible and definable characteristics is formed.

[0049] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A heterogeneous hybrid programmable switch architecture system, characterized in that, include: The target units are arranged in three levels: ASIC units, FPGA units, and CPU units, in descending order of processing speed. The ASIC unit is used to perform basic processing on the received data packets to generate data packets in a preset format; the ASIC unit includes a first-level parser, a first-level matching action module, a first-level inverse parser, a traffic management module, a second-level parser, a second-level matching action module, and a second-level inverse parser connected in sequence. The FPGA unit is used to receive data packets from the ASIC unit, process the received data packets according to rules, and generate data packets in a preset format; the FPGA unit includes an input queue module, a parser, a matching action module, an inverse parser, and an output queue module connected in sequence. The CPU unit is used to receive data packets from the ASIC unit and / or FPGA unit, process the received data packets according to rules, and generate data packets in a preset format; the CPU unit includes a parser, a first-level matching action module, a traffic management module, a second-level matching action module, and an inverse parser connected in sequence. The parser is used to perform protocol parsing and extract key information from the arriving data packets; the matching action module is used to perform a matching lookup based on the key information extracted by the parser, and execute corresponding actions according to the lookup results; the inverse parser is used to encapsulate the data into data packets of a preset format; and the traffic management module is used to perform data packet switching scheduling and traffic shaping. The preset format data packet includes a custom Ethernet header encapsulated outside the original data packet to encapsulate the original data packet and metadata together. The custom Ethernet header includes a reserved field, a CAT field, a source / destination device physical interface number field, an ETHTYPE field, and a VALUE field. The CAT field indicates whether the lookup in the previous target unit is successful, whether a custom calculation exists, and indicates the valid location of the custom calculation result. The source / destination device physical interface number field is a multiplexed field; when the data packet is sent to various target units for lookup matching, this field indicates the source device physical interface number of the data packet; when the lookup match is successful, this field indicates the destination device physical interface number of the data packet. The ETHTYPE field works in conjunction with the CAT field to indicate the internal encapsulation format. The VALUE field stores the corresponding five-tuple information and the custom calculation result when the lookup match is successful and / or a custom calculation exists. The data processing method of the system includes: the ASIC unit receives data packets arriving from the external network, performs protocol parsing on the received data packets and extracts key information, performs a lookup table based on the extracted key information, if the lookup table matches, executes the corresponding action according to the rules, and encapsulates the preset metadata together with the original data packet, and then forwards the encapsulated data packet to the FPGA unit, CPU unit or system output port according to the lookup result; if the lookup table does not match, the preset metadata is directly encapsulated together with the original data packet, and the encapsulated data packet is forwarded to the CPU unit. The FPGA unit extracts metadata from the received data packet, extracts the key from the metadata, and uses the key to perform a table lookup. If the lookup matches, the corresponding action is executed according to the rules, and the lookup result is filled into the metadata. Then, the metadata and the original data packet are encapsulated together, and the encapsulated data packet is forwarded to the ASIC unit according to the lookup result. If the lookup does not match, the metadata and the original data packet are directly encapsulated together, and the encapsulated data packet is forwarded to the CPU unit. The CPU unit extracts metadata from the received data packets, extracts the key from the metadata, uses the key to perform a table lookup match, and if the table lookup match is found, it executes the corresponding action according to the rules and forwards the table lookup result to the ASIC unit. The ASIC unit receives data packets from the FPGA unit or CPU unit and forwards the data packets directly according to the outgoing interface instructions in the metadata of the data packets.

2. The heterogeneous hybrid programmable switch architecture system according to claim 1, characterized in that, An external function module is also provided in the FPGA unit and / or the CPU unit, which is used to support user-defined operations; correspondingly, the FPGA unit and / or the CPU unit processes the received data packets according to the rules and / or the output of the external function module and generates data packets in a preset format.

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