Video data multi-scale down-sampling method and device based on FPGA (Field Programmable Gate Array)

Abstract

The invention provides a video data multi-scale down-sampling method and device based on an FPGA. The method comprises the following steps: counting line and field synchronization signals of received image data; according to the counting result of the row-field synchronizing signals, generating down-sampled row-field marking signals; enabling originally received image data to correspond to the generated down-sampling line field marking signal, carrying out image down-sampling, and writing the image into an FIFO (First In First Out); integrating the down-sampled image data into continuous line field image data by using FIFO (First In First Out), and outputting the continuous line field image data; and generating a new line field synchronization signal according to the down-sampled image data, aligning the new line field synchronization signal with the down-sampled line field image data, and synchronously outputting the line field synchronization signal and the down-sampled line field image data. According to the invention, multi-scale down-sampling of the video data based on the FPGA can be realized, down-sampling is carried out on a high-resolution image, the image resolution is reduced, the pressure of FPGA image processing is reduced, the sampling scale of down-sampling of the video data is variable, and setting of different sampling scales can be carried out according to actual needs.

Description

Technical Field

[0001] The present invention relates to the technical field of video image processing, and in particular to a multi-scale down-sampling method of video data based on FPGA. Background Art

[0002] At present, computer software technology provides a good development platform for video image processing technology, and the powerful processing power of computer processors has also been well applied in various video image processing algorithms. Highly integrated, high-performance, and low-power Field Programmable Gate Array (FPGA) devices provide broad development prospects for video image system designers. The unique performance advantages of FPGA occupy a very important position in embedded video image processing systems.

[0003] In practical applications, the image resolution that FPGA needs to process is constantly increasing, and there is a requirement for real-time image processing. In this case, the image is downsampled and the high-resolution image processing is accelerated by reducing the image resolution to achieve real-time processing of large amounts of data. If the image data resolution cannot be reduced, the data cache part of the subsequent image processing of the FPGA will occupy a lot of resources and time, and the real-time performance of the overall FPGA design will be greatly reduced. Summary of the invention

[0004] The technical problem to be solved by the present invention is how to perform real-time multi-scale downsampling of video data based on FPGA; in view of this, the present invention provides a multi-scale downsampling method and device for video data based on FPGA.

[0005] The technical solution adopted by the present invention is a multi-scale downsampling method of video data based on FPGA, comprising:

[0006] Step S1, counting the line and field synchronization signals of the received image data;

[0007] Step S2, generating a down-sampled line field mark signal according to the counting result of the line field synchronization signal, the line field mark signal indicating that the original data at the position is retained after down-sampling;

[0008] Step S3, matching the originally received image data with the generated down-sampled row and field mark signal, down-sampling the image and writing it into FIFO;

[0009] Step S4, using FIFO to integrate the down-sampled image data into continuous line and field image data for output;

[0010] Step S5, generating a new line-field synchronization signal according to the down-sampled image data, aligning the new line-field synchronization signal with the down-sampled line-field image data, and outputting the new signal synchronously.

[0011] In one embodiment, step S1 includes:

[0012] By detecting the rising edge and the falling edge of the horizontal and vertical synchronization signals, the horizontal synchronization signals and the vertical synchronization signals are counted using a preset sampling scale as a counting threshold.

[0013] In one embodiment, in step S2, the down-sampled line field mark signal is generated specifically at a position corresponding to a count of "1".

[0014] In one embodiment, the method further includes: the resolution of the originally received image data is greater than the resolution of the image data after the downsampling process.

[0015] Another aspect of the present invention further provides a video data multi-scale downsampling device based on FPGA, comprising:

[0016] A counting unit configured to count the line and field synchronization signals of the received image data;

[0017] A line field mark signal unit is configured to generate a down-sampled line field mark signal according to a counting result of the line field synchronization signal, wherein the line field mark signal indicates that the original data at the position is retained after down-sampling;

[0018] A down-sampling unit, configured to correspond the originally received image data to the generated down-sampled row and field mark signal, perform image down-sampling and write the image into FIFO;

[0019] An image integration unit configured to integrate the downsampled image data into continuous line and field image data for output using the FIFO;

[0020] The synchronous output unit is configured to generate a new line-field synchronization signal according to the down-sampled image data, align with the down-sampled line-field image data, and output it synchronously.

[0021] Another aspect of the present invention provides an electronic device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the computer program is executed by the processor, the steps of the FPGA-based video data multi-scale downsampling method as described in any one of the above items are implemented.

[0022] Another aspect of the present invention further provides a computer storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the FPGA-based video data multi-scale downsampling method as described above are implemented.

[0023] Compared with the prior art, the present invention can be used to realize multi-scale downsampling of video data based on FPGA. First, by downsampling the high-resolution image, the image resolution is reduced, thereby reducing the pressure of subsequent FPGA image processing; and the sampling scale of the video data downsampling is variable, and different sampling scales can be set according to actual application needs. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A schematic diagram of a flow chart of a multi-scale down-sampling method for video data based on FPGA according to an embodiment of the present invention;

[0025] Figure 2 A schematic diagram of processing logic of a multi-scale down-sampling method for video data based on FPGA according to an embodiment of the present invention;

[0026] Figure 3 It is a schematic diagram of the composition of a multi-scale down-sampling device for video data based on FPGA according to an embodiment of the present invention;

[0027] Figure 4 The figure is a schematic diagram of the composition of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0028] In order to further explain the technical means and effects adopted by the present invention to achieve the predetermined purpose, the present invention is described in detail below in conjunction with the accompanying drawings and preferred embodiments.

[0029] Unless otherwise defined, all terms (including technical terms and scientific terms) used in this article have the same meaning as commonly understood by ordinary technicians in the field to which this application belongs. It should also be understood that terms (such as terms defined in commonly used dictionaries) should be interpreted as having the same meaning as their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense unless explicitly defined in this article.

[0030] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0031] The embodiment of the present invention provides a multi-scale downsampling method for video data based on FPGA, such as Figure 1 As shown, including:

[0032] Step S1, counting the line and field synchronization signals of the received image data;

[0033] Step S2, generating a down-sampled line field mark signal according to the counting result of the line field synchronization signal, the line field mark signal indicating that the original data at the position is retained after down-sampling;

[0034] Step S3, matching the originally received image data with the generated down-sampled row and field mark signal, down-sampling the image and writing it into FIFO;

[0035] Step S4, using FIFO to integrate the down-sampled image data into continuous line and field image data for output;

[0036] Step S5, generating a new line-field synchronization signal according to the down-sampled image data, aligning the new line-field synchronization signal with the down-sampled line-field image data, and outputting the new signal synchronously.

[0037] In this embodiment, the rising edge and the falling edge of the horizontal and vertical synchronization signals are detected, and the preset sampling scale is used as the counting threshold to count the horizontal synchronization signals and the vertical synchronization signals.

[0038] In this embodiment, illustratively, the down-sampled line field mark signal is generated specifically at the position where the corresponding count is "1".

[0039] Furthermore, the method provided in this embodiment also includes: the resolution of the originally received image data is greater than the resolution of the image data after the downsampling process.

[0040] refer to Figure 2 , the method provided in this embodiment will be described in detail step by step below.

[0041] In this embodiment, firstly, the sampling mark signals at different scales are generated by counting the line and field signals of the image data;

[0042] Furthermore, the image data at the corresponding scale is cached, and the FIFO is used to integrate the data after sampling;

[0043] Further, the image data is read out according to a fixed format, and the down-sampled image data is output.

[0044] Finally, a valid enable signal for the image data is generated, including row enable and frame enable signals, which are aligned with the down-sampled data for transmission.

[0045] For ease of understanding, a specific application example is provided below.

[0046] 1. Counting the line and field synchronization signals of the received high-resolution image data, by detecting the rising edge and falling edge of the line and field synchronization signals, using the preset sampling scale as the counting threshold, and counting the line and field synchronization signals;

[0047] 2. After the counting is completed, according to the counting result of the line and field synchronization signal, a down-sampled line and field mark signal is generated at the position corresponding to the count of "1", and the line and field mark signal indicates that the original data at the position is retained after down-sampling;

[0048] 3. Corresponding the original high-resolution image data with the generated down-sampled row and field flag signal, down-sampling the high-resolution image and writing it into FIFO;

[0049] 4. Use FIFO to integrate the downsampled image data, and integrate the downsampled image data into continuous line and field image data for output, so as to facilitate subsequent image processing;

[0050] 5. Generate a new line and field synchronization signal based on the down-sampled image data, and output it synchronously with the down-sampled data.

[0051] Compared with the prior art, this embodiment has at least the following effects:

[0052] 1) The embodiment of the present invention can be used to implement multi-scale downsampling of video data based on FPGA;

[0053] 2) This embodiment reduces the image resolution by downsampling the high-resolution image, thereby reducing the pressure of subsequent FPGA image processing;

[0054] 3) The sampling scale of the video data downsampling in this embodiment is variable, and different sampling scales can be set according to actual application needs.

[0055] The second embodiment of the present invention corresponds to the first embodiment, and can be referred to Figure 3 This embodiment introduces a multi-scale downsampling device for video data based on FPGA, including the following components:

[0056] A counting unit configured to count the line and field synchronization signals of the received image data;

[0057] A line field mark signal unit is configured to generate a down-sampled line field mark signal according to a counting result of the line field synchronization signal, wherein the line field mark signal indicates that the original data at the position is retained after down-sampling;

[0058] A down-sampling unit, configured to correspond the originally received image data to the generated down-sampled row and field mark signal, perform image down-sampling and write the image into FIFO;

[0059] An image integration unit configured to integrate the downsampled image data into continuous line and field image data for output using the FIFO;

[0060] The synchronous output unit is configured to generate a new line-field synchronization signal according to the down-sampled image data, align with the down-sampled line-field image data, and output it synchronously.

[0061] A third embodiment of the present invention is an electronic device, such as Figure 4 As shown, it can be understood as a physical device, including a processor and a memory storing instructions executable by the processor. When the instructions are executed by the processor, the following operations are performed:

[0062] Step S1, counting the line and field synchronization signals of the received image data;

[0063] Step S2, generating a down-sampled line field mark signal according to the counting result of the line field synchronization signal, the line field mark signal indicating that the original data at the position is retained after down-sampling;

[0064] Step S3, matching the originally received image data with the generated down-sampled row and field mark signal, down-sampling the image and writing it into FIFO;

[0065] Step S4, using FIFO to integrate the down-sampled image data into continuous line and field image data for output;

[0066] Step S5, generating a new line-field synchronization signal according to the down-sampled image data, aligning the new line-field synchronization signal with the down-sampled line-field image data, and outputting the new signal synchronously.

[0067] The fourth embodiment of the present invention, the process of the FPGA-based video data multi-scale downsampling method of this embodiment is the same as the first, second or third embodiment, the difference is that, in engineering implementation, this embodiment can be implemented by means of software plus a necessary general hardware platform, of course, it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the method of the present invention can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM / RAM, disk, optical disk), including a number of instructions for a device to execute the method described in the embodiment of the present invention.

[0068] Through the description of the specific implementation methods, a deeper and more specific understanding of the technical means and effects adopted by the present invention to achieve the predetermined purpose should be obtained. However, the accompanying drawings are only for reference and illustration purposes and are not intended to limit the present invention.

Claims

1. A multi-scale downsampling method for video data based on FPGA, characterized in that: include: Step S1, counting the line and field synchronization signals of the received image data; Step S2, generating a down-sampled line field mark signal according to the counting result of the line field synchronization signal, the line field mark signal indicating that the original data at the position is retained after down-sampling; Step S3, matching the originally received image data with the generated down-sampled row and field mark signal, down-sampling the image and writing it into FIFO; Step S4, using FIFO to integrate the down-sampled image data into continuous line and field image data for output; Step S5, generating a new line-field synchronization signal according to the down-sampled image data, aligning the new line-field synchronization signal with the down-sampled line-field image data, and outputting the new signal synchronously.

2. The FPGA-based video data multi-scale downsampling method according to claim 1, characterized in that: The step S1 comprises: By detecting the rising edge and the falling edge of the horizontal and vertical synchronization signals, the horizontal synchronization signals and the vertical synchronization signals are counted using a preset sampling scale as a counting threshold.

3. The FPGA-based video data multi-scale downsampling method according to claim 2, characterized in that: In the step S2, the down-sampled line field mark signal is generated specifically at the position corresponding to the count of "1".

4. The FPGA-based video data multi-scale downsampling method according to claim 1, characterized in that: The method further includes: the resolution of the originally received image data is greater than the resolution of the image data after the downsampling process.

5. A multi-scale downsampling device for video data based on FPGA, characterized in that: include: A counting unit configured to count the line and field synchronization signals of the received image data; A line field mark signal unit is configured to generate a down-sampled line field mark signal according to a counting result of the line field synchronization signal, wherein the line field mark signal indicates that the original data at the position is retained after down-sampling; A down-sampling unit, configured to correspond the originally received image data to the generated down-sampled row and field mark signal, perform image down-sampling and write the image into FIFO; An image integration unit configured to integrate the downsampled image data into continuous line and field image data for output using the FIFO; The synchronous output unit is configured to generate a new line-field synchronization signal according to the down-sampled image data, align with the down-sampled line-field image data, and output it synchronously.

6. An electronic device, characterized in that: The electronic device comprises: a memory, a processor, and a computer program stored in the memory and executable on the processor. When the computer program is executed by the processor, the steps of the FPGA-based video data multi-scale down-sampling method as claimed in any one of claims 1 to 4 are implemented.

7. A computer storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the steps of the FPGA-based video data multi-scale downsampling method as claimed in any one of claims 1 to 4 are implemented.

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