Photoelectric conversion device, method for driving photoelectric conversion device, signal output device, light detection system, and movable body

Abstract

The invention provides a photoelectric conversion device, a driving method thereof, a signal output device, a light detection system, and a movable body. The photoelectric conversion device includes: pixel circuits arranged to form a plurality of rows and a plurality of columns; and a control circuit for driving the pixel circuit. Each of the pixel circuits includes: a signal generation circuit including a photoelectric conversion section; a memory for holding a signal output from the signal generation circuit; and a timing circuit including a first input node to which a signal from the memory is input, a second input node to which a control signal from the control circuit is input, a third input node, and an output node. The pixel circuits include a first pixel circuit and a second pixel circuit arranged in a same row or a same column, and an output node of a timing circuit of the first pixel circuit is connected to a third input node of a timing circuit of the second pixel circuit.

Description

Technical Field

[0001] The present invention relates to a photoelectric conversion device and a driving method thereof. Background Art

[0002] In recent years, performance improvements such as an increase in the number of pixels and an increase in the readout speed have been attempted in image sensors and ranging systems, and some proposals have been made regarding a method for reading out pixel information corresponding to an increase in the amount of information possessed by the entire pixel. Japanese Patent Laid-Open Nos. 2012-070170 and 2018-186478 disclose an image capture device in which image information of a light receiving unit is transmitted to an image processing unit via another light receiving unit, thereby reducing the length of interconnection lines connected to a plurality of light receiving units.

[0003] However, in the technology described in Japanese Patent Laid-Open No. 2012-070170, when there are a plurality of pixel rows, it is necessary to sequentially process pixel signals outside the pixel circuit, and it takes time to read out signals from all pixels. In addition, in the technology described in Japanese Patent Laid-Open No. 2018-186478, the readout circuit outside the pixel provided for each pixel column is responsible for processing the signal of the corresponding pixel column, and there is substantially the same problem as Japanese Patent Laid-Open No. 2012-070170. Summary of the invention

[0004] An object of the present invention is to provide a photoelectric conversion device and a driving method thereof that can reduce the time required to read out a pixel signal.

[0005] According to a disclosure of the present specification, a photoelectric conversion device is provided, which includes: a plurality of pixel circuits arranged to form a plurality of rows and a plurality of columns; and a control circuit configured to drive the plurality of pixel circuits, wherein the plurality of pixel circuits each include: a signal generating circuit including a photoelectric conversion unit, a memory configured to maintain a signal output from the signal generating circuit, and a timing circuit including a first input node to which a signal from the memory is input, a second input node to which a control signal from the control circuit is input, a third input node and an output node, and wherein the plurality of pixel circuits include a first pixel circuit and a second pixel circuit arranged in the same row or the same column, and the output node of the timing circuit of the first pixel circuit is connected to the third input node of the timing circuit of the second pixel circuit.

[0006] According to another disclosure of the present specification, a photoelectric conversion device is provided, which includes: a plurality of pixel circuits arranged to form a plurality of rows and a plurality of columns; and a control circuit configured to drive the plurality of pixel circuits, wherein the plurality of pixel circuits each include: a signal generating circuit including a photoelectric conversion unit, a memory configured to hold a signal output from the signal generating circuit, and a timing circuit for transmitting the signal from the memory to the timing circuit, wherein the plurality of pixel circuits include a first group and a second group each including two or more pixel circuits arranged in the same row, wherein the timing circuits constituting the pixel circuits of each of the first group and the second group are connected in series along a row direction and are configured to sequentially transmit the signals held by the respective pixel circuits along the row direction from one side to the other side according to a control signal from the control circuit, and wherein the control circuit is configured to perform a signal transmission operation in the pixel circuits of the first group and a signal transmission operation in the pixel circuits of the second group in parallel by supplying a common control signal to the pixel circuits of the first group and the pixel circuits of the second group.

[0007] According to another disclosure of the present specification, a signal output device is provided, which includes: a plurality of signal holding circuits arranged to form a plurality of rows and a plurality of columns; and a control circuit configured to drive the plurality of signal holding circuits, wherein the plurality of signal holding circuits each include: a memory configured to hold a predetermined signal, and a timing circuit that transmits the signal from the memory to the timing circuit, wherein the plurality of signal holding circuits include a first group and a second group each including two or more signal holding circuits arranged in the same row, wherein the timing circuits constituting the signal holding circuits of each of the first group and the second group are connected in series along the row direction, and are configured to sequentially transmit the signals held by each signal holding circuit along the row direction from one side to the other side according to a control signal from the control circuit, and wherein the control circuit is configured to perform the signal transmission operation in the signal holding circuit of the first group and the signal transmission operation in the signal holding circuit of the second group in parallel by supplying a common control signal to the signal holding circuit of the first group and the signal holding circuit of the second group.

[0008] According to another disclosure of the present specification, there is provided a driving method of a photoelectric conversion device, the photoelectric conversion device comprising: a plurality of pixel circuits arranged to form a plurality of rows and a plurality of columns, wherein the plurality of pixel circuits each comprises: a signal generating circuit comprising a photoelectric conversion unit, a memory configured to hold a signal output from the signal generating circuit, and a timing circuit for transmitting the signal from the memory to the timing circuit, wherein the plurality of pixel circuits comprise a first group and a second group each comprising two or more pixel circuits arranged in the same row, and wherein the timing circuits constituting the pixel circuits of each of the first group and the second group are connected in series along a row direction, the driving method comprising : In each of the plurality of pixel circuits, a signal based on the charge generated in the photoelectric conversion unit by the incidence of light is maintained in the memory; in each of the plurality of pixel circuits, the signal maintained in the memory is transmitted to the timing circuit; and the signal maintained by the timing circuit of the pixel circuits constituting each group of the first group and the second group is sequentially transmitted from one side to the other side along the row direction, wherein, in the sequential transmission, a common control signal is supplied to the pixel circuits of the first group and the pixel circuits of the second group, so that the signal transmission operation in the pixel circuits of the first group and the signal transmission operation in the pixel circuits of the second group are performed in parallel.

[0009] Further features of the present invention will become apparent from the following description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram showing a schematic configuration of a signal output device according to a first embodiment of the present invention.

[0011] Figure 2 : is a block diagram showing a configuration example of a signal holding circuit in a signal output device according to a first embodiment of the present invention.

[0012] Figure 3 , Figure 4 , Figure 5 and Figure 6 1 is a block diagram showing a configuration example of a clock buffer circuit in the signal output device according to the first embodiment of the present invention.

[0013] Figure 7 1 is a timing chart showing a driving method of the signal output device according to the first embodiment of the present invention.

[0014] Figure 8 is a circuit diagram showing a schematic configuration of a signal output device according to a second embodiment of the present invention.

[0015] Fig. 9 is a block diagram showing a schematic configuration of a signal output device according to a third embodiment of the present invention.

[0016] Fig.10 is a circuit diagram showing another configuration example of the signal output device according to the third embodiment of the present invention.

[0017] Fig.11 is a block diagram showing a schematic configuration of a photoelectric conversion apparatus according to a fourth embodiment of the present invention.

[0018] Fig.12 is a block diagram showing a schematic configuration of a light detection system according to a fifth embodiment of the present invention.

[0019] Fig.13 is a block diagram showing a schematic configuration of a range image sensor according to a sixth embodiment of the present invention.

[0020] Fig.14 : is a schematic diagram showing a configuration example of an endoscopic surgery system according to a seventh embodiment of the present invention.

[0021] Fig.15A , Fig. 15B and Fig. 15C is a schematic diagram showing an example of the configuration of a movable body according to an eighth embodiment of the present invention.

[0022] Fig.16 is a block diagram showing a schematic configuration of a light detection system according to an eighth embodiment of the present invention.

[0023] Fig.17 is a flowchart showing the operation of the light detection system according to the eighth embodiment of the present invention.

[0024] Fig.18A and Fig.18B is a schematic diagram showing a schematic configuration of a light detection system according to a ninth embodiment of the present invention. DETAILED DESCRIPTION

[0025] Preferred embodiments of the present disclosure will now be described in detail according to the accompanying drawings.

[0026] [First embodiment]

[0027] Reference Figures 1 to 7 A signal output device and a driving method thereof according to a first embodiment of the present invention are described. Figure 1 is a block diagram showing a schematic configuration of a signal output device according to the present embodiment. Figure 2 : is a block diagram showing a configuration example of a signal holding circuit in the signal output device according to the present embodiment. Figures 3 to 6 : is a circuit diagram showing a configuration example of a clock buffer circuit in the signal output device according to the present embodiment. Figure 7 is a timing chart showing a driving method of the signal output device according to the present embodiment.

[0028] First, refer to Figure 1 The schematic configuration of the signal output device according to the present embodiment is described. Figure 1 As shown, the signal output device 50 according to the present embodiment includes a signal holding area 10 and a clock buffer circuit 40 .

[0029] The signal holding area 10 is provided with a plurality of signal holding circuits 12 arranged in a matrix to form a plurality of rows and columns. Figure 1 , it is assumed that the signal holding area 10 is composed of a plurality of signal holding circuits 12 arranged in a matrix of (M rows)×(N columns). The plurality of signal holding circuits 12 are each provided with coordinates corresponding to the row number and the column number. For example, in addition to the reference numeral 12, a block of the signal holding circuits 12 arranged in the mth row and the nth column is also represented by the coordinates (m, n). Here, m is an integer from 1 to M, and n is an integer from 1 to N.

[0030] The number of signal holding circuits 12 constituting the signal holding area 10 is not particularly limited as long as M is an integer greater than 1 and N is an integer greater than 2. Note that rows and columns may be arbitrarily defined, and the rows described in this embodiment may be columns, and the columns described in this embodiment may be rows.

[0031] The N signal holding circuits 12 arranged in each row of the signal holding area 10 constitute a signal holding circuit group 14. Figure 1 , corresponding row numbers are attached to the reference numerals of the signal holding circuit groups 14 of each row. For example, the signal holding circuit group 14 arranged in the mth row is denoted by reference numeral 14 m N signal holding circuits 12 constituting one signal holding circuit group 14 are connected in series. For example, when describing the signal holding circuit group 14 m As an example, the input node of the signal holding circuit 12(m,1) is connected to the ground voltage node, and the output node of the signal holding circuit 12(m,1) is connected to the input node of the signal holding circuit 12(m,2) (not shown). The input node of the signal holding circuit 12(m,n) is connected to the output node of the signal holding circuit 12(m,n-1), and the output node of the signal holding circuit 12(m,n) is connected to the input node of the signal holding circuit 12(m,n+1). The input node of the signal holding circuit 12(m,N) is connected to the output node of the signal holding circuit 12(m,N-1) (not shown), and the output node of the signal holding circuit 12(m,N) is connected to the output line 18. m .

[0032] Signal lines 16 are arranged in columns of signal holding area 10. Figure 1 , the reference numerals of the signal lines 16 of each column are assigned the corresponding column numbers. For example, the signal line 16 arranged in the nth column is denoted by the reference numeral 16 n The signal lines 16 are each connected to the signal holding circuits 12 arranged in the corresponding columns. For example, the signal lines 16 n The signal line 16 is connected to the signal holding circuits 12 ( 1, n ), . . . , 12 ( m−1, n ), 12 ( m, n ), 12 ( m+1, n ), . . . , 12 ( M, n ) arranged in the n-th column.

[0033] The clock buffer circuit 40 is used as a control circuit for driving the signal holding circuit 12. The clock buffer circuit 40 has one input node to which a clock signal is input, and output nodes TAP corresponding to the number of columns of the signal holding area 10. Figure 1 In FIG. 1 , the reference numerals of the output nodes TAP of each column are assigned the corresponding column numbers. For example, the output nodes TAP arranged in the nth column are denoted by the reference numeral TAP. n The clock signal input to the clock buffer circuit 40 and processed by its internal circuit is output from each output node TAP.

[0034] Despite the Figure 1 The M signal holding circuit groups 141 to 14 M One clock buffer circuit 40 is provided, but the clock buffer circuit 40 may be provided in units of any row. For example, a plurality of signal holding circuit groups 141 to 14 M M clock buffer circuits 40 corresponding to each signal holding circuit group in the embodiment may be provided, or one clock buffer circuit 40 may be provided for every two or more arbitrary number of signal holding circuit groups 14. Reducing the number of clock buffer circuits 40 has the advantage of improving the power efficiency of the entire device.

[0035] Next, we will refer to Figure 2 A configuration example of the signal holding circuit 12 is described. Figure 2 The signal holding circuit groups 14 arranged in adjacent columns among the plurality of signal holding circuits 12 constituting the signal holding area 10 are shown. m The internal circuit configuration and connection relationship of the other signal holding circuits 12 are the same as those of the three signal holding circuits 12(m,n-1), 12(m,n) and 12(m,n+1). Figure 2The internal circuit configuration and connection relationship of the signal holding circuit 12 shown are similar. Although the circuit constituting the signal holding circuit 12 is not particularly limited as long as it has a function of holding a signal, a pixel circuit of a photoelectric conversion device will be described here as an example.

[0036] For example Figure 2 As shown, the signal holding circuit 12 may include a signal generating circuit 24, a memory 26, and a timing circuit 28. The signal generating circuit 24 is connected to the memory 26. The memory 26 is connected to the timing circuit 28. The signal generating circuit 24 includes a photoelectric conversion element, generates a signal corresponding to the incident light on the photoelectric conversion element, and outputs the generated signal to the memory 26. The memory 26 holds the signal input from the signal generating circuit 24, and outputs the held signal to the timing circuit 28 according to an external control signal. The timing circuit 28 is a circuit whose output state is determined by a combination of an external input signal and a held internal state, and may be configured by, for example, a D-type flip-flop having a set terminal.

[0037] The D-type flip-flop with a set terminal includes two input terminals (D terminal and S terminal), a clock input terminal (CK terminal) and an output terminal (Q terminal). When a signal is input to the S terminal, the data output from the Q terminal of the timing circuit 28 is at the level of the signal input to the S terminal regardless of the clock signal input to the CK terminal. When a signal is input to the D terminal, the data output from the Q terminal of the timing circuit 28 changes to the level of the signal input to the D terminal in synchronization with the level transition of the clock signal input to the CK terminal. The clock signal input to the CK terminal can also be referred to as a control signal of the timing circuit 28.

[0038] Note that a D-type flip-flop whose level of a signal output from a Q terminal changes according to the timing of a rising edge (positive edge) of a clock signal is referred to as a positive-edge-triggered D-type flip-flop. A D-type flip-flop whose level of a signal output from a Q terminal changes according to the timing of a falling edge (negative edge) of a clock signal is referred to as a negative-edge-triggered D-type flip-flop. Although the sequential circuit 28 may be configured by any D-type flip-flop, it is assumed here that the sequential circuit 28 is configured by a positive-edge-triggered D-type flip-flop.

[0039] The S terminal of the sequential circuit 28 is connected to the output node of the memory 26. The D terminal of the sequential circuit 28 is connected to the input node 20 of the signal holding circuit 12. The CK terminal of the sequential circuit 28 is connected to the input node 22 of the signal holding circuit 12. The Q terminal of the sequential circuit is connected to the output node 30 of the signal holding circuit 12.

[0040] The N signal holding circuits 12 arranged in the same row and constituting one signal holding circuit group 14 are connected in series as described above. For example, the input node 20 of the signal holding circuit 12 (m, n) is connected to the output node 30 of the signal holding circuit 12 (m, n-1), and the output node 30 of the signal holding circuit 12 (m, n) is connected to the input node 20 of the signal holding circuit 12 (m, n+1). The signal line 16 arranged in the corresponding column is connected to the input node 22 of the signal holding circuit 12. For example, the input node 22 of the signal holding circuit 12 (m, n) is connected to the signal line 16 n , the signal line 16 n connected to the output node TAP of the clock buffer circuit 40 n Thus, a series connection body of the sequential circuits 28 included in the signal holding circuits 12 of each column of one signal holding circuit group 14 constitutes a shift register.

[0041] It can also be said that the signal holding circuit group 14 of each row has one input node and one output node as a whole. For example, the input node 20 of the signal holding circuit 12 (m, 1) can be the signal holding circuit group 14. m The input node of the signal holding circuit 12 (m, N) and the output node 30 of the signal holding circuit group 14 can be m Although the input node 20 of the signal holding circuit 12(m,1) is connected to Figure 1 However, any logic signal can be input from the input node 20 of the signal holding circuit 12 (m, 1).

[0042] Next, we will refer to Figures 3 to 6 A configuration example of the clock buffer circuit 40 is described.

[0043] As described above, the clock buffer circuit 40 includes one input node CIN and N output nodes TAP1 to TAP2 corresponding to the number of columns constituting the signal holding area 10. N The clock signal is input to the input node CIN, and the clock signal formed by the internal circuit is output from the output node TAP1 to TAP N Output. Figures 3 to 6 As shown, the clock buffer circuit 40 may include a plurality of buffer circuits 42 or a plurality of inverting buffer circuits 46. The clock buffer circuit 40 may be configured by a buffer structure such as a tree type or a repeater type, and it is assumed here that the clock buffer circuit has a tree type buffer structure.

[0044] exist Figure 3In the clock buffer circuit 40 shown, N buffer circuits 42 corresponding to the number of columns constituting the signal holding area 10 are connected in series. The output nodes of the N buffer circuits 42 become the output node TAP of the clock buffer circuit 40 in order from the side close to the input node CIN. N 、TAP N-1 、……、TAP n+1 、TAP n 、TAP n-1 ,…,TAP2 and TAP1.

[0045] Figure 4 The clock buffer circuit 40 shown is a configuration example in which a logic circuit 44 is connected between the output node TAP of each column and the output node of the buffer circuit 42. Here, the logic circuit 44 is a circuit such as a buffer or an inverter for improving the bluntness of the voltage waveform. That is, by providing the logic circuit 44, the output nodes TAP1 to TAP2 can be reduced. N The dependency between the voltage waveform and the output impedance of the buffer circuit 42 can be improved, and the degree of freedom in circuit design can be increased.

[0046] exist Figure 5 In the clock buffer circuit 40 shown in FIG. 1 , the buffer circuit 42 is replaced by an inverting buffer circuit 46. The clock buffer circuit 40 does not necessarily have to be configured by a non-inverting buffer circuit, but can be configured by an inverting buffer circuit. The inverting buffer circuit 46 can be applied to Figure 4 Configuration example for .

[0047] Figure 6 The clock buffer circuit 40 shown includes (N / 2) buffer circuits 42 connected in series, where N is the number of columns constituting the signal holding area 10. The two output nodes TAP of the clock buffer circuit 40 are connected to the output nodes of the respective buffer circuits 42 of the (N / 2) buffer circuits 42. For example, the output node of the buffer circuit 42 arranged at the position closest to the input node CIN is connected to the output node TAP. N and TAP N-1 The output node of the (N / 2)th buffer circuit 42 from the input node CIN is connected to the output nodes TAP2 and TAP1. At the same timing, clock pulses are output from the two output nodes TAP connected to the output nodes of the same buffer circuit 42. Although an example in which two output nodes TAP are connected to the output nodes of the same buffer circuit 42 is described here, three or more output nodes TAP may be connected to the output nodes of the same buffer circuit 42.

[0048] This configuration can also be applied to Figure 4 or Figure 5 Configuration example for .

[0049] Although the input node CIN of the clock buffer circuit 40 may be set on the first column side of the signal holding circuit group 14, from the viewpoint of timing design controllability, as shown in FIG. Figures 3 to 6 As shown, it is more preferable to set the input node CIN on the N-th column side of the signal holding circuit group 14. In this case, for example, the number of buffer circuits 42 through which the clock signal supplied to the sequential circuit 28 of the signal holding circuit 12 of the (n-1)-th column passes is greater than the number of buffer circuits 42 through which the clock signal supplied to the sequential circuit 28 of the signal holding circuit 12 of the n-th column passes.

[0050] Next, we will refer to Figure 7 The operation of the signal output device according to the present embodiment is described. Figure 7 The operation of the signal output device in the Jth frame and the (J+1)th frame is schematically shown. The period from time t0 to time t2 is the Jth frame period, and the period from time t2 to time t4 is the (J+1)th frame period.

[0051] The period from time t1 to time t2 is the exposure period of the Jth frame. When light is incident on the signal holding area 10 during the exposure period, the signal generating circuit 24 of each signal holding circuit 12 generates a logic signal of logic H or logic L corresponding to the incident light, and outputs the generated logic signal to the memory 26. The logic signal output from the signal generating circuit 24 is stored in the memory 26. The logic signal stored in the memory 26 during the exposure period of the Jth frame is read out during the next (J+1)th frame period.

[0052] After determining the logic signal of the signal generating circuit 24 of each signal holding circuit 12 at time t2, the memory 26 of each signal holding circuit 12 outputs the held logic signal to the S terminal of the sequential circuit 28 according to the control signal from the control circuit (not shown). As a result, the logic signal transmitted from the memory 26 is held in the sequential circuit 28 as its output.

[0053] In the period from time t3 to time t4 after the transfer of the logic signal from the memory 26 in each signal holding circuit 12 to the timing circuit 28 is completed, the control circuit (not shown) inputs a predetermined number or more of clock pulses from the input node CIN of the clock buffer circuit 40. As a result, at a predetermined timing corresponding to the input timing of the clock pulse to the input node CIN and the number of buffer circuits 42 up to the respective output nodes TAP, a clock pulse is output from the respective output nodes TAP of the clock buffer circuit 40. The number of clock pulses input to the clock buffer circuit 40 (the predetermined number or more of clock pulses described above) may be equal to or greater than (N-1), where N is the number of signal holding circuits 12 included in the signal holding circuit group 14 (the number of columns).

[0054] The sequential circuits 28 of the signal holding circuits 12 of the columns constituting the signal holding circuit group 14 are driven by the clock pulses output from the corresponding output nodes TAP of the clock buffer circuit 40. The sequential circuits 28 transmit the logic signal set each time the clock pulse is received to the subsequent sequential circuits 28. For example, in response to the input of the clock pulse to the signal holding circuit 12(m,n), the logic signal set in the sequential circuit 28 of the signal holding circuit 12(m,n) is set in the sequential circuit 28 of the subsequent signal holding circuit 12(m,n+1). In addition, in response to the input of the clock pulse to the signal holding circuit 12(m,n-1), the logic signal set in the sequential circuit 28 of the signal holding circuit 12(m,n-1) is set in the sequential circuit 28 of the subsequent signal holding circuit 12(m,n). As a result, the logic signals held in the signal holding circuits 12 of each column are sequentially transmitted to the output line 18 side, and a number of logic signals corresponding to the number of clock pulses input to the clock buffer circuit 40 are output to the output line 18 of the signal holding circuit group 14 as a bit stream.

[0055] In this way, by inputting a number of clock pulses corresponding to the number of signal holding circuits 12 constituting each signal holding circuit group 14, the bit stream of the signal holding circuit group 14 of all rows can be output. That is, the data of all signal holding circuits 12 constituting the signal holding area 10 can be read out and output to a device (not shown) at a subsequent stage. For example, in the case where the signal holding area 10 is configured by the signal holding circuits 12 arranged in a matrix of (1000 rows) × (1000 columns), 1M bits of information held in the signal holding area 10 can be read out by inputting clock pulses 999 times, and the readout time can be shortened.

[0056] From output node TAP1 to TAP N The phases of the output clock pulses are different from each other, and the timing at which the sequential circuit 28 of the signal holding circuit 12 of each column sends the logic signal to the subsequent stage is also different from each other in time. n The phase of the output clock pulse is relative to the output node TAP. N The phase of the output clock pulse is delayed. As a result, the driving timing of the timing circuit 28 of the signal holding circuit 12 of the nth column becomes later than the driving timing of the timing circuit 28 of the signal holding circuit 12 of the Nth column. Therefore, the power bounce generated by the read operation of the logic signal from the signal holding area 10 is the superposition of small voltage peaks with different phases over the entire read time. Since the intensity of the power bounce is spread over time, it is possible to reduce the obstacles to the high-speed read operation.

[0057] Furthermore, when the input node CIN of the clock buffer circuit 40 is on the N-th column side of the signal holding area 10, it is easy to control the timing of the phase of the clock signal input by the control circuit (not shown) and the phase of the bit stream output from the signal holding circuit group 14. The ability to relax the constraints on timing in terms of design is an advantage in the high speed of the read operation.

[0058] The transfer period for outputting the logic signal acquired during the exposure period of the Jth frame can be performed in parallel with the exposure period of the next frame (the (J+1)th frame). This makes it possible to further increase the readout speed.

[0059] As described above, according to the present embodiment, in a photoelectric conversion apparatus including a plurality of pixel circuits, the time required to read out pixel signals can be reduced.

[0060] [Second embodiment]

[0061] Reference Figure 8 A signal output device and a driving method thereof according to a second embodiment of the present invention are described. The same components as those of the signal output device according to the first embodiment are denoted by the same reference numerals, and descriptions thereof will be omitted or simplified. Figure 8 is a circuit diagram showing a schematic configuration of a signal output device according to the present embodiment.

[0062] Reference Figure 8 A schematic configuration of a signal output device according to the present embodiment is described. Figure 8 The clock buffer circuit 40 and the signal holding circuit 12 constituting the signal holding area 10 are arranged in the signal holding circuit group 14. m The corresponding parts of the two signal holding circuits 12 (m, n) and 12 (m, n+1) in adjacent columns.

[0063] In the signal output device according to the present embodiment, the configuration of the timing circuit 28 in the signal holding circuit 12 arranged in the adjacent columns of the same row is different. Specifically, one of the two adjacent signal holding circuits 12 is configured by using a positive edge triggered D-type flip-flop (timing circuit 28P), and the other is configured by using a negative edge triggered D-type flip-flop (timing circuit 28N). For example, in the case where the signal holding circuit 12 (m, n) is configured by the positive edge triggered timing circuit 28P, the signal holding circuit 12 (m, n-1) and the signal holding circuit 12 (m, n+1) are configured by the negative edge triggered timing circuit 28N. The clock buffer circuit 40 is configured by the inverting buffer circuit 46 so as to adapt to the clock drive suitable for the operation of the timing circuits 28P and 28N.

[0064] Here, it is assumed that the signal generating circuit 24 is a SPAD (Single Photon Avalanche Diode) circuit, and outputs a logic signal of logic H when incident light is detected. Figure 8 As shown, the signal generating circuit 24 may include an avalanche photodiode PD, a quenching element Mq, a waveform shaping circuit INV, and a logic circuit AND1.

[0065] The voltage Vbias1 is supplied to the cathode of the avalanche photodiode PD via the quenching element Mq, and the voltage Vbias2 is supplied to the anode of the avalanche photodiode PD. The input node of the waveform shaping circuit INV is connected to the connection node between the cathode of the avalanche photodiode PD and the quenching element Mq. The output node of the waveform shaping circuit INV is connected to one input node of the logic circuit AND1, and the control signal sel is supplied from the control circuit (not shown) to the other input node of the logic circuit AND1. The output node of the logic circuit AND1 is the output node of the signal generating circuit 24.

[0066] When light is incident on the avalanche photodiode PD in a state where a reverse bias voltage corresponding to the potential difference between the voltage Vbias1 and the voltage Vbias2 is applied, electron-hole pairs are generated by photoelectric conversion, and an avalanche current flows using the charge as a seed. The waveform shaping circuit INV shapes the voltage change caused by the avalanche current flowing through the avalanche photodiode PD into a pulse signal, and outputs a logic signal of logic H corresponding to the light incidence. When both the output signal of the waveform shaping circuit INV and the control signal sel are logic H, the logic circuit AND1 outputs a logic signal of logic H.

[0067] For example Figure 8 As shown, the memory 26 may include an RS flip-flop circuit FF and a logic circuit AND2. The RS flip-flop circuit FF includes two input terminals (S terminal and R terminal) and one output terminal (Q terminal). The S terminal of the RS flip-flop circuit FF is connected to the output node of the signal generating circuit 24, and the Q terminal of the RS flip-flop circuit FF is connected to one input node of the logic circuit AND2. The R terminal of the RS flip-flop circuit FF is supplied with a control signal clear from a control circuit (not shown), and the other input nodes of the logic circuit AND2 are supplied with a control signal WRT from a control circuit (not shown). The output node of the logic circuit AND2 is the output node of the memory 26.

[0068] The RS flip-flop circuit FF has bistable properties, and when receiving a logic signal of logic H from the signal generating circuit 24, the RS flip-flop circuit FF holds the logic signal of logic H and outputs the logic signal from the Q terminal. When the RS flip-flop circuit FF receives a control signal clear of logic H from a control circuit (not shown), the RS flip-flop circuit FF resets the held logic signal. When both the output signal of the RS flip-flop circuit FF and the control signal WRT are logic H, the logic circuit AND2 outputs a logic signal of logic H.

[0069] The configuration and operation of the sequential circuits 28P and 28N are as described in the first embodiment. That is, the sequential circuit 28P can be configured by a positive edge triggered D-type flip-flop circuit, and the sequential circuit 28N can be configured by a negative edge triggered D-type flip-flop circuit. In the sequential circuits 28P and 28N, when the output of the memory 26 is logic H, the output of the Q terminal becomes logic H in response to a control signal at an appropriate timing from a control circuit (not shown).

[0070] Before this appropriate timing, the Q terminals of the timing circuits 28 of all the signal holding circuits 12 constituting the signal holding circuit group 14 must be logic L. This can be achieved by inputting clock pulses equal to or greater than the number of the signal holding circuits 12 constituting the signal holding circuit group 14 to the input node CIN of the clock buffer circuit 40 while fixing the input nodes of the signal holding circuit group 14 to logic L.

[0071] In the signal output device according to the present embodiment, the design of the clock buffer circuit 40 and the timing circuits 28P and 28N becomes simple, and the circuit area and power consumption can be reduced. In addition, even when the output driving force of the inverting repetitive buffer of the clock buffer circuit 40 is unbalanced at the rising edge and the falling edge of the signal, the driving force imbalance is offset during the repetitive inverted propagation. As a result, the adverse effect of the reduction or expansion of the duty cycle of the voltage waveform on the tap propagation to the upstream side of the signal holding circuit 12 can be alleviated. The reduction in area and power consumption and the improvement in the design of the buffer circuit are advantageous for accelerating the readout operation.

[0072] As described above, according to the present embodiment, in a photoelectric conversion apparatus including a plurality of pixel circuits, the time required to read out pixel signals can be reduced.

[0073] [Third embodiment]

[0074] Reference Fig. 9 and Fig.10 The same components as those of the signal output device according to the first or second embodiment are denoted by the same reference numerals, and description thereof will be omitted or simplified. Fig. 9 is a block diagram showing a schematic configuration of a signal output device according to the present embodiment. Fig.10 is a circuit diagram showing a configuration example of a signal output device according to the present embodiment.

[0075] Fig. 9 The plurality of signal holding circuits 12 constituting a row among the constituent elements of the signal output device according to the present embodiment are shown. In the present embodiment, the plurality of signal holding circuits 12 constituting a row (for example, the mth row) are divided into two signal holding circuit groups 14A. m and 14B m The signal holding circuit 12 is divided into two signal holding circuit groups 14A. m and 14B m The method of is not particularly limited, but for example, the signal holding circuits 12 may be alternately assigned to the signal holding circuit groups 14A in units of a predetermined number of columns. m and 14B m When the signal holding circuits 12 are alternately assigned to the signal holding circuit group 14A every two columns m and 14B m When, for example Fig. 9 As shown, the signal holding circuits 12(m,1), 12(m,2), . . . , 12(m,N-3) and 12(m,N-2) may be assigned to the signal holding circuit group 14A. m In addition, the signal holding circuits 12(m,3), 12(m,4), ..., 12(m,N-1), and 12(m,N) may be assigned to the signal holding circuit group 14B. m The signal holding circuit 12 sends a signal to the signal holding circuit group 14A. m and 14B m The allocation may be performed for each column or for a predetermined number of columns of three or more. The plurality of signal holding circuits 12 constituting one row may be divided into three or more signal holding circuit groups 14.

[0076] Output lines 18 arranged in rows m is divided into a signal holding circuit group 14A m and 14B m Corresponding output line 18A m and 18B m The clock buffer circuit 40 is used for the signal holding circuit group 14A. m and 14B m is common, and as in the first embodiment, is configured to input the clock signal output from each output node TAP to the signal holding circuit 12 of the corresponding column. m The signal of the signal holding circuit 12 is read out to the output line 18Am , and the signal holding circuit group 14B m The signal of the signal holding circuit 12 is read out to the output line 18B m Can be done in parallel.

[0077] Fig.10 1 shows a part of the sequential circuit 28 constituting a plurality of signal holding circuits 12 in two rows (the mth row and the (m+1)th row) among the components of the signal output device according to the present embodiment. Fig.10 In the configuration example, the signal holding circuit 12 including the timing circuit 28P and the signal holding circuit 12 including the timing circuit 28N are alternately arranged every four columns, and a common clock signal is input to every four columns. A plurality of signal holding circuits 12 in each row are alternately allocated to the signal holding circuit groups 14A and 14B for each column. For example, the signal holding circuits 12 arranged in the odd columns belong to the signal holding circuit group 14A, and the signal holding circuits 12 arranged in the even columns belong to the signal holding circuit group 14B.

[0078] In the present embodiment, the number of signal holding circuits 12 included in each of the signal holding circuit groups 14A and 14B is half the number of signal holding circuits 12 included in the signal holding circuit group 14 of the first embodiment or the second embodiment. In addition, reading out the signal from the signal holding circuit group 14A and reading out the signal from the signal holding circuit group 14B can be performed in parallel without newly replacing the clock buffer circuit 40. Therefore, according to the present embodiment, the readout time of the signal from the signal holding circuit 12 of each row can be reduced to half compared with the signal output device according to the first embodiment or the second embodiment. In addition, in the present embodiment, the number of clock pulses required to read out the signal from the plurality of signal holding circuits 12 constituting a row is also halved. As a result, the power consumption of the circuit in the signal processing can be reduced.

[0079] As described above, according to the present embodiment, in a photoelectric conversion apparatus including a plurality of pixel circuits, the time required to read out pixel signals can be reduced.

[0080] [Fourth embodiment]

[0081] Reference Fig.11 A photoelectric conversion device according to a fourth embodiment of the present invention is described. The same components as those of the signal output device according to the first to third embodiments are denoted by the same reference numerals, and description thereof will be omitted or simplified. Fig.11 is a block diagram showing a schematic configuration of a photoelectric conversion device according to the present embodiment.

[0082] In this embodiment, an example in which the configuration of the signal output device according to the first embodiment is applied to a photoelectric conversion device will be described. Although an example in which the signal output device according to the first embodiment is applied is described here, the signal output device according to the second embodiment or the third embodiment may be similarly applied. The configuration of the signal output device according to the first to third embodiments is applicable not only to a photoelectric conversion device but also to various devices configured to output signals from a plurality of signal holding units.

[0083] For example Fig.11 As shown, the photoelectric conversion device 100 according to the present embodiment may include a pixel area 110 , a vertical driving circuit 120 , a control circuit 130 , a clock buffer circuit 140 , a signal processing circuit 150 , and an output circuit 160 .

[0084] The pixel area 110 is provided with a plurality of pixels 112 arranged in an array to form a plurality of rows and columns. Each pixel 112 is a functional block corresponding to the signal holding circuit 12 of the first to third embodiments, and may include a photoelectric conversion unit including a photoelectric conversion element and a pixel signal processing unit for processing a signal output from the photoelectric conversion unit. The number of pixels 112 included in the pixel area 110 is not particularly limited. For example, as in a general digital camera, the pixel area 110 may be composed of a plurality of pixels 112 arranged in an array of thousands of rows × thousands of columns. Alternatively, the pixel area 110 may include a plurality of pixels 112 arranged in a row or a column.

[0085] In each row of the pixel array of the pixel region 110, the control lines 114 are arranged in a first direction ( Fig.11 The control lines 114 extend in a lateral direction in the horizontal direction of the pixel 112. Each of the control lines 114 is connected to the pixels 112 arranged in the first direction on the corresponding row, and forms a signal line common to these pixels 112. The first direction in which the control lines 114 extend may be referred to as a row direction or a horizontal direction. Each of the control lines 114 may include a plurality of signal lines for supplying a plurality of types of control signals to the pixel 112. The control lines 114 of each row are connected to the vertical drive circuit 120. The control signals supplied from the vertical drive circuit 120 to the pixel 112 may include, for example, the control signals sel, clear, and WRT described in the second embodiment.

[0086] Pixels 112 arranged in each row of the pixel array of the pixel area 110 are connected in series in the first direction. Output lines 118 are connected to output nodes of pixels 112 located at the ends of each row in the first direction. Output lines 118 of each row are connected to the signal processing circuit 150.

[0087] In each column of the pixel array of the pixel region 110, the signal lines 116 are arranged in a second direction ( Fig.11 Each of the signal lines 116 is connected to the pixels 112 arranged in the second direction on the corresponding column, and forms a signal line common to these pixels 112.

[0088] The second direction in which the signal lines 116 extend may be referred to as a column direction or a vertical direction. The signal lines 116 of each column are connected to the clock buffer circuit 140 .

[0089] Similar to the clock buffer circuits in the first to third embodiments, the clock buffer circuit 140 has a function of supplying a clock pulse to the pixels 112 of each column at a predetermined timing.

[0090] The signal processing circuit 150 is a functional block for performing predetermined signal processing on pixel signals output from the output line 118 of each row. The signal processing performed by the signal processing circuit 150 is not particularly limited, and examples of the signal processing include correction processing, binning processing, and addition averaging processing.

[0091] The output circuit 160 includes an external interface circuit, and is a functional block for outputting the pixel signal processed by the signal processing circuit 150 to the outside of the photoelectric conversion device 100. There is no particular limitation on the external interface circuit included in the output circuit 160. As the external interface circuit, for example, a SerDes (serializer / deserializer) transmission circuit such as an LVDS (low voltage differential signal) circuit or an SLVS (scalable low voltage signal) circuit can be applied.

[0092] The control circuit 130 is a control circuit for generating a control signal for controlling the operation and timing of the vertical drive circuit 120, the clock buffer circuit 140, and the signal processing circuit 150 and supplying the control signal to each functional block. At least a part of the control signal for controlling the operation and timing of the vertical drive circuit 120, the clock buffer circuit 140, and the signal processing circuit 150 may be supplied from the outside of the photoelectric conversion device 100. The control signal supplied from the control circuit 130 to the clock buffer circuit 140 may include the clock signal described in the first to third embodiments.

[0093] As described above, according to the present embodiment, by applying the signal output device according to the first to third embodiments, a photoelectric conversion device capable of high-speed readout of pixel signals can be realized.

[0094] [Fifth embodiment]

[0095] Reference Fig.12 A light detection system according to a fifth embodiment of the present invention is described. Fig.12 1 is a block diagram showing a schematic configuration of a light detection system according to the present embodiment. In the present embodiment, a light detection sensor to which the photoelectric conversion device 100 according to the fourth embodiment is applied will be described.

[0096] The photoelectric conversion device 100 described in the fourth embodiment is applicable to various light detection systems. Examples of applicable light detection systems include imaging systems such as digital still cameras, digital video cameras, surveillance cameras, copiers, fax machines, mobile phones, vehicle-mounted cameras, and observation satellites. A camera module including an optical system such as a lens and an imaging device is also included in the light detection system. Fig.12 A block diagram of a digital still camera is illustrated as one of these light detection systems.

[0097] Fig.12 The light detection system 200 shown includes a photoelectric conversion device 201, a lens 202 that forms an optical image of a subject on the photoelectric conversion device 201, an aperture 204 for changing the amount of light passing through the lens 202, and a baffle 206 for protecting the lens 202. The lens 202 and the aperture 204 form an optical system for focusing light on the photoelectric conversion device 201. The photoelectric conversion device 201 is the photoelectric conversion device 100 described in the fourth embodiment, and converts the optical image formed by the lens 202 into image data.

[0098] The light detection system 200 also includes a signal processing unit 208 for processing an output signal output from the photoelectric conversion device 201. The signal processing unit 208 generates image data based on the digital signal output from the photoelectric conversion device 201. In addition, the signal processing unit 208 performs various corrections and compressions as needed, and outputs the processed image data. The photoelectric conversion device 201 may include an AD conversion unit for generating a digital signal to be processed by the signal processing unit 208. The AD conversion unit may be formed on a semiconductor layer (semiconductor substrate) on which the photoelectric conversion element of the photoelectric conversion device 201 is formed, or may be formed on a semiconductor layer different from the semiconductor layer on which the photoelectric conversion element of the photoelectric conversion device 201 is formed. The signal processing unit 208 may be formed on the same semiconductor layer as the photoelectric conversion device 201.

[0099] The light detection system 200 also includes a memory unit 210 for temporarily storing image data and an external interface unit (external I / F unit) 212 for communicating with an external computer or the like. In addition, the light detection system 200 includes a storage medium 214 such as a semiconductor memory for storing or reading out the image data, and a storage medium control interface unit (storage medium control I / F unit) 216 for storing on or reading out from the storage medium 214. The storage medium 214 may be built into the light detection system 200 or may be detachable. The communication between the storage medium control I / F unit 216 and the storage medium 214 and the communication from the external I / F unit 212 may be performed wirelessly.

[0100] The light detection system 200 also includes a general control / operation unit 218 for performing various calculations and controlling the entire digital still camera, and a timing generation unit 220 for outputting various timing signals to the photoelectric conversion device 201 and the signal processing unit 208. Here, the timing signal and the like may be input from the outside, and the light detection system 200 may include at least the photoelectric conversion device 201 and the signal processing unit 208 for processing an output signal output from the photoelectric conversion device 201. The timing generation unit 220 may be mounted on the photoelectric conversion device 201. In addition, the general control / operation unit 218 and the timing generation unit 220 may be configured to perform part or all of the control function of the photoelectric conversion device 201.

[0101] The photoelectric conversion device 201 outputs the imaging signal to the signal processing unit 208. The signal processing unit 208 performs predetermined signal processing on the imaging signal output from the photoelectric conversion device 201 and outputs processed image data. The signal processing unit 208 generates an image using the imaging signal. The signal processing unit 208 may be configured to perform distance measurement calculation on the signal output from the photoelectric conversion device 201.

[0102] As described above, according to the present embodiment, by configuring a light detection system using the photoelectric conversion device according to the fourth embodiment, a light detection system capable of quickly acquiring an image can be realized.

[0103] [Sixth embodiment]

[0104] Reference Fig.13 A range image sensor according to a sixth embodiment of the present invention is described. Fig.13 : is a block diagram showing a schematic configuration of a distance image sensor according to the present embodiment. In the present embodiment, a distance image sensor will be described as an example of a light detection system to which the photoelectric conversion device 100 according to the fourth embodiment is applied.

[0105] like Fig.13As shown, the distance image sensor 300 according to the present embodiment may include an optical system 302, a photoelectric conversion device 304, an image processing circuit 306, a monitor 308, and a memory 310. The distance image sensor 300 receives light (modulated light or pulse light) emitted from a light source device 320 toward a subject 330 and reflected on a surface of the subject 330, and acquires a distance image corresponding to the distance to the subject 330.

[0106] The optical system 302 includes one or more lenses, and has a function of imaging image light (incident light) from the subject 330 on a light receiving surface (sensor unit) of the photoelectric conversion device 304 .

[0107] The photoelectric conversion device 304 is the photoelectric conversion device 100 described in the fourth embodiment, and has a function of generating a distance signal indicating the distance to the subject 330 based on image light from the subject 330 and supplying the generated distance signal to the image processing circuit 306 .

[0108] The image processing circuit 306 has a function of performing image processing for constructing a distance image based on the distance signal supplied from the photoelectric conversion device 304 .

[0109] The monitor 308 has a function of displaying a distance image (image data) obtained by the image processing in the image processing circuit 306. The memory 310 has a function of storing (recording) a distance image (image data) obtained by the image processing in the image processing circuit 306.

[0110] As described above, according to the present embodiment, by configuring a distance image sensor using the photoelectric conversion device according to the fourth embodiment, a distance image sensor capable of quickly acquiring a distance image can be realized.

[0111] [Seventh embodiment]

[0112] Reference Fig.14 An endoscopic surgery system according to a seventh embodiment of the present invention is described.

[0113] Fig.14 : is a schematic diagram showing a configuration example of an endoscopic surgery system according to the present embodiment. In the present embodiment, an endoscopic surgery system will be described as an example of a light detection system to which the photoelectric conversion device 100 according to the fourth embodiment is applied.

[0114] Fig.14 The diagram shows a state in which an operator (surgeon) 460 performs surgery on a patient 472 on a bed 470 using the endoscopic surgery system 400 .

[0115] like Fig.14As shown, the endoscopic surgery system 400 according to the present embodiment may include an endoscope 410, a surgical tool 420, and a cart 430 on which various devices for endoscopic surgery are installed. A CCU (camera control unit) 432, a light source device 434, an input device 436, a processing tool control device 438, a display device 440, etc. may be installed on the cart 430.

[0116] The endoscope 410 includes a barrel 412 inserted into a body cavity of a patient 472 at a predetermined length from a front end thereof, and a camera 414 connected to a base end of the barrel 412. Fig.14 The endoscope 410 is shown as being configured as a so-called rigid scope having a rigid scope barrel 412 , but the endoscope 410 may be configured as a so-called flexible scope having a flexible scope barrel. The endoscope 410 is held in a movable state by an arm 416 .

[0117] The front end of the lens barrel 412 is provided with an opening in which an objective lens is embedded. The light source device 434 is connected to the endoscope 410, and the light generated by the light source device 434 is guided to the front end of the lens barrel 412 through a light guide extending inside the lens barrel 412, and irradiated toward the observation object in the body cavity of the patient 472 through the objective lens. Note that the endoscope 410 may be a straight-view mirror, an oblique mirror, or a side-view mirror.

[0118] An optical system and a photoelectric conversion device (not shown) are provided inside the camera 414 , and reflected light (observation light) from an observation object is collected on the photoelectric conversion device through the optical system.

[0119] The photoelectric conversion device photoelectrically converts the observation light and generates an electric signal corresponding to the observation light (ie, an image signal corresponding to the observation image). As the photoelectric conversion device, the photoelectric conversion device 100 described in the fourth embodiment can be used. The image signal is transmitted to the CCU 432 as RAW data.

[0120] The CCU 432 may be configured by a CPU (Central Processing Unit) and a GPU (Graphics Processing Unit), etc., and integrally controls the operations of the endoscope 410 and the display device 440. In addition, the CCU 432 receives an image signal from the camera 414, and performs various types of image processing such as development processing (demosaic processing) on ​​the image signal for displaying an image based on the image signal.

[0121] The display device 440 displays an image based on the image signal subjected to the image processing by the CCU 432 under the control of the CCU 432 .

[0122] The light source device 434 may be configured by, for example, a light source such as an LED (Light Emitting Diode) or the like, and supplies the endoscope 410 with irradiation light when an image of a surgical site or the like is captured.

[0123] The input device 436 is an input interface for the endoscopic surgery system 400 .

[0124] The user can input various information and instructions to the endoscopic surgery system 400 via the input device 436 .

[0125] The treatment tool control device 438 controls the driving of the energy treatment tool 450 for tissue ablation, incision, blood vessel sealing, etc.

[0126] The light source device 434 that supplies irradiation light to the endoscope 410 when imaging the surgical site can be configured, for example, by a white light source configured by an LED, a laser light source, or a combination thereof. When the white light source is configured by a combination of RGB laser light sources, since the output intensity and output timing of each color (each wavelength) can be controlled with high precision, the white balance of the captured image can be adjusted in the light source device 434. In addition, in this case, it is also possible to capture images corresponding to each RGB in a time-division manner by irradiating the observation object with laser light from each RGB laser light source in a time-division manner and controlling the drive of the imaging element of the camera 414 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter in the image sensor.

[0127] In addition, the driving of the light source device 434 can be controlled so that the intensity of the light to be output is changed every predetermined time. By controlling the driving of the image sensor of the camera 414 in synchronization with the timing of the change in the intensity of the light to acquire images in a time-division manner and synthesize the images, an image with a high dynamic range without so-called dark part loss and highlight overflow can be generated.

[0128] The light source device 434 may be configured to be capable of supplying light of a predetermined wavelength band corresponding to special light observation. In special light observation, for example, the wavelength dependence of light absorption in body tissue is utilized. Specifically, by irradiating a narrow band of light, predetermined tissues such as blood vessels in the surface layer of a mucosa are photographed with high contrast compared to the irradiation light (i.e., white light) during normal observation. Alternatively, in special light observation, fluorescence observation may be performed to obtain an image by using fluorescence generated by irradiation with excitation light. In fluorescence observation, body tissue is irradiated with excitation light to observe fluorescence from the body tissue, or a reagent such as indocyanine green (ICG) is locally injected into the body tissue, and the body tissue is irradiated with excitation light corresponding to the fluorescence wavelength of the reagent to obtain a fluorescent image. The light source device 434 may be configured to be capable of supplying narrow band light and / or excitation light corresponding to such special light observation.

[0129] As described above, according to the present embodiment, by configuring an endoscopic surgery system using the photoelectric conversion device according to the fourth embodiment, an endoscopic surgery system capable of quickly acquiring images can be realized.

[0130] [Eighth Embodiment]

[0131] Reference FIG. 15A to FIG. 17 A light detection system and a movable body according to an eighth embodiment of the present invention are described. FIG. 15A to FIG. 15C is a schematic diagram showing a configuration example of a movable body according to the present embodiment. Fig.16 is a block diagram showing a schematic configuration of a light detection system according to the present embodiment. Fig.17 : is a flowchart showing the operation of the light detection system according to the present embodiment. In the present embodiment, an application example of a vehicle-mounted camera will be described as a light detection system to which the photoelectric conversion device 100 according to the fourth embodiment is applied.

[0132] FIG. 15A to FIG. 15C : is a schematic diagram showing a configuration example of a movable body (vehicle system) according to the present embodiment. FIG. 15A to FIG. 15C A vehicle 500 (automobile) is shown as a configuration of an example of a vehicle system incorporating a light detection system to which the photoelectric conversion device according to the fourth embodiment is applied. Fig.15A is a schematic front view of a vehicle 500, Fig. 15B is a schematic plan view of a vehicle 500, and Fig. 15C 500 is a schematic rear view of a vehicle 500. The vehicle 500 includes a pair of photoelectric conversion devices 502 on its front surface. Here, the photoelectric conversion device 502 is the photoelectric conversion device 100 described in the fourth embodiment. The vehicle 500 includes an integrated circuit 503, an alarm device 512, and a main control unit 513.

[0133] Fig.16 5 is a block diagram showing a configuration example of a light detection system 501 mounted on a vehicle 500. The light detection system 501 includes a photoelectric conversion device 502, an image preprocessing unit 515, an integrated circuit 503, and an optical system 514. The photoelectric conversion device 502 is the photoelectric conversion device 100 described in the fourth embodiment. The optical system 514 forms an optical image of a subject on the photoelectric conversion device 502. The photoelectric conversion device 502 converts the optical image of the subject formed by the optical system 514 into an electrical signal. The image preprocessing unit 515 performs predetermined signal processing on a signal output from the photoelectric conversion device 502. The function of the image preprocessing unit 515 may be included in the photoelectric conversion device 502. At least two groups of the optical system 514, the photoelectric conversion device 502, and the image preprocessing unit 515 are provided in the light detection system 501, and the output from each group of the image preprocessing unit 515 is input to the integrated circuit 503.

[0134] The integrated circuit 503 is an integrated circuit for camera system application, and includes an image processing unit 504, an optical ranging unit 506, a parallax calculation unit 507, an object recognition unit 508, and an abnormality detection unit 509. The image processing unit 504 processes the image signal output from the image preprocessing unit 515. For example, the image processing unit 504 performs image processing such as development processing and defect correction on the output signal of the image preprocessing unit 515. The image processing unit 504 includes a memory 505 for temporarily storing the image signal. The memory 505 can, for example, store the position of a known defective pixel in the photoelectric conversion device 502.

[0135] The optical ranging unit 506 performs focusing and distance measurement of the subject. The parallax calculation unit 507 calculates distance measurement information (distance information) from a plurality of image data (parallax images) acquired by the plurality of photoelectric conversion devices 502. Each photoelectric conversion device 502 may have a configuration capable of acquiring various information such as distance information. The object recognition unit 508 recognizes a subject such as a vehicle, a road, a sign, or a person.

[0136] Upon detecting an abnormality in the photoelectric conversion device 502 , the abnormality detection unit 509 notifies the main control unit 513 of the abnormality.

[0137] The integrated circuit 503 may be implemented by specially designed hardware, may be implemented by a software module, or may be implemented by a combination thereof. In addition, the integrated circuit 503 may be implemented by an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit), or may be implemented by a combination thereof.

[0138] The main control unit 513 integrally controls operations of the light detection system 501 , the vehicle sensor 510 , the control unit 520 , etc. The vehicle 500 may not include the main control unit 513 .

[0139] In this case, the photoelectric conversion device 502, the vehicle sensor 510, and the control unit 520 transmit and receive control signals via a communication network. For example, the CAN (Controller Area Network) standard may be applied to the transmission and reception of control signals.

[0140] The integrated circuit 503 has a function of receiving a control signal from the main control unit 513 or transmitting a control signal and a setting value to the photoelectric conversion device 502 through its own control unit.

[0141] The light detection system 501 is connected to the vehicle sensor 510 and can detect the driving state of the host vehicle such as vehicle speed, yaw rate, and steering angle, the environment outside the host vehicle, and the states of other vehicles and obstacles.

[0142] The vehicle sensor 510 is also a distance information acquisition unit for acquiring distance information to an object. In addition, the light detection system 501 is connected to a driving support control unit 511 for performing various driving supports such as automatic steering, automatic driving, and collision avoidance functions. In particular, with respect to the collision judgment function, the driving support control unit 511 estimates a collision with another vehicle or obstacle, and judges whether there is a collision with another vehicle or obstacle based on the detection results of the light detection system 501 and the vehicle sensor 510. Thus, avoidance control when a collision is estimated and activation of a safety device at the time of a collision are performed.

[0143] The light detection system 501 is also connected to an alarm device 512 for issuing an alarm to the driver based on the judgment result of the collision judgment unit. For example, when the judgment result of the collision judgment unit is that the possibility of collision is high, the main control unit 513 performs vehicle control for avoiding collision and reducing damage by applying brakes, returning the accelerator, or suppressing engine output, etc. The alarm device 512 warns the user by issuing an alarm such as sound, displaying an alarm message on a display screen of a car navigation system or an instrument panel, etc., or vibrating a seat belt or a steering wheel.

[0144] In this embodiment, an image of the surrounding environment (eg, the front or rear) of the vehicle is captured by the light detection system 501 . Fig. 15B An arrangement example of the light detection system 501 in the case where the light detection system 501 captures an image in front of a vehicle is shown.

[0145] As described above, the photoelectric conversion device 502 is arranged in front of the vehicle 500. Specifically, preferably, the center line relative to the forward / reverse direction or the outer shape (such as the width of the vehicle) of the vehicle 500 is regarded as a symmetry axis, and the two photoelectric conversion devices 502 are symmetrically arranged relative to the symmetry axis, so as to obtain the distance information between the vehicle 500 and the object to be photographed and judge the possibility of collision. In addition, the photoelectric conversion device 502 is preferably configured so as not to interfere with the driver's field of vision when the driver visually recognizes the situation outside the vehicle 500 from the driver's seat. The alarm device 512 is preferably configured to easily enter the driver's field of vision.

[0146] Next, we will refer to Fig.17 The fault detection operation of the photoelectric conversion device 502 in the optical detection system 501 is described. The fault detection operation of the photoelectric conversion device 502 can be performed according to Fig.17 Steps S110 to S180 are performed as shown.

[0147] Step S110 is a step of performing settings at the start-up of the photoelectric conversion device 502. That is, settings for the operation of the photoelectric conversion device 502 are transmitted from the outside of the light detection system 501 (for example, the main control unit 513) or the inside of the light detection system 501, and the imaging operation and the fault detection operation of the photoelectric conversion device 502 are started.

[0148] Next, in step S120, a pixel signal is acquired from the effective pixel. In step S130, an output value from a fault detection pixel set for fault detection is acquired. The fault detection pixel includes a photoelectric conversion element in the same manner as the effective pixel. A predetermined voltage is written into the photoelectric conversion element. The fault detection pixel outputs a signal corresponding to the voltage written into the photoelectric conversion element. Note that step S120 and step S130 may be reversed.

[0149] Next, in step S140, the output expected value of the fault detection pixel and the actual output value from the fault detection pixel are classified. As a result of the classification in step S140, when the output expected value is consistent with the actual output value, the process proceeds to step S150, it is determined that the camera operation is normally performed, and the processing step proceeds to step S160. In step S160, the pixel signal of the scan line is transferred to the memory 505 and is temporarily stored. Thereafter, the process returns to step S120 to continue the fault detection operation. On the other hand, as a result of the classification in step S140, when the output expected value is inconsistent with the actual output value, the process proceeds to step S170. In step S170, it is determined that there is an abnormality in the camera operation, and an alarm is notified to the main control unit 513 or the alarm device 512. The alarm device 512 causes the display unit to display that an abnormality has been detected. Thereafter, in step S180, the photoelectric conversion device 502 is stopped, and the operation of the light detection system 501 is ended.

[0150] In the present embodiment, an example in which the flowchart loops for each row is described, but the flowchart may loop for each plurality of rows, or the failure detection operation may be performed for each frame. The alarm of step S170 may be notified to the outside of the vehicle via a wireless network.

[0151] In addition, in the present embodiment, the control in which the own vehicle does not collide with other vehicles is described, but the present invention can also be applied to the control in which the own vehicle follows other vehicles and performs automatic driving and the control in which the vehicle performs automatic driving in a manner not to protrude from the lane, etc. In addition, the light detection system 501 is not limited to vehicles such as the own vehicle, and can be applied to other movable bodies (mobile devices) such as ships, airplanes, or industrial robots, for example. In addition, the present invention is not limited to movable bodies, and can be widely applied to equipment using object recognition such as ITS (Intelligent Transport System).

[0152] [Ninth Embodiment]

[0153] Reference Fig.18A and Fig.18B A light detection system according to a ninth embodiment of the present invention is described. Fig.18A and Fig.18B : is a schematic diagram showing a configuration example of the light detection system according to the present embodiment. In the present embodiment, an application example to glasses (smart glasses) will be described as a light detection system to which the photoelectric conversion device 100 according to the fourth embodiment is applied.

[0154] Fig.18A A pair of glasses 600 (smart glasses) according to one application example is shown. The glasses 600 include a lens 601 , a photoelectric conversion device 602 , and a control device 603 .

[0155] The photoelectric conversion device 602 is the photoelectric conversion device 100 described in the fourth embodiment, and is provided on the lens 601. One photoelectric conversion device 602 may be provided, or a plurality of photoelectric conversion devices may be provided. When a plurality of photoelectric conversion devices 602 are used, a combination of a plurality of types of photoelectric conversion devices 602 may be used. The arrangement position of the photoelectric conversion device 602 is not limited to Fig.18A A display device (not shown) including a light emitting device such as an OLED (Organic Light Emitting Diode) or an LED (Light Emitting Diode) may be provided on the back side of the lens 601 .

[0156] The control device 603 functions as a power source for supplying power to the photoelectric conversion device 602 and the display device. The control device 603 has a function of controlling the operation of the photoelectric conversion device 602 and the display device. The lens 601 is provided with an optical system for focusing light on the photoelectric conversion device 602.

[0157] Fig.18B Glasses 610 (smart glasses) according to another application example are shown. The glasses 610 include lenses 611 and a control device 612. A photoelectric conversion device (not shown) and a display device corresponding to the photoelectric conversion device 602 may be mounted on the control device 612.

[0158] The lens 611 is provided with a photoelectric conversion device in a control device 612 and an optical system for projecting light from a display device, and an image is projected on the lens 611. The control device 612 serves as a power source for supplying power to the photoelectric conversion device and the display device, and has a function of controlling the operation of the photoelectric conversion device and the display device.

[0159] The control device 612 may also include a line of sight detection unit for detecting the line of sight of the wearer. In this case, an infrared light emitting unit is provided in the control device 612, and the infrared light emitted from the infrared light emitting unit can be used for line of sight detection. Specifically, the infrared light emitting unit emits infrared light to the eyeball of the user who is viewing the displayed image. A captured image of the eyeball is obtained by detecting the reflected light of the emitted infrared light from the eyeball by a camera unit having a light receiving element. By providing a reduction unit for reducing light from the infrared light emitting unit in the plan view to the display unit, degradation of image quality can be reduced.

[0160] The line of sight of the user relative to the displayed image can be detected from a captured image of the eyeball obtained by capturing infrared light. Any known technology can be applied to line of sight detection using a captured image of the eyeball. As an example, a line of sight detection method based on a Purkinje image caused by reflection of irradiated light on the cornea can be used. More specifically, a line of sight detection process based on a pupil-corneal reflection method is performed. The line of sight of the user can be detected by calculating a line of sight vector representing the orientation (rotation angle) of the eyeball based on an image of the pupil and a Purkinje image included in the captured image of the eyeball using the pupil-corneal reflection method.

[0161] The display device according to the present embodiment may include a photoelectric conversion device having a light receiving element, and may be configured to control a display image based on the line of sight information of the user from the photoelectric conversion device. Specifically, the display device determines a first viewing area that the user is gazing at and a second viewing area other than the first viewing area based on the line of sight information. The first viewing area and the second viewing area may be determined by a control device of the display device, or may be determined by an external control device. When the determination is made by an external control device, the determination result is transmitted to the display device via communication. In the display area of ​​the display device, the display resolution of the first viewing area may be controlled to be higher than the display resolution of the second viewing area. That is, the resolution of the second viewing area may be lower than the resolution of the first viewing area.

[0162] The display area may include a first display area and a second display area different from the first display area, and a zone with a high priority may be determined from the first display area and the second display area based on line of sight information. The first display area and the second display area may be determined by a control device of the display device, or may be determined by an external control device. When the determination is made by the external control device, the determination result is transmitted to the display device via communication. The resolution of the high priority zone may be controlled to be higher than the resolution of the zone other than the high priority zone. That is, the resolution of the zone with a relatively low priority may be reduced.

[0163] Note that AI (artificial intelligence) can be used to determine the first viewing area or an area with high priority. AI can be a model configured to use an image of the eyeball and the direction of the image of the eyeball actually viewing the eyeball as teacher data to estimate the angle of sight and the distance to the target object in front of the sight from the image of the eyeball. The AI ​​program can be included in a display device, a photoelectric conversion device, or an external device. When the external device has information, the information is transmitted to the display device via communication.

[0164] In the case of performing display control based on visual recognition detection, the present invention can be preferably applied to smart glasses further including a photoelectric conversion device for capturing an image of the outside world. The smart glasses can display the captured external information in real time.

[0165] [Variation Example]

[0166] The present invention is not limited to the above-described embodiments, and various modifications are possible.

[0167] For example, an example in which a part of the configuration of any embodiment is added to other embodiments or an example in which a part of the configuration of any embodiment is replaced with some configurations of other embodiments is also an embodiment of the present invention.

[0168] Furthermore, in the first to third embodiments, in order to simplify the description, the signal held by each of the plurality of signal holding circuits 12 constituting the signal holding area 10 is a 1-bit signal, but the signal does not necessarily have to be a 1-bit signal and may be a multi-bit signal. For example, the pulse signal output from the signal holding circuit 12 may be counted, the count value may be held in the memory 26, and the multi-bit signal held in the memory 26 may be transmitted to the timing circuit 28.

[0169] Other embodiments

[0170] The embodiments of the present invention may also be implemented by providing software (program) for performing the functions of the above-described embodiments to a system or device via a network or various storage media, and a computer or a central processing unit (CPU) or a microprocessing unit (MPU) of the system or device reads and executes the program.

[0171] According to the present invention, in a photoelectric conversion device including a plurality of pixel circuits, the time required to read out pixel signals can be reduced.

[0172] While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments.The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.

Claims

1. A photoelectric conversion device, comprising: a plurality of pixel circuits arranged to form a plurality of rows and a plurality of columns; as well as a control circuit configured to drive the plurality of pixel circuits, Wherein, each of the plurality of pixel circuits comprises: A signal generating circuit comprising a photoelectric conversion unit, a memory configured to hold a signal output from the signal generating circuit, and a sequential circuit including a first input node to which a signal from the memory is input, a second input node to which a control signal from the control circuit is input, a third input node, and an output node, and The plurality of pixel circuits include a first pixel circuit and a second pixel circuit arranged in the same row or the same column, and an output node of a sequential circuit of the first pixel circuit is connected to a third input node of a sequential circuit of the second pixel circuit.

2. The photoelectric conversion device according to claim 1, wherein The plurality of pixel circuits include a group of pixel circuits arranged in the same row or the same column, and sequential circuits of the pixel circuits constituting the group are connected in series to connect output nodes and the third input node of the sequential circuits of pixel circuits adjacent to each other.

3. The photoelectric conversion device according to claim 2, wherein: The control circuit is configured to supply the control signal common to pixel circuits of columns of two or more rows of a group each including the pixel circuits or to pixel circuits of rows of two or more columns of a group each including the pixel circuits.

4. The photoelectric conversion device according to any one of claims 1 to 3, in, The control circuit is configured to supply the control signal to the pixel circuits arranged in the same row or the same column via at least a part of the plurality of buffer circuits connected in series, and The number of buffer circuits through which the control signal supplied to the timing circuit of the first pixel circuit passes is greater than the number of buffer circuits through which the control signal supplied to the timing circuit of the second pixel circuit passes.

5. The photoelectric conversion device according to claim 4, wherein: Each of the plurality of buffer circuits is configured by a non-inverting buffer circuit.

6. The photoelectric conversion device according to claim 4, in, Each of the plurality of buffer circuits is configured by an inverting buffer circuit, and The sequential circuit of the first pixel circuit is configured to operate synchronously with a rising edge of the control signal, and the sequential circuit of the second pixel circuit is configured to operate synchronously with a falling edge of the control signal.

7. The photoelectric conversion device according to claim 4, wherein: The control circuit further includes a logic circuit configured between an output of each buffer circuit of the plurality of buffer circuits and a second input node of a timing circuit of a corresponding pixel circuit of the buffer circuit.

8. The photoelectric conversion device according to claim 1, wherein The multiple pixel circuits include a first group and a second group of pixel circuits arranged in the same row or the same column, and the timing circuits of the pixel circuits constituting each group in the first group and the second group are connected in series to connect the output nodes and the third input nodes of the timing circuits of the pixel circuits adjacent to each other.

9. The photoelectric conversion device according to claim 8, wherein: The pixel circuits constituting the first group and the pixel circuits constituting the second group are alternately arranged every predetermined number.

10. The photoelectric conversion device according to claim 8 or 9, wherein: The control circuit is configured to output respective signals of the pixel circuits constituting the first group and respective signals of the pixel circuits constituting the second group in parallel.

11. The photoelectric conversion device according to claim 8 or 9, in, the first group includes the first pixel circuit and the second pixel circuit, and the second group includes a third pixel circuit, wherein the control circuit is configured to supply the control signal to the pixel circuits arranged in the same row or the same column via at least a part of the plurality of buffer circuits connected in series, wherein the number of buffer circuits through which the control signal supplied to the timing circuit of the first pixel circuit passes is greater than the number of buffer circuits through which the control signal supplied to the timing circuit of the second pixel circuit passes, and The number of buffer circuits through which the control signal supplied to the timing circuit of the second pixel circuit passes is equal to the number of buffer circuits through which the control signal supplied to the timing circuit of the third pixel circuit passes.

12. The photoelectric conversion device according to any one of claims 1 to 3, wherein: The pixel circuit in which the output node of the sequential circuit is connected to the third input node of the other pixel circuit is configured to output the holding signal via the other pixel circuit.

13. The photoelectric conversion device according to any one of claims 1 to 3, wherein: The sequential circuit is configured to hold a signal input from the memory to the first input node, and output the held signal from the output node.

14. The photoelectric conversion device according to any one of claims 1 to 3, wherein: The sequential circuit is configured to hold a signal input from the third input node in response to a control signal input to the second input node, and output the held signal from the output node.

15. A photoelectric conversion device comprising: a plurality of pixel circuits arranged to form a plurality of rows and a plurality of columns; as well as a control circuit configured to drive the plurality of pixel circuits, Wherein, each of the plurality of pixel circuits comprises: A signal generating circuit comprising a photoelectric conversion unit, a memory configured to hold a signal output from the signal generating circuit, and a sequential circuit, transmitting the signal from the memory to the sequential circuit, wherein the plurality of pixel circuits include a first group and a second group each including two or more pixel circuits arranged in the same row, wherein the sequential circuits constituting the pixel circuits of each of the first group and the second group are connected in series along a row direction and are configured to sequentially transmit signals held by each pixel circuit from one side to the other side along the row direction according to a control signal from the control circuit; and The control circuit is configured to perform signal transfer operations in the first group of pixel circuits and signal transfer operations in the second group of pixel circuits in parallel by supplying a common control signal to the first group of pixel circuits and the second group of pixel circuits.

16. The photoelectric conversion device according to claim 15, wherein The pixel circuits constituting the first group and the pixel circuits constituting the second group are arranged in different rows.

17. The photoelectric conversion device according to claim 15, wherein: The pixel circuits constituting the first group and the pixel circuits constituting the second group are arranged in the same row.

18. A signal output device, comprising: a plurality of signal holding circuits arranged to form a plurality of rows and a plurality of columns; as well as a control circuit configured to drive the plurality of signal holding circuits, Wherein, each of the plurality of signal holding circuits comprises: a memory configured to hold a predetermined signal, and a sequential circuit, transmitting the signal from the memory to the sequential circuit, wherein the plurality of signal holding circuits include a first group and a second group each including two or more signal holding circuits arranged in the same row, wherein the sequential circuits constituting the signal holding circuits of each of the first group and the second group are connected in series along a row direction and are configured to sequentially transmit the signals held by each signal holding circuit from one side to the other side along the row direction according to a control signal from the control circuit; and The control circuit is configured to perform signal transfer operations in the first group of signal holding circuits and signal transfer operations in the second group of signal holding circuits in parallel by supplying a common control signal to the first group of signal holding circuits and the second group of signal holding circuits.

19. A method for driving a photoelectric conversion device, the photoelectric conversion device comprising: a plurality of pixel circuits arranged to form a plurality of rows and a plurality of columns, Wherein, each of the plurality of pixel circuits comprises: A signal generating circuit comprising a photoelectric conversion unit, a memory configured to hold a signal output from the signal generating circuit, and a sequential circuit, transmitting the signal from the memory to the sequential circuit, wherein the plurality of pixel circuits include a first group and a second group each including two or more pixel circuits arranged in the same row, and The sequential circuits constituting the pixel circuits of each of the first group and the second group are connected in series along the row direction. The driving method comprises: in each of the plurality of pixel circuits, holding a signal based on the charge generated in the photoelectric conversion unit by incidence of light in the memory; In each of the plurality of pixel circuits, transmitting the signal held in the memory to the timing circuit; and sequentially transmitting signals held by sequential circuits of pixel circuits constituting each of the first group and the second group from one side to the other side along the row direction, In the sequential transfer, a common control signal is supplied to the pixel circuits of the first group and the pixel circuits of the second group, so that a signal transfer operation in the pixel circuits of the first group and a signal transfer operation in the pixel circuits of the second group are performed in parallel.

20. The method for driving a photoelectric conversion device according to claim 19, wherein: The sequential transmission overlaps in time with the retention in the next frame.

21. A light detection system comprising: The photoelectric conversion device according to any one of claims 1 to 17; as well as A signal processing device is configured to process the signal output from the photoelectric conversion device.

22. The optical detection system of claim 21, wherein: The signal processing device generates a distance image representing distance information to an object based on the signal.

23. A movable body, comprising: The photoelectric conversion device according to any one of claims 1 to 17; a distance information acquisition unit configured to acquire distance information to a subject from a parallax image based on a signal output from the photoelectric conversion device; as well as A control unit is configured to control the movable body based on the distance information.

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