Gas explosion reduction at power-on in audio systems

Abstract

The invention relates to gas explosion reduction at power up in audio systems. An apparatus includes a first power stage circuit (PS1) having a first output (108) and a power terminal (PVDD), and a second power stage circuit (PS2) having a second output (110) and a power terminal (PVDD). The apparatus further includes a control circuit (203, Fig. 2A) having a control input (PVDD), a first control output (211), and a second control output (215). In an example, the control input (PVDD) is coupled to the power terminal, the first control output (211) is coupled to the first output (108), and the second control output (215) is coupled to the second output (110). In an example, the control circuit is configured to set the first and second outputs to a second voltage (e.g., a ground voltage) in response to a first voltage at the power terminal (PVDD) being below a threshold voltage.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is related to U.S. application No. 17 / 402,264, filed on August 13, 2021, entitled “Methods and Apparatus to Generated a Modulation Protocol to Output Audio” and U.S. application No. 17 / 491,133, filed on September 30, 2021, entitled “Switching amplifier having linear transition totem pole modulation”, both of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to audio systems, and in particular to reducing gas pop at power-up in audio systems. Background Art

[0004] Various audio systems may include an audio amplifier and a speaker. The audio amplifier may receive an audio signal representing a sound from an audio source, amplify and / or process the audio signal, and provide an amplified / processed audio signal at two electrical terminals of the speaker based on the amplified / converted electrical signal. The amplified / processed electrical signal may set a voltage difference across the two electrical terminals of the speaker, and the speaker may produce sound based on the voltage difference. In some cases, the audio amplifier may transmit a transient signal that does not originate from the audio source to the speaker. For example, such a transient signal may occur when the audio amplifier is powered on (e.g., from a cold start or after a system reset). Such a transient signal may be in an audible frequency band. The transient signal may introduce a transient voltage difference between the two electrical terminals of the speaker, which may produce an audible popping sound in response to the transient signal. Such a popping sound is undesirable. Summary of the invention

[0005] In an example, an apparatus includes: a first power stage circuit having a first output and a first power terminal; and a second power stage circuit having a second output and a second power terminal. The apparatus further includes a control circuit having a control input, a first control output, and a second control output, the control input being coupled to the power terminal, the first control output being coupled to the first output, and the second control output being coupled to the second output, the control circuit being configured to set the first output to a second voltage and the second output to a third voltage in response to a first voltage at the first and second power terminals being lower than a threshold voltage.

[0006] In another example, an apparatus includes: a first power stage circuit having a first output and a power terminal; and a second power stage circuit having a second output and a power terminal. The apparatus further includes: a capacitor coupled between the first output and a ground terminal; a speaker having a first speaker terminal and a second speaker terminal, the first speaker terminal being coupled to the first output; and an inductor coupled between the second output and the second speaker terminal. The apparatus further includes a control circuit having a control input, a first control output, and a second control output, the control input being coupled to the power terminal, the first control output being coupled to the first output, and the second control output being coupled to the second output or the second speaker terminal, the controller being configured to set the first and second outputs to a second voltage in response to a first voltage at the power terminal being lower than a threshold voltage.

[0007] In yet another example, a method includes receiving a first voltage ramped at respective power terminals of a first power stage circuit and a second power stage circuit, wherein the first power stage circuit has a first output and the second power stage circuit has a second output; determining whether the first voltage is below a threshold; and in response to the first voltage being below the threshold, setting the first and second outputs to a second voltage.

[0008] In another example, a method includes receiving a first voltage ramped at a first power terminal of a power stage circuit coupled to a speaker and at a second power terminal of a power supply circuit; in response to the first voltage reaching a first threshold voltage, enabling a first voltage regulator of the power supply circuit to provide a second voltage at a driver power terminal of a driver circuit of the power stage circuit; and after enabling the first voltage regulator, enabling a second voltage regulator of the power supply circuit to increase the second voltage by no more than a specific percentage of the second voltage or at a rate that does not exceed a specific slew rate, wherein the percentage or the slew rate is based on a pop noise level limit at the speaker. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A and 1B is a schematic diagram showing an example of an audio system.

[0010] Figure 1C Contains shown Figure 1A and 1B A graph of an example operation of an audio system.

[0011] Figure 2A , 2C , 2D, 2E, 2F and 2G are shown Figure 1A and 1B Schematic diagrams of additional examples of audio systems.

[0012] Figure 2B Contains shown Figure 2A and 2C Graph of example operation of an example system for -2G.

[0013] Figure 3 To show Figure 2A-2G Schematic diagram of an example control signal generating circuit.

[0014] Figure 4 To show Figure 1A and 1B Schematic diagrams of additional examples of audio systems.

[0015] Figure 5 To show Figure 4 A schematic diagram of an example of a power supply control circuit and a power supply circuit.

[0016] Figure 6 Contains shown Figure 4 Graphs of example operations of a power control circuit and a power circuit.

[0017] Figure 7 Contains shown Figure 2A-2G and Figure 4-6 A graph of an example operation of an audio system.

[0018] Figure 8 To show Figure 4 A schematic diagram of another example of a power control circuit and a power supply circuit of a system.

[0019] Fig. 9 Contains shown Figure 8 Graphs of example operations of a power control circuit and a power circuit.

[0020] Fig.10 To show Figure 4 A schematic diagram of yet another example of a power supply circuit of a system.

[0021] Fig.11 Contains shown Fig.10 A graph of an example operation of a power supply circuit.

[0022] Fig.12 is a flow chart showing an example of a method of operating a speaker.

[0023] Fig.13 is another example flow chart representing a method of operating a speaker. DETAILED DESCRIPTION

[0024] Described herein are techniques for eliminating or otherwise reducing the gas popping sound that sometimes occurs during the startup of an audio system, whether in the context of a cold start or a reset. In an example, an apparatus includes: a first power stage circuit having a first output and coupled to a power terminal; and a second power stage circuit having a second output and coupled to the power terminal. The apparatus further includes a control circuit having a control input, a first control output, and a second control output. In some such examples, the control input is coupled to the power terminal, the first control output is coupled to the first output, and the second control output is coupled to the second output, and the control circuit is configured to set the first and second outputs to a second voltage in response to a first voltage at the power terminal being lower than a threshold voltage. In some such cases, the techniques may be implemented in conjunction with a number of auxiliary transistors coupled at certain nodes of the system. The apparatus may be, for example, part of an audio amplifier system, such as those included in a desktop computer, a laptop computer, a mobile computer (e.g., a smartphone), a game console, or any other electronic device or system that includes a speaker driven by an audio amplifier.

[0025] In some examples, switching amplifiers are used to output audio in various electronic devices including cell phones, televisions, hearing aids, home theater systems, vehicle audio systems, instrument amplifiers, radio frequency amplifiers, subwoofers, etc. The switching amplifier includes a power stage that generates a signal having a binary magnitude by selectively connecting the power stage output to one of two power rails (e.g., a voltage supply and ground, a power supply voltage, and a negative voltage supply, etc.). In some examples, the switching amplifier can be operated as a class D amplifier. The switching amplifier can be driven by a modulation circuit that receives a sinusoidal audio signal and generates a pulse width modulation signal, a pulse density signal, and / or any other type of modulated control signal to control the power stage to additionally generate a modulated signal. The modulated signal provided by the power stage may have timing properties that are modulated / changed to reflect the instantaneous magnitude of the audio signal, such as duty cycle, pulse width, etc. The modulated signal generated by the power stage may be filtered (e.g., by a low pass filter) to generate an amplified version of the sinusoidal audio signal, and the amplified sinusoidal audio signal may be fed to a speaker. The low pass filter may include an LC filter including a series inductor coupled between the output of the switching amplifier and the speaker, and a shunt inductor coupled between the speaker and ground. In some examples, the audio amplifier may include two switching amplifiers as two power stages to provide two modulated signals with opposite polarities at two terminals of the speaker, and an LC filter coupled between each power stage output and a respective terminal of the speaker. The switching amplifier may provide improved power efficiency when driving the speaker, but having two LC filters (especially the inductors) may generally increase the footprint of the audio system.

[0026] In some examples, the audio system may also include a non-switching amplifier. The non-switching amplifier may include another power stage driven by a control circuit, the control circuit including a linear amplifier. The control circuit may receive a sinusoidal audio signal and provide a control signal having a magnitude that varies (e.g., linearly or nearly linearly) according to the instantaneous magnitude of the audio signal to the non-switching amplifier. In response to the control signal, the non-switching amplifier may also generate a signal having a magnitude that varies (e.g., linearly or nearly linearly) with the audio signal. In some examples, the non-switching amplifier may operate as a class A amplifier, a class AB amplifier, etc. The output of the non-switching amplifier may also be filtered (e.g., by another low-pass filter) to remove nonlinearity. However, because the signal output by the non-switching amplifier has a relatively high linearity (at least compared to the modulated signal provided by the switching amplifier), the low-pass filter may have fewer components. For example, instead of an LC filter, the audio system may include a capacitor at the output of the non-switching amplifier to perform filtering. In some examples, the audio system may include two non-switching amplifiers as two power stages to provide two linear signals with opposite polarities at two terminals of a speaker, and capacitors coupled to each power stage output (and the corresponding terminals of the speaker) to perform filtering. The lack of inductors can reduce the footprint of the filter and the audio system, but the power efficiency of the non-switching amplifier may be significantly worse than that of the switching amplifier.

[0027] In some examples, the audio system may also include: a switching amplifier for driving a first terminal of the speaker; and a non-switching amplifier for driving a second terminal of the speaker. The audio system may include: an LC filter coupled between the switching amplifier output and the first terminal; and a capacitor filter coupled to the non-switching amplifier output and the second terminal. With such an arrangement, the total number of inductors included in the low-pass filter can be halved compared to a case where the audio system includes two switching amplifiers. Power efficiency can also be improved compared to a case where the audio system includes two non-switching amplifiers.

[0028] In all of these examples of audio systems, there may be asymmetry in the power stage driving the speaker. The asymmetry may be due to a random mismatch between two amplifiers of the same type (e.g., between two switching or non-switching amplifiers), or may be due to a systematic mismatch (e.g., between a switching amplifier and a non-switching amplifier). Due to the asymmetry, the power stage may introduce a time-varying / transient voltage difference across the speaker terminals during startup or reset of the audio system when the supply voltage to the power stage is ramped up and the audio signal has not yet been provided to the amplifier. If the time-varying voltage difference has a frequency within the human audio band, the speaker may produce an audible pop, which is undesirable. The examples disclosed herein provide techniques for avoiding such pop noises during the startup or reset process.

[0029] Figure 1A An example audio system 100 is shown. As shown, system 100 includes a first amplifier (labeled amplifier A) and a second amplifier (labeled amplifier B) driving a speaker 102. Amplifier A may be coupled to terminal 104 of speaker 102, and amplifier B may be coupled to terminal 106 of speaker 102. Amplifiers A and B may be of the same type (e.g., both switching amplifiers or non-switching amplifiers), or may be of different types and / or have different control schemes (e.g., one is a switching amplifier and the other is a non-switching amplifier). Due to asymmetry between amplifiers A and B (e.g., random device mismatch or system mismatch), the amplifiers may introduce a time-varying / transient voltage difference between terminals 104 and 106 during startup or initialization of system 100 (e.g., when power supply voltage PVDD is ramped up), which may cause speaker 102 to output a popping sound. Later, as terminals 104 and 106 are fully charged, a DC voltage offset may be generated across capacitor C1 (see Figure 1B ) and is generated between terminals 104 and 106, and the gas explosion sound may end.

[0030] Specifically, during startup or reset of the system 100, the power supply voltage PVDD of the amplifiers A and B may be ramped up (e.g., as part of a power sequencing operation) while no audio signals are provided to the amplifiers A and B. During this time, the voltages VN and VP may track each other so that the voltage difference may be zero, or a DC value, or vary over time but have a very low value (e.g., <10 mV) to avoid (or reduce the likelihood of) the speaker producing an audible pop. However, due to the aforementioned asymmetry, when the power supply voltage PVDD is ramped up (e.g., during the startup or reset process), the amplifiers A and B may generate a transient voltage difference, which may result in a transient difference between the voltages VN and VP, thereby causing the speaker 102 to produce a pop. The intensity of the pop may be based on the transient difference between the voltages VP and VN, and if this difference is relatively large, such as greater than 10 mV, 20 mV, or 50 mV, the pop may be audible, and the intensity of the pop may be set based on the volume of the speaker 102.

[0031] Figure 1B Show Figure 1A An example of internal components of system 100. Figure 1B The system 100 includes: a first power stage PS1 having a first output terminal 108; and a second power stage PS2 having a second output terminal 110. The first power stage PS1 may represent Figure 1A The amplifier A (or part thereof), and the second power stage PS2 may represent Figure 1BThe first output terminal 108 and the second output terminal 110 are coupled to an LC filter circuit 112. The two speaker terminals 104 and 106 (also relative to Figure 1A Description) is coupled to the speaker 102.

[0032] The power stage PS1 includes a first transistor S1 and a second transistor S2 coupled in series between a power terminal 116a (e.g., receiving power supply PVDD) and a ground terminal. For example, a first current terminal of transistor S1 is coupled to the power terminal 116a, and a second current terminal of transistor S1 is coupled to the output terminal 108. A first current terminal of transistor S2 is coupled to the output terminal 108, and a second current terminal of transistor S2 is coupled to the ground terminal.

[0033] Transistor S1 further includes a control terminal coupled to a first power stage input that receives a control signal CS1 from a driver D1, and transistor S2 includes a control terminal coupled to a second power stage input that receives a control signal CS2 from another driver D2. Transistors S1 and S2 can set a voltage VN at an output terminal 108 of power stage PS1 in response to control signals CS1 and CS2. Figure 1B In the embodiment of the present invention, the power stage PS1 can be controlled as a non-switching amplifier (e.g., class AB, class A, etc.) so that CS1 and CS2 can each have a magnitude that varies (e.g., linearly or nearly linearly) according to the instantaneous magnitude of the audio signal. CS1 and CS2 can have opposite polarities. For example, during the first half cycle of the audio signal, transistor S1 is turned on or enabled, transistor S2 is turned off or disabled, and transistor S1 can change the magnitude of voltage VN based on the magnitude of CS1, which reflects the instantaneous magnitude of the audio signal during the first half cycle. And, during the second half cycle of the audio signal, transistor S1 is turned off or disabled, transistor S2 is turned on or enabled, and transistor S2 can change the magnitude of voltage VN based on the magnitude of CS2, which also reflects the instantaneous magnitude of the audio signal during the second half cycle, and voltage VN can have opposite polarities between the first half cycle and the second half cycle. In the case where the audio signal is a sinusoidal signal, voltage VN can be (or nearly be) an amplified version of the sinusoidal signal.

[0034] In some examples, the power stage PS1 can be controlled as a switching amplifier (e.g., class D), wherein the control signals CS1 and CS2 are pulse width modulation signals, pulse density signals, and / or any other type of modulated control signals having binary magnitudes. Depending on the polarity of the audio signal, one of the transistors S1 or S2 can be turned on to connect one of the power terminal 116a or the ground terminal to the output terminal 110. In response to CS1 and CS2, the power stage PS2 can also generate a modulated signal as VN. The modulated signal provided by the power stage can have a timing property, such as duty cycle, pulse width, etc., that is modulated / changed to reflect the instantaneous magnitude of the audio signal. CS1 and CS2 can have opposite polarities. For example, during the first half cycle of the audio signal, transistor S1 is turned on or enabled, transistor S2 is disconnected or disabled, and transistor S1 can provide VN as a modulated signal at the output terminal 108 in response to CS1. Also, during the second half cycle of the audio signal, transistor S2 is turned on or enabled, transistor S1 is turned off or disabled, and transistor S2 can provide VN as a modulated signal at the output terminal 108 in response to CS2.

[0035] Furthermore, power stage PS2 includes a third transistor S3 and a fourth transistor S4 coupled in series between a power terminal 116b (e.g., receiving power supply PVDD) and a ground terminal. In an example, power terminals 116a and 116b may be the same power terminal shared by both power stages PS1 and PS2, while in another example, power terminals 116a and 116b may be coupled to different voltage sources.

[0036] As shown, a first current terminal of transistor S3 is coupled to power terminal 116b and a second current terminal of transistor S3 is coupled to output terminal 110 having voltage VY. A first current terminal of transistor S4 is coupled to output terminal 110 and a second current terminal of transistor S4 is coupled to a ground terminal.

[0037] Transistor S3 further includes a control terminal coupled to a third power stage input that receives a control signal CS3 from driver D3, and transistor S4 further includes a control terminal coupled to a fourth power stage input that receives a control signal CS4 from another driver D4. Transistors S3 and S4 can set a voltage VY at output terminal 110 of power stage PS2 in response to control signals CS3 and CS4. Figure 1BIn the embodiment of the present invention, power stage PS2 can be controlled as a switching amplifier (e.g., class D), wherein control signals CS3 and CS4 are pulse width modulation signals, pulse density signals, and / or any other type of modulated control signals with binary magnitude. Depending on the polarity of the audio signal, one of transistors S3 or S4 can be turned on to connect one of the power terminal 116b or the ground terminal to the output terminal 110. In response to CS3 and CS4, power stage PS2 can also generate a modulated signal. The modulated signal provided by the power stage can have a timing property such as duty cycle, pulse width, etc. that is modulated / changed to reflect the instantaneous magnitude of the audio signal. CS3 and CS4 can have opposite polarities. For example, during the first half cycle of the audio signal, transistor S3 is turned on or enabled, transistor S4 is disconnected or disabled, and transistor S3 can provide VY as a modulated signal at the output terminal 110 in response to CS3. And, during the second half cycle of the audio signal, transistor S4 is turned on or enabled, transistor S3 is turned off or disabled, and transistor S4 can provide VY as a modulated signal at output terminal 110 in response to CS4. In some examples, power stage PS2 can also be controlled as a non-switching amplifier. In such examples, CS3 and CS4 can each have a magnitude that varies (e.g., linearly or nearly linearly) according to the instantaneous magnitude of the audio signal.

[0038] exist Figure 1B In the embodiment, transistors S1, S2, S3 and S4 are illustrated as n-channel metal oxide semiconductor (NMOS) field effect transistors (FETs). In other examples, transistors S1, S2, S3 and S4 may be other types of transistors, such as p-channel MOSFETs (PMOS), NPN or PNP bipolar junction transistors (BJTs), etc.

[0039] The LC filter circuit 112 includes an inductor L1 coupled between the output terminal 110 and the speaker terminal 106, a capacitor C1 coupled between the speaker terminals 104 and 106, and another capacitor C2 coupled between the speaker terminal 104 and the ground terminal. The inductor L1 and the capacitor C1 filter the modulated signal VY output at the output terminal 110 into a sinusoidal signal at the speaker terminal 106, which is output to the speaker 102 to output the corresponding audio. The capacitor C2 can also filter the signal VY to further suppress nonlinearity in the signal VY. In the case where the power stage PS2 is controlled as a switching amplifier, the LC filter circuit 112 also includes another inductor ( Figure 1B (not shown). Figure 1B , the output terminal 110 may be a capacitor terminal coupled to the capacitor C2, and the output terminal 108 may be an inductor terminal coupled to the inductor L1.

[0040] The system 100 also includes a control circuit ( Figure 1B (not shown), the control circuit generates control signals that drive driver circuits D1, D2, D3, and D4 respectively based on the audio signal. Example operations of system 100 are described in related U.S. application No. 17 / 402,264, entitled “Method and Apparatus for Generating Modulation Protocols to Output Audio,” filed on August 13, 2021, and related U.S. application No. 17 / 491,133, entitled “Switching Amplifier with Linear Transition Totem Pole Modulation,” filed on September 30, 2021, both of which are incorporated herein by reference in their entirety, as described above.

[0041] Figure 1C Contains graphs showing example changes in the VN and VP voltages as the power supply voltage PVDD ramps up. Figure 1C , the power supply voltage PVDD ramps up from time t0 to time t2 and has a steady state value after time t2. The time period t0-t2 may depict a startup (eg, cold start) or reset operation of the system 100.

[0042] Also in Figure 1C 1 and 2. A voltage VN (shown using a solid line) and a voltage VP (shown using a dashed line) are shown in FIG. For reasons described below, both VP and VN increase between time t0 and t1, decrease between time t1 and t2, and have substantially steady-state values ​​from time t2 onward. However, between time t0 and t1, voltage VP differs from VN, thereby producing a non-zero transient voltage difference across terminals 104 and 106 of speaker 102. If the transient voltage difference exceeds a certain threshold (e.g., 10 mV) and / or is within an audible frequency band, speaker 102 may produce an audible popping sound between time t0-t1 during a startup or reset operation.

[0043] Power stages PS1 and PS2 may introduce transient voltage differences due to various asymmetries between the power stages. During the ramping of the power supply voltage PVDD, charge may be coupled from the power terminals of the power stages to their outputs (e.g., from 116a to 108, from 116b to 110), which causes the voltage at terminals 108 and 110 to also ramp up. However, due to the asymmetry, the voltage at terminals 108 and 110 may ramp up differently, which may cause transient voltage differences across terminals 104 and 106, as well as gas pop noises.

[0044] Specifically, each of transistors S1-S4 has a parasitic capacitance represented by the dashed capacitor symbol in FIG. 1. When PVDD ramps up from 0 to a steady state value, the rate of increase of voltage relative to time (e.g., dV / dT) may be high. In an example, the rate of increase of PVDD relative to time may be in the range of 10V / microsecond to 100V / microsecond. And, at this time, drivers D1, D2, D3, D4 or circuits supplying control signals to drivers D1, D2, D3, D4 may be disabled. The control terminals of transistors S1-S4 may not be actively driven and may be in a floating state. Via the parasitic capacitance of transistor S1, when PVDD ramps up, charge may move to output terminal 108 and speaker terminal 104, which may produce a non-zero voltage VN that increases with PVDD. And, charge may move to the gate of S1 via the parasitic capacitance and increase the voltage VGS. Between t0-t1, transistor S1 may be turned on and may be connected between power terminal 116a and output terminal 108 (and speaker terminal 104). Thus, output terminal 108 experiences a ramp up of voltage VN between time period t0-t1, as shown in FIG. Figure 1C For similar reasons, when PVDD is ramping up, the output terminal 110 also experiences a ramp up of the voltage VY (and the speaker terminal 106 experiences a ramp up of the voltage VP) during the time period t0-t1.

[0045] There are various sources of asymmetry between power stages PS1 and PS2 that can result in different ramps of voltages VN and VP. One source of asymmetry is filter mismatch. Specifically, output terminal 108 is coupled to ground via capacitor C2, but there is no corresponding capacitor coupled to output terminal 110. Also, output terminal 110 is coupled to speaker terminal 106 via inductor L1, but there is no corresponding inductor coupled between output terminal 118 and speaker terminal 104. Therefore, capacitor C2 can provide a low resistance to ground to attenuate the ramped voltage VN (or ground it), while voltage VP is not grounded / attenuated in a similar manner. Voltage VP also depends on the relative impedances of inductor L1 and capacitors C1 and C2, while voltage VN and L1 do not have such a correlation. All of this can result in different ramps of voltages VN and VP, resulting in transient differences between VN and VP.

[0046] In addition, power stages PS1 and PS2 may be of different types (e.g., PS1 is a switching amplifier and PS2 is a non-switching amplifier), where transistors S1 and S3 have different sizes, and transistors S2 and S4 have different sizes. Even if power stages PS1 and PS2 are of the same type, there may still be a mismatch in transistor size between S1 and S3 and between S2 and S4. The mismatch in transistor size may also result in a mismatch in parasitic capacitance and a different amount of charge flowing to output terminals 108 and 110, which may further increase the transient difference between VN and VY.

[0047] Figure 2A An example of a system 100 including a control circuit 203 configured to eliminate or reduce gas pop noise is shown. The control circuit is used to configure the system 100 to set the voltages VP and VN at the speaker terminals 104 and 106 of the system 100 to the same DC voltage, or otherwise reduce the magnitude of the transient voltage difference between the two terminals.

[0048] See also Figure 2A , control circuit 203 has control outputs 209, 211, 215, and 217. In an example, control circuit 203 may have control output 213 instead of or in addition to control output 215. Figure 2A As shown in , control output 209 is coupled to the control terminal of transistor S1, control output 211 is coupled to output terminal 108, control output 213 is coupled to speaker terminal 106, control output 215 is coupled to output terminal 110, and control output 217 is coupled to the control terminal of transistor S3.

[0049] In an example and as will be described below, when the voltage PVDD is ramping and below a threshold voltage, the control outputs 209 and 217 may connect the control terminals of the transistors S1 and S3, respectively, to a ground terminal, or to a state that disables the transistors S1 and S3. With the transistors S1 and S3 disabled, the output terminal 108 may be disconnected from the power terminal 116a, and the output terminal 110 may be disconnected from the power terminal 116b, which may reduce (or eliminate) the flow of charge from the power terminals 116a and 116b to the respective output terminals 108 and 110 through the current terminals of the transistors S1 and S3 during the ramping of the power supply voltage PVDD. Such an arrangement may reduce the ramping of VP and VN and the resulting transient difference between VP and VN.

[0050] Furthermore, the control circuit 203 is configured to set the terminals 108, 106 and / or 110 to the same voltage in response to the power supply voltage PVDD at the power terminals 116a and / or 116b being below a threshold voltage, for example using control outputs 211, 213 and / or 215, respectively. Such an arrangement may further reduce the difference between VP and VN (and the voltage difference between the speaker terminals 104 and 106) due to the asymmetric charge flow from the power terminals 116a and 116b to the respective output terminals 108 and 110 through the parasitic capacitances of the transistors S1 and S3.

[0051] In an example and as will be described below, when voltage PVDD is ramped and below a threshold voltage, control outputs 211 and 213 can couple terminals 108 and 106 to a ground terminal, respectively. Thus, voltages VN and VP can be substantially the same (at 0 volts), and the above-mentioned pop noise from speaker 102 can be avoided or at least reduced.

[0052] In another example and as will be described below, when voltage PVDD is ramped and below a threshold voltage, control outputs 211 and 215 can couple terminals 108 and 110 to ground terminals, respectively. Thus, voltages VN and VY can be substantially zero, and thus voltage VN can also be substantially zero. Thus, the above-mentioned pop noise from speaker 102 can be avoided or at least reduced.

[0053] In yet another example and as will be described below, when voltage PVDD is ramped and below a threshold voltage, control outputs 211 and 213 may connect terminals 108 and 106 to a fixed / DC voltage, respectively. Thus, voltages VN and VP may be substantially the same, and any difference between voltages VN and VP may be eliminated or at least reduced. Thus, the above-mentioned pop noise from speaker 102 may be avoided or at least reduced.

[0054] In yet another example, and as will be described below, when the voltage PVDD ramps and is below a threshold voltage, the control outputs 211 and 213 may connect the terminals 108 and 106 to different DC voltages, respectively, which may cause a DC voltage offset between the terminals 108 and 106 and eliminate / reduce a transient voltage difference between the speaker terminals 104 and 106. Thus, the above-mentioned pop noise from the speaker 102 may be avoided or at least reduced.

[0055] Figure 2B For example, when the power supply voltage PVDD is ramped up, Figure 2A The timing diagram of the voltages VN and VP at the speaker terminals 104 and 106 of the system 100 is shown in FIG. Figure 2B , the power supply voltage PVDD gradually increases from time t4 to time t5 and has a steady state value after time t5. Therefore, the time period t4-t5 depicts a startup (e.g., cold start) or reset operation of the system 100. Due to the above-described operation of the control circuit 203, the voltages VN and VP are relatively small and generally track each other (e.g., with Figure 1B This may eliminate or at least reduce pop noise at the speaker 102 during the ramp-up of the supply voltage PVDD.

[0056] See again Figure 2A , the control circuit 203 includes one or more transistors, such as auxiliary transistors AS1, AS2, AS3 and AS4, each of which will be described below. Figure 2A As shown in FIG. 2 , the control circuit 203 further includes a control signal generating circuit 207 generating a control signal CSS, wherein CSS is coupled to a control terminal of each of the auxiliary transistors AS1 , AS2 , AS3 , and AS4 .

[0057] Figure 2C Another example of a system 100 including a control circuit 203 is shown. Figure 2C , an auxiliary transistor AS1 is coupled to the control terminal of transistor S1 of power stage PS1, another auxiliary transistor AS3 is coupled to the control terminal of transistor S3 of power stage PS2, another auxiliary transistor AS2 is coupled to output terminal 108 of power stage PS1, and another auxiliary transistor AS4 is coupled to output terminal 110 of power stage PS2. Control circuit 203 includes auxiliary transistors AS1, AS2, AS3 and AS4 and control signal generating circuit 207. The outline of control circuit 203 is not shown in FIG. Figure 2C (For an outline of the control circuit 203, see Figure 2A ).

[0058] In one example, system 100 includes a die 208 that includes power stages PS1 and PS2, auxiliary transistors AS1, AS2, AS3, and AS4, control signal generation circuit 207, and drivers D1-D4. Figure 2C In the embodiment, the auxiliary transistor AS1 is coupled to the control output 209 (which is coupled to the control terminal of the transistor S1, see Figure 2A ) and the ground terminal. The auxiliary transistor AS3 is coupled to the control output 217 (which is coupled to the control terminal of the transistor S3, see Figure 2A ) and the ground terminal.

[0059] Auxiliary transistor AS2 is coupled to control output 211 (see also Figure 2A , wherein the control output 211 is coupled between the output terminal 108) and the ground terminal. The auxiliary transistor AS4 is coupled between the control output 215 (see also Figure 2A , where the control output 215 is coupled between the output terminal 110) and the ground terminal.

[0060] In one example, the control circuit 203 includes a control signal generating circuit 207 that generates a control signal CSS, wherein CSS is coupled to a control terminal of each of the auxiliary transistors AS1, AS2, AS3, and AS4. The generation of the control signal CSS is described below with respect to Figure 3 For example, each of the auxiliary transistors AS1, AS2, AS3, and AS4 receives the same control signal CSS.

[0061] like Figure 2BAs shown in FIG, the control signal generating circuit 207 generates a control signal CSS so that the auxiliary transistors AS1-AS4 are at least partially enabled or turned on during the gradual rise of the power supply voltage PVDD (the generation of the control signal CSS will be described in further detail below). For example, Figure 2B The timing diagram of FIG. 1 shows that from time t4 to at least time t5, for example based on PVDD being less than a threshold voltage, the auxiliary transistor control signal CSS is enabled and the auxiliary transistors AS1-AS4 are turned on, where time t5 occurs when or after PVDD reaches a steady state value. In some examples, the auxiliary transistors may continue to be enabled (e.g., for a shorter duration) after time t5 or for the entire duration when PVDD is ramping up (e.g., between t4 and t5).

[0062] As mentioned above about Figure 2A As described, when the voltage PVDD ramps up and is below the threshold voltage, the auxiliary transistors AS1 and AS3 are enabled, and the control terminals of the transistors S1 and S3 are connected to the ground terminal, or to a state where the transistors S1 and S3 are disabled, respectively. Therefore, the transistors S1 and S3 remain disconnected or disabled, and the power supply terminals 116a and 116b are disconnected from the output terminals 108 and 110, respectively.

[0063] By such an arrangement, the ramping of voltages VN and VY caused by the ramping of PVDD and the charge flow through transistors S1 and S3 can be reduced. Also, as described above, auxiliary transistors AS2 and AS4 can connect output terminals 108 and 110, respectively, to a ground terminal, which can connect both voltages VN and VY to ground between times t4 and t5 (see Figure 2B ). Therefore, the voltage difference between the speaker terminals 104 and 106 is relatively small and can be substantially zero. This eliminates or reduces the popping sound during the ramp-up of PVDD.

[0064] Figure 2D Another example of a system 100 including a control circuit 203 is shown. Figure 2D , an auxiliary transistor AS1 is coupled to the control terminal of transistor S1 of power stage PS1, another auxiliary transistor AS3 is coupled to the control terminal of transistor S3 of power stage PS2, another auxiliary transistor AS2 is coupled to output terminal 108 of power stage PS1, and another auxiliary transistor AS4 is coupled to speaker terminal 106. Therefore, Figure 2C and 2D The connection and / or operation of the auxiliary transistors AS1, AS2 and AS3 in FIG. 1 are the same. Figure 2D In FIG. 1 , auxiliary transistor AS4 is coupled to speaker terminal 106. Figure 2D In FIG. 1 , the speaker terminals 106 are on the bare die 208. In operation, in Figure 2DFor example, when PVDD is Figure 2B When ramping up during time t4-t5, auxiliary transistor AS4 grounds the speaker terminal 106 (eg, instead of the output terminal 110). Figure 2C Description, Figure 2D The operation of the auxiliary transistors AS1-AS4 in will be apparent.

[0065] exist Figure 2D In (and in Figure 2E and 2F ), the output terminal 212 is on the die 208. In an example, the inductor L1 is part of the power stage PS2, where the power stage P2 includes transistors S3, S4 and the inductor L1. In addition to the output terminal 110, the speaker terminal 106 can also be coupled to the output terminal 212 of the power stage PS2. In some examples, the inductor L1 is external to the power stage PS2. In such examples, the power stage PS2 has an output terminal 110, the die 208 has an output terminal 212, and the inductor L1 is coupled between the output terminals 212 and 110.

[0066] Figure 2E Another example of a system 100 including a control circuit 203 is shown. Figure 2E , the output terminal 108 of the power stage PS1 and the output terminal 212 of the power stage PS2 (or the die 208) may be selectively shorted together using the auxiliary transistor AS2, for example, between times t4-t5 when PVDD is below a threshold. And, Figure 2C and 2E The connection and / or operation of the auxiliary transistors AS1 and AS3 in the embodiment are the same. By shorting the output terminals 108 and 212, the voltages VN and VP can become substantially the same, thereby Figure 2E Eliminate or reduce air pop noise during startup of the system 100.

[0067] Figure 2F Another example of a system 100 including a control circuit 203 is shown. Figure 2F , the output terminal 108 of the power stage PS1 and the output terminal 212 (of the power stage PS2 and / or the die 208 ) are each selectively connected to the voltage source Vs, for example, between times t4 - t5 . Figure 2D and 2F The connection and / or operation of the auxiliary transistors AS1 and AS3 in the embodiment are the same. Because the output terminals 108 and 212 are each connected to the voltage source Vs during this period, the voltages VN and VP are substantially the same (eg, the same as the voltage VS), thereby Figure 2F Eliminate or reduce air pop noise during startup of the system 100.

[0068] Figure 2GAnother example of a system 100 including a control circuit 203 is shown. Figure 2G , the current terminals of auxiliary transistors AS1, AS2, AS3, and AS4 are connected to voltages V1, V2, V3, and V4, respectively. Each of the voltages V1-V4 can be a zero voltage (e.g., ground) or a non-zero DC voltage. Auxiliary transistors AS2 and AS4, when enabled, can connect output terminal 212 and output terminal 108 to voltages V2 and V3, respectively, for example, between time t4-t5. In an example, voltages V2 and V3 are the same, thereby causing a DC offset (and cancellation of transient voltage differences) between speaker terminals 104 and 106, thereby causing a DC offset between the speaker terminals 104 and 106. Figure 2F Elimination or reduction of air pop noise during startup of the system 100.

[0069] Figure 3 2 shows an example of the internal components of the control signal generating circuit 207. Figure 2A-2G As described, the control signal generating circuit 207 generates the control signal CSS, which is used to control the auxiliary transistors AS1 - AS4 .

[0070] The control signal generating circuit 207 includes a voltage regulator 304 configured to receive a power supply voltage PVDD (e.g., from power supply terminals 116a and / or 116b) and generate a regulated voltage GVDD_f. In an example, the voltage regulator 304 is a relatively fast regulator, for example, generating the output voltage GVDD_f within a few microseconds of PVDD ramping up, so that the output voltage GVDD_f is almost instantaneous as soon as the voltage PVDD starts to ramp up (e.g., see Figure 2B ), the auxiliary transistors AS1-AS4 can be turned on. In an example, the capacity of the voltage regulator 304 can be relatively small and the speed can be relatively fast (for example, as described below with respect to Figure 5 ) as compared to the voltage regulator described above, for example, because the voltage regulator 304 can supply the GVDD_f voltage and power for operation of a relatively small number of components, such as the control signal generating circuit 207 and the auxiliary transistors AS1-AS4. The suffix "_f" is added to Figure 3 GVDD in order to compare this GVDD supply with the following Figure 4 and 5 The different GVDD supplies are described separately.

[0071] The control signal generation circuit 207 further includes an undervoltage lockout circuit 308 configured to receive the power supply voltage PVDD and generate an undervoltage lockout (UV) signal 309. In one example, the undervoltage lockout circuit 308 is biased or powered by GVDD_f.

[0072] In an example, the undervoltage lockout circuit 308 has a control input 307 coupled to the power supply terminals 116a and / or 116b and receives the power supply voltage PVDD. The undervoltage lockout circuit 308 compares PVDD with a threshold voltage Vth and generates a UV signal 309 in a first state when PVDD is below the threshold voltage and generates the UV signal 309 in a second state when PVDD is above the threshold voltage. For example, during startup or reset of the system 200, PVDD ramps from zero to a steady state value, such as Figure 2B As shown in the timing diagram of . For example, during the time period t4-t5, PVDD is less than the threshold voltage, and UV 309 is in a first logic state (e.g., logic high) during this time period. After time t5, PVDD is higher than the threshold voltage, and therefore, UV 309 is in a second logic state (e.g., logic low) during this time period. In an example, the undervoltage lockout circuit 308 acts as a voltage comparator and can be replaced by a voltage comparator.

[0073] As in Figure 3 As further shown in the example embodiment of , logic circuit 312 receives UV signal 309 and generates control signal CSS in response to UV signal 309. For example, in response to UV signal 309 indicating that PVDD is below the threshold voltage (e.g., during time period t4 to t5), and in this particular example, further in response to SC signal 317 indicating that a short circuit is not detected, control signal CSS is set to a first logic state (e.g., logic high) to enable auxiliary transistors AS1-AS4, as described below. Figure 2B On the other hand, in response to UV signal 309 being logic low, thereby indicating that PVDD is above the threshold voltage (eg, after time t5), control signal CSS is set to a second logic state (eg, logic low) to disable auxiliary transistors AS1-AS4.

[0074] like Figure 3As further shown in the example embodiment of , the control signal generation circuit 207 may further include a short circuit protection circuit 316. For example, the short circuit protection circuit 316 may be configured to detect any short circuit occurring in the system 100, such as by sensing a high current relative to a given reference current, or by sensing a low voltage relative to a given reference voltage. For example, in response to a short circuit occurring between the power supply terminal 116a or 116b and the ground or other node that will cause a detectable high current condition (e.g., in some cases, any of the terminals 108, 104, 106, or 110), the short circuit protection circuit 316 generates a short circuit (SC) signal 317 in a particular state (e.g., logic low) indicating a short circuit. In response to the SC signal 317 indicating a short circuit (and / or regardless of the state of UV 309), the logic 312 may generate a CSS in a second logic state. In some such examples, in response to the signal 317 being a logic low signal, the logic 312 may be an AND gate, and may set the CSS to a logic low state, thereby indicating a short circuit. If a short circuit is not detected, short circuit protection circuit 316 sets SC signal 317 to another state (e.g., logic high), indicating normal operation, which in turn allows logic 322 to determine CSS based on UV signal 309. For example, and continuing with the example of logic 312 being an AND gate, logic 312 may set CSS to a logic high state in response to UV signal 309 also having a logic high state (indicating that PVDD is below the threshold voltage during the startup process) and signal 317 having a logic high state (indicating that a short circuit is not detected).

[0075] Thus, in the event of any short circuit, the auxiliary transistors AS2 and AS4 can be disconnected. Such a configuration can be used to prevent damage caused by high currents caused by a short circuit, such as damage caused by a short circuit between the power supply PVDD and the ground terminal and either of the auxiliary transistors AS2 or AS4 (e.g., when the auxiliary transistors AS2 and AS4 are disabled or disconnected). In addition, disconnecting the auxiliary transistors AS2 and AS4 during a short circuit can also reduce or eliminate overvoltage stress on the gate terminals of S1 and S3.

[0076] In still other examples, circuits 312 and 316 are not included, and UV signal 309 generated by circuit 308 is used to enable or disable auxiliary transistors AS1-AS4. Other configurations may also be used, and logic 312 may be adjusted to allow for consideration of other sensed conditions (e.g., open circuit conditions, floating conditions, high capacitance conditions, to name a few examples).

[0077] Figure 4 A bootstrap circuit 404 is shown for bootstrapping a driver D3 of a power stage PS2 of a system 100 , wherein a power supply circuit 414 of the system 100 includes a mechanism for avoiding popping sounds at a speaker output of the system 100 . Figure 4The system 100 further includes auxiliary transistors AS1-AS4, which are Figure 4 Not shown.

[0078] like Figure 4 As shown in , each of the drivers D1-D4 has a respective driver output coupled to a control terminal of one of the transistors S1-S4. For example, driver D1 has a first driver output coupled to a control terminal of transistor S1 that provides a first power stage input. Similarly, driver D2 has a second driver output coupled to a control terminal of transistor S2 that provides a second power stage input. Similarly, driver D3 has a third driver output coupled to a control terminal of transistor S3 that provides a third power stage input. Similarly, driver D4 has a fourth driver output coupled to a control terminal of transistor S4 that provides a fourth power stage input.

[0079] In an example, the system 100 includes a charge pump 408 for biasing the driver D1 of the power stage PS1, and the bootstrap circuit 404 can bias the driver D3 of the power stage PS2. In one example, the bootstrap circuit 404 includes a bootstrap switch SBST coupled between a power supply terminal 407 supplying a regulated power supply GVDD and a bootstrap capacitor CBST. The bootstrap capacitor CBST has a first terminal coupled to the bootstrap switch SBST, and a second terminal coupled to the output terminal 110 of the power stage PS2. The first terminal of the bootstrap capacitor CBST is also coupled to a driver power terminal 409 of the driver D3. In an example, during the bootstrap of the driver D3, energy is stored in the capacitor CBST from the GVDD power supply terminal 407 through the switch SBST. This energy provides bias power to the driver D3. Another driver power terminal 413 is coupled to the output terminal 110. Therefore, the driver power terminals 409 and 413 bias the driver D3.

[0080] exist Figure 4 In the example of FIG. 4 , the second power stage PS2 can be operated as a switching amplifier and include a bootstrap circuit 404 to increase the supply voltage of driver D3. This allows D3 to increase the voltage swing of control signal CS3 to fully turn on / off transistor S3. Also, the first power stage PS1 can be operated as a non-switching amplifier and the supply voltage of driver D1 does not need to be as high as driver D3. Therefore, driver D1 can be biased by charge pump 408.

[0081] The power for biasing driver D3 through bootstrap circuit 404 is supplied by a regulated supply voltage GVDD from supply terminal 407. Power supply circuit 414 has a power output 416 that supplies voltage GVDD at supply terminal 407. Power supply circuit 414 has a power input 417 coupled to supply terminals 116a, 116b, and thus, power input 417 to power supply circuit 414 receives supply voltage PVDD. Figure 4 In the example of FIG. 4 , the power circuit 414 is external to the die 208 , but in another example, the power circuit 414 may be at least partially internal to the die 208 .

[0082] Power circuit 414 has a power control input 418 coupled to a power control output 419 of power control circuit 420 from control circuit 203. Power control input 418 receives power control signal GVDD_En_delayed from control circuit 203 and generates a regulated voltage GVDD from power supply PVDD based at least in part on power control signal GVDD_En_delayed.

[0083] In addition to the auxiliary switches AS1-AS4 and the control signal generating circuit 207, the control circuit 203 further includes a power control circuit 420. The power control circuit 420 generates a power control signal GVDD_En_delayed and supplies the power control signal GVDD_En_delayed to the power circuit 414.

[0084] In an example, during startup or reset of the system 100, if the rate of increase of GVDD is too high (e.g., above a threshold level), the voltage VY may also increase with GVDD. Specifically, during startup or reset of the system 100, the control terminal of the switch SBST may be floating or not yet actively driven. As GVDD increases, charge may flow to the control terminal (e.g., gate) of the SBST (e.g., due to the parasitic capacitance of the switch SBST), which may increase the gate voltage and turn on the SBST. And, with the SBST turned on, the capacitor CBST may transfer the increased GVDD voltage (via AC coupling) to the output terminal 110 and increase the voltage VY, which may also increase the voltage VP at the speaker terminal 106. On the other hand, at least because the first power stage PS1 does not have a bootstrap circuit coupled between GVDD and the output terminal 108, and / or due to the mismatch between the first power stage and the second power stage PS2 as explained above, the voltage VN at the output terminal 108 may not experience the same increase as the voltage VP. Also, when the charge pump 408 biases the driver D1, the output terminal 108 does not receive a voltage that increases at the same high rate as the output terminal 110. Therefore, the voltage VY (and the voltage VP) may be different from (e.g., higher than) the voltage VN. This transient voltage difference between the voltages VN and VP may produce a popping sound at the speaker 102, as described above. In some examples, as will be described below, the power supply circuit 414 may control the rise of the GVDD voltage to avoid or reduce such a popping sound.

[0085] Figure 5 Show Figure 4 An example implementation of the power control circuit 420 and the power circuit 414 of the system 400, and Figure 6 A timing diagram 600 depicting the operation of the power control circuit 420 and the power circuit 414 is shown.

[0086] See also Figure 5 In one example, the power circuit 414 includes a weak GVDD regulator 504 and a strong GVDD regulator 508 configured to generate a regulated power supply GVDD from a power supply PVDD. The adjectives "weak" and "strong" are used herein, for example, to indicate that the weak GVDD regulator has a relatively smaller power rating (e.g., supplies a lower current) relative to the strong GVDD regulator.

[0087] For example, during startup or reset of system 400, weak GVDD regulator 504 is first started or reset and powers one or more components of system 400 that are involved in the startup or reset process. In an example, weak GVDD regulator 504 may not have the capacity to supply current to all components of the system that are to receive the GVDD voltage. Therefore, in order to strengthen (or later replace) the power of weak GVDD regulator 504, strong GVDD regulator 508 is initialized after a certain time (described below with respect to Figure 6 ). For example, after starting the strong GVDD regulator 508, only the strong GVDD regulator 508 (or both the strong GVDD regulator 508 and the weak GVDD regulator 504) can supply power to components that consume GVDD. Therefore, after starting the strong GVDD regulator 508, the weak GVDD regulator 504 can continue to remain on, or can be turned off.

[0088] Reference Figure 6 , showing the GVDD voltage distribution at the power supply terminal 407. The straight portion 604 shows the GVDD produced by the weak GVDD regulator 504, and the two curve portions 604 and 608 show two different scenarios, where each scenario depicts the contribution from the strong GVDD regulator 508 and the weak GVDD regulator 504.

[0089] exist Figure 6 In the example of , the steady state value of GVDD at the terminal 407 is about 5V, which is merely an example. At time t9, the weak GVDD regulator 504 is started, for example, based on the ramping or steady state value of the power supply PVDD. For example, a weak_en control signal 510 is received by the weak GVDD regulator 504 (e.g., from the power supply control circuit 420), where the weak_en control signal 510 is received in response to PVDD ramping up or at least reaching a threshold. The weak GVDD regulator 504 generates GVDD using the power supply PVDD starting at time t9 based on receiving the weak_en control signal 510. This causes the GVDD at the power supply terminal 407 to gradually increase.

[0090] In the first example, the strong GVDD regulator 508 is started at time t10 (at Figure 6 and in the second example, the strong GVDD regulator 508 is started at time t11 (in Figure 6 612).

[0091] If the strong GVDD regulator 508 is activated at time t10 (see the resulting dashed curve 608), then the GVDD at the power supply terminal 407 has a relatively small value at time t10, such as a value of about 2.5V. Figure 6. Once the strong GVDD regulator 508 starts at time t10, the GVDD at the power supply terminal 407 jumps. For example, the GVDD at the power supply terminal 407 jumps from about 2.5V to about 5V during a relatively short period of time. It should be noted that at this time, the control terminal of the switch SBST is not powered, and due to the parasitic capacitance of the switch, this sudden increase in GVDD turns on the switch SBST. And, due to the high rate of rise of GVDD (e.g., high dV / dT), the capacitor CBST AC couples GVDD to the output terminal 110. Therefore, due to the high rate of rise of GVDD (e.g., dV / dT) starting from time t10 (e.g., based on the strong GVDD regulator 508 turning on at time t10), the capacitor CBST can supply at least a portion of the GVDD voltage to the output terminal 110, thereby increasing VY and, therefore, increasing the voltage VP at the speaker terminal 106. This can cause a popping noise at the speaker 102.

[0092] In contrast, if the strong GVDD regulator 508 is activated at time t11 (see solid curve 612), the GVDD at the power supply terminal 407 has a relatively large value at time t11, such as a value of about 4.6V. Figure 6 . Once the strong GVDD regulator 508 is started at time t11, a relatively small jump occurs in the GVDD at the power supply terminal 407. For example, the GVDD at the power supply terminal 407 jumps from about 4.6V to about 5V. Therefore, since this jump is small, this jump may not cause the above-mentioned problems associated with the strong GVDD regulator starting at time t10.

[0093] Therefore, by delaying the activation of the strong GVDD regulator 508 from time t10 to time t11, the rate of rise of GVDD is reduced. For example, activation at t10 causes GVDD to rise quickly from 2.5V to 5V (e.g., a jump of 2.5V); while activation at t11 ​​causes GVDD to rise from 4.6V to 5V (e.g., a jump of only 0.4V). Therefore, by delaying the activation of the strong GVDD regulator 508 from time t10 to time t11, the popping sound in the speaker 102 caused by the jump of GVDD can be avoided or at least reduced.

[0094] See again Figure 5 , the power control circuit 420 includes an undervoltage lockout circuit 424 configured to receive feedback of a reference voltage Vref1 and a regulated power supply GVDD from the power supply terminal 407. The undervoltage lockout circuit 424 compares the feedback voltage GVDD with the reference voltage Vref1. In response to the feedback voltage GVDD being at least as high as the reference voltage Vref1, the undervoltage lockout circuit 424 enables the power control signal GVDD_En. Figure 6According to the example timing diagram of , the reference voltage Vref1 may be approximately 2.5V, or any other voltage less than 4.6V.

[0095] It should be noted that if the strong GVDD regulator 508 is enabled based on the power control signal GVDD_En, the stable GVDD may experience a relatively high jump (e.g., high dV / dT), which may cause the above-mentioned popping noise. Therefore, the power control signal GVDD_En is delayed by the delay circuit 428, which receives the power control signal GVDD_En and generates a delayed power control signal GVDD_En_delayed. For example, if the power control signal GVDD_En is enabled at time t10, then after some preconfigurable delay, such as at Figure 6 The delayed power control signal GVDD_En_delayed is enabled at time t11.

[0096] Thus, for example, the delayed power control signal GVDD_En_delayed is enabled at time t11. In response to the delayed power control signal GVDD_En_delayed being enabled at time t11, the strong GVDD regulator 508 receives the delayed power control signal GVDD_En_delayed and initiates the generation of GVDD. Figure 6 As described, enabling the strong GVDD regulator 508 at time t11 causes a relatively small jump in the GVDD at the power supply terminal 407 and thus eliminates or reduces the probability of generating a pop noise at the speaker 102 .

[0097] Thus, in an example, the delay 428 is configured such that the power circuit 414 increases GVDD by a relatively small amount (eg, within 1 second) in response to the delayed power control signal GVDD_En_delayed. Figure 6 In various examples, the increase in GVDD in response to GVDD_En_delayed may have a specific upper limit, such as 2V, 1.5V, 1V, 0.5V, etc., and may be implementation specific (e.g., depending on system design). Figure 6 In the example, GVDD is increased by 0.4V.

[0098] In various examples, the increase in GVDD in response to GVDD_En_delayed may be limited to a particular percentage of the current GVDD value (e.g., 50%, 40%, 30%, 20%, or 10%), and may be implementation specific (e.g., depending on system design). Figure 6 , GVDD increases from 4.6V to about 5V at time t11 or increases by 0.4V, which is less than about 10% of 4.6V.

[0099] In various examples, the increase in GVDD in response to GVDD_En_delayed may have a slew rate equal to or lower than, for example, 1V / 20 microseconds, 1V / 10 microseconds, 1V / 5 microseconds, 1V / 1 microsecond, etc., and may be implementation specific (eg, depending on system design).

[0100] In an example, the increase in GVDD in response to GVDD_En_delayed, whether expressed as a voltage value or a percentage or a slew rate, can be based on the speaker pop noise limit and / or sensitivity of the system (e.g., the ability of the system to handle the increase). For example, if the speaker 102 can tolerate a 2V increase or a 20% increase in GVDD at time t11 without producing an audible pop, the power control circuit 420 can be configured to increase GVDD by at most 2V or 20% each time GVDD_En_delayed is enabled. Of course, there can be an error margin, and therefore, the power control circuit 420 can be configured to increase GVDD by at most 1.8V or 18% each time GVDD_En_delayed is enabled, for example.

[0101] Figure 7 A timing diagram is shown, which shows Figure 2A-2G The operation of auxiliary transistors AS1-AS4 and Figure 4-6 For example, comparing Figure 2B and 6 The timing diagram and Figure 7 , the auxiliary transistors are turned on during time period t4 to t5, during which time GVDD_f provides power for operating auxiliary transistors AS1-AS4. The weak GVDD regulator 504 is then started at time t9, and the strong GVDD regulator 508 is started at time t11.

[0102] Figure 8 Show Figure 4 An example implementation of the power control circuit 420 and the power circuit 414 of the system 400, and Fig. 9 Show description Figure 8 4 is a timing diagram of the operation of the power control circuit 420 and the power circuit 414.

[0103] For example, in Figure 5 and 6 In , the generation of GVDD_En_delayed is a two-step process: (i) initially generating the power control signal GVDD_En at time t10 by comparing the feedback of GVDD with Vref1, and (ii) subsequently delaying GVDD_En using delay 428 to generate GVDD_En_delayed at time t11. Figure 8 and 9In the embodiment, the undervoltage lockout circuit 424 directly generates the power control signal GVDD_En_delayed at time t11 by, for example, comparing the feedback of GVDD with another reference voltage Vref2. Figure 8 and 9 The GVDD_En_delayed is generated at time t11, where Figure 5 and 6 The delay has been incorporated into GVDD_En_delayed.

[0104] In the example, Figure 8 Vref2 is higher than Figure 5 For example, for Vref1 Figure 6 and 9 Example timing diagram, Vref1 is 2.5V, and Figure 8 and 9 In the example, Vref2 is 4.6V.

[0105] In the example, about Figure 5 and 6 The above description of the relatively small jump of GVDD also applies to Figure 8 and 9 For example, Fig. 9 The jump in GVDD at about time t11 is only 0.5 V (as an example) or other jump criteria described above, and therefore, the speaker 102 may not produce an audible pop noise.

[0106] Fig.10 Show Figure 4 Another example embodiment of the power supply circuit 414 of the system 400 is Fig.11 Show description Fig.10 A timing diagram of the operation of the power supply circuit 414 is shown in FIG. Fig.10 In the example of , the weak and strong voltage regulators are replaced by a single GVDD voltage regulator 524 . Fig.11 The resulting GVDD graph is shown in . In an example, the GVDD regulator 524 ramps up the GDVV at a relatively slow slew rate equal to or lower than, for example, 1V / 20 microseconds, 1V / 5 microseconds, 1V / 1 microsecond, etc. Therefore, the change in GVDD over time (e.g., dV / dT) is not high enough to cause a popping sound in the speaker 102.

[0107] Fig.12 1 is an example flow chart showing a method 1200 for operating a speaker, such as the speaker 102. The method 1200 may be performed by, for example, the control circuit 203 in conjunction with Figure 2A-11 For example, the method 1200 is directed to the operation of the auxiliary transistors AS1 - AS4 described above.

[0108] At block 1204 of method 1200, a first voltage ramped up at respective power terminals of a first power stage circuit and a second power stage circuit is received. In an example, the first power stage circuit has a first output and the second power stage circuit has a second output. For example, the first power stage circuit is Figure 2A-2G PS1 having an output terminal 108, and the second power stage circuit is Figure 2A-2G PS2 having output terminal 110 (or terminal 106, which may also be considered as an output terminal of power stage PS2). The first voltage is PVDD at power terminals 116a and / or 116b, which ramps up at startup or during a reset process.

[0109] Method 1200 continues from 1204 to 1208. At 1208, a determination is made as to whether the first voltage is below a threshold voltage, e.g., see Figure 3 The operation of the undervoltage lockout circuit 308.

[0110] Method 1200 continues from 1208 to 1212. At 1212, in response to the first voltage being below the threshold, the first and second outputs are set to a second voltage. For example, in response to the first voltage being below the threshold (e.g., Figure 2B During the time period t4 to t5), Figure 3 The control signal generating circuit 207 enables the auxiliary transistor control signal CSS and enables or turns on the auxiliary transistors AS1-AS4. Figure 2C In the example of , the output terminals 108 and 110 are grounded through auxiliary transistors AS2 and AS4, respectively. Figure 2D As shown in , the output terminal 108 and the speaker terminal 106 are grounded through auxiliary transistors AS2 and AS4, respectively. Figure 2E As shown in , the output terminal 108 and the speaker terminal 110 are short-circuited by the auxiliary transistor AS2. Figure 2F As shown in , output terminal 108 and speaker terminal 110 are shorted and coupled to a common voltage VS. In an example, setting the first and second outputs to a second voltage eliminates or reduces the possibility of pop noise from speaker 102, for example due to a substantially zero offset voltage difference between voltages VN and VP.

[0111] In an example, setting the first and second outputs to a second voltage implies that the first and second outputs are "substantially" equal to the second voltage. The voltage difference between the first and second outputs can be limited to various percentages of the voltage of the first and second outputs, such as 10%, 5%, 3% or 2%, 1%, 0.5%, 0.1%, 0.01%, etc.

[0112] Fig.13 1 is another example flow chart of a method 1300 for operating a speaker, such as the speaker 102. The method 1300 may be performed by, for example, the control circuit 203, the power circuit 414, the power control circuit 420, and in combination with Figure 2A-11 For example, the method 1300 is directed to the generation of a regulated voltage GVDD at the power supply terminal 407 of the system 400 described above.

[0113] At block 1304, a first voltage ramped up at a power supply circuit is received. In an example, the first power stage circuit is Figure 2A-11 The first voltage is PVDD at power terminals 116a and / or 116b, which ramps up at startup or during a reset process. The first voltage is also received at power terminals of a power stage circuit coupled to the speaker, such as a first power stage PS1 and a second power stage PS2.

[0114] The method 1300 proceeds from 1304 to 1308. At 1308, in response to the first voltage reaching the first threshold voltage, a first voltage regulator is enabled to provide a second voltage at a driver power terminal of a driver circuit of the power stage circuit. For example, the first voltage regulator is a weak GVDD regulator 504, which is enabled based on the weak_en control signal 510 at time t9 described above. The second voltage is a GVDD voltage at a driver power terminal of a driver D3 of the power stage PS2.

[0115] The method 1300 then proceeds from 1308 to 1312. At 1312, after enabling the first voltage regulator, a second voltage regulator (e.g., strong voltage regulator 508) is enabled to increase a second voltage (e.g., GVDD) by no more than a certain percentage of the second voltage or at a rate that does not exceed a certain slew rate, wherein the percentage or slew rate is based on a gas pop noise level limit at the speaker 102. For example, the strong voltage regulator 508 is enabled so that the jump in GVDD is less than a threshold percentage or threshold slew rate, which is associated with a gas pop noise level limit at the speaker, as described above.

[0116] Other Examples

[0117] In this specification, the term "coupled" may encompass connections, communications, or signal paths that enable a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B through a direct connection; or (b) in a second instance, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not change the functional relationship between device A and device B, so that device B is controlled by device A via the control signal generated by device A.

[0118] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by a manufacturer, and / or may be configured (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. The configuration may be performed through firmware and / or software programming of the device, through the construction and / or layout of hardware components and interconnection of the device, or a combination thereof.

[0119] As used herein, the terms "terminal", "node", "interconnection", "pin" and "lead" are used interchangeably. Unless otherwise specified, these terms are generally used to refer to the interconnection or the termination of a device element, circuit element, integrated circuit, device or other electronic device or semiconductor component.

[0120] A circuit or device described herein as including certain components may actually be adapted to be coupled to those components to form the described circuit or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may actually include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure at the time of manufacture or after manufacture, for example, by an end user and / or a third party.

[0121] Although the use of specific transistors is described herein, other transistors (or equivalent devices) may be used instead. For example, a p-channel field effect transistor (PFET) may be used in place of an n-channel field effect transistor (NFET) with little or no change to the circuit. In addition, other types of transistors (e.g., bipolar junction transistors (BJTs)) may be used. Furthermore, the devices may be implemented in / on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0122] Reference herein to a field effect transistor (FET) being "on" means that there is a conductive channel of the FET and drain current can flow through the FET. Reference herein to a FET being "off" means that there is no conductive channel, and therefore drain current does not flow through the FET. However, an off FET can have current flowing through the body diode of the transistor.

[0123] The circuits described herein may be reconfigured to include additional or different components to provide functionality at least partially similar to functionality available before component replacement. Unless otherwise specified, components shown as resistors generally represent any one or more elements coupled in series and / or in parallel to provide the amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may alternatively be a plurality of resistors or capacitors coupled in parallel between the same nodes, respectively. For example, a resistor or capacitor shown and described herein as a single component may actually be a plurality of resistors or capacitors coupled in series between the same two nodes as a single resistor or capacitor, respectively.

[0124] The use of the phrase "ground" in the foregoing description includes chassis ground, ground wire ground, floating ground, virtual ground, digital ground, universal ground, and / or any other form of ground connection that is applicable or suitable for the teachings of this specification. In this specification, unless otherwise specified, "about", "substantially" or "generally" before a parameter means within the + / -10% range of the parameter.

[0125] Modifications are possible in the described embodiments and examples, and other embodiments and examples are possible within the scope of the claims, such as the examples below.

[0126] Example 1. A device comprising: a first power stage circuit having a first output and a first power terminal; a second power stage circuit having a second output and a second power terminal; and a control circuit having a control input, a first control output, and a second control output, the control input being coupled to the power terminal, the first control output being coupled to the first output, and the second control output being coupled to the second output, the control circuit being configured to set the first output to a second voltage and the second output to a third voltage in response to a first voltage at the first and second power terminals being lower than a threshold voltage.

[0127] Example 2. An apparatus according to Example 1, wherein the control circuit includes: a first transistor coupled between a first control output and a first voltage terminal; and a second transistor coupled between a second control output and a second voltage terminal, wherein the control circuit is configured to enable the first and second transistors in response to the first voltage being lower than a threshold voltage.

[0128] Example 3. The apparatus of example 2, wherein the first and second voltage terminals are ground terminals.

[0129] Example 4. An apparatus according to any of Examples 2 to 3, wherein the first voltage terminal is coupled to a first voltage source configured to provide a first direct current (DC) voltage, and the second voltage terminal is coupled to a second voltage source configured to provide a second DC voltage.

[0130] Example 5. The apparatus of example 4, wherein the first and second DC voltages are substantially the same.

[0131] Example 6. The apparatus of example 4, wherein the first and second DC voltages are different DC voltages.

[0132] Example 7. The apparatus of any of Examples 2 to 6, wherein the first voltage terminal and the second voltage terminal are coupled to a voltage source, and the first and second voltages are the same voltage.

[0133] Example 8. The apparatus of any of Examples 1-7, wherein the control circuit includes a transistor coupled between the first and second control outputs, and the control circuit is configured to enable the transistor in response to the first voltage being below a threshold voltage.

[0134] Example 9. An apparatus according to any one of Examples 1 to 8, wherein: the control circuit has a third control output and a fourth control output; and the first power stage circuit has a first power stage control input, the second power stage circuit has a second power stage control input, the first power stage control input is coupled to the third control output, and the second power stage control input is coupled to the fourth control output; wherein the control circuit is configured to set the first and second power stage control inputs to a disabled state in response to a first voltage at the first and second power terminals being lower than a threshold; wherein the first power stage circuit is configured to disconnect the first output from the first power terminal in response to the first power stage control input being in a disabled state; and wherein the second power stage circuit is configured to disconnect the second output from the second power terminal in response to the second power stage control input being in a disabled state.

[0135] Example 10. An apparatus according to Example 9, wherein the control circuit includes: a first transistor coupled between the third control output and the voltage terminal; and a second transistor coupled between the fourth control output and the voltage terminal, wherein the control circuit is configured to enable the first and second transistors in response to the first voltage being below a threshold.

[0136] Example 11. The apparatus of Example 10, wherein the voltage terminal is a ground terminal.

[0137] Example 12. An apparatus according to any one of Examples 9 to 10, wherein: the first power stage has a third power stage control input and includes: a first transistor coupled between the first power terminal and the first output, the first transistor having a first control terminal coupled to the first power stage control input; and a second transistor coupled between the first output and the ground terminal, the second transistor having a second control terminal coupled to the third power stage control input; and the second power stage has a fourth power stage control input and includes: a third transistor coupled between the second power terminal and the second output, the third transistor having a third control terminal coupled to the second power stage control input; and a fourth transistor coupled between the second output and the ground terminal, the fourth transistor having a fourth control terminal coupled to the fourth power stage control input.

[0138] Example 13. An apparatus according to any one of Examples 1 to 12, wherein the control circuit has a power control output and is configured to provide a power control signal at the power control output in response to a first voltage at the first and second power terminals exceeding a second threshold voltage; and wherein the apparatus further includes: a first driver circuit having a first driver output, the first driver output coupled to a first power stage control input; a second driver circuit having a second driver output and a driver power terminal, the second driver output coupled to a second power stage control input; a third driver circuit having a third driver output, the third driver output coupled to a third power stage control input; a fourth driver circuit having a fourth driver output, the fourth driver output coupled to a fourth power stage control input; and a power supply circuit having a power input, a power control input and a power output, the power input being coupled to the first and second power terminals, the power control input being coupled to the power control output, the power output being coupled to the driver power terminal via the third power terminal, the power supply circuit being configured to provide a fourth voltage at the driver power terminal and to increase the fourth voltage in response to the power control signal.

[0139] Example 14. The apparatus of Example 13, wherein the power circuit is configured to increase the fourth voltage by no more than a certain percentage of the fourth voltage or at a rate that does not exceed a certain slew rate in response to the power control signal, wherein the percentage and the slew rate are based on a speaker pop noise limit.

[0140] Example 15. An apparatus according to any one of Examples 13 to 14, wherein the power control signal is a first power control signal, the power control input is a first power control input, the control circuit has a second power control output, the power circuit has a second power control input coupled to the second power control output, and the power circuit includes: a first voltage regulator having a first regulator input, a first regulator enable input, and a first regulator output, the first regulator input coupled to the power input, the first regulator enable input coupled to the first power control input, the first regulator output coupled to the power output, and the first voltage regulator responsive to the first voltage a second regulator having a second regulator input, a second regulator enable input, and a second regulator output, the second regulator input being coupled to the power input, the second regulator enable input being coupled to the second power control input, and the second regulator output being coupled to the power output, the second voltage regulator being configured to supply a smaller current at the power output than the first voltage regulator and being enabled in response to the second power control signal at the second regulator enable input; wherein the control circuit is configured to provide the second power control signal to enable the second voltage regulator and subsequently provide the first power control signal to enable the first voltage regulator.

[0141] Example 16. The apparatus of Example 15, wherein the control input is a first control input, the control circuit has a second control input coupled to the third power terminal, and the control circuit is configured to provide the first power control signal in response to the second voltage exceeding a third threshold voltage.

[0142] Example 17. An apparatus according to Example 16, wherein the control circuit is configured to provide a third power control signal in response to the second voltage exceeding a third threshold voltage, and the control circuit includes a delay circuit configured to provide the third power control signal by adding a specific delay to the third power control signal.

[0143] Example 18 The apparatus of any of Examples 13 to 17, further comprising a bootstrap circuit coupled between the second power terminal and the driver power terminal.

[0144] Example 19. The apparatus of any of Examples 1 to 18, wherein the first and second power stages and the control circuit are part of an integrated circuit.

[0145] Example 20. A device comprising: a first power stage circuit having a first output and a first power terminal; a second power stage circuit having a second output and a second power terminal; a capacitor coupled between the first output and a ground terminal; a speaker having a first speaker terminal and a second speaker terminal, the first speaker terminal being coupled to the first output; an inductor coupled between the second output and the second speaker terminal; and a control circuit having a control input, a first control output, and a second control output, the control input being coupled to the first and second power terminals, the first control output being coupled to the first output, and the second control output being coupled to the second output or the second speaker terminal, the controller being configured to set the first output to a second voltage and the second output to a third voltage in response to a first voltage at the first and second power terminals being lower than a threshold voltage.

[0146] Example 21. An apparatus according to Example 20, wherein the control circuit includes: a first transistor coupled between a first control output and a first voltage terminal; and a second transistor coupled between a second control output and a second voltage terminal, wherein the control circuit is configured to enable the first and second transistors in response to the first voltage being lower than a threshold voltage.

[0147] Example 22. The apparatus of Example 21, wherein each of the first and second voltage terminals is a ground terminal.

[0148] Example 23. A method includes: receiving a first voltage ramped up at corresponding power terminals of a first power stage circuit and a second power stage circuit, wherein the first power stage circuit has a first output and the second power stage circuit has a second output; determining whether the first voltage is lower than a threshold; and in response to the first voltage being lower than the threshold, setting the first and second outputs to a second voltage.

[0149] Example 24. The method of Example 23, wherein the second voltage is a voltage of a ground terminal.

[0150] Example 25. A method includes: receiving a first voltage ramped at a first power terminal of a power stage circuit coupled to a speaker and at a second power terminal of a power supply circuit; in response to the first voltage reaching a first threshold voltage, enabling a first voltage regulator of the power supply circuit to provide a second voltage at a driver power terminal of a driver circuit of the power stage circuit; and after enabling the first voltage regulator, enabling a second voltage regulator of the power supply circuit to increase the second voltage by no more than a specific percentage of the second voltage or at a rate that does not exceed a specific slew rate, wherein the percentage or the slew rate is based on a pop noise level limit at the speaker.

[0151] Example 26. The method of example 25, wherein enabling the second voltage regulator includes enabling the second voltage regulator in response to the second voltage exceeding a threshold voltage.

[0152] Example 27. The method of example 27, wherein enabling the second voltage regulator comprises enabling the second voltage regulator after a delay time has elapsed since the second voltage exceeded a threshold voltage.

Claims

1. A device comprising: a first power stage circuit having a first output and a first power terminal; a second power stage circuit having a second output and a second power terminal; as well as a control circuit having a control input coupled to the first and second power terminals, a first control output coupled to the first output, and a second control output A control output is coupled to the second output, the control circuit being configured to set the first output to a second voltage and the second output to a third voltage in response to a first voltage at the first and second power terminals being below a threshold voltage.

2. The apparatus of claim 1 , wherein the control circuit comprises: a first transistor coupled between the first control output and a first voltage terminal; and a second transistor coupled between the second control output and a second voltage terminal, Wherein the control circuit is configured to enable the first and second transistors in response to the first voltage being lower than the threshold voltage. 3 . The apparatus of claim 2 , wherein each of the first and second voltage terminals is a ground terminal. 4 . The device of claim 2 , wherein the first voltage terminal is coupled to a first voltage source configured to provide a first direct current (DC) voltage, and the second voltage terminal is coupled to a second voltage source configured to provide a second DC voltage.

5. The apparatus of claim 4, wherein the first and second DC voltages are substantially the same.

6. The apparatus of claim 4, wherein the first and second DC voltages are different DC voltages.

7. The apparatus of claim 2, wherein the first voltage terminal and the second voltage terminal are coupled to a voltage source, and the first and second voltages are the same voltage.

8. The apparatus of claim 1, wherein the control circuit comprises a transistor coupled between the first and second control outputs, and the control circuit is configured to enable the transistor in response to the first voltage being below the threshold voltage.

9. The apparatus of claim 1, wherein: The control circuit has a third control output and a fourth control output; and The first power stage circuit has a first power stage control input, the second power stage circuit has a second power stage control input, the first power stage control input is coupled to the third control output, and the second power stage control input is coupled to the fourth control output; wherein the control circuit is configured to set the first and second power stage control inputs to a disabled state in response to the first voltage at the first and second power terminals being below the threshold voltage; wherein the first power stage circuit is configured to disconnect the first output from the first power terminal in response to the first power stage control input being in the deactivated state; and Wherein the second power stage circuit is configured to disconnect the second output from the second power terminal in response to the second power stage control input being in the disabled state.

10. The apparatus of claim 9, wherein the control circuit comprises: a first transistor coupled between the third control output and a voltage terminal; and a second transistor coupled between the fourth control output and the voltage terminal, Wherein the control circuit is configured to enable the first and second transistors in response to the first voltage being lower than the threshold. The apparatus of claim 10 , wherein the voltage terminal is a ground terminal.

12. The apparatus of claim 9, wherein: The first power stage circuit has a third power stage control input and comprises: a first transistor coupled between the first power terminal and the first output, the first transistor having a first control terminal coupled to the first power stage control input; as well as a second transistor coupled between the first output and a ground terminal, the second transistor having a second control terminal coupled to the third power stage control input; and The second power stage circuit has a fourth power stage control input and comprises: a third transistor coupled between the second power terminal and the second output, the third transistor having a third control terminal coupled to the second power stage control input; as well as A fourth transistor is coupled between the second output and the ground terminal, the fourth transistor having a fourth control terminal coupled to the fourth power stage control input.

13. The apparatus of claim 1 , wherein the control circuit has a power control output and is configured to provide a power control signal at the power control output in response to the first voltage at the first and second power terminals exceeding a second threshold voltage; and The device further comprises: a first driver circuit having a first driver output coupled to a first power stage control input; a second driver circuit having a second driver output and a driver power terminal, the second driver output coupled to the second power stage control input; a third driver circuit having a third driver output coupled to a third power stage control input; a fourth driver circuit having a fourth driver output coupled to a fourth power stage control input; and A power supply circuit having a power input, a power control input and a power output, wherein the power input is coupled to the first and second power terminals, the power control input is coupled to the power control output, and the power output is coupled to the driver power terminal via a third power terminal, wherein the power supply circuit is configured to provide a fourth voltage at the driver power terminal and increase the fourth voltage in response to the power control signal.

14. The apparatus of claim 13, wherein the power circuit is configured to increase the fourth voltage by no more than a certain percentage of the fourth voltage or at a rate not exceeding a certain slew rate in response to the power control signal, wherein the percentage and the slew rate are based on a speaker pop noise limit.

15. The apparatus of claim 13, wherein the power control signal is a first power control signal, the power control input is a first power control input, the control circuit has a second power control output, the power circuit has a second power control input coupled to the second power control output, and the power circuit comprises: a first voltage regulator having a first regulator input, a first regulator enable input, and a first regulator output, the first regulator input being coupled to the power input, the first regulator enable input being coupled to the first power control input, the first regulator output being coupled to the power output, and the first voltage regulator being enabled in response to the first power control signal; as well as a second voltage regulator having a second regulator input coupled to the power input, a second regulator enable input coupled to the second power supply control input, and a second regulator output coupled to the power output, the second voltage regulator configured to supply less current at the power output than the first voltage regulator and enabled in response to a second power supply control signal at the second regulator enable input; The control circuit is configured to provide the second power supply control signal to enable the second voltage regulator and then provide the first power supply control signal to enable the first voltage regulator.

16. The apparatus of claim 15, wherein the control input is a first control input, the control circuit has a second control input coupled to the third power terminal, and the control circuit is configured to provide the first power control signal in response to the second voltage exceeding a third threshold voltage.

17. The apparatus of claim 16, wherein the control circuit is configured to provide a third power control signal in response to the second voltage exceeding the third threshold voltage, and the control circuit includes a delay circuit configured to provide the third power control signal by adding a specific delay to the third power control signal.

18. The apparatus of claim 13, further comprising a bootstrap circuit coupled between the third power terminal and the driver power terminal.

19. The apparatus of claim 1, wherein the first and second power stages and the control circuit are part of an integrated circuit.

20. An apparatus comprising: a first power stage circuit having a first output and a first power terminal; a second power stage circuit having a second output and a second power terminal; a capacitor coupled between the first output and a ground terminal; a speaker having a first speaker terminal and a second speaker terminal, the first speaker terminal being coupled to the first output; an inductor coupled between the second output and the second speaker terminal; as well as a control circuit having a control input coupled to the first and second power terminals, a first control output coupled to the first output, and a second control output A control output is coupled to the second output or the second speaker terminal, the control circuit being configured to set the first output to a second voltage and the second output to a third voltage in response to a first voltage at the first and second power terminals being below a threshold voltage.

21. The apparatus of claim 20, wherein the control circuit comprises: a first transistor coupled between the first control output and a first voltage terminal; and a second transistor coupled between the second control output and a second voltage terminal, Wherein the control circuit is configured to enable the first and second transistors in response to the first voltage being lower than the threshold voltage.

22. The apparatus of claim 21, wherein each of the first and second voltage terminals is a ground terminal.

23. A method comprising: receiving a first voltage ramped up at respective power terminals of a first power stage circuit and a second power stage circuit, wherein the first power stage circuit has a first output and the second power stage circuit has a second output; determining whether the first voltage is lower than a threshold; as well as In response to the first voltage being lower than the threshold, the first and second outputs are set to a second voltage. The method according to claim 23 , wherein the second voltage is a voltage of a ground terminal.

25. A method comprising: receiving a first voltage ramped at a first power terminal of a power stage circuit coupled to a speaker and at a second power terminal of a power supply circuit; in response to the first voltage reaching a first threshold voltage, enabling a first voltage regulator of the power supply circuit to provide a second voltage at a driver power terminal of a driver circuit of the power stage circuit; as well as After enabling the first voltage regulator, enabling a second voltage regulator of the power supply circuit to increase the second voltage by no more than a certain percentage of the second voltage or at a rate that does not exceed a certain slew rate, wherein the percentage or slew rate is based on a pop noise level limit at the speaker.

26. The method of claim 25, wherein enabling the second voltage regulator comprises enabling the second voltage regulator in response to the second voltage exceeding a threshold voltage.

27. The method of claim 26, wherein enabling the second voltage regulator comprises enabling the second voltage regulator after a delay time has elapsed since the second voltage exceeded the threshold voltage.

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