Radio frequency controller and electronic equipment

Abstract

The embodiment of the invention provides a radio frequency controller and electronic equipment, which are used for improving the success rate of data transmission. The electronic equipment comprises a central processing unit and the radio frequency controller, the radio frequency controller comprises a switching network, at least one frame timer and at least one time sequence processor, and the at least one frame timer and the at least one time sequence processor are connected with the timing switching network; wherein the central processing unit is used for determining a target frame timer corresponding to a first task from at least one frame timer and determining a target time sequence processor corresponding to the first task from at least one time sequence processor when the first task is started; the target frame timer is used for counting frames; the timing switching network is used for associating the target frame timer with the target time sequence processor; and the target time sequence processor is used for executing the first task when the count value of the target frame timer is the same as the time parameter stored in the target time sequence processor.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a radio frequency controller and electronic equipment. Background Art

[0002] In wireless communication systems, in order to synchronize data transmission between electronic devices and the network, the most common method is to achieve data transmission through a radio frequency controller. For example, the frame timing module in the radio frequency controller is compared with the time parameters stored in the timing processing module. When the count value of the frame timing module is the same as the time parameter stored in the timing processing module, data transmission is performed.

[0003] However, in a dual-mode or multi-mode system, when switching from one communication mode to another, the frame timing module may need to be phase adjusted. After the phase of the frame timing module is adjusted, the RF controller may trigger data transmission at the wrong time, resulting in data transmission failure. Summary of the invention

[0004] The embodiments of the present application provide a radio frequency controller and an electronic device for improving the success rate of data transmission.

[0005] In a first aspect, a radio frequency controller is provided, which can be set in an electronic device, the electronic device includes a central processing unit and a radio frequency controller, the central processing unit is connected to the radio frequency controller, the radio frequency controller includes a switching network, at least one frame timer and at least one timing processor, the at least one frame timer and the at least one timing processor are connected to the timing switching network; wherein the central processing unit is used to determine the target frame timer corresponding to the first task from the at least one frame timer when the first task is started, and determine the target timing processor corresponding to the first task from the at least one timing processor; the target frame timer is used to perform frame counting; the timing switching network is used to associate the target frame timer with the target timing processor; the target timing processor is used to execute the first task when the count value of the target frame timer is the same as the time parameter stored in the target timing processor.

[0006] In a possible implementation, the RF controller further includes a first arbitrator, which is connected to the at least one timing processor and is used to determine whether the data transmission instruction output by the target timing processor conflicts with the data transmission instruction output by other timing processors, wherein the other timing processors are timing processors other than the target timing processor in the at least one timing processor.

[0007] In a possible implementation, the first arbitrator is specifically used to: determine the data transmission interface indicated by the data transmission instruction output by each timing processor of the at least one timing processor; if the first data transmission instruction output by the target timing processor is the same as the data transmission interface indicated by the second data transmission instruction output by the first timing processor of the other timing processors, then determine that the data transmission instructions output by the target timing processor and the first timing processor conflict.

[0008] In a possible implementation manner, the radio frequency controller further includes an interface control module, the interface control module is connected to the first arbitrator, and the interface control module includes at least one data transmission interface.

[0009] In a possible implementation, the radio frequency controller further includes at least one instruction cache module, and the at least one instruction cache module corresponds one-to-one to the at least one data transmission interface.

[0010] In a possible implementation, the first arbitrator is further used for: when a first data transfer instruction output by the target timing processor conflicts with a second data transfer instruction output by a first timing processor in the other timing processors, determining an execution order of the first data transfer instruction and the second data transfer instruction according to the priority of the target timing processor and the first timing processor; inputting the first data transfer instruction and the second data transfer instruction into a first instruction cache module in the at least one instruction cache module based on the execution order, the first instruction cache module corresponding to a first data transfer interface, and the first data transfer interface being the data transfer interface indicated by the first data transfer instruction and the second data transfer instruction.

[0011] In a possible implementation, the RF controller further includes a data storage device, which is connected to the at least one timing processor and is used to store intermediate data generated when the at least one timing processor performs a task, and / or task data required for the at least one timing processor to perform a task.

[0012] In a possible implementation, the RF controller also includes a second arbitrator, the RF controller also includes a second arbitrator, the second arbitrator is connected to the at least one timing processor and the data storage device, and is used to determine whether the data read and write instructions output by the target timing processor conflict with the data read and write instructions output by other timing processors, and the other timing processors are timing processors other than the target timing processor in the at least one timing processor.

[0013] In a possible implementation, the second arbitrator is further used to determine the execution order of the first data read and write instruction and the second data read and write instruction according to the priority of the target timing processor and the second timing processor when the first data read and write instruction output by the target timing processor conflicts with the second data read and write instruction output by the second timing processor among the other timing processors.

[0014] In a second aspect, a data transmission method is provided, which can be applied to the electronic device described in the first aspect, and the method includes: when a first task is started, determining a target frame timer corresponding to the first task from at least one frame timer, determining a target timing processor corresponding to the first task from at least one timing processor, and executing the first task when the count value of the target frame timer is the same as the time parameter stored in the target timing processor.

[0015] In a possible implementation, the method further includes: determining whether the data transfer instruction output by the target timing processor conflicts with the data transfer instruction output by other timing processors, where the other timing processors are timing processors other than the target timing processor in the at least one timing processor.

[0016] In one possible implementation, determining whether the data transfer instruction output by the target timing processor conflicts with the data transfer instruction output by other timing processors includes: determining the data transfer interface indicated by the data transfer instruction output by each timing processor in the at least one timing processor; if the first data transfer instruction output by the target timing processor is the same as the data transfer interface indicated by the second data transfer instruction output by the first timing processor in the other timing processors, determining that the data transfer instructions output by the target timing processor conflict with the first timing processor.

[0017] In a possible implementation, the method further includes: when a first data transmission instruction output by the target timing processor conflicts with a second data transmission instruction output by a first timing processor among the other timing processors, executing the first data transmission instruction and the second data transmission instruction according to the priority of the target timing processor and the first timing processor.

[0018] In a possible implementation, the method further includes: determining whether the data read and write instructions output by the target timing processor conflict with the data read and write instructions output by other timing processors, wherein the other timing processors are timing processors other than the target timing processor in the at least one timing processor.

[0019] In one possible implementation, determining whether a data read and write instruction output by the target timing processor conflicts with a data read and write instruction output by other timing processors includes: when a first data read and write instruction output by the target timing processor conflicts with a second data read and write instruction output by a second timing processor among the other timing processors, determining the execution order of the first data read and write instruction and the second data read and write instruction according to the priority of the target timing processor and the second timing processor.

[0020] In a third aspect, an electronic device is provided, comprising a radio frequency controller and a central processing unit as described in any one of the first aspects above.

[0021] According to a fourth aspect, a communication device is provided, the device comprising:

[0022] A memory for storing program instructions;

[0023] The processor is used to call the program instructions stored in the memory and execute the steps included in any one of the methods described in the two aspects according to the obtained program instructions.

[0024] In a fifth aspect, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the steps included in any one of the methods described in the second aspect.

[0025] In a sixth aspect, a computer program product comprising instructions is provided, and when the computer program product is run on a computer, the computer is enabled to execute the data transmission method described in the above-mentioned various possible implementations.

[0026] In an embodiment of the present application, the RF processor may include multiple frame timers, so that in a dual-mode or multi-mode system, the central processor can configure frame timers for different communication modes respectively, so that when switching from one communication mode to another communication mode, there is no need to adjust the phase of the frame timer, which reduces the probability of data transmission instructions being triggered at the wrong time and improves the success rate of data transmission. In addition, in an embodiment of the present application, the RF processor may also include multiple timing processors, so that in a dual-mode or multi-mode system, data transmission instructions under different communication modes can be stored through different timing processors, that is, the time included in the data transmission instructions stored in different timing processors is related to their corresponding communication modes, so even if switching from one communication mode to another communication mode, even if the phase of the frame timer is adjusted, the data transmission instruction can be avoided from being triggered at the wrong time, which helps to improve the success rate of data transmission.

[0027] In addition, in an embodiment of the present application, the timing processor can be scheduled as a shared resource without designing frame timers and timing processors in pairs. That is, in a certain communication mode, at most all timing processors can be called to execute timing tasks, so that multiple tasks can be performed in parallel, effectively improving resource utilization. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for describing the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application.

[0029] Figure 1 A schematic diagram of the structure of an electronic device;

[0030] Figure 2 A schematic diagram of the structure of another electronic device provided in an embodiment of the present application;

[0031] Figure 3 A schematic diagram of the structure of a timing processor;

[0032] Figure 4 A schematic diagram of the structure of a radio frequency controller provided in an embodiment of the present application;

[0033] Figure 5 A flowchart of a data transmission method provided in an embodiment of the present application;

[0034] Figure 6 It is a schematic diagram of the structure of a communication device in an embodiment of the present invention. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical scheme and advantages of the present application clearer, the technical scheme in the embodiment of the present application will be clearly and completely described below in conjunction with the drawings in the embodiment of the present application. Obviously, the described embodiment is only a part of the embodiment of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application. In the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined with each other arbitrarily. In addition, although the logical order is shown in the flow chart, in some cases, the steps shown or described can be performed in an order different from that here.

[0036] The terms "first" and "second" in the specification and claims of the present application and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the term "comprising" and any of their variations are intended to cover non-exclusive protection. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the listed steps or units, but optionally also includes steps or units that are not listed, or optionally also includes other steps or units inherent to these processes, methods, products or devices. "Multiple" in the present application can mean at least two, for example, two, three or more, and the embodiments of the present application are not limited.

[0037] The design concept of this application is introduced as follows.

[0038] As mentioned above, in a wireless communication system, in order to synchronize the data transmission of an electronic device with the network, the most commonly used method is to realize data transmission through a radio frequency controller. For example, in a time division synchronous code division multiple access (D-SCDMA) system, in order for an electronic device to receive information in a certain time slot, at least two instructions are stored in a timing processing module, one is a data reception start instruction, and the other is a data reception stop instruction. These instructions contain time parameters, and the timing processing module can compare the time parameters contained in each instruction with the count value of the frame timing module. When the count value of the frame timing module is consistent with the time parameter contained in the data reception start instruction, the interface control module is triggered to start receiving data; when the count value of the frame timing module is consistent with the time parameter in the data reception stop instruction, the interface control module is triggered to stop receiving data.

[0039] However, in a dual-mode or multi-mode system, when switching from one communication mode to another communication mode, it is often necessary to adjust the phase of the frame timing module of the current communication mode. Once the phase of the frame timing module is adjusted, it may affect the triggering of the instructions that have been configured in the timing processing module before the adjustment. For example, if the data reception start instruction 1 and the data reception stop instruction 1 have been stored in the timing processing module before the phase of the frame timing module is adjusted, then after adjusting the phase of the frame timing module, the data reception start instruction 1 and the data reception stop instruction 1 may be triggered at the wrong time, resulting in data reception failure.

[0040] In the related art, in order to solve this technical problem, one solution is to bind the frame timing module and the timing processor in pairs to support multiple communication modes. However, in more communication modes, if the number of timing processors is configured according to the type of communication mode, design redundancy may occur, that is, the resource utilization of the timing processor is low, and in the same communication mode, multiple timing tasks can only be processed serially, and the data transmission efficiency is low.

[0041] In view of this, an embodiment of the present application provides a radio frequency controller, which can be applied to an electronic device, the electronic device includes the radio frequency controller and a central processing unit (CPU), the radio frequency controller includes a timing switching network, at least one frame timer and at least one timing processor, the central processing unit can flexibly configure the association between the frame timer and the timing processor, so that a timing processor can be associated with different frame timers at different times, reducing the number of settings of the timing processor. In addition, the timing processor can be scheduled as a shared resource, without designing the frame timer and the timing processor in pairs, that is, in a certain communication mode, at most all the timing processors can be called to perform timing tasks, so that multiple tasks can be performed in parallel, effectively improving resource utilization.

[0042] After introducing the design ideas of the embodiments of the present application, the following briefly introduces the application scenarios to which the technical solutions of the embodiments of the present application can be applied. It should be noted that the application scenarios introduced below are only used to illustrate the embodiments of the present application and are not limited. In specific implementation, the technical solutions provided by the embodiments of the present application can be flexibly applied according to actual needs.

[0043] In the embodiment of the present application, the provided radio frequency controller can be applied to electronic devices. Figure 1 , Figure 1 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application, the electronic device includes a central processing unit and a radio frequency controller. The central processing unit can generate an instruction file and a data file according to the requirements of the upper-layer software, wherein the instruction file includes a time parameter, which can indicate the time of data transmission, and the data file can include task data required for the radio frequency controller to perform a task. After generating the instruction file and the data file, the central processing unit can send the instruction file and the data file to the radio frequency controller.

[0044] Based on the above content, the radio frequency controller provided in the embodiment of the present application is introduced below in conjunction with the drawings in the specification.

[0045] See also Figure 2 , is a schematic diagram of the structure of another electronic device provided in an embodiment of the present application, the radio frequency controller can be applied to Figure 1The RF controller includes at least one frame timer (such as Figure 1 Frame timer 1, frame timer 2, ..., frame timer m), a timing switching network and at least one timing processor (such as Figure 1 The timing processor 1, timing processor 2, ..., timing processor n) shown in the figure, m and n are positive integers. Among them,

[0046] The central processing unit is used to determine the target frame timer corresponding to the first task from at least one (for example, m) frame timers and the target timing processor corresponding to the first task from at least one (for example, n) timing processors when the first task is started.

[0047] The frame timer is used to synchronously track the wireless frames of electronic devices, that is, to count. The counting frequency is determined by the timing control accuracy requirement. For example, the chip rate of TD-SCDMA is 1.28M, the timing control accuracy requirement is one eighth of a chip, and the frame timer counting frequency is 10.24M.

[0048] A timing switching network is used to associate the target frame timer with a target timing processor.

[0049] The timing processor is used to execute the data transmission task when the time parameter stored in the timing processor is the same as the count value of the associated frame timer. For example, the target timing processor executes the first task when the time parameter stored in the timing processor is the same as the count value of the target frame timer.

[0050] Optionally, m may be related to the number of communication modes included in the current communication system. For example, if the current communication system includes 4 communication modes, m may be less than or equal to 4. When m=4, one frame timer may correspond to one communication mode, so that when switching from one communication mode to another, there is no need to adjust the phase of the frame timer.

[0051] In an embodiment of the present application, when an electronic device transmits data with a network (for example, to start a first task), the central processor of the electronic device can generate instruction files and data files according to the requirements of the upper-level software, and determine at least one idle timing processor from the n timing processors, and determine a target timing processor for executing the first task from the at least one idle timing processor.

[0052] For example, the central processing unit may determine the target timing processor from the at least one idle timing processor according to the importance of the first task. For example, when designing the baseband chip, the n timing processors may be prioritized, and when the central processing unit determines that the importance of the first task is high, it may determine that the timing processor with the highest priority among the at least one idle timing processor is the target timing processor. Optionally, if the RF controller includes multiple data transmission interfaces, the priorities of the n timing processors may be different for different data transmission interfaces. For example, if the RF controller includes two interfaces, namely interface 1 and interface 2, and n=3, then for interface 1, the three timing processors are arranged in order from high to low priority, for example, timing processor 2, timing processor 3, and timing processor 1, and for interface 2, the three timing processors are arranged in order from high to low priority, for example, timing processor 1, timing processor 2, and timing processor 3.

[0053] Alternatively, the central processor may also randomly select a timing processor from the at least one idle timing processor and determine the timing processor as the target timing processor. It should be noted that the above method of determining the target timing processor is only an example. In the specific implementation process, the target timing processor may also be determined by other methods, and the embodiments of the present application are not limited to this.

[0054] And, the central processor can determine the target frame timer corresponding to the first task from the m frame timers according to the current communication mode of the electronic device. For example, if the number of the frame timers is the same as the types of communication modes included in the current communication system, the central processor can pre-configure the association between the frame timer and the communication mode. When the first task is started, the central processor can determine the current communication mode of the electronic device and determine the frame timer associated with the communication mode as the target frame timer. Optionally, the frame timer corresponding to the first task can be a frame timer corresponding to other tasks, wherein the other tasks and the first task are tasks under the same communication mode.

[0055] Alternatively, the central processor may also randomly determine a frame timer from the m frame timers, and determine the target frame timer with the frame timer. Optionally, when the central processor randomly determines the target frame timer from the m frame timers, if the current phase of the target frame timer is different from the phase corresponding to the current communication mode, the phase of the target frame timer may also be adjusted based on the current communication mode.

[0056] After determining the target frame timer and the target timing processor, the central processor may send configuration information to the timing switching network, where the configuration information includes information for indicating the target frame timer and the target timing processor.

[0057] The timing switching network may determine the target frame timer and the target timing processor based on the configuration information, and configure the target frame timer and the target timing processor to be associated.

[0058] Optionally, after determining the target sequential processor, the central processor may write the generated instruction file into the random access memory (RAM) of the target sequential processor. The target sequential processor may execute the first task based on the time parameters included in the instruction file stored in its RAM and the count value of the corresponding frame timer.

[0059] For example, see Figure 3 , is a schematic diagram of the structure of a timing processor. Figure 3 As shown, the timing processor includes an instruction extraction module, a storage module, a decoding module and an execution module. Among them, the storage module is used to store instruction files; the instruction extraction module is used to read instructions from the storage module and cache them in the instruction extraction module; the decoding module is used to decode the instructions in the instruction extraction module; the execution module is used to execute the data transmission task when the time indicated by the decoded instruction arrives (that is, the time indicated by the decoded instruction is the same as the count value of the corresponding frame timer). Optionally, the timing processor may also include a sequence timer, which is controlled by the frame timer and can be started by the frame timer. After the sequence timer is started, the timing processor can compare the count value of the sequence timer with the time parameters included in the instruction stored in its storage module. When the time parameters included in the instruction stored in its storage module are the same as the count value of its sequence timer, the data transmission task is executed.

[0060] Optional, please refer to Figure 4 The RF controller further includes a first arbitrator and an interface controller module. The first arbitrator is connected to the n timing processors and is used to determine whether the data transmission instructions output by the n timing processors conflict. For example, the first arbitrator can determine whether the data transmission instruction output by the target timing processor conflicts with the data transmission instruction output by other timing processors among the n timing processors except the target timing processor.

[0061] The interface control module includes at least one (e.g., K) data transmission interface, which is connected to the first arbitrator and is used to receive data from the network or send data to the network according to the data transmission instruction output by the timing processor. The K data transmission interfaces include, for example: a general purpose output interface (GPO), a serial peripheral interface (SPI) / radio frequency front-end (RFFE), a transistor-transistor logic (TTL) interface, a JESD interface, a digital radio frequency (DigRF) interface, etc.

[0062] For example, the first arbitrator can determine the data transmission interface indicated by the data transmission instruction output by each of the n timing processors. If the data transmission instruction output by the first timing processor among the other timing processors (for example, the second data transmission instruction) and the data transmission instruction output by the target timing processor (for example, the first data transmission instruction) are the same, for example, the data transmission interfaces indicated by the first data transmission instruction and the second data transmission instruction are both GPO, then the first arbitrator can determine that the data transmission instructions output by the target timing processor and the first timing processor conflict.

[0063] Optionally, before determining whether the data transmission instructions output by the n sequential processors conflict, the first arbitrator may also determine whether the data transmission times indicated by the data transmission instructions output by the n sequential processors are the same, and perform conflict detection on the data transmission instructions with the same data transmission times, i.e., determine whether the data transmission instructions conflict. Taking the aforementioned first data transmission instruction and the third data transmission instruction as an example, if the data transmission times indicated by the first data transmission instruction and the third data transmission instruction are different, i.e., the execution times of the first task and the second task (the data transmission task corresponding to the third data transmission instruction) are different, it indicates that there is no conflict between the first data transmission instruction and the third data transmission instruction, and conflict detection may not be performed on the first data transmission instruction and the third data transmission instruction.

[0064] Optionally, the RF controller may further include K instruction cache modules, which may be, for example, first-in-first-out memories. The K instruction cache modules correspond one-to-one to the aforementioned K data transmission interfaces, and are used to cache data transmission instructions of their corresponding interfaces. For example, instruction cache module 1 corresponds to data transmission interface 1, and instruction cache module 1 is used to cache data transmission instructions for indicating data transmission through data transmission interface 1. Among them, the K instruction cache modules may be arranged in the first arbitrator; or, they may also be arranged independently, for example, the K instruction cache modules may be arranged as independent devices between the first arbitrator and the interface control module. The embodiment of the present application does not limit the setting position of the instruction cache module, Figure 4 The K instruction cache modules are set as independent devices as an example.

[0065] When the first arbitrator determines that the first data transmission instruction does not conflict with the data transmission instructions output by other timing processors, the first data transmission instruction may be input into the instruction cache module corresponding to the data transmission interface indicated by the first data transmission instruction. For example, if the data transmission interface indicated by the first data transmission instruction is data transmission interface i, and the instruction cache module corresponding to data transmission interface i is instruction cache module i, then the first arbitrator may input the first data transmission instruction into the instruction cache module i.

[0066] When the first arbitrator determines that the first data transmission instruction conflicts with the second data transmission instruction, it can determine the execution order of the first data transmission instruction and the second data transmission instruction according to the priority of the target timing processor and the first timing processor, and then input the first data transmission instruction and the second data transmission instruction into the first instruction cache module based on the execution order. The first instruction cache module is the instruction cache module corresponding to the first data transmission interface, and the first data transmission interface is the data transmission interface indicated by the first data transmission instruction and the second data transmission instruction. Optionally, the priority of the target timing processor and the first timing processor is the priority between the timing processors corresponding to the first data transmission interface.

[0067] For example, among the priorities of the timing processors corresponding to the first data transmission interface, the priority of the target timing processor is higher than the priority of the first timing processor. The first arbitrator can input the first data transmission instruction into the first instruction cache module first, and then input the second data transmission instruction into the first instruction cache module. In this way, since the first instruction cache module is a first-in-first-out memory, the first data transmission instruction can be executed first.

[0068] Optionally, the first arbitrator may also feed back the conflict information of the timing processor to the central processor, so that the central processor can grasp the conflict information in the working process of the timing processor in real time and take corresponding measures. For example, instruct the high-priority timing processor to re-execute the task corresponding to the conflicting data transmission instruction, or modify the execution time of other instructions related to the conflicting data transmission instruction.

[0069] Optionally, the RF controller may further include a data storage device, which is connected to the n timing processors and is used to store intermediate data generated when the n timing processors perform tasks and / or task data required by the n timing processors to perform tasks. The task data required by the n timing processors to perform tasks is, for example, generated by the aforementioned central processor according to the requirements of the upper-layer software. For example, the task data required by the target timing processor to perform tasks is data included in a data file generated by the central processor according to the requirements of the upper-layer software; the intermediate data generated by the n timing processors when performing tasks includes, for example, operands, condition lists, etc. In this way, the RF controller can act as a coprocessor to reduce the processing pressure of the central processor, which helps to improve the autonomous control capability of the RF controller.

[0070] Optionally, when the multiple timing processors read and write data from the data storage device, conflicts may occur, for example, two timing processors read or write data from the data storage device at the same time. Therefore, in an embodiment of the present application, the RF controller may further include a second arbitrator, which is connected to the n timing processors and the data storage module to determine whether the data read and write instructions output by the n timing processors conflict.

[0071] For example, the second arbitrator may determine whether the data read and write instructions output by the target timing processor conflict with the data read and write instructions output by other timing processors. If the target timing processor and the second timing processor output data read and write instructions at the same time, it is considered that the data read and write instructions output by the target timing processor conflict with the data read and write instructions output by the second timing processor; if there is no timing processor among the other timing processors that outputs data read and write instructions at the same time as the target timing processor, it is considered that the data read and write instructions output by the target timing processor and the other timing processors do not conflict.

[0072] If the second arbitrator determines that the data read and write instruction output by the target timing processor conflicts with the data read and write instruction output by the second timing processor, the second arbitrator may also determine the execution order of the first data read and write instruction and the second data read and write instruction according to the priority of the target processor and the second timing processor. For example, the priority of the target timing processor is higher than the priority of the second timing processor, and the second arbitrator determines to execute the first data read and write instruction first. Among them, the priority is, for example, configured when the baseband chip is designed, and the priority may be different from the aforementioned priority.

[0073] When the target sequential processor has executed all the instructions stored in its RAM, it can send indication information for indicating the end of the task to the central processor, so that the central processor can report to the upper layer software to complete the first task.

[0074] In the embodiment of the present application, compared with the traditional RF controller, a timing exchange network is added between the timing processor and the frame timer, which can realize flexible pairing of the frame timer and the timing processor without binding; and a first arbitrator is added between the interface control module and the timing processor to solve the problem of conflict in data transmission instructions output by multiple timing processors; and a new data storage device is added to store complex task data (i.e., data required for executing tasks and data generated by executing tasks), which improves the autonomous control capability of the RF controller and reduces the processing pressure of the central processing unit, and a second arbitrator is added between the data storage device and the timing processor to solve the problem of conflict in data read and write instructions of multiple timing processors.

[0075] Based on the same inventive concept, the embodiment of the present application provides a data transmission method, which can be Figure 1 , Figure 2 or Figure 4 The electronic device described is implemented. Please refer to Figure 5 , which is a flowchart of a data transmission method provided in an embodiment of the present application.

[0076] S501: When a first task is started, a target frame timer corresponding to the first task is determined from at least one frame timer, and a target timing processor corresponding to the first task is determined from at least one timing processor.

[0077] S502: When it is determined that the count value of the target frame timer is the same as the time parameter stored in the target timing processor, execute the first task.

[0078] Optionally, before executing the first task, the electronic device may also determine whether the data transmission instruction output by the target timing processor conflicts with the data transmission instruction output by other timing processors, where the other timing processors are timing processors other than the target timing processor in the at least one (for example, n) timing processors.

[0079] For example, the electronic device can determine whether the data transmission interfaces indicated by the data transmission instructions output by each of the n timing processors are the same. If the first data transmission instruction output by the target timing processor is the same as the data transmission interface indicated by the second data transmission instruction output by any of the other timing processors (for example, the first timing processor), it is determined that the data transmission instruction output by the target timing processor conflicts with the first timing processor.

[0080] When the electronic device determines that the first data transmission instruction output by the target timing processor conflicts with the second data transmission instruction output by the first timing processor, it can also determine the execution order of the first data transmission instruction and the second data transmission instruction according to the priority of the target timing processor and the first timing processor.

[0081] Optionally, the electronic device may also determine whether the data read and write instruction output by the target timing processor conflicts with the data read and write instruction output by other timing processors. If the first data read and write instruction output by the target timing processor conflicts with the second data read and write instruction output by the second timing processor in the other timing processors, the electronic device may determine the execution order of the first data read and write instruction and the second data read and write instruction according to the priority of the target timing processor and the second timing processor.

[0082] It should be noted that the technical features involved in the aforementioned embodiments of the electronic device can all be referred to the implementation process corresponding to the data transmission method in the embodiments of the present application, and will not be repeated here.

[0083] Based on the same inventive concept, the present application embodiment provides a communication device. Figure 6 As shown, the communication device includes at least one processor 601 and a memory 602 connected to the at least one processor. The specific connection medium between the processor 601 and the memory 602 is not limited in the embodiment of the present application. Figure 6 In the example, the processor 601 and the memory 602 are connected via a bus 600. Figure 6 The connection between other components is shown by bold lines, and is not intended to be limiting. The bus 600 can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 6 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0084] In the embodiment of the present application, the memory 602 stores instructions that can be executed by at least one processor 601. The at least one processor 601 can execute the steps included in the aforementioned data transmission method by executing the instructions stored in the memory 602.

[0085] Among them, the processor 601 is the control center of the communication device, and can use various interfaces and lines to connect various parts of the entire communication device, and monitor the communication device as a whole by running or executing instructions stored in the memory 602 and calling data stored in the memory 602, various functions of the communication device and processing data. Optionally, the processor 601 may include one or more processing units, and the processor 601 may integrate an application processor and a modem processor, wherein the application processor mainly processes operating systems and application programs, and the modem processor mainly processes wireless communications. It is understandable that the above-mentioned modem processor may not be integrated into the processor 601. In some embodiments, the processor 601 and the memory 602 may be implemented on the same chip, and in some embodiments, they may also be implemented separately on independent chips.

[0086] Processor 601 can be a general-purpose processor, such as a central processing unit (CPU), a digital signal processor, an application-specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, and can implement or execute the various methods, steps and logic block diagrams disclosed in the embodiments of the present application. A general-purpose processor can be a microprocessor or any conventional processor, etc. The steps of the data transmission method disclosed in the embodiments of the present application can be directly embodied as a hardware processor to be executed, or a combination of hardware and software modules in the processor can be executed.

[0087] The memory 602 is a non-volatile computer-readable storage medium that can be used to store non-volatile software programs, non-volatile computer executable programs and modules. The memory 602 may include at least one type of storage medium, such as a flash memory, a hard disk, a multimedia card, a card-type memory, a random access memory (Random Access Memory, RAM), a static random access memory (Static Random Access Memory, SRAM), a programmable read-only memory (Programmable Read Only Memory, PROM), a read-only memory (Read Only Memory, ROM), an electrically erasable programmable read-only memory (Electrically Erasable Programmable Read-Only Memory, EEPROM), a magnetic memory, a disk, an optical disk, etc. The memory 602 is any other medium that can be used to carry or store a desired program code in the form of an instruction or data structure and can be accessed by a computer, but is not limited thereto. The memory 602 in the embodiment of the present application can also be a circuit or any other device that can realize a storage function, for storing program instructions and / or data.

[0088] By designing and programming the processor 601, the code corresponding to the data transmission method introduced in the aforementioned embodiment can be solidified into the chip, so that the chip can execute the steps of the aforementioned data transmission method during operation. How to design and program the processor 601 is a technology well known to those skilled in the art and will not be repeated here.

[0089] Based on the same inventive concept, an embodiment of the present application also provides a computer-readable storage medium, which stores computer instructions. When the computer instructions are executed on a computer, the computer executes the steps of the aforementioned data transmission method.

[0090] In some possible implementations, various aspects of the data transmission method provided by the present application may also be implemented in the form of a program product, which includes a program code. When the program product is run on a communication device, the program code is used to enable the detection device to execute the steps of the data transmission method according to various exemplary embodiments of the present application described above in this specification.

[0091] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0092] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0093] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0094] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0095] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A radio frequency controller, characterized in that: Applied to an electronic device, the electronic device comprises a central processor and a radio frequency controller, the central processor is connected to the radio frequency controller, the radio frequency controller comprises a timing switching network, at least one frame timer and at least one timing processor, the at least one frame timer and the at least one timing processor are connected to the timing switching network; wherein, The central processor is used to determine, when the first task is started, a target frame timer corresponding to the first task from the at least one frame timer, and a target timing processor corresponding to the first task from the at least one timing processor; The target frame timer is used for frame counting; The timing switching network is used to associate the target frame timer with the target timing processor; The target timing processor is used to execute the first task when the count value of the target frame timer is the same as the time parameter stored in the target timing processor.

2. The radio frequency controller according to claim 1, characterized in that: The RF controller also includes a first arbitrator, which is connected to the at least one timing processor and is used to determine whether the data transmission instruction output by the target timing processor conflicts with the data transmission instruction output by other timing processors, and the other timing processors are timing processors other than the target timing processor in the at least one timing processor.

3. The radio frequency controller according to claim 2, characterized in that: The first arbitrator is specifically used for: Determine a data transmission interface indicated by a data transmission instruction output by each timing processor of the at least one timing processor; If the first data transfer instruction output by the target timing processor has the same data transfer interface as the second data transfer instruction output by the first timing processor of the other timing processors, it is determined that the data transfer instructions output by the target timing processor and the first timing processor conflict.

4. The radio frequency controller according to claim 3, characterized in that: The radio frequency controller further comprises an interface control module, the interface control module is connected to the first arbitrator, and the interface control module comprises at least one data transmission interface.

5. The radio frequency controller according to claim 4, characterized in that: The radio frequency controller further comprises at least one instruction cache module, and the at least one instruction cache module corresponds one-to-one with the at least one data transmission interface.

6. The radio frequency controller according to claim 5, characterized in that: The first arbitrator is further configured to: When a first data transmission instruction output by the target timing processor conflicts with a second data transmission instruction output by a first timing processor among the other timing processors, determining an execution order of the first data transmission instruction and the second data transmission instruction according to the priority of the target timing processor and the first timing processor; Based on the execution order, the first data transfer instruction and the second data transfer instruction are input into the first instruction cache module in the at least one instruction cache module, the first instruction cache module corresponds to a first data transfer interface, and the first data transfer interface is the data transfer interface indicated by the first data transfer instruction and the second data transfer instruction.

7. The radio frequency controller according to any one of claims 1 to 6, characterized in that: The RF controller also includes a data storage device, which is connected to the at least one timing processor and is used to store intermediate data generated when the at least one timing processor performs a task, and / or task data required for the at least one timing processor to perform a task.

8. The radio frequency controller according to claim 7, characterized in that: The RF controller also includes a second arbitrator, which is connected to the at least one timing processor and the data storage device, and is used to determine whether the data read and write instructions output by the target timing processor conflict with the data read and write instructions output by other timing processors, and the other timing processors are timing processors other than the target timing processor in the at least one timing processor.

9. The radio frequency controller according to claim 8, characterized in that: The second arbitrator is further configured to: When a first data read / write instruction output by the target timing processor conflicts with a second data read / write instruction output by a second timing processor among the other timing processors, the execution order of the first data read / write instruction and the second data read / write instruction is determined according to the priority of the target timing processor and the second timing processor.

10. An electronic device, characterized in that: It comprises a radio frequency controller and a central processing unit as described in any one of claims 1 to 9.

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