A semiconductor device, a manufacturing method thereof, and a storage system
By forming gate line structures on the stop layer in 3D integrated DRAM, the problem of etching process inhomogeneity is solved, and a more efficient etching effect is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- YANGTZE MEMORY TECH CO LTD
- Filing Date
- 2023-07-28
- Publication Date
- 2026-06-05
AI Technical Summary
In 3D integrated DRAM, how can we improve the etching process of transistor and capacitor structures to enhance etching uniformity?
Semiconductor pillars are formed within the semiconductor layer, and gate line structures are formed on the stop layer. The etching process is then used to stop the etching on the stop layer, thereby improving etching uniformity.
By stopping the etching process on the stop layer, the uniformity of the etching process is improved, the etching difficulty is reduced, and the etching process window is increased.
Smart Images
Figure CN119451086B_ABST
Abstract
Description
Technical Field
[0001] This application generally relates to the field of electronic devices, and more specifically, to a semiconductor device and its fabrication method and a storage system. Background Technology
[0002] Transistors in semiconductor structures are widely used in integrated circuits as switching devices or driving devices. For example, the storage cells of Dynamic Random Access Memory (DRAM) may include transistors and capacitor structures, with the transistors controlling the writing or reading of data from the capacitor structures.
[0003] However, in three-dimensional integrated DRAM, a transistor and a capacitor structure constitute a memory cell. In the fabrication process, how to improve the etching process is an urgent problem to be solved.
[0004] Application content
[0005] The purpose of this application is to provide a semiconductor device and a method for fabricating the same, which aims to improve the etching uniformity of the semiconductor pillar.
[0006] In a first aspect, this application provides a method for fabricating a semiconductor device, the method comprising:
[0007] Obtain a base including a stop layer;
[0008] A semiconductor layer is formed on the stop layer;
[0009] Semiconductor pillars are formed within the semiconductor layer. The semiconductor pillars are arranged in an array in a first direction and a second direction and extend along a third direction. The first direction, the second direction, and the third direction intersect each other.
[0010] A gate line structure is formed extending along the third direction, the gate line structure being located between two adjacent rows of semiconductor pillars in the first direction.
[0011] In some embodiments, the step of forming semiconductor pillars within the semiconductor layer includes:
[0012] A first trench is formed extending along the first direction, and a spacer is formed in the first trench, the first trench penetrating the semiconductor layer along the third direction and having the stop layer as its bottom;
[0013] A second trench is formed extending along the second direction, the second trench penetrating the semiconductor layer and the spacer along the third direction to divide the semiconductor layer into a plurality of semiconductor pillars.
[0014] In some embodiments, the semiconductor layer comprises amorphous silicon, and the step of forming the gate line structure extending along the third direction includes:
[0015] A bottom isolation structure is formed at the bottom of the second trench;
[0016] A channel layer, a first insulating layer, a gate layer, and a fill insulating layer are sequentially formed on the sidewall of the second trench, located on the bottom isolation structure.
[0017] In some embodiments, the step of forming the gate line structure extending along the third direction further includes:
[0018] A second insulating layer is formed between the sidewall of the semiconductor pillar and the channel layer.
[0019] In some embodiments, the semiconductor layer comprises polysilicon, and the step of forming the gate line structure extending along the third direction includes:
[0020] A bottom isolation structure is formed at the bottom of the second trench;
[0021] A first insulating layer, a gate layer, and a fill insulating layer are sequentially formed on the sidewall of the second trench, which is located on the bottom isolation structure.
[0022] In some embodiments, the method for fabricating the semiconductor device further includes:
[0023] The end of the semiconductor pillar away from the stop layer is ion-doped to form a source electrode;
[0024] A capacitor is formed on the side of the semiconductor pillar opposite to the stop layer.
[0025] In some embodiments, the method for fabricating the semiconductor device further includes:
[0026] Remove the substrate;
[0027] The end of the semiconductor pillar furthest from the capacitor is ion-doped to form a drain electrode;
[0028] A bit line is formed connecting the drain.
[0029] In some embodiments, the method for fabricating the semiconductor device further includes:
[0030] An isolation trench is formed extending along the second direction, the isolation trench penetrating the semiconductor layer and the spacer along the third direction, and located between two adjacent second trenches;
[0031] A sacrificial layer is formed in the isolation groove and the second trench;
[0032] Remove the sacrificial layer located in the isolation trench;
[0033] A shielding structure is formed in the isolation groove;
[0034] Remove the sacrificial layer located in the second trench.
[0035] In some embodiments, the step of forming the gate line structure extending along the third direction further includes:
[0036] The sidewalls of the second trench are etched to increase the width of the second trench in the first direction;
[0037] Wherein, the width of the second trench along the first direction is greater than the width of the isolation groove along the first direction.
[0038] In some embodiments, the step of obtaining a substrate including a stop layer includes:
[0039] Obtain the substrate;
[0040] An oxide layer is formed on the substrate as the stop layer.
[0041] Secondly, this application provides a semiconductor device, the semiconductor device comprising:
[0042] Semiconductor structures fabricated by the semiconductor device fabrication method in any of the above embodiments.
[0043] Thirdly, this application provides a semiconductor device, the semiconductor device comprising:
[0044] Semiconductor pillars are arranged in an array in a first direction and a second direction and extend along a third direction, wherein the first direction, the second direction and the third direction intersect each other;
[0045] A gate line structure extends along the third direction and is located between two adjacent rows of semiconductor pillars in the first direction;
[0046] The semiconductor pillars include polycrystalline silicon or amorphous silicon.
[0047] In some embodiments, the semiconductor pillar comprises amorphous silicon, and the semiconductor device further comprises:
[0048] A channel layer is located between the semiconductor pillar and the gate line structure;
[0049] A first insulating layer is located between the channel layer and the gate structure.
[0050] In some embodiments, the semiconductor device further includes:
[0051] A second insulating layer is located between the channel layer and the semiconductor pillar.
[0052] Fourthly, this application provides a storage system, comprising:
[0053] Semiconductor devices in any of the above embodiments;
[0054] A controller, electrically connected to the semiconductor device, is used to control the semiconductor device to store data.
[0055] This application provides a semiconductor device and its fabrication method, as well as a memory system. The semiconductor device fabrication method includes first obtaining a substrate including a stop layer, then forming a semiconductor layer on the stop layer, and then forming semiconductor pillars within the semiconductor layer. The semiconductor pillars are arranged in an array along a first direction and a second direction and extend along a third direction, wherein the first direction, the second direction, and the third direction intersect each other. Finally, a gate line structure extending along the third direction is formed, the gate line structure being located between two adjacent rows of semiconductor pillars in the first direction. Since the semiconductor layer is formed on the stop layer, when forming the semiconductor pillars within the semiconductor layer through an etching process, the etching process can stop on the stop layer, thereby improving the etching uniformity of the semiconductor layer. Attached Figure Description
[0056] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.
[0057] Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor device provided in some embodiments of this application;
[0058] Figures 2a-2q These are schematic diagrams illustrating the structure of semiconductor devices provided in some embodiments of this application during the fabrication process;
[0059] Figure 3 This is a schematic diagram of the structure of a storage system provided in some embodiments of this application. Detailed Implementation
[0060] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0061] It should be understood that although the terms first, second, etc., may be used herein to describe various components, these components should not be limited to these terms. These terms are used to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of this application.
[0062] It should be understood that when a component is said to be "on" or "connected" to another component, it can be directly on or connected to the other component, or there may be an inserted component. Other terms used to describe relationships between components should be interpreted in a similar manner.
[0063] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far from the substrate. A layer may extend over the entire lower or upper layer structure, or may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and contact layers (where contacts, interconnects, and one or more dielectric layers are formed).
[0064] This paper uses Cartesian coordinates to represent directions, where "X" represents the first direction, "Y" represents the second direction, and "Z" represents the third direction. The first, second, and third directions intersect each other, that is, X, Y, and Z intersect each other, for example, they can be perpendicular to each other or form a certain angle.
[0065] It should be noted that the illustrations provided in the embodiments of this application are only schematic representations of the basic concept of this application. Although the illustrations only show the components related to this application and are not drawn according to the actual number, shape and size of the components, the form, quantity and proportion of each component in actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.
[0066] Please see Figure 1 , Figure 1 This is a schematic flowchart illustrating the fabrication method of a semiconductor device provided in some embodiments of this application. Please also refer to... Figures 2a-2q , Figures 2a-2q These are schematic diagrams illustrating the fabrication process of semiconductor devices provided in some embodiments of this application. Figure 2d yes Figure 2cA schematic diagram of the cross-sectional structure along A-A1. Figure 2f yes Figure 2e A structural diagram along B-B1. Figure 2h yes Figure 2g A schematic diagram of the cross-sectional structure along C-C1. Figure 2j yes Figure 2i A schematic diagram of the cross-sectional structure along point D-D1. Figure 2l yes Figure 2k A schematic diagram of the cross-sectional structure along E-E1. Figure 2n and Figure 2o yes Figure 2m A schematic cross-sectional view along F-F1. The fabrication method of this semiconductor device includes the following steps S1-S4.
[0067] Step S1: Obtain a substrate 10 including a stop layer 101.
[0068] See Figure 2b Taking the self-prepared substrate 10 as an example, specifically, a substrate 102 can be obtained first, and then an oxide layer can be formed on the substrate 102 as a stop layer 101 to form the substrate 10. The substrate 102 can be a semiconductor substrate, such as silicon (Si), germanium (Ge), SiGe substrate, etc. In other embodiments, the semiconductor substrate can also be a substrate including other element semiconductors or compound semiconductors, and can also be a stacked structure, such as Si / SiGe, etc. The oxide layer can be formed on the substrate 102 by an oxidation process or a deposition process, and the oxide layer can be silicon oxide.
[0069] In some embodiments, the substrate 10 can be obtained directly, for example, by purchasing the substrate 10 including the stop layer 101 directly from the manufacturer.
[0070] Step S2: Form a semiconductor layer 20 on the stop layer 101.
[0071] like Figure 2b As shown, a semiconductor layer 20 can be formed on the stop layer 101 by a deposition process. The semiconductor layer 20 can be a semiconductor material, such as polycrystalline silicon or amorphous silicon. Figure 2a The diagram shows a top view of the semiconductor layer 20. The substrate 102, oxide layer, and semiconductor layer 20 can form a silicon-on-insulator (SOI) structure.
[0072] The deposition process of semiconductor layer 20 can be carried out by various methods, including but not limited to chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD) such as thermal oxidation, evaporation, sputtering, etc.
[0073] Step S3: A semiconductor pillar 21 is formed in the semiconductor layer 20. The semiconductor pillar 21 is arranged in an array in a first direction (X) and a second direction (Y) and extends along a third direction (Z). The first direction (X), the second direction (Y) and the third direction (Z) intersect each other.
[0074] In some embodiments, step S3 may include: 1) see Figure 2c and Figure 2d A first trench T1 is formed extending along the first direction (X), and a spacer 22 is formed in the first trench T1. The first trench T1 penetrates the semiconductor layer 20 along the third direction (Z) and has the stop layer 101 as its bottom; 2) See Figure 2e and Figure 2f A second trench T2 is formed extending along the second direction (Y), and the second trench T2 penetrates the semiconductor layer 20 and the spacer 22 along the third direction (Z) to divide the semiconductor layer 20 into a plurality of semiconductor pillars 21.
[0075] Specifically, such as Figure 2d As shown, the semiconductor layer 20 can be etched to form the first trench T1 and the semiconductor wall 20a. The etching process stops at the stop layer 101, so the bottom of the first trench T1 is located on the stop layer 101. Before etching, a protective layer 30 and a hard mask layer 40 can be formed on the semiconductor layer 20. The protective layer 30 is used to ensure that the top of the semiconductor layer 20 is not damaged during the etching process, and the hard mask layer 40 is patterned to form the first trench T1. The protective layer 30 may include silicon oxide, and the hard mask layer 40 may include silicon nitride.
[0076] Then, spacers 22 are filled into the first trench T1. Spacers 22 can be any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride, including but not limited to. The patterns of the semiconductor wall 20a and spacers 22 are as follows: Figure 2c As shown, the semiconductor wall 20a extends along the first direction (X) and is spaced apart along the second direction (Y), and spacers 22 are formed in other areas of the semiconductor layer 20 except for the semiconductor wall 20a.
[0077] like Figure 2e and Figure 2fAs shown, the semiconductor wall 20a and spacer 22 are then etched to form a second trench T2 extending along the second direction (Y), which divides the semiconductor wall 20a into a plurality of semiconductor pillars 21.
[0078] In some embodiments, the height H2 of the second trench T2 in the third direction (Z) may be less than the height H1 of the first trench T1 in the third direction (Z).
[0079] Step S4: Form a gate line structure 50 extending along the third direction (Z), the gate line structure 50 being located between two adjacent rows of semiconductor pillars 21 in the first direction (X).
[0080] In some embodiments, the material of the semiconductor layer 20 may include amorphous silicon, that is, the semiconductor pillar 21 may include amorphous silicon. Step S4 may include the following steps: 1) See Figure 2k and Figure 2l 1) Etch the sidewalls of the second trench T2 to increase the width of the second trench T2 in the first direction (X) to form the second trench T2'; 2) See Figure 2m and Figure 2n A bottom isolation structure 51 is formed at the bottom of the second trench T2'; 3) A channel layer 52, a first insulating layer 53, a gate layer 54, and a filling insulating layer 55 are sequentially formed on the sidewall of the second trench T2' on the bottom isolation structure 51. The material of the channel layer 52 may include semiconductor materials such as silicon (monocrystalline silicon or polycrystalline silicon), germanium, or silicon carbide.
[0081] Specifically, in Figure 2e Based on this, the second trench T2 is further etched to increase its width in the first direction (X) so as to form a gate line structure 50 in the second trench T2'. The second trench T2' with increased width is as follows: Figure 2k and Figure 2l As shown. Figure 2m and Figure 2n As shown, a bottom isolation structure 51 is first formed at the bottom of the second trench T2', and then a channel layer 52, a first insulating layer 53, a gate layer 54, and a fill insulating layer 55 are sequentially deposited on the sidewall of the second trench T2'. The channel layer 52 can serve as a channel, the first insulating layer 53 can serve as a gate insulating layer, and the channel layer 52 and the gate layer 54 can constitute a transistor. Since the height H2 of the second trench T2' in the third direction (Z) can be less than the height H1 of the first trench T1 in the third direction (Z), a semiconductor layer 20 remains between the bottom isolation structure 51 and the stop layer 101. The bottom isolation structure 51 can isolate the gate layer 54 and the semiconductor layer 20.
[0082] The bottom isolation structure 51 can be a single film layer, such as a silicon oxide layer or a silicon nitride layer. The bottom isolation structure 51 can also be a composite film layer, such as including a silicon oxide layer and a silicon nitride layer. The materials of the first insulating layer 53 and the filling insulating layer 55 can be one or more of silicon oxide, silicon nitride, and silicon oxynitride. The gate layer 54 can be one or more of conductive materials such as poly-Si (p-Si, polycrystalline silicon), TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), and Ag (silver).
[0083] In some embodiments, a second insulating layer (not shown) may be formed between the sidewall of the semiconductor pillar 21 and the channel layer 52. The second insulating layer can isolate the channel layer 52 and the semiconductor pillar 21 to improve device performance. The second insulating layer may be one or more of silicon oxide, silicon nitride, and silicon oxynitride.
[0084] In other embodiments, the material of semiconductor layer 20 may include polysilicon, in which case semiconductor pillars 21 can serve as channels without the need to form a separate channel layer 52. See also Figure 2o Step S4 may only include: 1) forming a bottom isolation structure 51 at the bottom of the second trench T2'; 2) sequentially forming a first insulating layer 53, a gate layer 54, and a filling insulating layer 55 on the sidewall of the second trench T2'. Therefore, the semiconductor pillar 21 and the gate layer 54 can constitute a transistor, and the semiconductor pillar 21 serves as the channel of the transistor. The bottom isolation structure 51 can isolate the bottom of the semiconductor pillar 21 from the bottom of the gate layer 54 to prevent channel leakage.
[0085] The gate layer 54 may include an anti-diffusion layer 541 (e.g., titanium nitride) and a metal layer 541 (e.g., tungsten), with the anti-diffusion layer 541 located between the first insulating layer 53 and the metal layer 541.
[0086] See Figure 2e-2j The method for fabricating the semiconductor device may further include the following steps: 1) forming an isolation trench T3 extending along the second direction (Y), the isolation trench T3 penetrating the semiconductor layer 20 and the spacer 22 along the third direction (Z) and located between two adjacent second trenches T2; 2) forming a sacrificial layer 60 in the isolation trench T3 and the second trenches T2; 3) removing the sacrificial layer 60 located in the isolation trench T3; 4) forming a shielding structure 70 in the isolation trench T3; 5) removing the sacrificial layer 60 located in the second trenches T2.
[0087] like Figure 2eAs shown, the isolation groove T3 and the second groove T2 can be formed under the same mask. The isolation groove T3 and the second groove T2 can be arranged alternately along the first direction (X), and the length of the second groove T2 along the second direction (Y) can be greater than the length of the isolation groove T3 along the second direction (Y).
[0088] like Figure 2g and Figure 2h As shown, in order to form the shielding structure 70 only in the isolation trench T3, the second trench T2 and the isolation trench T3 are filled with a sacrificial layer 60. The sacrificial layer 60 can be carbon or spin-on carbon (SOC). Figure 2i and Figure 2j As shown, the sacrificial layer 60 in the isolation trench T3 is then removed, and a shielding structure 70 is formed in the isolation trench T3. The shielding structure 70 may include an insulating layer and a metal layer (not shown) formed sequentially. The metal layer includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), or other metallic materials. Finally, the sacrificial layer 60 in the second trench T2 is removed, and the above step S4 is performed.
[0089] It should be noted that, as Figure 2m As shown, the shielding structure 70 divides a semiconductor pillar 21 located between two rows of second trenches T2' into two sub-semiconductor pillars 21a. Therefore, the gate layer 54 in a gate line structure 50 can control the two rows of sub-semiconductor pillars 21a located on both sides of it. The annular gate layer 54 can be divided into two rows of gates, and the two rows of gates respectively control the conduction of the two rows of sub-semiconductor pillars 21a on both sides of the gate layer 54.
[0090] In some embodiments, see Figure 2p The method for fabricating this semiconductor device may further include: 1) in Figure 2n Based on this, the end of the channel layer 52 away from the stop layer 101 is ion-doped to form a source, and then a capacitor 80 connected to the source is formed; 2) The substrate 10 is removed, and the end of the channel layer 52 away from the capacitor 80 is ion-doped to form a drain 52D, and a bit line 90 connected to the drain 52D is formed.
[0091] In some embodiments, see Figure 2q The method for fabricating this semiconductor device may further include: 1) in Figure 2o Based on this, the end of the semiconductor pillar 21 away from the stop layer 101 is ion-doped to form a source, and then a capacitor 80 is formed on the side of the semiconductor pillar 21 away from the stop layer 101; 2) Remove the substrate 10, and the end of the semiconductor pillar 21 away from the array of capacitors 80 is ion-doped to form a drain 52D, and a bit line 90 connecting the drain 52D is formed.
[0092] In this device, the semiconductor pillar 21 can be polysilicon used as the channel, and the capacitor 80 can be connected to the source of the semiconductor pillar 21. The fabrication method of this semiconductor device may further include an annealing process on the polysilicon of the semiconductor pillar 21 to reduce impurities in the polysilicon channel, thereby better controlling the switching current.
[0093] The semiconductor device fabrication method provided in this application first obtains a substrate 10 including a stop layer 101, and then forms a semiconductor layer 20 on the substrate 10. Therefore, during the formation of the semiconductor pillar, the etching process of the first trench T1 can stop on the stop layer 101, thereby improving the etching uniformity of the first trench T1, reducing the etching difficulty, and improving the etching process window. In addition, the semiconductor pillar can be directly used as a channel to form a transistor with the gate layer 54 to control the capacitor 80 to store data.
[0094] This application also provides a semiconductor device, which includes a semiconductor structure fabricated by the method described in any of the above embodiments. For example, the semiconductor structure may include a substrate 10, i.e., a stop layer 101.
[0095] This application also provides a semiconductor device, which can be referred to in the embodiments. Figure 2m , Figure 2p and Figure 2q The semiconductor device includes semiconductor pillars and a gate structure 50. The semiconductor pillars are arranged in an array along a first direction (X) and a second direction (Y) and extend along a third direction (Z), the first direction (X), the second direction (Y), and the third direction (Z) intersecting each other. The gate structure 50 extends along the third direction (Z) and is located between two adjacent rows of semiconductor pillars in the first direction (X). The semiconductor pillars comprise polycrystalline silicon or amorphous silicon.
[0096] In some embodiments, the semiconductor device can be fabricated using the semiconductor device fabrication method provided in the above embodiments. For example... Figure 2p As shown, the semiconductor pillar 21 includes amorphous silicon, and the semiconductor device further includes a channel layer 52 and a first insulating layer 53. The channel layer 52 is located between the semiconductor pillar 21 and the gate line structure 50, and the first insulating layer 53 is located between the channel layer 52 and the gate line structure 50.
[0097] In some embodiments, the semiconductor device may further include a second insulating layer (not shown) located between the channel layer 52 and the semiconductor pillar 21.
[0098] In other embodiments, the semiconductor device can be fabricated using the semiconductor device fabrication method provided in the above embodiments. For example... Figure 2q As shown, the semiconductor pillar 21 includes polysilicon, and the semiconductor device further includes a first insulating layer 53 located between the semiconductor pillar 21 and the gate structure 50.
[0099] In the semiconductor device provided in this application embodiment, amorphous silicon can be used as the semiconductor pillar, and a channel layer 52 connected to the gate structure can be additionally formed on the sidewall of the semiconductor pillar. The amorphous silicon semiconductor pillar can reduce costs. Alternatively, polycrystalline silicon can be directly used as the channel layer 52 to simplify the structure and reduce costs.
[0100] The semiconductor device can be a memory or a part of a memory. It can be used as computer memory in a memory system or as a cache in a memory system.
[0101] In some embodiments, this semiconductor device can be used in conjunction with a solid-state drive (SSD) to improve read and write speeds. Currently, high-end SSDs often incorporate dynamic random access memory (DRAM) to enhance performance and improve random read / write speeds. For example, during file writing, especially small file writing, small files are processed by DRAM before being stored in flash memory, resulting in higher SSD storage efficiency and faster speeds.
[0102] Please see Figure 3 , Figure 3 This is a schematic diagram of the structure of a storage system provided in some embodiments of this application. The storage system 100 includes a semiconductor device 101 and a controller 102. The semiconductor device 101 may include any of the semiconductor devices in the above embodiments, and the semiconductor device 101 may be a memory or part of a memory. The controller 102 is electrically connected to the semiconductor device 101 and is used to control the semiconductor device 101 to store data. The semiconductor device 101 can perform data storage operations based on the control of the controller 102.
[0103] The semiconductor device 101 includes semiconductor pillars and a gate line structure. The semiconductor pillars are arranged in an array along a first direction and a second direction and extend along a third direction, wherein the first direction, the second direction, and the third direction intersect each other. The gate line structure extends along the third direction and is located between two adjacent rows of semiconductor pillars in the first direction. The semiconductor pillars comprise polycrystalline silicon or amorphous silicon.
[0104] The above description of the embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application; those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
Claims
1. A method for fabricating a semiconductor device, characterized in that, The method for fabricating the semiconductor device includes: Obtain a base including a stop layer; A semiconductor layer is formed on the stop layer; Semiconductor pillars are formed within the semiconductor layer. The semiconductor pillars are arranged in an array in a first direction and a second direction and extend along a third direction. The first direction, the second direction, and the third direction intersect each other. A gate line structure is formed extending along the third direction, the gate line structure being located between two adjacent rows of semiconductor pillars in the first direction.
2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The step of forming semiconductor pillars within the semiconductor layer includes: A first trench is formed extending along the first direction, and a spacer is formed in the first trench, the first trench penetrating the semiconductor layer along the third direction and having the stop layer as its bottom; A second trench is formed extending along the second direction, the second trench penetrating the semiconductor layer and the spacer along the third direction to divide the semiconductor layer into a plurality of semiconductor pillars.
3. The method for fabricating a semiconductor device according to claim 2, characterized in that, The semiconductor layer comprises amorphous silicon, and the step of forming the gate line structure extending along the third direction includes: A bottom isolation structure is formed at the bottom of the second trench; A channel layer, a first insulating layer, a gate layer, and a fill insulating layer are sequentially formed on the sidewall of the second trench, located on the bottom isolation structure.
4. The method for fabricating a semiconductor device according to claim 3, characterized in that, The step of forming the gate line structure extending along the third direction further includes: A second insulating layer is formed between the sidewall of the semiconductor pillar and the channel layer.
5. The method for fabricating a semiconductor device according to claim 2, characterized in that, The semiconductor layer comprises polysilicon, and the step of forming the gate line structure extending along the third direction includes: A bottom isolation structure is formed at the bottom of the second trench; A first insulating layer, a gate layer, and a fill insulating layer are sequentially formed on the sidewall of the second trench, which is located on the bottom isolation structure.
6. The method for fabricating a semiconductor device according to claim 1, characterized in that, The method for fabricating the semiconductor device further includes: The end of the semiconductor pillar away from the stop layer is ion-doped to form a source electrode; A capacitor is formed on the side of the semiconductor pillar opposite to the stop layer.
7. The method for fabricating a semiconductor device according to claim 6, characterized in that, The method for fabricating the semiconductor device further includes: Remove the substrate; The end of the semiconductor pillar furthest from the capacitor is ion-doped to form a drain electrode; A bit line is formed connecting the drain.
8. The method for fabricating a semiconductor device according to claim 2, characterized in that, The method for fabricating the semiconductor device further includes: An isolation trench is formed extending along the second direction, the isolation trench penetrating the semiconductor layer and the spacer along the third direction, and located between two adjacent second trenches; A sacrificial layer is formed in the isolation groove and the second trench; Remove the sacrificial layer located in the isolation trench; A shielding structure is formed in the isolation groove; Remove the sacrificial layer located in the second trench.
9. The method for fabricating a semiconductor device according to claim 8, characterized in that, The step of forming the gate line structure extending along the third direction further includes: The sidewalls of the second trench are etched to increase the width of the second trench in the first direction; Wherein, the width of the second trench along the first direction is greater than the width of the isolation groove along the first direction.
10. The method for fabricating a semiconductor device according to claim 1, characterized in that, The step of obtaining a substrate including a stop layer includes: Obtain the substrate; An oxide layer is formed on the substrate as the stop layer.
11. A semiconductor device, characterized in that, The semiconductor device includes: The semiconductor structure fabricated by the method of fabricating a semiconductor device as described in any one of claims 1 to 10.
12. A semiconductor device, characterized in that, The semiconductor device includes: Semiconductor pillars are arranged in an array in a first direction and a second direction and extend along a third direction, wherein the first direction, the second direction and the third direction intersect each other; A gate line structure extends along the third direction and is located between two adjacent rows of semiconductor pillars in the first direction; The semiconductor pillars include polycrystalline silicon or amorphous silicon.
13. The semiconductor device according to claim 12, characterized in that, The semiconductor pillar comprises amorphous silicon, and the semiconductor device further comprises: A channel layer is located between the semiconductor pillar and the gate line structure; A first insulating layer is located between the channel layer and the gate structure.
14. The semiconductor device according to claim 13, characterized in that, The semiconductor device further includes: A second insulating layer is located between the channel layer and the semiconductor pillar.
15. A storage system, characterized in that, include: The semiconductor device according to claim 11; A controller, electrically connected to the semiconductor device, is used to control the semiconductor device to store data.