Memory cell structure, memory cell array structure, and method of manufacturing the same

Abstract

The embodiment of the present disclosure relates to the technical field of semiconductor, and provides a storage unit structure, a storage unit array structure and a manufacturing method thereof, the storage unit structure comprises: a gate electrode extending along a first direction, the gate electrode has opposite first and second surfaces, the second surface has spaced first and second recessed surfaces, and the first and second recessed surfaces are recessed towards the first surface; a gate dielectric layer at least conformally covers the second surface; a semiconductor layer conformally covers a side of the gate dielectric layer away from the gate electrode, the semiconductor layer has a contact surface opposite to the second surface, the contact surface has a third recessed surface corresponding to the first recessed surface and a fourth recessed surface corresponding to the second recessed surface; a capacitor structure comprising a lower electrode layer, an upper electrode layer and a capacitor dielectric layer between the upper electrode layer and the lower electrode layer, the lower electrode layer is in contact with the third recessed surface; and a bit line structure is in contact with the fourth recessed surface. At least the electrical performance of the storage unit structure can be improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the field of semiconductor, and particularly, to a memory cell structure, a memory cell array structure and a manufacturing method thereof. BACKGROUND

[0002] With the continuous development of semiconductor structure, its critical dimension is continuously reduced, but due to the limitation of the photoetching machine, there is a limit to the reduction of the critical dimension, so how to make a chip with higher storage density on a wafer is the research direction of many researchers and semiconductor practitioners. In two-dimensional or planar semiconductor devices, the memory cells are arranged in the horizontal direction, so the integration density of the two-dimensional or planar semiconductor device can be determined by the area occupied by the unit memory cell, and the continuous increase of the integration density of the two-dimensional or planar semiconductor device is greatly affected by the technology of forming fine patterns, so there is a limit to the continuous increase of the integration density of the two-dimensional or planar semiconductor device. Thus, the development of semiconductor devices goes to three-dimensional semiconductor devices.

[0003] However, the arrangement mode of each functional device in the current three-dimensional semiconductor device needs a new design, for example, while ensuring that each functional device is not affected, fully utilizing the existing layout space to improve the integration density of the three-dimensional semiconductor device SUMMARY

[0004] Embodiments of the present disclosure provide a memory cell structure, a memory cell array structure and a manufacturing method thereof, which at least facilitate to improve the electrical performance of the memory cell structure.

[0005] According to some embodiments of the present disclosure, in one aspect, a memory cell structure is provided, comprising: a gate electrode extending along a first direction, the gate electrode having a first surface and a second surface opposite along a second direction, the second surface having a first recessed surface and a second recessed surface spaced apart along the first direction, the first recessed surface and the second recessed surface are recessed towards the first surface, the first direction and the second direction intersect; a gate dielectric layer conformally covering at least the second surface; a semiconductor layer conformally covering a side of the gate dielectric layer away from the gate electrode, the semiconductor layer having a contact surface opposite to the second surface, the contact surface having a third recessed surface corresponding to the first recessed surface, and a fourth recessed surface corresponding to the second recessed surface; a capacitor structure comprising a lower electrode layer, an upper electrode layer and a capacitor dielectric layer between the upper electrode layer and the lower electrode layer, the lower electrode layer being in contact with the third recessed surface; a bit line structure being in contact with the fourth recessed surface.

[0006] In some embodiments, the lower electrode layer is in a ring structure, and the outer wall of the lower electrode layer and the entire third recessed surface are in contact; the first direction and the second direction form a reference surface, and the normal projection shape of the ring structure on the reference surface is a square ring, a circular ring, an elliptical ring, or an N-sided ring, where N is a positive integer greater than or equal to 5.

[0007] In some embodiments, the sidewall of the bit line structure extending along the third direction and the entire fourth recessed surface are in contact, and the first direction, the second direction, and the third direction intersect each other.

[0008] In some embodiments, the plurality of capacitor structures are in parallel with each other, the lower electrode layer of one of the plurality of capacitor structures is in contact with the third recessed surface, and the lower electrode layers of the remaining capacitor structures are sequentially in contact.

[0009] In some embodiments, among the plurality of capacitor structures other than the capacitor structure in contact with the third recessed surface, the lower electrode layers of at least some of the capacitor structures are arranged along the first direction, and / or the lower electrode layers of at least some of the capacitor structures are arranged along the second direction.

[0010] In some embodiments, the gate further has a third surface and a fourth surface opposite along a third direction, the first direction, the second direction, and the third direction intersect each other; the gate dielectric layer further conformally covers the third surface and / or the fourth surface; and the semiconductor layer further conformally covers a side of the gate dielectric layer away from the third surface and a side of the gate dielectric layer away from the fourth surface.

[0011] According to some embodiments of the present disclosure, another aspect of the present disclosure further provides a storage unit array structure, comprising: a plurality of storage unit structures as described in any one of the above embodiments; and the plurality of storage unit structures are sequentially and spacedly arranged along the first direction and / or the third direction, and the first direction, the second direction, and the third direction intersect each other.

[0012] In some embodiments, the plurality of storage unit structures are sequentially and spacedly arranged along the first direction, the gates in the adjacent storage unit structures along the first direction are electrically connected through a first electrical connection layer, and the semiconductor layers in the adjacent storage unit structures along the first direction have a dielectric layer therebetween.

[0013] In some embodiments, the plurality of memory cell structures are sequentially and spacedly arranged along the third direction; the lower electrode layers of the plurality of memory cell structures spacedly arranged along the third direction are surrounded by the same capacitor dielectric layer; the inner side of the capacitor dielectric layer forms a first via hole, and the upper electrode layer fills the first via hole.

[0014] In some embodiments, the plurality of memory cell structures are also spacedly arranged along the second direction, two adjacent memory cell structures along the second direction are axisymmetric along the first direction, and two gate electrodes of the adjacent memory cell structures along the second direction are respectively in contact with two first electrical connection layers, and the two first electrical connection layers are electrically connected by a second electrical connection layer.

[0015] According to some embodiments of the present disclosure, in yet another aspect, the present disclosure further provides a manufacturing method of a memory cell array structure, comprising: providing a substrate; forming a plurality of memory cell structures arranged along a first direction and / or a third direction on the substrate; the memory cell structure comprises: a gate electrode extending along the first direction, the gate electrode having a first surface and a second surface opposite to each other along a second direction, the second surface having a first recessed surface and a second recessed surface spacedly arranged along the first direction, and the first recessed surface and the second recessed surface are recessed towards the first surface; a gate dielectric layer conformally covering at least the second surface; a semiconductor layer conformally covering a side of the gate dielectric layer away from the gate electrode, the semiconductor layer having a contact surface opposite to the second surface, the contact surface having a third recessed surface corresponding to the first recessed surface and a fourth recessed surface corresponding to the second recessed surface; a capacitor structure comprising a lower electrode layer, an upper electrode layer, and a capacitor dielectric layer between the upper electrode layer and the lower electrode layer, the lower electrode layer being in contact with the third recessed surface; a bit line structure being in contact with the fourth recessed surface; and the first direction, the second direction and the third direction intersecting with each other.

[0016] In some embodiments, the step of forming the capacitor structure and the bit line structure in the plurality of memory cell structures comprises: forming a stack structure on the substrate, the stack structure comprising first isolation layers and second isolation layers alternately stacked along the third direction; patterning the stack structure to form at least one first opening and at least one second opening, the first opening and the second opening being alternately arranged along the first direction; conformally covering a layer of initial lower electrode layer and a layer of capacitor dielectric layer on the inner wall of the first opening in sequence; forming the upper electrode layer to fill the remaining first opening; forming the bit line structure to fill the second opening; removing the first isolation layer to form a third opening, the third opening exposing a portion of the initial lower electrode layer along the third direction; removing the exposed initial lower electrode layer to form a plurality of lower electrode layers arranged at intervals along the third direction.

[0017] In some embodiments, the step of forming the semiconductor layer in the plurality of memory cell structures comprises: forming a third isolation layer to fill the third opening; laterally etching a portion of the second isolation layer along the second direction to form a fourth opening, the fourth opening exposing the outer wall of the lower electrode layer away from the capacitor dielectric layer and exposing a portion of the sidewall of the bit line structure, the fourth opening having a first inner wall exposing the lower electrode layer and the bit line structure, and a second inner wall and a third inner wall oppositely arranged along the third direction; forming an initial semiconductor layer extending along the first direction, the initial semiconductor layer covering at least the first inner wall; forming an initial gate dielectric layer on a side of the initial semiconductor layer away from the lower electrode layer, the initial gate dielectric layer extending along the first direction; forming an initial gate on a side of the initial gate dielectric layer away from the initial semiconductor layer, the initial gate extending along the first direction; patterning the initial semiconductor layer to form a plurality of semiconductor layers arranged at intervals along the first direction, one semiconductor layer being in contact with one lower electrode layer and one bit line structure, respectively.

[0018] In some embodiments, the initial semiconductor layer further covers the second inner wall and / or the third inner wall, the initial gate dielectric layer is further between the initial semiconductor layer covering the second inner wall and the initial gate, and / or the initial gate dielectric layer is further between the initial semiconductor layer covering the third inner wall and the initial gate.

[0019] In some embodiments, the semiconductor layers adjacent along the first direction have a spacing therebetween, the initial gate comprises the gate directly opposite the semiconductor layer and a first electrical connection layer directly opposite the spacing.

[0020] The technical solutions provided by the embodiments of the present disclosure have at least the following advantages.

[0021] The first recessed surface and the second recessed surface are designed to be arranged at intervals along the first direction, and the gate dielectric layer and the semiconductor layer both have two recessed surfaces corresponding to the first recessed surface and the second recessed surface respectively. Based on the structure, the capacitor structure and the bit line structure can be respectively embedded in the two recesses in the semiconductor layer, to realize a 1T1C type of storage unit structure, that is, one transistor source or drain and one capacitor are electrically connected to form a storage unit structure. It can be understood that the capacitor structure and the bit line structure can both be considered as being partially embedded in the semiconductor layer, that is, the lower electrode layer is in contact with the third recessed surface, and the bit line structure is in contact with the fourth recessed surface. In this way, it is beneficial to increase the contact area between the lower electrode layer and the semiconductor layer to reduce the contact resistance therebetween, and to increase the contact area between the bit line structure and the semiconductor layer to reduce the contact resistance therebetween, thereby being beneficial to improving the transmission efficiency and transmission accuracy of the electrical signal between the lower electrode layer and the semiconductor layer, and improving the transmission efficiency and transmission accuracy of the electrical signal between the bit line structure and the semiconductor layer. Thus, it is beneficial to improve the electrical performance of the storage unit structure. BRIEF DESCRIPTION OF DRAWINGS

[0022] One or more embodiments are illustrated by way of example in the drawings that are not intended to be limiting of the embodiments so as to illustrate exemplary principles of the embodiments. The same reference numbers in different drawings identify the same elements. The drawings are not necessarily to scale, except that of a conventional drawing, and elements of drawings can have been exaggerated in size, especially thickness, for purposes of explanation. None of the drawings are necessarily inclusive of all implementations of the embodiments. Some embodiments will now be described more fully in the following examples and implementations, without limitation, since the basic principles of the embodiments have been demonstrated above. Other embodiments can be devised without departing from the basic principles of exemplary embodiments.

[0023] Figure 1 A perspective structural schematic diagram of a storage unit structure provided by an embodiment of the present disclosure;

[0024] Figure 2 A cross-sectional structural schematic diagram of a storage unit structure provided by an embodiment of the present disclosure;

[0025] Figure 3 A perspective structural schematic diagram of a gate electrode provided by an embodiment of the present disclosure;

[0026] Figure 4 A perspective structural schematic diagram of a gate electrode, a gate dielectric layer and a semiconductor layer provided by an embodiment of the present disclosure;

[0027] Figure 5Another perspective view of the structure of the storage unit provided by an embodiment of the present disclosure is shown in FIG. 2B.

[0028] Figure 6 A top view of the structure of the storage unit provided by an embodiment of the present disclosure is shown in FIG. 3A.

[0029] Figure 7 Another top view of the structure of the storage unit provided by an embodiment of the present disclosure is shown in FIG. 3B.

[0030] Figure 8 Yet another top view of the structure of the storage unit provided by an embodiment of the present disclosure is shown in FIG. 3C.

[0031] Figure 9 Still another top view of the structure of the storage unit provided by an embodiment of the present disclosure is shown in FIG. 3D.

[0032] Figure 10 A perspective view of the structure of the storage unit array provided by another embodiment of the present disclosure is shown in FIG. 4A.

[0033] Figure 11 A perspective view of the structure of the capacitor and the bit line in the storage unit array provided by another embodiment of the present disclosure is shown in FIG. 4B.

[0034] Figure 12 A front view of the structure of the storage unit array provided by another embodiment of the present disclosure is shown in FIG. 5A.

[0035] Figure 13 Another front view of the structure of the storage unit array provided by another embodiment of the present disclosure is shown in FIG. 5B.

[0036] Figure 14 A top view of the structure of the storage unit array provided by another embodiment of the present disclosure is shown in FIG. 6A.

[0037] Figure 15 Another top view of the structure of the storage unit array provided by another embodiment of the present disclosure is shown in FIG. 6B.

[0038] Figures 16 to 23 The structure of each step of the manufacturing method of the storage unit array provided by yet another embodiment of the present disclosure is shown in FIG. 7. DETAILED DESCRIPTION

[0039] As known from the background, the electrical performance of the storage unit structure needs to be improved.

[0040] The embodiment of the present disclosure provides a storage unit structure, a storage unit array structure and a manufacturing method thereof. In the storage unit structure, a first recessed surface and a second recessed surface are arranged along a first direction, and the gate dielectric layer and the semiconductor layer are both provided with two recessed surfaces corresponding to the first recessed surface and the second recessed surface respectively. Based on the structure, the capacitor structure and the bit line structure can be partially embedded in the semiconductor layer, that is, the lower electrode layer is connected with the third recessed surface, and the bit line structure is connected with the fourth recessed surface. In this way, the contact area between the lower electrode layer and the semiconductor layer is increased to reduce the contact resistance therebetween, and the contact area between the bit line structure and the semiconductor layer is increased to reduce the contact resistance therebetween, so that the transmission efficiency and transmission accuracy of the electrical signal between the lower electrode layer and the semiconductor layer are improved, and the transmission efficiency and transmission accuracy of the electrical signal between the bit line structure and the semiconductor layer are improved. Therefore, the electrical performance of the storage unit structure is improved.

[0041] The embodiments of the present disclosure will be described in detail below with reference to the drawings. However, those skilled in the art can understand that, in the embodiments of the present disclosure, many technical details are proposed in order to enable the readers to better understand the embodiments of the present disclosure. However, the technical solutions claimed by the embodiments of the present disclosure can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0042] The embodiment of the present disclosure provides a storage unit structure, and the storage unit structure provided by the embodiment of the present disclosure will be described in detail below with reference to the drawings. Figure 1 A perspective structural schematic diagram of the storage unit structure provided by the embodiment of the present disclosure;

[0043] Figure 2 A cross-sectional structural schematic diagram of the storage unit structure provided by the embodiment of the present disclosure; Figure 3 A perspective structural schematic diagram of the gate in the storage unit structure provided by the embodiment of the present disclosure; Figure 4 A perspective structural schematic diagram of the gate, the gate dielectric layer and the semiconductor layer provided by the embodiment of the present disclosure; Figure 5 Another perspective structural schematic diagram of the storage unit structure provided by the embodiment of the present disclosure; Figures 6 to 9 Four top view structural schematic diagrams of the storage unit structure provided by the embodiment of the present disclosure. It should be noted that, Figures 1 to 9 All are partial structural schematic diagrams of the storage unit structure.

[0044] Reference Figures 1 to 4 and Figure 6The storage unit structure comprises: a gate 100 extending along a first direction X, the gate 100 having a first surface 101 and a second surface 102 opposite along a second direction Y, the second surface 102 having a first recessed surface 103 and a second recessed surface 104 arranged at intervals along the first direction X, the first recessed surface 103 and the second recessed surface 104 are recessed towards the first surface 101, and the first direction X and the second direction Y intersect; a gate dielectric layer 110 at least conformally covering the second surface 102; a semiconductor layer 120 conformally covering a side of the gate dielectric layer 110 away from the gate 100, the semiconductor layer 120 having a contact surface 121 opposite the second surface 102, the contact surface 121 having a third recessed surface 122 corresponding to the first recessed surface 103 and a fourth recessed surface 123 corresponding to the second recessed surface 104; a capacitor structure 130 comprising a lower electrode layer 131, an upper electrode layer 132 and a capacitor dielectric layer 133 between the upper electrode layer 132 and the lower electrode layer 131, the lower electrode layer 131 being in contact with the third recessed surface 122; and a bit line structure 140 in contact with the fourth recessed surface 123.

[0045] It can be understood that the gate 100 is designed to have the first recessed surface 103 and the second recessed surface 104 arranged at intervals along the first direction X, and the gate dielectric layer 110 and the semiconductor layer 120 are both designed to have two recessed surfaces corresponding to the first recessed surface 103 and the second recessed surface 104 respectively, wherein the semiconductor layer 120 has the third recessed surface 122 corresponding to the first recessed surface 103 and the fourth recessed surface 123 corresponding to the second recessed surface 104, based on this structure, the capacitor structure 130 and the bit line structure 140 can be embedded in the two recesses in the semiconductor layer 120 respectively, to realize a 1T1C type storage unit structure, i.e. one transistor source or drain and one capacitor electrically connected to form one storage unit structure. It can be understood that the capacitor structure 130 and the bit line structure 140 can be regarded as partially embedded in the semiconductor layer 120, i.e. the lower electrode layer 131 is in contact with the third recessed surface 122, and the bit line structure 140 is in contact with the fourth recessed surface 123, thus, it is beneficial to increase the contact area between the lower electrode layer 131 and the semiconductor layer 120 to reduce the contact resistance therebetween, and to increase the contact area between the bit line structure 140 and the semiconductor layer 120 to reduce the contact resistance therebetween, thereby benefiting the transmission efficiency and accuracy of the electrical signal between the lower electrode layer 131 and the semiconductor layer 120, and benefiting the transmission efficiency and accuracy of the electrical signal between the bit line structure 140 and the semiconductor layer 120. Thus, it is beneficial to improve the electrical performance of the storage unit structure.

[0046] The storage unit structure provided by an embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0047] In some embodiments, the material of the gate 100 can be a metal material, such as titanium, tungsten, or copper, etc., and can also be a compound material such as titanium nitride, etc.

[0048] In some embodiments, in combination with reference to Figure 3 and Figure 4 , the gate 100 also has a third surface 105 and a fourth surface 106 opposite along a third direction Z, and the first direction X, the second direction Y, and the third direction Z are all orthogonal to each other; the gate dielectric layer 110 also conformally covers the third surface 105 and / or the fourth surface 106; and the semiconductor layer 120 also conformally covers the side of the gate dielectric layer 110 away from the third surface 105 and / or the side of the gate dielectric layer 110 away from the fourth surface 106. It can be understood that no matter the layout area of the semiconductor layer 120, the gate dielectric layer 110 is spaced between the semiconductor layer 120 and the gate 100.

[0049] In other words, the surface of the semiconductor layer 120 opposite to the gate 100 can also include part of the third surface 105 and / or the fourth surface 106, for example, the gate dielectric layer 110 also conformally covers the third surface 105 and the fourth surface 106, and the semiconductor layer 120 also conformally covers the side of the gate dielectric layer 110 away from the third surface 105 and the side of the gate dielectric layer 110 away from the fourth surface 106, that is, the surface of the gate 100 opposite to the semiconductor layer 120 includes part of the third surface 105, part of the fourth surface 106, and part of the second surface 102, compared with the semiconductor layer 120 only opposite to part of the second surface 102, it is beneficial to further increase the opposite area between the gate 100 and the semiconductor layer 120, and increase the control ability of the gate 100 to the semiconductor layer 120.

[0050] In some embodiments, the material of the gate dielectric layer 110 can be hafnium oxide or zirconium oxide, etc., which has a relatively high relative dielectric constant. It should be noted that the relative dielectric constant here is a physical parameter representing the dielectric or polarization properties of the dielectric material. Its value is equal to the ratio of the capacitance of a capacitor made of a predetermined material as the dielectric to the capacitance of a capacitor of the same size made of vacuum as the dielectric.

[0051] In some embodiments, the material of the semiconductor layer 120 can be a metal semiconductor compound layer such as indium gallium zinc oxide or zinc tin oxide, etc.

[0052] In combination with reference to Figure 1 , Figure 4 and Figure 6 , in some embodiments, the lower electrode layer 131 can have a ring structure, and the outer wall of the lower electrode layer 131 and the entire third recessed surface 122 are in contact and connected. That is, the outer wall of the lower electrode layer 131 and the entire third recessed surface 122 are mutually fitted, that is, the outer wall of the lower electrode layer 131 and the entire third recessed surface 122 are mutually adhered.

[0053] It can be understood that if the surface of the third recessed surface 122 is flat, the outer wall surface of the corresponding lower electrode layer 131 is also flat, if the surface of the third recessed surface 122 is curved, the outer wall surface of the corresponding lower electrode layer 131 is also curved, for example, the third recessed surface 122 is a curved surface recessed towards the gate 100, then the outer wall surface of the lower electrode layer 131 and the corresponding position has a protrusion embedded therein to fit the third recessed surface 122. In this way, it is beneficial to increase the contact area between the lower electrode layer 131 and the semiconductor layer 120 to reduce the contact resistance therebetween, and it is beneficial to improve the transmission efficiency and transmission accuracy of the electrical signal between the lower electrode layer 131 and the semiconductor layer 120, to improve the electrical performance of the storage unit structure.

[0054] In some embodiments, only part of the outer wall of the lower electrode layer 131 can be in contact with the third recessed surface 122. It can be understood that the greater the contact area between the outer wall of the lower electrode layer 131 and the third recessed surface 122, the smaller the contact resistance between the lower electrode layer 131 and the semiconductor layer 120.

[0055] In some embodiments, the first direction X and the second direction Y constitute a reference surface, and the orthographic projection shape of the ring structure on the reference surface is a square ring, a circular ring, an elliptical shape, or an N-sided ring, N being a positive integer greater than or equal to 5. In other words, the orthographic projection shape of the lower electrode layer 131 on the reference surface is a square ring, a circular ring, an elliptical shape, or an N-sided ring, thereby facilitating the parallel arrangement of multiple capacitor structures 130, thereby increasing the capacitance of the storage unit structure.

[0056] In some embodiments, the orthographic projection shape of the capacitor structure 130 on the reference surface can be a circle, a triangle, a square, or an N-sided shape (N can be greater than or equal to 5). For example, if the orthographic projection shape of the capacitor structure 130 on the reference surface is a circle, then the orthographic projection shape of the lower electrode layer 131 on the reference surface is a circular ring, the upper electrode layer 132 is located within the circle formed by the lower electrode layer 131 and is spaced apart from the lower electrode layer 131, and the capacitor dielectric layer 133 is located between the lower electrode layer 131 and the upper electrode layer 132.

[0057] Reference Figure 5 In some embodiments, the space enclosed by the upper electrode layer 132 can also include a filling layer 134, which can fill the space enclosed by the upper electrode layer 132. The material of the filling layer 134 can be a semiconductor material such as polysilicon. In some embodiments, the filling layer 134 can be part of the upper electrode layer 132.

[0058] Reference Figures 7 to 9In some embodiments, the storage unit structure can include a plurality of capacitor structures 130 connected in parallel with each other, the lower electrode layer 131 of one of the plurality of capacitor structures 130 is in contact with the third recessed surface 122, and the lower electrode layers 131 of the remaining capacitor structures 130 are sequentially in contact.

[0059] It should be noted that, Figure 7 In some embodiments, the plurality of capacitor structures 130 can be divided into a first capacitor structure, a second capacitor structure, and a third capacitor structure, wherein the lower electrode layer 131 of the first capacitor structure is in contact with the third recessed surface 122 (see FIG. 6), the lower electrode layer 131 of the second capacitor structure is in contact with the lower electrode layer 131 of the first capacitor structure, and the lower electrode layer 131 of the third capacitor structure is in contact with the lower electrode layer 131 of the second capacitor structure. By arranging a plurality of capacitor structures 130 connected in parallel with each other, the capacitance of the storage unit structure can be increased, thereby improving the electrical performance of the storage unit structure. Figure 4

[0060] In some embodiments, the lower electrode layers 131 of at least some of the plurality of capacitor structures 130 other than the capacitor structure 130 in contact with the third recessed surface 122 are arranged along the first direction X, and / or the lower electrode layers 131 of at least some of the plurality of capacitor structures 130 other than the capacitor structure 130 in contact with the third recessed surface 122 are arranged along the second direction Y.

[0061] It should be understood that the lower electrode layers 131 of at least some of the plurality of capacitor structures 130 other than the capacitor structure 130 in contact with the third recessed surface 122 can be arranged along the first direction X, and / or the lower electrode layers 131 of at least some of the plurality of capacitor structures 130 other than the capacitor structure 130 in contact with the third recessed surface 122 can be arranged along the second direction Y. In some embodiments, the lower electrode layers 131 of all of the plurality of capacitor structures 130 other than the capacitor structure 130 in contact with the third recessed surface 122 are arranged along the first direction X, or the lower electrode layers 131 of all of the plurality of capacitor structures 130 other than the capacitor structure 130 in contact with the third recessed surface 122 are arranged along the second direction Y, or the lower electrode layers 131 of some of the plurality of capacitor structures 130 other than the capacitor structure 130 in contact with the third recessed surface 122 are arranged along the first direction X, and the lower electrode layers 131 of some of the plurality of capacitor structures 130 other than the capacitor structure 130 in contact with the third recessed surface 122 are arranged along the second direction Y.

[0062] The arrangement of the plurality of capacitor structures 130 will be described below.

[0063] In some embodiments, the plurality of capacitor structures 130 are sequentially arranged along the second direction Y, as shown in FIG. 6. Figure 7 In practical applications, the plurality of capacitor structures can also be sequentially arranged along the first direction, and the plurality of capacitor structures as a whole are spaced apart from the bit line structure.

[0064] In some other embodiments, the plurality of capacitor structures 130 are sequentially arranged along the first direction X, as shown in FIG. 7. Figure 8 ​The plurality of mutually parallel capacitor structures 130 include a first portion extending along the second direction Y and a second portion extending along the first direction X, the first portion has opposite first and second ends in the second direction Y, the capacitor structure 130 as the first end is in contact with the third recessed surface 122 (refer to Figure 4 ), and the capacitor structure 130 as the second end is in contact with a capacitor structure 130 in the second portion; wherein the plurality of capacitor structures 130 included in the first portion are arranged in sequence along the second direction Y, and the plurality of capacitor structures 130 included in the second portion are arranged in sequence along the first direction X.

[0065] In still other embodiments, referring to Figure 9 , on the basis that the plurality of mutually parallel capacitor structures 130 include a first portion extending along the second direction Y and a second portion extending along the first direction X, the second portion has opposite third and fourth ends in the first direction X; the plurality of mutually parallel capacitor structures 130 can further include a third portion extending along the second direction Y, the plurality of capacitor structures 130 included in the third portion are arranged in sequence along the second direction Y; wherein the capacitor structure 130 as the third end is in contact with the capacitor structure 130 as the second end, and the capacitor structure 130 as the fourth end is in contact with a capacitor structure 130 in the third portion.

[0066] It can be understood that in the above examples, the storage unit structure includes seven capacitor structures 130, which are respectively a first capacitor structure, a second capacitor structure, a third capacitor structure, …, and a seventh capacitor structure, wherein the lower electrode layer 131 of the first capacitor structure is in contact with the third recessed surface 122, and the lower electrode layer 131 of the second capacitor structure is in contact with the lower electrode layer 131 of the first capacitor structure. On this basis, the plurality of capacitor structures 130 other than the capacitor structure 130 in contact with the third recessed surface 122 are arranged along the first direction X, which means that the second capacitor structure to the seventh capacitor structure are arranged in sequence along the first direction X, and the lower electrode layers 131 are in contact in sequence. The plurality of capacitor structures 130 other than the capacitor structure 130 in contact with the third recessed surface 122 are arranged along the second direction Y, which means that the second capacitor structure to the seventh capacitor structure are arranged in sequence along the second direction Y, and the lower electrode layers 131 are in contact in sequence. The plurality of capacitor structures 130 other than the capacitor structure 130 in contact with the third recessed surface 122 are partially arranged along the first direction X and partially arranged along the second direction Y, which means that the second capacitor structure to the fourth capacitor structure are arranged in sequence along the first direction X, and the lower electrode layers 131 are in contact in sequence, the fourth capacitor structure to the sixth capacitor structure are arranged in sequence along the second direction Y, and the lower electrode layers 131 are in contact in sequence, and the seventh capacitor structure is located on the side of the sixth capacitor structure close to the semiconductor layer 120 or on the side of the sixth capacitor structure away from the semiconductor layer 120.

[0067] It should be noted that the number and arrangement of the capacitor structure 130 are merely examples for facilitating the description, and the number and arrangement of the capacitor structure 130 can also be other arrangements or other arrangement directions, which are also within the protection scope of the embodiments of the present disclosure, and will not be illustrated one by one below.

[0068] In some embodiments, the material of the lower electrode layer 131 and / or the upper electrode layer 132 can be titanium nitride or cobalt nitride, etc.

[0069] In some embodiments, referring to Figures 1 to 9 The sidewall of the bit line structure 140 extending along the third direction Z and the entire fourth recessed surface 123 are in contact connection, and the first direction X, the second direction Y, and the third direction Z are mutually intersected. In this way, by arranging the bit line structure 140 extending along the third direction Z and the entire fourth recessed surface 123 in contact connection, the contact area between the bit line structure 140 and the fourth recessed surface 123 is increased, thereby reducing the contact resistance between the bit line structure 140 and the semiconductor layer 120, and improving the electrical performance of the storage unit structure.

[0070] In some embodiments, the surface of the bit line structure 140 facing the fourth recessed surface 123 is mutually fitted with the fourth recessed surface 123, that is, if the surface of the fourth recessed surface 123 is flat, the corresponding surface of the bit line structure 140 is also flat, and if the surface of the fourth recessed surface 123 is curved, the corresponding surface of the bit line structure 140 is also curved, for example, the fourth recessed surface 123 is a curved surface recessed toward the gate 100, and the surface of the bit line structure 140 and the corresponding position thereof have a protrusion embedded therein to fit the fourth recessed surface 123.

[0071] In some embodiments, the first direction X and the second direction Y constitute a reference surface, and the orthographic projection shape of the bit line structure 140 on the reference surface can be circular, triangular, square, or N-sided (N can be greater than or equal to 5) polygonal, etc.

[0072] In some embodiments, the bit line structure 140 can include a bit line conductive layer 141 and a bit line barrier layer 142, wherein the bit line barrier layer 142 is at least located between the bit line conductive layer 141 and the semiconductor layer 120, which is beneficial to avoid the diffusion of ions in the bit line conductive layer 141 and other film layers into the semiconductor layer 120, so as to avoid the influence on the electrical performance of the semiconductor layer 120.

[0073] In some embodiments, the material of the bit line conductive layer 141 can be metal such as tungsten or copper, and the material of the bit line barrier layer 142 can be titanium nitride (TiN), tungsten nitride (WN), or titanium silicon nitride (TiSiN), etc.

[0074] In summary, the first recessed surface 103 and the second recessed surface 104 are arranged along the first direction X, and the gate dielectric layer 110 and the semiconductor layer 120 have two recessed surfaces corresponding to the first recessed surface 103 and the second recessed surface 104 respectively. The semiconductor layer 120 has a third recessed surface 122 corresponding to the first recessed surface 103 and a fourth recessed surface 123 corresponding to the second recessed surface 104. Based on the structure, the capacitor structure 130 and the bit line structure 140 can be embedded in the two recesses in the semiconductor layer 120 respectively to realize a 1T1C type of memory cell structure, that is, one transistor source or drain and one capacitor are electrically connected to form a memory cell structure. It can be understood that the capacitor structure 130 and the bit line structure 140 can be considered as partially embedded in the semiconductor layer 120, that is, the lower electrode layer 131 is in contact with the third recessed surface 122, and the bit line structure 140 is in contact with the fourth recessed surface 123. In this way, it is beneficial to increase the contact area between the lower electrode layer 131 and the semiconductor layer 120 to reduce the contact resistance therebetween, and to increase the contact area between the bit line structure 140 and the semiconductor layer 120 to reduce the contact resistance therebetween, thereby being beneficial to improve the transmission efficiency and transmission accuracy of the electrical signal between the lower electrode layer 131 and the semiconductor layer 120, and to improve the transmission efficiency and transmission accuracy of the electrical signal between the bit line structure 140 and the semiconductor layer 120. Thus, it is beneficial to improve the electrical performance of the memory cell structure.

[0075] Another embodiment of the present disclosure also provides a memory cell array structure composed of a plurality of memory cell structures provided by the foregoing embodiments. Figure 10 A perspective structural schematic diagram of a memory cell array structure provided by another embodiment of the present disclosure; Figure 11 A perspective structural schematic diagram of a capacitor structure and a bit line structure in a memory cell array structure provided by another embodiment of the present disclosure; Figure 12 A front view structural schematic diagram of a memory cell array structure provided by another embodiment of the present disclosure; Figure 13 Another front view structural schematic diagram of a memory cell array structure provided by another embodiment of the present disclosure; Figure 14 A top view structural schematic diagram of a memory cell array structure provided by another embodiment of the present disclosure; Figure 15 Another top view structural schematic diagram of a memory cell array structure provided by another embodiment of the present disclosure.

[0076] The memory cell array structure provided by another embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that the same or corresponding parts as the foregoing embodiments will not be described herein.

[0077] Reference Figures 10 to 15The memory cell array structure can comprise a plurality of memory cell structures provided in the foregoing embodiments, and the plurality of memory cell structures are arranged in sequence and spaced apart along the first direction X and / or the third direction Z, and the first direction X, the second direction Y and the third direction Z are perpendicular to each other.

[0078] In some embodiments, referring to Figure 10 and Figure 13 wherein, Figure 13 is Figure 10 FIG. 1 shows a front view structural schematic diagram of a memory cell array structure, and a plurality of memory cell structures are arranged in sequence and spaced apart along the first direction X, the gate 100 in the adjacent memory cell structure along the first direction X is electrically connected through the first electrical connection layer 150, and the semiconductor layer 120 in the adjacent memory cell structure along the first direction X is separated by the dielectric layer 160. That is, the gates 100 of the memory structures arranged along the first direction X are electrically connected to each other, and the semiconductor layers 120 of the memory structures arranged along the first direction X are insulated from each other.

[0079] In some other embodiments, referring to Figure 10 , Figure 12 and Figure 14 wherein, Figure 12 is Figure 10 FIG. 2 shows another front view structural schematic diagram of a memory cell array structure, Figure 14 is Figure 10 FIG. 3 shows a top view structural schematic diagram of a memory cell array structure, and the plurality of gates 100 and the plurality of first electrical connection layers 150 spaced apart along the first direction X can also be an integral structure. It can be understood that the plurality of gates 100 are formed at the same time as the plurality of first electrical connection layers 150.

[0080] In some embodiments, the material of the first electrical connection layer 150 can be the same as the material of the gate 100, thereby facilitating the reduction of the interface state between the gate 100 and the first electrical connection layer 150, and thereby facilitating the improvement of the electrical performance of the memory cell array structure.

[0081] In some embodiments, continuing to refer to Figure 10 and Figure 13 the semiconductor layers 120 are isolated by the dielectric layer 160, thereby facilitating the avoidance of electrical connection between the plurality of semiconductor layers 120 arranged in sequence and spaced apart along the first direction X, and thereby facilitating the avoidance of signal abnormalities of the memory cell array structure.

[0082] In some embodiments, the material of the dielectric layer 160 can include insulating materials such as silicon oxide or silicon nitride; in some other embodiments, the dielectric layer 160 can also be composed of air. In this way, the plurality of semiconductor layers 120 arranged in sequence and spaced apart along the first direction X are interrupted by the dielectric layer 160.

[0083] In some embodiments, the gate dielectric layers 110 in the adjacent memory cell structures along the first direction X can be separated by the dielectric layers 160; in other embodiments, the gate dielectric layers 110 in the adjacent memory cell structures along the first direction X can be connected to each other; in yet other embodiments, the gate dielectric layers 110 in the adjacent memory cell structures along the first direction X can be formed as an integral structure.

[0084] Referring to Figure 10 and Figure 11 wherein, Figure 11 is a structural schematic diagram of a capacitor structure 130 and a bit line structure 140. In some embodiments, a plurality of memory cell structures are sequentially and spacedly arranged along a third direction Z; the lower electrode layers 131 in the plurality of memory cell structures arranged spacedly along the third direction Z have the dielectric layers 160 therebetween; the plurality of lower electrode layers 131 arranged spacedly along the third direction Z surround the outer sidewalls of the same capacitor dielectric layer 133; the inner side of the capacitor dielectric layer 133 forms a first through hole, and the upper electrode layer 132 fills the first through hole. By arranging the plurality of memory cell structures arranged spacedly along the third direction Z to have the dielectric layers 160 between the lower electrode layers 131, the capacitor structures 130 arranged along the third direction Z can be spaced. By arranging the upper electrode layer 132 to fill the first through hole, that is, the capacitor structures 130 arranged along the third direction Z share the upper electrode layer 132. By arranging the capacitor structures 130 arranged along the third direction Z to share the upper electrode layer 132, the electrical performance of the memory cell array structure can be improved.

[0085] In some embodiments, the capacitor structures 130 in the plurality of memory cell structures arranged spacedly along the third direction Z can also be separated by the dielectric layers 160, that is, the upper electrode layers 132 arranged spacedly along the third direction Z are also separated by the dielectric layers 160, and the capacitor dielectric layers 133 arranged spacedly along the third direction Z are also separated by the dielectric layers 160.

[0086] In some embodiments, referring to Figure 10 and Figure 15 wherein, Figure 15 is a top view structural schematic diagram of the memory cell array structure shown in Figure 10 The plurality of memory cell structures are also arranged spacedly along a second direction Y. The two adjacent memory cell structures along the second direction Y are axially symmetrical along the first direction X. The two gates 100 in the adjacent memory cell structures along the second direction Y are respectively in contact with the two first electrical connection layers 150, and the two first electrical connection layers 150 are electrically connected by the second electrical connection layer 170.

[0087] It can be understood that the first electric connection layer 150 connects two adjacent gates 100 along the first direction X, two adjacent gates 100 located on one side of the second electric connection layer 170 and along the first direction X, and the first electric connection layer 150 connecting the two gates 100, two adjacent gates 100 located on one side of the second electric connection layer 170 and along the first direction X, and the first electric connection layer 150 and the second electric connection layer 170 connecting the two gates 100 together form a I-shaped structure. The two first electric connection layers 150 are electrically connected through the second electric connection layer 170, that is, the first gates 100 of the storage unit structure symmetrical along the first direction X are electrically connected through the second electric connection layer 170. Compared with the storage unit array structure without the second electric connection layer 170, the gates 100 of the storage unit structure symmetrical along the first direction X are electrically connected through the second electric connection layer 170, which is beneficial to reduce the resistance of the gate 100 itself.

[0088] It should be noted that the plurality of storage unit structures can also be arranged along the first direction X and / or the third direction Z on the basis of being arranged at intervals along the second direction Y as in the above-mentioned embodiments.

[0089] In some embodiments, with reference to Figure 10 and Figure 11 The bit line structure 140 extends along the third direction Z, and the semiconductor layers 120 of the plurality of storage unit structures arranged at intervals along the third direction Z are connected to the same bit line structure 140. That is, an electrical signal can be transmitted to the plurality of storage unit structures arranged along the third direction Z through one bit line structure 140.

[0090] Another embodiment of the present disclosure further provides a manufacturing method of a storage unit array structure for forming the storage unit array structure provided in the above-mentioned embodiments. Figures 16 to 23 The manufacturing method of the storage unit array structure provided in another embodiment of the present disclosure corresponds to the structure schematic diagram of each step. The manufacturing method of the storage unit array structure provided in another embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that the same or corresponding parts as in the above-mentioned embodiments can refer to the content of the above-mentioned embodiments, which will not be described hereinafter.

[0091] With reference to Figures 16 to 23The manufacturing method of the memory cell array structure can comprise the following steps: providing a substrate 200; forming a plurality of memory cell structures arranged along a first direction X and / or a third direction Y on the substrate 200; the memory cell structure comprises: a gate 100 extending along the first direction X, the gate 100 having a first surface 101 and a second surface 102 opposite to each other along a second direction Y, the second surface 102 having a first recessed surface 103 and a second recessed surface 104 arranged at intervals along the first direction X, both the first recessed surface 103 and the second recessed surface 104 are recessed towards the first surface 101, and the first direction X and the second direction Y intersect with each other; a gate dielectric layer 110 conformally covering at least the second surface 102; a semiconductor layer 120 conformally covering a side of the gate dielectric layer 110 away from the gate 100, the semiconductor layer 120 having a contact surface 121 opposite to the second surface 102, the contact surface 121 having a third recessed surface 122 corresponding to the first recessed surface 103 and a fourth recessed surface 123 corresponding to the second recessed surface 104; a capacitor structure 130 comprising a lower electrode layer 131, an upper electrode layer 132 and a capacitor dielectric layer 133 between the upper electrode layer 132 and the lower electrode layer 131, the lower electrode layer 131 being in contact with the third recessed surface 122; a bit line structure 140 being in contact with the fourth recessed surface 123; the first direction X, the second direction Y and the third direction Z intersect with each other in pairs.

[0092] It should be noted that the order of the steps of forming the gate 100, the gate dielectric layer 110, the semiconductor layer 120, the capacitor structure 130 and the bit line structure 140 can be adjusted, which will be described in detail below.

[0093] Reference Figures 16 to 18 The steps of forming the capacitor structure 130 and the bit line structure 140 in the plurality of memory cell structures can comprise the following steps: forming a stack structure 210 on the substrate 200, the stack structure 210 comprising first isolation layers 211 and second isolation layers 212 alternately stacked along a third direction Z; performing a patterning process on the stack structure 210 to form at least one first opening 220 and at least one second opening 230, the first opening 220 and the second opening 230 being arranged alternately along the first direction X; conformally covering an initial lower electrode layer 135 and a capacitor dielectric layer 133 on the inner wall of the first opening 220 in sequence; forming an upper electrode layer 132 to fill the remaining first opening 220; forming a bit line structure 140 to fill the second opening 230; laterally etching a part of the width of the first isolation layer 211 along the second direction Y to form a third opening 240, the third opening 240 exposing a part of the thickness of the initial lower electrode layer 135 along the third direction Z; removing the exposed initial lower electrode layer 135 to form a plurality of lower electrode layers 131 arranged at intervals along the third direction Z.

[0094] The above steps will be described in detail below.

[0095] Reference Figure 16 The stack structure 210 is formed on the substrate 200.

[0096] It can be understood that the materials of the first isolation layer 211 and the second isolation layer 212 can be different. In some embodiments, the material of the first isolation layer 211 can be silicon oxide, and the material of the second isolation layer 212 can be silicon nitride. In other embodiments, the material of the first isolation layer 211 can be silicon oxide, and the material of the second isolation layer 212 can be polysilicon.

[0097] It should be noted that Figure 16 In the above example, three layers of the first isolation layer 211 and three layers of the second isolation layer 212 are stacked along the third direction Z. In actual applications, the number of the first isolation layer 211 and the number of the second isolation layer 212 stacked along the third direction Z can be flexibly adjusted according to requirements.

[0098] Continuing to refer to Figure 16 The stack structure 210 is subjected to a patterning process to form the first opening 220 and the second opening 230.

[0099] It can be understood that the first opening 220 and the second opening 230 can both penetrate the stack structure 210 to expose the surface of the substrate 200.

[0100] In combination with reference to Figure 16 and Figure 17 The initial lower electrode layer 135, the capacitor dielectric layer 133, and the upper electrode layer 132 filling the first opening 220 are formed.

[0101] In some embodiments, during the process of forming the initial lower electrode layer 135, the capacitor dielectric layer 133, and the upper electrode layer 132 filling the first opening 220, the second opening 230 can be covered first, so that when the initial lower electrode layer 135, the capacitor dielectric layer 133, and the upper electrode layer 132 filling the first opening 220 are formed, it is beneficial to avoid that the second opening 230 is also filled.

[0102] In combination with reference to Figure 16 and Figure 17 The bit line structure 140 is formed, and the bit line structure 140 fills the second opening 230.

[0103] In combination with reference to Figure 17 and Figure 18 The first isolation layer 211 is etched to form the third opening 240, and the initial lower electrode layer 135 with a partial thickness is exposed by the third opening 240 along the third direction Z. The initial lower electrode layer 135 exposed by the third opening 240 is etched to form the lower electrode layer 131 arranged at intervals along the third direction Z.

[0104] It can be understood that, in one etching process, the initial lower electrode layer 135 in the plurality of first openings 220 is etched into a plurality of lower electrode layers 131 which are disconnected from each other.

[0105] With reference to Figures 19 to 23 , the forming of the semiconductor layer 120 in the plurality of memory cell structures can include the following steps: forming a third isolation layer 213 which fills the third openings 240 (see Figure 18 ); etching a partial width of the second isolation layer 212 in the second direction Y to form fourth openings 250 which expose the outer wall of the lower electrode layer 131 and expose part of the sidewall of the bit line structure 140, the fourth openings 250 have a first inner wall which exposes the lower electrode layer 131 and the bit line structure 140, and a second inner wall and a third inner wall which are oppositely arranged along the third direction Z; forming an initial semiconductor layer 124 which extends along the first direction X and covers at least the first inner wall; forming an initial gate dielectric layer 111 which is located on the side of the initial semiconductor layer 124 away from the lower electrode layer 131 and extends along the first direction X; forming an initial gate electrode 107 which is located on the side of the initial gate dielectric layer 111 away from the initial semiconductor layer 124 and extends along the first direction X; and performing a patterning process on the initial semiconductor layer 124 to form a plurality of semiconductor layers 120 which are arranged at intervals along the first direction X, one semiconductor layer 120 is in contact with one lower electrode layer 131 and one bit line structure 140, respectively.

[0106] The above steps are described in detail as follows.

[0107] With reference to Figure 19 , the third isolation layer 213 is formed, and part of the third isolation layer 213 can also serve as the dielectric layer in the above-mentioned embodiment of the memory cell array structure.

[0108] With reference to Figure 20 , the partial width of the second isolation layer 212 is etched to form the fourth openings 250, the first inner wall of the fourth openings 250 is actually the contact surface 121 corresponding to the subsequently formed semiconductor layer 120, and the second inner wall and the third inner wall are the top surface and the bottom surface of the fourth openings 250 which are oppositely arranged along the third direction Z.

[0109] With reference to Figure 21 and Figure 22 , wherein Figure 22 is Figure 21A top view structural schematic diagram of the structure shown, forming an initial semiconductor layer 124, an initial gate dielectric layer 111 and an initial gate 107, the initial semiconductor layer 124 covering at least the first inner wall, the surface of the initial semiconductor layer 124 covering the first inner wall being the contact surface of the subsequently formed semiconductor layer, by setting the initial semiconductor layer 124 to cover at least the first inner wall, the subsequently formed semiconductor layer is in contact with the capacitor structure 130.

[0110] Reference Figure 23 The initial semiconductor layer is patterned to form the spaced semiconductor layers 120.

[0111] In some embodiments, the initial gate dielectric layer 111 is also patterned in the process of patterning the initial semiconductor layer, and the remaining initial gate dielectric layer 111 serves as the gate dielectric layer 110; in other embodiments, the initial gate dielectric layer 111 can also not be patterned, and the initial gate dielectric layer 111 directly serves as the gate dielectric layer 110.

[0112] In some embodiments, the initial gate 107 is also patterned in the process of patterning the initial semiconductor layer, and the remaining initial gate 107 serves as the gate 100; in other embodiments, the initial gate 107 can also not be patterned, and the initial gate 107 directly serves as the gate 100.

[0113] In some embodiments, in combination with reference to Figure 20 , Figure 21 and Figure 10 , the initial semiconductor layer 124 also covers the second inner wall and / or the third inner wall, the initial gate dielectric layer 111 is also located between the initial semiconductor layer 124 covering the second inner wall and the initial gate 107, and / or, the initial gate dielectric layer 111 is also located between the initial semiconductor layer 124 covering the third inner wall and the initial gate 107.

[0114] It can be understood that the initial semiconductor layer 124 can only cover the first inner wall and the second inner wall, or the initial semiconductor layer 124 can only cover the first inner wall and the third inner wall, or the initial semiconductor layer 124 can cover the first inner wall, the second inner wall and the third inner wall, and the initial gate dielectric layer 111 is always located between the initial semiconductor layer 124 and the initial gate 107, by setting the initial semiconductor layer 124 to also cover the second inner wall and / or the third inner wall, the facing area between the formed initial gate 107 and the initial semiconductor layer 124 is increased, and the facing area between the subsequently formed gate 100 and the semiconductor layer 120 is also increased, thereby facilitating the increase of the control ability of the gate 100 on the semiconductor layer 120.

[0115] In some embodiments, in combination with referenceFigure 23 、 Figure 12 and Figure 13 , the initial gate 107 includes the gate 100 opposite to the semiconductor layer 120 and the first electric connection layer 150 opposite to the interval.

[0116] It can be understood that in the process of forming the initial gate 107, the gate 100 and the first electric connection layer 150 connecting the adjacent gates 100 can be formed respectively, or the part of the initial gate 107 opposite to the semiconductor layer 120 is formed as the gate 100 and the part opposite to the interval between the semiconductor layers 120 is formed as the first electric connection layer 150.

[0117] In some embodiments, reference can be made to Figure 23 and Figure 15 , the plurality of storage unit structures arranged along the first direction X form a storage unit structure group, in the step of forming the plurality of storage unit structures arranged along the first direction X, a plurality of storage unit structure groups are formed along the second direction Y, and two adjacent storage unit structure groups along the second direction Y are axisymmetric along the first direction X; the manufacturing method of the storage unit array structure further includes: forming a second electric connection layer 170, the second electric connection layer 170 is electrically connected with the gates 100 in the adjacent storage unit structures along the second direction Y.

[0118] It can be understood that the two storage unit structure groups axisymmetric along the first direction X and the second electric connection layer 170 connecting the gates 100 in the adjacent storage unit structures together form an H-shaped structure. By electrically connecting the gates 100 in the storage unit structure groups axisymmetric along the first direction X through the second electric connection layer 170, the resistance of the gates 100 in the storage unit structure groups can be reduced.

[0119] It should be noted that Figure 22 and Figure 23 do not completely correspond to the top view structural schematic diagram of Figure 21 , Figure 21 only show the manufacturing method of the storage unit structure arranged along the third direction Z, and the structural schematic diagram of the manufacturing method corresponding to Figures 16 to 21 and Figure 22 and Figure 23 can be obtained by extending the structure shown in Figures 16 to 21 along the first direction.

[0120] In some embodiments, the method of forming the capacitor structure 130, the semiconductor layer 120, the gate dielectric layer 110 and the gate 100 in the storage unit structure group can be formed by referring to the above-mentioned embodiments, and then the second electric connection layer 170 connecting the gates 100 in the adjacent storage unit structures along the second direction Y is formed.

[0121] It should be noted that the sequence of the above steps of forming the capacitor structure 130, forming the bit line structure 140, and forming the semiconductor layer 120, the gate dielectric layer 110 and the gate 100 can be changed, for example, the bit line structure 140 can be formed first, then the capacitor structure 130 is formed, and finally the semiconductor layer 120, the gate dielectric layer 110 and the gate 100 are formed, or the semiconductor layer 120, the gate dielectric layer 110 and the gate 100 can be formed first, then the capacitor structure 130 is formed, and finally the bit line structure 140 is formed, and so on.

[0122] In addition, the manufacturing method of the memory cell structure is similar to the manufacturing method of the memory cell array structure, and the difference lies in that the process steps of the manufacturing method are shorter when forming the individual memory cell structure.

[0123] In summary, the manufacturing method provided by the further embodiment of the present disclosure is advantageous to increase the number of memory cell structures in the memory cell array structure in a unit volume, that is, advantageous to improve the integration density of the memory cell array structure, and furthermore, advantageous to improve the electrical performance of the memory cell array structure.

[0124] Those skilled in the art can understand that the above embodiments are specific embodiments for implementing the present disclosure, and in actual applications, various changes can be made in form and details without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make various modifications and changes without departing from the spirit and scope of the embodiments of the present disclosure, and therefore, the protection scope of the embodiments of the present disclosure should be subject to the scope defined by the claims.

Claims

1. A memory cell structure, characterized in that: include: A gate extending along a first direction, the gate having a first surface and a second surface opposite to each other along a second direction, the second surface having a first concave surface and a second concave surface spaced apart along the first direction, the first concave surface and the second concave surface both being concave toward the first surface, and the first direction and the second direction intersecting; a gate dielectric layer, conformally covering at least the second surface; a semiconductor layer conformally covering a side of the gate dielectric layer away from the gate electrode, the semiconductor layer having a contact surface facing the second surface, the contact surface having a third recessed surface corresponding to the first recessed surface, and a fourth recessed surface corresponding to the second recessed surface; a capacitor structure comprising a lower electrode layer, an upper electrode layer, and a capacitor dielectric layer located between the upper electrode layer and the lower electrode layer, wherein the lower electrode layer is in contact with and connected to the third recessed surface; The bit line structure is in contact with the fourth recessed surface.

2. The memory cell structure according to claim 1, wherein: The lower electrode layer is a ring-shaped structure, and the outer wall of the lower electrode layer is in contact with the entire third concave surface; The first direction and the second direction constitute a reference plane, and the orthographic projection shape of the annular structure on the reference plane is a square ring, a circular ring, an elliptical ring or an N-gonal ring, where N is a positive integer greater than or equal to 5.

3. The memory cell structure according to claim 1, wherein: The sidewalls of the bit line structure extending along the third direction are in contact with the entire fourth recessed surface, and the first direction, the second direction and the third direction intersect with each other.

4. The memory cell structure according to any one of claims 1 to 3, wherein: It comprises a plurality of capacitor structures connected in parallel with each other, the lower electrode layer of one of the plurality of capacitor structures is in contact with and connected to the third recessed surface, and the lower electrode layers of the remaining capacitor structures are in contact with and connected in sequence.

5. The memory cell structure according to claim 4, wherein: Among the multiple capacitor structures other than the capacitor structure in contact with the third recessed surface, the lower electrode layers in at least some of the capacitor structures are arranged along the first direction, and / or, the lower electrode layers in at least some of the capacitor structures are arranged along the second direction.

6. The memory cell structure according to any one of claims 1 to 3, wherein: The gate further has a third surface and a fourth surface opposite to each other along a third direction, and the first direction, the second direction and the third direction intersect with each other; The gate dielectric layer also conformally covers the third surface and / or the fourth surface; The semiconductor layer also conformally covers a side of the gate dielectric layer away from the third surface and a side of the gate dielectric layer away from the fourth surface.

7. A memory cell array structure, characterized in that: include: A plurality of memory cell structures according to any one of claims 1 to 6; The plurality of storage unit structures are sequentially arranged at intervals along the first direction and / or the third direction, and the first direction, the second direction and the third direction intersect with each other.

8. The memory cell array structure according to claim 7, wherein: The plurality of memory cell structures are arranged in sequence along the first direction, the gates in the adjacent memory cell structures along the first direction are electrically connected through a first electrical connection layer, and a dielectric layer is provided between the semiconductor layers in the adjacent memory cell structures along the first direction.

9. The memory cell array structure according to claim 7, wherein: The plurality of storage unit structures are sequentially spaced apart along the third direction; A dielectric layer is provided between the lower electrode layers in the plurality of storage unit structures arranged at intervals along the third direction; the plurality of lower electrode layers arranged at intervals along the third direction surround the outer side wall of the same capacitor dielectric layer; The inner side of the capacitor dielectric layer forms a first through hole, and the upper electrode layer completely fills the first through hole.

10. The memory cell array structure according to claim 8 or 9, wherein: The multiple memory cell structures are also arranged at intervals along the second direction, and the two adjacent memory cell structures along the second direction are axially symmetrical along the first direction, and the two gates in the adjacent memory cell structures along the second direction are respectively contacted and connected to the two first electrical connection layers, and the two first electrical connection layers are electrically connected through the second electrical connection layer.

11. A method for manufacturing a memory cell array structure, characterized in that: include: providing a substrate; forming a plurality of memory cell structures arranged along a first direction and / or a third direction on the substrate; The memory cell structure includes: a gate extending along the first direction, the gate having a first surface and a second surface opposite to each other along the second direction, the second surface having a first concave surface and a second concave surface arranged at intervals along the first direction, the first concave surface and the second concave surface both being concave toward the first surface; a gate dielectric layer conformally covering at least the second surface; a semiconductor layer conformally covering a side of the gate dielectric layer away from the gate, the semiconductor layer having a contact surface facing the second surface, the contact surface having a third concave surface corresponding to the first concave surface, and a fourth concave surface corresponding to the second concave surface; a capacitor structure including a lower electrode layer, an upper electrode layer, and a capacitor dielectric layer located between the upper electrode layer and the lower electrode layer, the lower electrode layer being in contact with and connected to the third concave surface; and a bit line structure being in contact with and connected to the fourth concave surface. The first direction, the second direction, and the third direction intersect with each other.

12. The manufacturing method according to claim 11, characterized in that: The step of forming the capacitor structure and the bit line structure in the plurality of memory cell structures includes: forming a stacking structure on the substrate, the stacking structure comprising first isolation layers and second isolation layers alternately stacked along the third direction; Performing a patterning process on the stacked structure to form at least one first opening and at least one second opening, wherein the first opening and the second opening are alternately arranged along the first direction; Conformally covering the inner wall of the first opening with an initial lower electrode layer and a capacitor dielectric layer in sequence; forming the upper electrode layer that fills the remaining first opening; forming the bit line structure that completely fills the second opening; The first isolation layer is removed to form a third opening, wherein the third opening exposes a portion of the thickness of the initial lower electrode layer along the third direction; and the exposed initial lower electrode layer is removed to form a plurality of lower electrode layers spaced apart along the third direction.

13. The manufacturing method according to claim 12, characterized in that: The step of forming the semiconductor layer in a plurality of the memory cell structures comprises: forming a third isolation layer that completely fills the third opening; Laterally etching a portion of the width of the second isolation layer along the second direction to form a fourth opening, wherein the fourth opening exposes an outer wall of the lower electrode layer away from the capacitor dielectric layer and a portion of a sidewall of the bit line structure, the fourth opening having a first inner wall exposing the lower electrode layer and the bit line structure, and a second inner wall and a third inner wall opposite to each other along the third direction; forming an initial semiconductor layer extending along the first direction, the initial semiconductor layer at least covering the first inner wall; forming an initial gate dielectric layer located on a side of the initial semiconductor layer away from the lower electrode layer, the initial gate dielectric layer extending along the first direction; forming an initial gate located on a side of the initial gate dielectric layer away from the initial semiconductor layer, wherein the initial gate extends along the first direction; The initial semiconductor layer is patterned to form a plurality of semiconductor layers spaced apart along the first direction, wherein each semiconductor layer is in contact with and connected to a lower electrode layer and a bit line structure respectively.

14. The manufacturing method according to claim 13, characterized in that: The initial semiconductor layer also covers the second inner wall and / or the third inner wall, the initial gate dielectric layer is also located between the initial semiconductor layer covering the second inner wall and the initial gate, and / or the initial gate dielectric layer is also located between the initial semiconductor layer covering the third inner wall and the initial gate.

15. The manufacturing method according to claim 13 or 14, characterized in that: There is a gap between the semiconductor layers adjacent to each other along the first direction, and the initial gate includes the gate facing the semiconductor layer and a first electrical connection layer facing the gap.

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