Memory, preparation method thereof and electronic equipment

Abstract

The invention relates to a memory, a preparation method thereof and electronic equipment. The preparation method comprises the following steps: providing a substrate; a stacking structure is formed on the upper surface of the substrate, the stacking structure comprises a plurality of first stacking structures which are arranged at intervals in the first direction and the second direction, and each first stacking structure comprises sacrificial layers and conductive layers which are sequentially and alternately stacked from bottom to top; the first direction and the second direction are parallel to the substrate and intersect with each other; etching each conductive layer in the first stack structure, and partially removing each conductive layer to form a first gap; forming a first electrode in the first gap, wherein the first electrode covers the surface of the first gap; forming a capacitor dielectric layer, wherein the capacitor dielectric layer at least covers the surface of the first electrode; and forming a second electrode on the surface of the capacitor dielectric layer. The preparation method can increase the capacitance area so as to increase the capacitance, and can reduce the metal work function and contact resistance, thereby improving the performance of the memory.

Description

Technical Field

[0001] The present application relates to the field of semiconductors, and in particular to a memory device and a method for preparing the memory device, and an electronic device. Background Art

[0002] Three-dimensional dynamic random access memory (3D-DRAM) can have a higher integration density and a larger storage capacity, and has gradually become one of the important research directions of memory. A typical three-dimensional dynamic random access memory usually includes: transistors, word lines, bit lines and capacitors. Among them, the preparation method of the capacitor is generally as follows: first, the insulating dielectric layer in the stacked structure including insulating dielectric layers and metal layers alternately stacked from bottom to top is etched and removed to form a gap; a capacitor dielectric layer and an upper electrode are formed in the gap; the metal layer in the stacked structure is the lower electrode of the capacitor. The channel layer of the transistor in the three-dimensional dynamic random access memory is in contact with the metal layer in the stacked structure. Since the metal layer in the stacked structure is retained as the lower electrode in the above-mentioned capacitor, the area S of the capacitor plate formed is the outer surface of the metal layer (C = εS / d), and the plate area is limited by the length and thickness of the metal layer. Moreover, when forming the trenches for preparing transistors, the metal layer in the stacked structure that is in contact with the channel layer of the transistor will be oxidized, which will inevitably lead to an increase in the metal work function, and then to an increase in the contact resistance between the transistor and the capacitor, thereby affecting the performance of the three-dimensional dynamic random access memory. Summary of the invention

[0003] Based on this, it is necessary to provide a memory and a preparation method thereof, and an electronic device to address the above-mentioned technical problems, which can increase the capacitor area, thereby increase the capacitor capacity, and reduce the metal work function and contact resistance, thereby effectively improving the performance of the memory.

[0004] On the one hand, some embodiments of the present application provide a method for preparing a memory, comprising the following steps.

[0005] providing a substrate;

[0006] A stacking structure is formed on the upper surface of the substrate, the stacking structure comprising a plurality of first stacking structures arranged at intervals along a first direction and a second direction, each of the first stacking structures comprising a sacrificial layer and a conductive layer alternately stacked in sequence from bottom to top; the first direction and the second direction are both parallel to the substrate and intersect each other;

[0007] Etching each conductive layer in the first stacked structure to partially remove each conductive layer to form a first gap;

[0008] forming a first electrode in the first gap, wherein the first electrode covers a surface of the first gap;

[0009] forming a capacitor dielectric layer, wherein the capacitor dielectric layer at least covers the surface of the first electrode;

[0010] A second electrode is formed on the surface of the capacitor dielectric layer.

[0011] In the embodiment of the present application, a first stacking structure consisting of multiple sacrificial layers and conductive layers alternately stacked is first formed; then, each conductive layer in the first stacking structure is partially etched to form a first interval; and then, a capacitor including a first electrode, a capacitor dielectric layer, and a second electrode is formed in the first interval. The first electrode also conformally covers the surface of the first interval. Compared with the electrode structure obtained by filling the entire layer of space in the related art, the first electrode obtained in the present application can have a larger surface area, thereby effectively increasing the capacitance per unit substrate area.

[0012] In some embodiments, forming the first electrode in the first gap includes: using an atomic layer deposition process to form a first electrode that conformally covers the surface of the first gap; wherein the material of the first electrode includes: one of titanium nitride, tantalum nitride and molybdenum nitride.

[0013] In the embodiment of the present application, the first electrode with uniform thickness can be obtained on the surface of the first gap by using an atomic layer deposition process, thereby ensuring the electrical performance of the first electrode. In addition, the material of the first electrode can include metal nitrides including titanium nitride, tantalum nitride and molybdenum nitride, which can effectively avoid accidental oxidation in subsequent processes. In this way, in some embodiments where the first electrode needs to be electrically connected to other devices (such as transistors) to form a complete memory, the metal work function and contact resistance can be effectively reduced, thereby further improving the electrical performance of the obtained memory.

[0014] In some embodiments, after forming the stacked structure on the upper surface of the substrate and before etching each conductive layer in the first stacked structure, the preparation method further includes the following steps.

[0015] A release hole is formed in the first stacking structure, and the release hole penetrates the first stacking structure along a thickness direction;

[0016] Etching each conductive layer in the first stacked structure includes: etching each conductive layer in the first stacked structure based on the release hole.

[0017] In some embodiments, after forming the first electrode in the first gap and before forming the capacitor dielectric layer, the preparation method further includes the following steps.

[0018] Etching each sacrificial layer in the first stacked structure to partially remove each sacrificial layer to form a second gap; the length of the second gap along the first direction is smaller than the length of the first gap along the first direction;

[0019] The capacitor dielectric layer is formed, including: forming the capacitor dielectric layer at least in the release hole, the first gap and the second gap, and the capacitor dielectric layer at least covers the surface of the first electrode, the inner wall of the release hole and the surface of the second gap.

[0020] In an embodiment of the present application, after forming the first gap, the sacrificial layers in the first stacked structure are further etched to form a second gap; so that the capacitor dielectric layer and the second electrode also cover the second gap, further increasing the capacitor area, thereby improving the charge storage capacity of the capacitor.

[0021] In some embodiments, after forming the second electrode on the surface of the capacitor dielectric layer, the preparation method further includes: forming an electrode connection layer on the surface of the second electrode, wherein the electrode connection layer fills the release hole, the first gap and the second gap.

[0022] In some embodiments, the stacking structure also includes: a second stacking structure, the second stacking structure extends along the second direction, the second stacking structure includes sacrificial layers and conductive layers alternately stacked from bottom to top; the conductive layer in the second stacking structure serves as a bit line, and the sacrificial layer in the second stacking structure serves as a bit line isolation layer for adjacent bit lines; the first stacking structures arranged at intervals along the first direction are located on opposite sides of the second stacking structure.

[0023] In some embodiments, the capacitor dielectric layer, the second electrode and the electrode connection layer are also located on the stacked structure; the first electrode, the capacitor dielectric layer and the second electrode constitute a capacitor; after the electrode connection layer is formed on the surface of the second electrode, the preparation method also includes the following steps.

[0024] forming a covering dielectric layer on the upper surface of the electrode connection layer;

[0025] An isolation groove is formed, wherein the isolation groove penetrates through the covering dielectric layer, the electrode connection layer, the second electrode and the capacitor dielectric layer in the thickness direction; the orthographic projection of the isolation groove on the upper surface of the stacked structure covers the second stacked structure;

[0026] An isolation layer is formed in the isolation groove, and the isolation layer insulates and isolates the capacitors on two opposite sides of the second stacking structure; and a plurality of capacitors located on the same side of the second stacking structure share the second electrode.

[0027] In some embodiments, the manufacturing method further includes: forming a plurality of transistors in the first stack structure, wherein the transistors are connected to the first electrode and the bit line located in the same layer.

[0028] In some embodiments, forming a plurality of transistors in the first stack structure includes the following steps.

[0029] A plurality of first through holes are formed in the first stacking structure, wherein the first through holes are located between the capacitor and the second stacking structure and penetrate the isolation layer and the first stacking structure along the thickness direction;

[0030] removing the conductive layer retained in the first stacked structure based on the first through hole to obtain a second through hole;

[0031] A channel layer is formed at least on the sidewall and the bottom of the second through hole, wherein the channel layer is in contact with the first electrode and the bit line located in the same layer;

[0032] forming a gate dielectric layer on the surface of the channel layer;

[0033] A gate conductive layer is formed on the surface of the gate dielectric layer; the gate conductive layer also serves as a word line.

[0034] In an embodiment of the present application, a plurality of first through holes are first formed in the first stacking structure, and the conductive layer retained in the first stacking structure is removed based on the first through holes to obtain a second through hole; then a channel layer, a gate dielectric layer and a gate conductive layer are sequentially formed in the first through hole and the second through hole to form a transistor, so that the channel layer is in direct contact with the first electrode and the bit line located on the same layer, thereby ensuring that the work function and the contact resistance are reduced.

[0035] In some embodiments, after forming a stacking structure on the upper surface of the substrate and before etching each conductive layer in the first stacking structure, the preparation method further includes: forming a filling dielectric layer, the filling dielectric layer fills the gaps between adjacent first stacking structures and covers the upper surface of the stacking structure.

[0036] On the other hand, some embodiments of the present application provide a memory as a practical application of the memory preparation method described in some of the above embodiments. The memory also has the technical advantages possessed by the memory preparation method described in some of the above embodiments, which will not be described in detail here.

[0037] In some embodiments, a memory includes: a substrate and a plurality of memory cell stacking structures; wherein the plurality of memory cell stacking structures are arranged at intervals along a first direction and a second direction; each memory cell stacking structure includes a capacitor and a plurality of first gaps arranged at intervals from bottom to top; the capacitor includes a first electrode, a capacitor dielectric layer and a second electrode, the first electrode at least covers the surface of the first gap; the capacitor dielectric layer covers the surface of the first electrode, and the second electrode covers the surface of the capacitor dielectric layer; the first direction and the second direction are both parallel to the substrate and intersect with each other.

[0038] In some embodiments, the memory cell stacking structure further includes: a sacrificial layer, in which a second gap is formed; the sacrificial layer and the second gap are alternately arranged with the first gap from bottom to top; and the length of the second gap along the first direction is less than the length of the first gap along the first direction.

[0039] Correspondingly, the memory further includes: a release hole, which penetrates the memory unit stacking structure along the thickness direction and is connected to both the first gap and the second gap; the capacitor dielectric layer also covers the surface of the release hole and the surface of the second gap.

[0040] In some embodiments, the memory further includes: an electrode connection layer, which is located on a surface of the second electrode and fills the release hole, the first gap, and the second gap.

[0041] In some embodiments, the memory further includes: a bit line stack structure and a plurality of transistors, wherein the bit line stack structure extends along the second direction, and the bit line stack structure includes bit line isolation layers and bit lines alternately stacked in sequence from bottom to top; a memory cell stack structure arranged at intervals along the first direction is located on two opposite sides of the bit line stack structure; and a plurality of transistors are located on two opposite sides of the bit line stack structure, penetrate the memory cell stack structure along the thickness direction, and are connected to the first electrode and the bit line located on the same layer.

[0042] In some embodiments, the capacitor dielectric layer, the second electrode and the electrode connection layer are also located on the memory cell stacking structure and the bit line stacking structure; the memory also includes: a covering dielectric layer, an isolation groove and an isolation layer, wherein the covering dielectric layer is located on the upper surface of the electrode connection layer; the isolation groove penetrates the covering dielectric layer, the electrode connection layer, the second electrode and the capacitor dielectric layer along the thickness direction; the orthographic projection of the isolation groove on the upper surface of the stacking structure covers the second stacking structure; the isolation layer is located in the isolation groove, and the isolation layer insulates and isolates the capacitors on opposite sides of the bit line stacking structure; multiple capacitors located on the same side of the bit line stacking structure share the second electrode.

[0043] On the other hand, some embodiments of the present application provide an electronic device, including the memory described in some of the above embodiments. The electronic device also has the technical advantages possessed by the memory described in some of the above embodiments, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0045] Figure 1A schematic diagram of the structure of a memory provided in some embodiments;

[0046] Figure 2 For along Figure 1 Schematic diagram of the cross section in the AA direction;

[0047] Figure 3 For along Figure 1 Schematic diagram of the cross section in the BB direction;

[0048] Figure 4 For along Figure 1 Schematic diagram of the cross section in the CC direction;

[0049] Figure 5 For along Figure 1 Schematic diagram of the cross section in the middle DD direction;

[0050] Figure 6 For along Figure 1 Schematic diagram of the cross section in the EE direction;

[0051] Figure 7 For along Figure 1 Schematic diagram of the cross section in the FF direction;

[0052] Figure 8 A schematic diagram of a process for preparing a memory provided in some embodiments;

[0053] Fig. 9 A schematic flow chart of another method for preparing a memory provided in some embodiments;

[0054] Fig.10 A schematic flow chart of another method for preparing a memory provided in some embodiments;

[0055] Fig.11 is a flowchart of step S1100 provided in some embodiments;

[0056] Fig.12 A schematic diagram of a structure obtained after an initial stacking structure is formed provided in some embodiments;

[0057] Fig.13 A schematic diagram of a top view of a structure obtained after executing step S200 provided in some embodiments;

[0058] Fig.14 For along Fig.13 Schematic diagram of the cross section in the AA direction;

[0059] Fig.15 For along Fig.13 Schematic diagram of the cross section in the BB direction;

[0060] Fig.16 For along Fig.13 Schematic diagram of the cross section in the CC direction;

[0061] Fig.17 A schematic diagram of a top view of a structure obtained after executing step S250 provided in some embodiments;

[0062] Fig.18 For along Fig.17 Schematic diagram of the cross section in the AA direction;

[0063] Fig.19 For along Fig.17 Schematic diagram of the cross section in the BB direction;

[0064] Fig. 20 For along Fig.17 Schematic diagram of the cross section in the CC direction;

[0065] Fig.21 A schematic diagram of a top view of a structure obtained after executing step S260 provided in some embodiments;

[0066] Fig. 22 For along Fig.21 Schematic diagram of the cross section in the AA direction;

[0067] Fig.23 A structure obtained after executing step S300 provided in some embodiments is Fig.21 Schematic diagram of the cross section in the AA direction;

[0068] Fig.24 A structure obtained after executing step S300 provided in some embodiments is Fig.21 Schematic diagram of the cross section in the CC direction;

[0069] Fig.25 A structure obtained after executing step S400 provided in some embodiments is Fig.21 Schematic diagram of the cross section in the AA direction;

[0070] Fig.26 A structure obtained after executing step S400 provided in some embodiments is Fig.21 Schematic diagram of the cross section in the CC direction;

[0071] Fig. 27 A structure obtained after executing step S450 is provided in some embodiments. Fig.21 Schematic diagram of the cross section in the AA direction;

[0072] Fig.28 A structure obtained after executing step S450 is provided in some embodiments. Fig.21 Schematic diagram of the cross section in the CC direction;

[0073] Fig.29 A structure obtained after executing step S500 provided in some embodiments is Fig.21 Schematic diagram of the cross section in the AA direction;

[0074] Fig.30 A structure obtained after executing step S500 provided in some embodiments is Fig.21 Schematic diagram of the cross section in the CC direction;

[0075] Fig.31 A structure obtained after executing step S600 provided in some embodiments is Fig.21 Schematic diagram of the cross section in the AA direction;

[0076] Fig.32 A structure obtained after executing step S600 provided in some embodiments is Fig.21 Schematic diagram of the cross section in the CC direction;

[0077] Fig.33 A structure obtained after executing step S700 provided in some embodiments is Fig.21 Schematic diagram of the cross section in the AA direction;

[0078] Fig.34 A structure obtained after executing step S700 provided in some embodiments is Fig.21 Schematic diagram of the cross section in the CC direction;

[0079] Fig.35 A structure obtained after executing step S800 provided in some embodiments is Fig.21 Schematic diagram of the cross section in the AA direction;

[0080] Fig.36 A structure obtained after executing step S800 provided in some embodiments is Fig.21 Schematic diagram of the cross section in the CC direction;

[0081] Fig.37 A structure obtained after executing step S900 provided in some embodiments is Fig.21 Schematic diagram of the cross section in the AA direction;

[0082] Fig.38 A structure obtained after executing step S900 provided in some embodiments is Fig.21 Schematic diagram of the cross section in the CC direction;

[0083] Fig.39 A structure obtained after executing step S1000 is provided in some embodiments. Fig.21 Schematic diagram of the cross section in the AA direction;

[0084] Fig.40 A structure obtained after executing step S1000 is provided in some embodiments. Fig.21 Schematic diagram of the cross section in the CC direction;

[0085] Fig.41 A schematic diagram of a top view of a structure obtained after executing step S1101 provided in some embodiments;

[0086] Fig.42 For along Fig.41 Schematic diagram of the cross section in the AA direction;

[0087] Fig.43 For along Fig.41 Schematic diagram of the cross section in the EE direction;

[0088] Fig.44 A structure obtained after executing step S1102 is provided in some embodiments. Fig.41 Schematic diagram of the cross section in the AA direction;

[0089] Fig.45 A structure obtained after executing step S1102 is provided in some embodiments. Fig.41 Schematic diagram of the cross section in the EE direction;

[0090] Fig.46 A structure obtained after executing step S1103 is provided in some embodiments. Fig.41 Schematic diagram of the cross section in the AA direction;

[0091] Fig.47 A structure obtained after executing step S1103 is provided in some embodiments. Fig.41 Schematic diagram of the cross section in the EE direction;

[0092] Fig.48 A structure obtained after executing step S1104 is provided in some embodiments. Fig.41 Schematic diagram of the cross section in the AA direction;

[0093] Fig.49 A structure obtained after executing step S1104 is provided in some embodiments. Fig.41 Schematic diagram of the cross section in the EE direction;

[0094] Fig.50 A structure obtained after executing step S1105 is provided in some embodiments. Fig.41 Schematic diagram of the cross section in the AA direction;

[0095] Fig.51A structure obtained after executing step S1105 is provided in some embodiments. Fig.41 Schematic diagram of the cross section in the EE direction;

[0096] Fig.52 A structure obtained after performing a planarization process is provided in some embodiments. Fig.41 Schematic diagram of the cross section along the AA direction.

[0097] Description of reference numerals:

[0098] 10-substrate, 20-storage cell stacking structure, 30-capacitor, 31-first electrode, 32-capacitor dielectric layer, 33 second electrode, 40-stacked structure, 40A-first stacked structure, 40B-second stacked structure, 41-sacrificial layer, 42-conductive layer, 50-electrode connecting layer, 60-bit line stacking structure, 61-bit line isolation layer, 62-bit line, 70-transistor, 71-channel layer, 72-gate dielectric layer, 73-gate conductive layer, 80-filling dielectric layer, 90-covering dielectric layer, 100-isolation layer, G1-first gap, G2-second gap, G3-isolation groove, H1-release hole, H2-first through hole, H3-second through hole. DETAILED DESCRIPTION

[0099] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0100] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0101] It should be noted that when an element is considered to be "connected" to another element, it can be directly connected to the other element, or connected to the other element through an intermediate element. In addition, the "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc. if there is transmission of electrical signals or data between the connected objects.

[0102] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.

[0103] Three-dimensional dynamic random access memory (3D-DRAM) can have a higher integration density and a larger storage capacity, and has gradually become one of the important research directions of memory. A typical three-dimensional dynamic random access memory usually includes: transistors, word lines, bit lines and capacitors. Among them, the preparation method of the capacitor is generally as follows: first, the insulating dielectric layer in the stacked structure including the insulating dielectric layer and the metal layer alternately stacked from bottom to top is etched and removed to form a gap; a capacitor dielectric layer and an upper electrode are formed in the gap; the metal layer in the stacked structure is the lower electrode of the capacitor, and the area of ​​the capacitor is only the surface area of ​​the metal layer. The channel layer of the transistor in the three-dimensional dynamic random access memory is in contact with the metal layer in the stacked structure. Since the metal layer in the stacked structure is retained as the lower electrode in the above-mentioned capacitor, the area S of the capacitor plate formed is the outer surface of the metal layer (C = εS / d), and the plate area is limited by the length and thickness of the metal layer. Moreover, when forming the trenches for preparing transistors, the metal layer in the stacked structure that is in contact with the channel layer of the transistor will be oxidized, which will inevitably lead to an increase in the metal work function, and then to an increase in the contact resistance between the transistor and the capacitor, thereby affecting the performance of the three-dimensional dynamic random access memory.

[0104] See also Figures 1 to 7 It is understood that in some embodiments, a memory is provided. The memory includes: a substrate 10 and a plurality of memory cell stacking structures 20; wherein the plurality of memory cell stacking structures 20 are arranged at intervals along the first direction and the second direction; each memory cell stacking structure 20 includes a plurality of first gaps G1 and a capacitor 30 arranged at intervals from bottom to top; the capacitor 30 includes a first electrode 31, a capacitor dielectric layer 32 and a second electrode 33, the first electrode 31 at least covers the surface of the first gap G1; the material of the first electrode 31 includes a metal nitride; the capacitor dielectric layer 32 covers the surface of the first electrode 31, and the second electrode 33 covers the surface of the capacitor dielectric layer 32; the first direction and the second direction are parallel to the substrate 10 and intersect with each other.

[0105] For example, the substrate 10 may be made of any combination of semiconductor materials, insulating materials, conductor materials or their material types. The substrate 10 may be a single-layer structure or a multi-layer structure. For example, the substrate 10 may be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 10 may be a layered substrate including a stack of Si and SiGe, a stack of Si and SiC, a silicon on insulator (SOI) or a silicon germanium on insulator, etc. This application is not limited by comparison.

[0106] For example, the first direction is, for example, the X direction, the second direction is, for example, the Y direction, the first direction and the second direction are both parallel to the substrate 10 and intersect each other, and the third direction is perpendicular to the substrate direction, for example, the Z direction. To more clearly illustrate the structure of the memory provided by the present application, unless otherwise specified, the following embodiments and drawings will continue the above-mentioned definitions of various directions.

[0107] For example, an atomic layer deposition process may be used to form the first electrode 31 conformally covering the surface of the first gap G1 .

[0108] By way of example, the material of the first electrode 31 may include titanium nitride, tungsten nitride, molybdenum nitride, aluminum nitride, magnesium nitride or tantalum nitride.

[0109] For example, the material of the capacitor dielectric layer 32 may include silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass or borosilicate glass.

[0110] By way of example, the material of the second electrode 33 may include: metal tungsten, metal titanium, metal aluminum, metal copper or metal nickel.

[0111] In some embodiments, the sum of the thicknesses of the first electrode 31 , the capacitor dielectric layer 32 , and the second electrode 33 is less than or equal to half the height of the first gap G1 , so as to facilitate the arrangement of other related film layers in the first gap G1 .

[0112] Please continue reading Figure 1 and Figure 2In some embodiments, the memory cell stack structure 20 further includes: a sacrificial layer 41, in which a second gap G2 is formed; the sacrificial layer 41 and the second gap G2 are arranged alternately with the first gap G1 from bottom to top; the length of the second gap G2 along the first direction (e.g., X direction) is less than the length of the first gap G1 along the first direction (e.g., X direction). Correspondingly, the memory further includes: a release hole H1, which penetrates the memory cell stack structure 20 along the thickness direction (e.g., Z direction) and is connected to both the first gap G1 and the second gap G2; the capacitor dielectric layer 32 also covers the surface of the release hole H1 and the surface of the second gap G2.

[0113] Here, the sacrificial layer 41 and the second gaps G2 in the same layer are arranged as a whole, alternately arranged with the first gaps G1 from bottom to top. It can be understood that due to the existence of the sacrificial layer 41, the length of the second gaps G2 along the X direction is shorter than the length of the first gaps G1 along the X direction.

[0114] For example, the first gap G1 and the second gap G2 extend along the X direction at the same end of the memory cell stack structure 20 , and the release hole H1 is adjacent to the end. Thus, the release hole H1 can communicate with both the first gap G1 and the second gap G2 .

[0115] By way of example, the material of the sacrificial layer 41 may include silicon oxide, silicon nitride, phosphosilicate glass or borosilicate glass.

[0116] In some embodiments, the memory further includes a filling dielectric layer 80 filling the gaps between the memory cell stack structures 20 and covering the surface of the stack structures.

[0117] Please continue reading Figure 2 In some embodiments, the memory further includes: an electrode connection layer 50 , which is located on the surface of the second electrode 33 and fills the release hole H1 , the first gap G1 , and the second gap G2 .

[0118] Here, the electrode connection layer 50 is used to connect the second electrodes 33 of each capacitor 30 together, so as to increase the capacitance storage capacity.

[0119] For example, the electrode connection layer 50 may also cover the upper surface of the memory cell stack structure 20 to facilitate corresponding connection between the electrode connection layer 50 and an external circuit.

[0120] By way of example, the material of the electrode connection layer 50 includes: metal tungsten, metal copper, metal aluminum or doped polysilicon.

[0121] Please continue reading Figures 1 to 3 as well as Figure 7It is understood that in some embodiments, the memory also includes: a bit line stack structure 60 and a plurality of transistors 70, wherein the bit line stack structure 60 extends along a second direction (e.g., the Y direction), and the bit line stack structure 60 includes a bit line isolation layer 61 and a bit line 62 alternately stacked from bottom to top; the memory cell stack structure 20 arranged at intervals along a first direction (e.g., the X direction) is located on two opposite sides of the bit line stack structure 60; the plurality of transistors 70 are located on two opposite sides of the bit line stack structure 60, penetrate the memory cell stack structure 20 along the thickness direction (e.g., the Z direction), and are connected to the first electrode 31 and the bit line 62 located on the same layer.

[0122] For example, the first sacrificial layer 41 and the second gap G2 in the memory cell stack structure 20 are arranged in the same layer as the bit line isolation layer 61 in the bit line stack structure 60; the first gap G1 in the memory cell stack structure 20 is arranged in the same layer as the bit line 62 in the bit line stack structure 60. Alternatively, the memory cell stack structure 20 and the bit line stack structure 60 can also be prepared separately based on different regions of the same film layer stack structure.

[0123] Please continue reading Figure 1 to Figure 2 In some embodiments, the capacitor dielectric layer 32, the second electrode 33 and the electrode connection layer 50 are also located on the memory cell stacking structure 20 and the bit line stacking structure 60; the memory further includes: a covering dielectric layer 90, an isolation groove G3 and an isolation layer 100, wherein the covering dielectric layer 90 is located on the upper surface of the electrode connection layer 50; the isolation groove G3 penetrates the covering dielectric layer 90, the electrode connection layer 50, the second electrode 33 and the capacitor dielectric layer 32 along the thickness direction; the positive projection of the isolation groove G3 on the upper surface of the stacking structure covers the bit line stacking structure 60; the isolation layer 100 is located in the isolation groove G3, and the isolation layer 100 insulates and isolates the capacitors 30 on opposite sides of the bit line stacking structure 60; multiple capacitors 30 located on the same side of the bit line stacking structure 60 share the second electrode 33.

[0124] It should be noted that, in order to facilitate the display of some structures, the structures located above the filling dielectric layer 80, such as the capacitor dielectric layer 32, the second electrode 33 and the electrode connection layer 50, are not shown in FIG. Figure 1 Shown in.

[0125] Here, by forming an isolation trench and an isolation layer located in the isolation trench, at least the capacitor dielectric layer 32, the second electrode 33 and the electrode connection layer 50 located on the storage cell stack structure 20 and the bit line stack structure 60 are disconnected, so that the second electrodes 33 of multiple capacitors 30 located on the same side of the bit line stack structure 60 are connected together, so as to facilitate the regional control of each capacitor 30.

[0126] See also Figure 8Some embodiments of the present application also provide a method for preparing a memory, which is used to prepare the memory described in some of the above embodiments. The technical advantages of the memory described in some of the above embodiments are also possessed by the preparation method, which will not be described in detail here. The preparation method includes steps S100 to S600.

[0127] S100 , providing a substrate.

[0128] S200, forming a stacking structure on the upper surface of the substrate, the stacking structure comprising a plurality of first stacking structures arranged at intervals along a first direction and a second direction, each first stacking structure comprising a sacrificial layer and a conductive layer alternately stacked in sequence from bottom to top; the first direction and the second direction are both parallel to the substrate and intersect with each other.

[0129] S300, etching each conductive layer in the first stacked structure to partially remove each conductive layer to form a first gap.

[0130] S400, forming a first electrode in the first gap, wherein the first electrode covers a surface of the first gap; a material of the first electrode includes metal nitride.

[0131] S500, forming a capacitor dielectric layer, wherein the capacitor dielectric layer at least covers a surface of the first electrode.

[0132] S600, forming a second electrode on the surface of the capacitor dielectric layer.

[0133] In the embodiment of the present application, a first stacking structure consisting of multiple sacrificial layers and conductive layers alternately stacked is first formed; then, a first gap is formed by partially etching each conductive layer in the first stacking structure; then, a capacitor including a first electrode, a capacitor dielectric layer and a second electrode is formed in the first gap, and by making the first electrode cover the surface of the first gap, the relative area between the first electrode and the second electrode is effectively increased, thereby improving the charge storage capacity of the capacitor.

[0134] See also Fig. 9 In some embodiments, after step S200 and before step S300, the preparation method further includes step S260.

[0135] S260, forming a release hole in the first stacking structure, wherein the release hole penetrates the first stacking structure along a thickness direction.

[0136] Correspondingly, step S300 includes: etching each conductive layer in the first stacked structure based on the release holes.

[0137] Please continue reading Fig. 9 In some embodiments, after step S200 and before step S300, the preparation method further includes step S450.

[0138] S450, etching each sacrificial layer in the first stacked structure, and partially removing each sacrificial layer to form a second gap; the length of the second gap along the first direction is smaller than the length of the first gap along the first direction.

[0139] Correspondingly, step S500 includes: forming a capacitor dielectric layer at least in the release hole, the first gap and the second gap, the capacitor dielectric layer at least covering the surface of the first electrode, the inner wall of the release hole and the surface of the second gap.

[0140] See also Fig.10 In some embodiments, after step S200 and before step S300, the preparation method further includes step S250.

[0141] S250 , forming a filling dielectric layer, wherein the filling dielectric layer fills the gaps between adjacent first stacked structures and covers the upper surface of the stacked structure.

[0142] Please continue reading Fig.10 In some embodiments, after step S600, the preparation method further includes step S700.

[0143] S700, forming an electrode connection layer on the surface of the second electrode, wherein the electrode connection layer fills the release hole, the first gap and the second gap.

[0144] In some embodiments, the stacking structure also includes: a second stacking structure, the second stacking structure extends along the second direction, the second stacking structure includes sacrificial layers and conductive layers alternately stacked from bottom to top; the conductive layer in the second stacking structure serves as a bit line, and the sacrificial layer in the second stacking structure serves as a bit line isolation layer for adjacent bit lines; the first stacking structures arranged at intervals along the first direction are located on opposite sides of the second stacking structure.

[0145] Please continue reading Fig.11 In some embodiments, the capacitor dielectric layer, the second electrode and the electrode connection layer are also located on the stacked structure; the first electrode, the capacitor dielectric layer and the second electrode constitute a capacitor; after step S700, the preparation method further includes steps: S800~S1000.

[0146] S800, forming a covering dielectric layer on the upper surface of the electrode connection layer.

[0147] S900, forming an isolation groove, wherein the isolation groove penetrates through the covering dielectric layer, the electrode connection layer, the second electrode and the capacitor dielectric layer along the thickness direction; the orthographic projection of the isolation groove on the upper surface of the stacked structure covers the second stacked structure.

[0148] S1000, forming an isolation layer in the isolation trench, the isolation layer insulates and isolates the capacitors on two opposite sides of the second stacking structure; a plurality of capacitors located on the same side of the second stacking structure share a second electrode.

[0149] Please continue reading Fig.10 In some embodiments, after step S1000, the preparation method further includes step S1100.

[0150] S1100 , forming a plurality of transistors in a first stack structure, wherein the transistors are connected to first electrodes and bit lines located in the same layer.

[0151] For example, see Fig.11 , step S1100 includes steps: S1101~S1105.

[0152] S1101, forming a plurality of first through holes in the first stacking structure, wherein the first through holes are located between the capacitor and the second stacking structure and penetrate the isolation layer and the first stacking structure along a thickness direction.

[0153] S1102, removing the conductive layer retained in the first stacked structure based on the first through hole to obtain a second through hole.

[0154] S1103, forming a channel layer at least on the sidewall and the bottom of the second through hole, wherein the channel layer contacts the first electrode and the bit line located in the same layer.

[0155] S1104, forming a gate dielectric layer on the surface of the channel layer.

[0156] S1105, forming a gate conductive layer on the surface of the gate dielectric layer; the gate conductive layer also serves as a word line.

[0157] In addition, in the above embodiments of the present application, unless otherwise specified herein, the execution of each step in the method is not strictly limited in order, and these steps may not necessarily be executed in the order described, but may be executed in other ways. Moreover, at least a part of any step may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but may be executed at different times, and the execution order of these sub-steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least a part of the sub-steps or stages of other steps.

[0158] In order to more clearly illustrate the method for preparing the memory in some of the above embodiments, the following embodiments are combined with Figure 10 to Figure 52 The preparation methods of some memories are described in detail.

[0159] In step S100, refer to Fig.10S100 and Fig.12 , providing a substrate 10.

[0160] For example, the substrate 10 may be made of any combination of semiconductor materials, insulating materials, conductor materials or their material types. The substrate 10 may be a single-layer structure or a multi-layer structure. For example, the substrate 10 may be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 10 may be a layered substrate including a stack of Si and SiGe, a stack of Si and SiC, a silicon on insulator (SOI) or a silicon germanium on insulator, etc. This application is not limited by comparison.

[0161] In step S200, refer to Fig.10 S200 and Figures 13 to 16 A stacking structure is formed on the upper surface of the substrate 10, and the stacking structure includes a plurality of first stacking structures 40A arranged at intervals along a first direction (for example, the X direction) and a second direction (for example, the Y direction), and each first stacking structure 40A includes a sacrificial layer 41 and a conductive layer 42 alternately stacked from bottom to top; the first direction (for example, the X direction) and the second direction (for example, the Y direction) are parallel to the substrate and intersect with each other.

[0162] For example, an initial stacking structure consisting of multiple sacrificial layers 41 and conductive layers 42 alternately stacked in sequence may be formed on the substrate 10 first, and the initial stacking structure may be patterned to obtain a stacking structure 40 including a plurality of first stacking structures 40A.

[0163] By way of example, the material of the sacrificial layer 41 includes silicon oxide, silicon nitride or silicon oxynitride.

[0164] By way of example, the material of the conductive layer 42 includes: metal tungsten, metal titanium, metal aluminum, metal copper or metal nickel.

[0165] In one example, the material of the sacrificial layer 41 is, for example, silicon oxide; the material of the conductive layer 42 is, for example, metal tungsten.

[0166] In some embodiments, a second stacking structure 40B is formed simultaneously with the formation of the first stacking structure 40A. The second stacking structure 40B extends along a second direction (e.g., the Y direction), and the second stacking structure 40B includes sacrificial layers 41 and conductive layers 42 alternately stacked from bottom to top; the conductive layers 42 in the second stacking structure 40B serve as bit lines 62, and the sacrificial layers 41 in the second stacking structure 40B serve as bit line isolation layers 61 of adjacent bit lines 62; the first stacking structures 40A arranged at intervals along the first direction (e.g., the X direction) are located on opposite sides of the second stacking structure 40B.

[0167] Here, the conductive layers 42 located in the second stacked structure 40B and located in the same layer in the first stacked structure 40A are connected as one; and the sacrificial layers 41 located in the second stacked structure 40B and located in the same layer in the first stacked structure 40A are connected as one.

[0168] In step S250, refer to Fig.10 S250 and Figures 17 to 20 , forming a filling dielectric layer 80 , the filling dielectric layer 80 fills the gaps between adjacent first stacked structures 40A and covers the upper surface of the stacked structure 40 .

[0169] For example, a filling dielectric layer 80 that fills the gaps between adjacent first stacked structures 40A and covers the upper surface of the stacked structure 40 may be formed by processes such as chemical vapor deposition, physical vapor deposition, thermal oxidation, evaporative growth, molecular beam epitaxy or vapor phase film formation.

[0170] For example, the material filling the dielectric layer 80 includes silicon oxide, silicon nitride or silicon oxynitride. In one example, the material filling the dielectric layer 80 is, for example, silicon nitride.

[0171] In step S260, refer to Fig.10 S260 and Figure 21 to Figure 22 A release hole H1 is formed in the first stack structure 40A, and the release hole H1 penetrates the first stack structure 40A along the thickness direction (eg, Z direction).

[0172] Here, the release hole H1 may be formed at one end of the first stack structure 40A away from the second stack structure 40B to expose the conductive layer 42 in the first stack structure 40A.

[0173] For example, a patterned mask layer may be formed on the surface of the filling dielectric layer 80 facing away from the stacking structure 40, the patterned mask layer having an opening pattern defining the formation position of the release hole H1, and the filling dielectric layer 80 and the first stacking structure 40A are etched based on the patterned mask layer to obtain the release hole H1.

[0174] For example, the number of the release holes H1 matches the number of the first stacking structures 40A, which is not limited in the present application.

[0175] For example, a dry etching process may be used, and the formation direction and depth of the release hole H1 may be accurately controlled by adjusting parameters such as the etching direction and etching time.

[0176] It should be noted that, since this step does not involve further direct processing of the filling dielectric layer 80 between adjacent first stacked structures 40A, the cross-sectional schematic diagram of the structure obtained after executing this step along the BB direction can be referred to as follows: Fig.19 Understanding; the cross-sectional diagram along the CC direction can be referred to Fig. 20 understand.

[0177] In step S300, refer to Fig.10 S300 and Figure 23 to Figure 24 , each conductive layer 42 in the first stacked structure 40A is etched to partially remove each conductive layer 42 to form a first gap G1.

[0178] For example, a wet etching process may be used to etch and remove one end of the exposed conductive layer 42 , and parameters such as etching time may be adjusted to facilitate controlling the extension length of the obtained first gap G1 along the first direction (eg, X direction).

[0179] It should be noted that, since this step does not involve further direct processing of the filling dielectric layer 80 between adjacent first stacked structures 40A, the cross-sectional schematic diagram of the structure obtained after executing this step along the BB direction can be referred to as follows: Fig.19 understand.

[0180] In step S400, refer to Fig.10 S400 and Figure 25 to Figure 26 , a first electrode 31 is formed in the first gap G1 , and the first electrode 31 covers the surface of the first gap G1 ; the material of the first electrode 31 includes metal nitride.

[0181] For example, the first electrode 31 covering the surface of the first gap G1 may be formed by processes such as chemical vapor deposition, physical vapor deposition, evaporation, electroplating or atomic layer deposition. In one example, the first electrode 31 is prepared by an atomic layer deposition process.

[0182] The material of the first electrode 31 may include titanium nitride, tungsten nitride, molybdenum nitride, aluminum nitride, magnesium nitride or tantalum nitride.

[0183] It should be noted that, since this step does not involve further direct processing of the filling dielectric layer 80 between adjacent first stacked structures 40A, the cross-sectional schematic diagram of the structure obtained after executing this step along the BB direction can be referred to as follows: Fig.19 understand.

[0184] In step S450, refer to Fig.10 S450 and Figure 27 to Figure 28 , etching each sacrificial layer 41 in the first stacked structure 40A, partially removing each sacrificial layer 41 to form a second gap G2; the length of the second gap G2 along the first direction (eg, X direction) is smaller than the length of the first gap G1 along the first direction (eg, X direction).

[0185] Here, the orthographic projection of the second gap G2 on the substrate falls into the orthographic projection of the first gap G1 on the substrate.

[0186] For example, a wet etching process may be used to etch and remove one end of the exposed sacrificial layer 41 , and parameters such as etching time may be adjusted to facilitate controlling the extension length of the obtained second gap G2 along the first direction (eg, X direction).

[0187] In step S500, refer to Fig.10 S500 and Figure 29 to Figure 30 , forming a capacitor dielectric layer 32 , wherein the capacitor dielectric layer 32 at least covers the surface of the first electrode 31 .

[0188] For example, the capacitor dielectric layer 32 may be formed by covering the surface of the first electrode 31 using processes such as chemical vapor deposition, physical vapor deposition, thermal oxidation, atomic layer deposition, evaporation growth, molecular beam epitaxy or vapor phase film formation.

[0189] By way of example, the capacitor dielectric layer 301 includes silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass or borosilicate glass.

[0190] For example, in some embodiments, the capacitor dielectric layer 32 also covers the second gap G1 , the release hole H1 , and the surface of the filling dielectric layer 80 .

[0191] In step S600, refer to Fig.10 S600 and Figure 31 to Figure 32 , a second electrode 33 is formed on the surface of the capacitor dielectric layer 32 .

[0192] For example, the second electrode 33 covering the surface of the capacitor dielectric layer 32 may be formed by using processes such as chemical vapor deposition, physical vapor deposition, evaporation, electroplating or atomic layer deposition.

[0193] By way of example, the material of the second electrode 33 may include: metal tungsten, metal titanium, metal aluminum, metal copper or metal nickel.

[0194] In step S700, refer to Fig.10 S700 and Figure 33 to Figure 34 An electrode connection layer 50 is formed on the surface of the second electrode 33 , and the electrode connection layer 50 fills the release hole H1 , the first gap G1 , and the second gap G2 .

[0195] For example, the electrode connection layer 50 filling the release hole H1 , the first gap G1 and the second gap G2 and covering the surface of the second electrode 33 may be formed by processes such as chemical vapor deposition, physical vapor deposition, evaporation, electroplating or atomic layer deposition.

[0196] By way of example, the material of the electrode connection layer 50 may include: metal tungsten, metal copper, metal aluminum or doped polysilicon.

[0197] By way of example, the electrode connection layer 50 also covers the filling dielectric layer 80 .

[0198] In step S800, refer to Fig.10 S800 and Figure 35 to Figure 36 , a covering dielectric layer 90 is formed on the upper surface of the electrode connection layer 50 .

[0199] For example, the covering dielectric layer 90 may be formed by covering the upper surface of the electrode connection layer 50 using processes such as chemical vapor deposition, physical vapor deposition, thermal oxidation, atomic layer deposition, evaporative growth, molecular beam epitaxy or vapor phase film formation.

[0200] By way of example, the material of the cover dielectric layer 90 may include silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass or borosilicate glass.

[0201] In step S900, refer to Fig.10 S900 and Figures 37 to 38 , forming an isolation groove G3, the isolation groove G3 penetrates the covering dielectric layer 90, the electrode connection layer 50, the second electrode 33 and the capacitor dielectric layer 32 along the thickness direction (for example, the Z direction); the orthographic projection of the isolation groove G3 on the upper surface of the stacked structure 40 covers the second stacked structure 40B.

[0202] For example, an etching process may be used to etch from the surface of the covering dielectric layer 90 toward the substrate, and the filling dielectric layer 80 may be used as an etching stop layer to obtain the isolation groove G3.

[0203] In step S1000, refer to Fig.10 S1000 and Figure 39 to Figure 40An isolation layer 100 is formed in the isolation groove G3 , and the isolation layer 100 insulates and isolates the capacitors 30 on opposite sides of the second stacking structure 40B; multiple capacitors 30 located on the same side of the second stacking structure 40B share the second electrode 33 .

[0204] By way of example, the isolation layer 100 filling the isolation trench G3 may be formed by processes such as chemical vapor deposition, physical vapor deposition, thermal oxidation, atomic layer deposition, evaporative growth, molecular beam epitaxy, or vapor phase film formation.

[0205] By way of example, the material of the isolation layer 100 may include silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass or borosilicate glass.

[0206] In step S1100, refer to Fig.10 S1100 and Figures 41 to 48 , a plurality of transistors 70 are formed in the first stack structure 40A, and the transistors 70 are connected to the first electrode 31 and the bit line 62 located in the same layer.

[0207] Illustratively, step S1100 includes steps S1101 to S1105.

[0208] In step S1101, refer to Fig.11 S1101 and Figure 41 to Figure 43 A plurality of first through holes H2 are formed in the first stack structure 40A. The first through holes H2 are located between the capacitor 30 and the second stack structure 40B and penetrate the isolation layer 100 and the first stack structure 40A along the thickness direction (eg, the Z direction).

[0209] For example, a patterned mask layer is first formed on the cover dielectric layer 90 and the isolation layer 100. The patterned mask layer has an opening pattern defining a formation position of the first through hole H2. The isolation layer 100 and the first stacked structure 40A are etched based on the patterned mask layer to obtain the first through hole H2.

[0210] For example, a dry etching process may be used, and the formation direction and depth of the first through hole H2 may be accurately controlled by adjusting parameters such as the etching direction and etching time.

[0211] In step S1102, refer to Fig.10 S1102 and Figure 44 to Figure 45 , the conductive layer 42 retained in the first stacked structure 40A is removed based on the first through hole H2 to obtain a second through hole H3.

[0212] For example, a wet etching process may be used to selectively etch the conductive layer 42 retained in the first stacked structure 40A using an etching solution with a selectivity ratio, and the second electrode 33 is used as an etching stop layer to obtain the second through hole H3.

[0213] For example, in some embodiments, when the conductive layer 42 is removed, a portion of the bit line 62 in the second stack structure 40B is also removed simultaneously.

[0214] In step S1103, refer to Fig.10 S1103 and Figure 46 to Figure 47 A channel layer 71 is formed at least on the sidewall and the bottom of the second through hole H3 , and the channel layer 71 is in contact with the first electrode 31 and the bit line 62 located on the same layer.

[0215] For example, a process such as chemical vapor deposition, physical vapor deposition, thermal oxidation, atomic layer deposition, evaporation growth, molecular beam epitaxy or vapor phase film formation may be used to form the channel layer 71 covering the sidewall and bottom of the second through hole H3 .

[0216] For example, the material of the channel layer 71 includes: single crystal silicon, polycrystalline silicon, germanium silicon or indium tin zinc oxide. In one example, the material of the channel layer 71 is, for example, indium tin zinc oxide.

[0217] For example, in some embodiments, the channel layer 71 also covers the sidewall and the bottom of the first through hole H2 and covers the surface of the dielectric layer 90 .

[0218] Optionally, in some embodiments, after forming the channel layer 71, the method further includes: removing the portion of the channel layer 71 covering the surface of the sacrificial layer 41. Here, by removing part of the channel layer 71, formation of a parasitic transistor can be avoided, thereby further ensuring and improving the electrical performance of the memory.

[0219] In step S1104, refer to Fig.10 S1104 and Figure 48 to Figure 49 , a gate dielectric layer 72 is formed on the surface of the channel layer 71 .

[0220] For example, the gate dielectric layer 72 may be formed by covering the surface of the channel layer 71 by using processes such as chemical vapor deposition, physical vapor deposition, thermal oxidation, atomic layer deposition, evaporation growth, molecular beam epitaxy or vapor phase film formation.

[0221] By way of example, the material of the gate dielectric layer 72 includes silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide or hafnium dioxide.

[0222] In step S1105, refer to Fig.10 S1105 and Figure 50 to Figure 51 , a gate conductive layer 73 is formed on the surface of the gate dielectric layer 72; the gate conductive layer 73 also serves as a word line.

[0223] Here, the gate conductive layer 73 also fills the second through hole H3 ; ​​the channel layer 71 , the gate dielectric layer 72 and the gate conductive layer 73 together constitute the transistor 70 .

[0224] For example, the gate conductive layer 73 covering the surface of the channel layer 71 and filling the second through hole H3 may be formed by using a process such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, or evaporation.

[0225] By way of example, the material of the gate conductive layer 73 includes: metal tungsten, metal titanium, metal aluminum, metal copper or metal nickel.

[0226] See also Fig.52 In some embodiments, a planarization process may be performed on the semiconductor structure after the transistor 70 is formed.

[0227] In some embodiments, an electronic device is provided, including the memory described in some of the aforementioned embodiments. The electronic device also has the technical advantages possessed by the memory described in some of the aforementioned embodiments, which will not be described in detail here.

[0228] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0229] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0230] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention. It should be pointed out that, for a person of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A method for preparing a memory, characterized in that: The method comprises: providing a substrate; A stacking structure is formed on the upper surface of the substrate, the stacking structure comprising a plurality of first stacking structures arranged at intervals along a first direction and a second direction, each of the first stacking structures comprising a sacrificial layer and a conductive layer alternately stacked in sequence from bottom to top; the first direction and the second direction are both parallel to the substrate and intersect each other; Etching each of the conductive layers in the first stacked structure to partially remove each of the conductive layers to form a first gap; forming a first electrode in the first gap, wherein the first electrode covers a surface of the first gap; forming a capacitor dielectric layer, wherein the capacitor dielectric layer at least covers a surface of the first electrode; A second electrode is formed on the surface of the capacitor dielectric layer.

2. The method for preparing a memory according to claim 1, characterized in that: The forming of the first electrode in the first gap includes: using an atomic layer deposition process to form a first electrode that conformally covers the surface of the first gap; wherein, The material of the first electrode includes: one of titanium nitride, tantalum nitride and molybdenum nitride.

3. The method for preparing a memory according to claim 1, characterized in that: After forming a stacked structure on the upper surface of the substrate and before etching each conductive layer in the first stacked structure, the method further includes: forming a release hole in the first stacked structure, wherein the release hole penetrates the first stacked structure along a thickness direction; The etching of each conductive layer in the first stacked structure includes: etching each conductive layer in the first stacked structure based on the release hole.

4. The method for preparing a memory according to claim 3, characterized in that: After forming the first electrode in the first gap and before forming the capacitor dielectric layer, the method further includes: etching each sacrificial layer in the first stacked structure to partially remove each sacrificial layer to form a second gap; the length of the second gap along the first direction is less than the length of the first gap along the first direction; The forming of the capacitor dielectric layer includes: forming the capacitor dielectric layer at least in the release hole, the first gap and the second gap, and the capacitor dielectric layer at least covers the surface of the first electrode, the inner wall of the release hole and the surface of the second gap.

5. The method for preparing a memory according to claim 4, characterized in that: After forming the second electrode on the surface of the capacitor dielectric layer, the method further comprises: An electrode connection layer is formed on the surface of the second electrode, and the electrode connection layer fills the release hole, the first gap and the second gap.

6. The method for preparing a memory according to claim 5, characterized in that: The stacking structure further comprises: A second stacking structure, wherein the second stacking structure extends along the second direction, and the second stacking structure includes sacrificial layers and conductive layers alternately stacked from bottom to top; the conductive layers in the second stacking structure serve as bit lines, and the sacrificial layers in the second stacking structure serve as bit line isolation layers for adjacent bit lines; the first stacking structures spaced apart along the first direction are located on opposite sides of the second stacking structure.

7. The method for preparing a memory according to claim 6, characterized in that: The capacitor dielectric layer, the second electrode and the electrode connection layer are also located on the stacked structure; the first electrode, the capacitor dielectric layer and the second electrode constitute a capacitor; After forming the electrode connection layer on the surface of the second electrode, the method further includes: forming a covering dielectric layer on the upper surface of the electrode connection layer; forming an isolation groove, wherein the isolation groove penetrates the covering dielectric layer, the electrode connection layer, the second electrode and the capacitor dielectric layer in the thickness direction; the orthographic projection of the isolation groove on the upper surface of the stacked structure covers the second stacked structure; An isolation layer is formed in the isolation groove, and the isolation layer insulates and isolates the capacitors on two opposite sides of the second stacking structure; a plurality of the capacitors located on the same side of the second stacking structure share a second electrode.

8. The method for preparing a memory according to claim 7, characterized in that: A plurality of transistors are formed in the first stack structure, and the transistors are connected to the first electrode and the bit line located in the same layer.

9. The method for preparing a memory according to claim 8, characterized in that: The forming of a plurality of transistors in the first stack structure comprises: forming a plurality of first through holes in the first stacking structure, wherein the first through holes are located between the capacitor and the second stacking structure and penetrate the isolation layer and the first stacking structure along a thickness direction; removing the conductive layer retained in the first stacked structure based on the first through hole to obtain a second through hole; forming a channel layer at least on the sidewall and the bottom of the second through hole, wherein the channel layer contacts both the first electrode and the bit line located on the same layer; forming a gate dielectric layer on a surface of the channel layer; A gate conductive layer is formed on the surface of the gate dielectric layer; the gate conductive layer also serves as a word line.

10. The method for preparing a memory according to claim 1, characterized in that: After forming a stacked structure on the upper surface of the substrate and before etching each conductive layer in the first stacked structure, the method further includes: A filling dielectric layer is formed, wherein the filling dielectric layer fills the gaps between adjacent first stacked structures and covers the upper surfaces of the stacked structures.

11. A memory, characterized in that: include: substrate; A plurality of storage unit stacking structures are arranged at intervals along the first direction and the second direction; Each of the storage unit stacking structures includes a capacitor and a plurality of first gaps spaced from bottom to top; the capacitor includes a first electrode, a capacitor dielectric layer and a second electrode, the first electrode at least covers the surface of the first gap, and the material of the first electrode includes a metal nitride; the capacitor dielectric layer covers the surface of the first electrode, and the second electrode covers the surface of the capacitor dielectric layer; the first direction and the second direction are both parallel to the substrate and intersect with each other.

12. The memory according to claim 11, characterized in that: The memory cell stack structure further includes: a sacrificial layer, a second gap formed in the sacrificial layer; the sacrificial layer and the second gap are alternately arranged with the first gap from bottom to top; the length of the second gap along the first direction is less than the length of the first gap along the first direction; The memory also includes a release hole, which penetrates the memory unit stacking structure along the thickness direction and is connected to both the first gap and the second gap; the capacitor dielectric layer also covers the surface of the release hole and the surface of the second gap.

13. The memory according to claim 12, characterized in that: The device also includes an electrode connection layer, which is located on the surface of the second electrode and fills the release hole, the first gap and the second gap.

14. The memory according to claim 13, characterized in that: Also includes: A bit line stack structure, the bit line stack structure extending along the second direction, the bit line stack structure comprising bit line isolation layers and bit lines alternately stacked in sequence from bottom to top; The memory cell stack structures arranged at intervals along the first direction are located on two opposite sides of the bit line stack structure; A plurality of transistors are located on two opposite sides of the bit line stack structure, penetrate the memory cell stack structure along the thickness direction, and are connected to the first electrode and the bit line located in the same layer.

15. The memory according to claim 14, characterized in that: The capacitor dielectric layer, the second electrode and the electrode connection layer are also located on the memory cell stack structure and the bit line stack structure; the memory further includes: A covering dielectric layer, located on the upper surface of the electrode connection layer; an isolation groove, penetrating the covering dielectric layer, the electrode connection layer, the second electrode and the capacitor dielectric layer in a thickness direction; the orthographic projection of the isolation groove on the upper surface of the stacked structure covers the second stacked structure; An isolation layer is located in the isolation groove, and the isolation layer insulates and isolates the capacitors on two opposite sides of the bit line stack structure; a plurality of the capacitors located on the same side of the bit line stack structure share a second electrode.

16. An electronic device, characterized in that: include: A memory as claimed in any one of claims 11 to 15.

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